1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Dingxian Wen <shawn.wen@rock-chips.com>
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01
9 * 1. add BT656 mode support.
10 * 2. add ddr mode support.
11 * 3. fix 576i and 480i support mode.
12 * V0.0X01.0X02 add 4K30 mode.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/slab.h>
18 #include <linux/i2c.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_graph.h>
24 #include <linux/videodev2.h>
25 #include <linux/workqueue.h>
26 #include <linux/platform_device.h>
27 #include <linux/v4l2-dv-timings.h>
28 #include <linux/hdmi.h>
29 #include <linux/version.h>
30 #include <linux/compat.h>
31 #include <linux/rk-camera-module.h>
32 #include <media/v4l2-dv-timings.h>
33 #include <media/v4l2-device.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-event.h>
36 #include <media/v4l2-fwnode.h>
37 #include <linux/regmap.h>
38 #include "lt8619c.h"
39
40 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
41 #define LT8619C_NAME "LT8619C"
42
43 static int debug;
44 module_param(debug, int, 0644);
45 MODULE_PARM_DESC(debug, "debug level (0-2)");
46
47 #define RK_CAMERA_MODULE_DUAL_EDGE "rockchip,dual-edge"
48 #define LT8619C_DEFAULT_DUAL_EDGE 1U
49 #define RK_CAMERA_MODULE_DVP_MODE "rockchip,dvp-mode"
50 #define LT8619C_DEFAULT_DVP_MODE BT1120_OUTPUT
51
52 struct lt8619c_mode {
53 u32 width;
54 u32 height;
55 struct v4l2_fract max_fps;
56 u32 hts_def;
57 u32 vts_def;
58 u32 exp_def;
59 };
60
61 struct lt8619c {
62 struct device *dev;
63 struct v4l2_subdev sd;
64 struct media_pad pad;
65 struct v4l2_ctrl_handler hdl;
66 struct i2c_client *i2c_client;
67 struct mutex confctl_mutex;
68 struct v4l2_ctrl *detect_tx_5v_ctrl;
69 struct delayed_work delayed_work_enable_hotplug;
70 struct delayed_work delayed_work_monitor_resolution;
71 struct v4l2_dv_timings timings;
72 struct regmap *reg_map;
73 struct gpio_desc *reset_gpio;
74 struct gpio_desc *power_gpio;
75 struct gpio_desc *plugin_det_gpio;
76 struct clk *xvclk;
77 const struct lt8619c_mode *cur_mode;
78 const char *module_facing;
79 const char *module_name;
80 const char *len_name;
81 bool nosignal;
82 bool enable_hdcp;
83 u32 clk_ddrmode_en;
84 bool BT656_double_clk_en;
85 bool hpd_output_inverted;
86 int plugin_irq;
87 u32 edid_blocks_written;
88 u32 mbus_fmt_code;
89 u32 module_index;
90 u32 yuv_output_mode;
91 u32 cp_convert_mode;
92 u32 yc_swap;
93 u32 yuv_colordepth;
94 u32 bt_tx_sync_pol;
95 };
96
97 static const struct v4l2_dv_timings_cap lt8619c_timings_cap = {
98 .type = V4L2_DV_BT_656_1120,
99 /* keep this initialization for compatibility with GCC < 4.4.6 */
100 .reserved = { 0 },
101 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 410000000,
102 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
103 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
104 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
105 V4L2_DV_BT_CAP_REDUCED_BLANKING |
106 V4L2_DV_BT_CAP_CUSTOM)
107 };
108
109 static u8 edid_init_data[] = {
110 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
111 0x49, 0x78, 0x01, 0x88, 0x00, 0x88, 0x88, 0x88,
112 0x1C, 0x1F, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
113 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
114 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
115 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
116 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
117 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
118 0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
119 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
120 0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00,
121 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
122 0x37, 0x34, 0x39, 0x2D, 0x66, 0x48, 0x44, 0x37,
123 0x32, 0x30, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
124 0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
125 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x64,
126
127 0x02, 0x03, 0x1C, 0x71, 0x49, 0x90, 0x04, 0x02,
128 0x5F, 0x11, 0x07, 0x05, 0x16, 0x22, 0x23, 0x09,
129 0x07, 0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03,
130 0x0C, 0x00, 0x10, 0x00, 0x8C, 0x0A, 0xD0, 0x8A,
131 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00,
132 0x13, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0xD8, 0x09,
133 0x80, 0xA0, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x60,
134 0xA2, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x18,
135 0x8C, 0x0A, 0xD0, 0x90, 0x20, 0x40, 0x31, 0x20,
136 0x0C, 0x40, 0x55, 0x00, 0x48, 0x39, 0x00, 0x00,
137 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38,
138 0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0xC0, 0x6C,
139 0x00, 0x00, 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18,
140 0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00,
141 0xC0, 0x6C, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB3,
143 };
144
145 static u8 phase_num[10] = {
146 0x20, 0x28, 0x21, 0x29, 0x22,
147 0x2a, 0x23, 0x2b, 0x24, 0x2c,
148 };
149
150 static const struct lt8619c_mode supported_modes[] = {
151 {
152 .width = 3840,
153 .height = 2160,
154 .max_fps = {
155 .numerator = 10000,
156 .denominator = 300000,
157 },
158 .hts_def = 4400,
159 .vts_def = 2250,
160 }, {
161 .width = 1920,
162 .height = 1080,
163 .max_fps = {
164 .numerator = 10000,
165 .denominator = 600000,
166 },
167 .hts_def = 2200,
168 .vts_def = 1125,
169 }, {
170 .width = 1920,
171 .height = 1080,
172 .max_fps = {
173 .numerator = 10000,
174 .denominator = 300000,
175 },
176 .hts_def = 2200,
177 .vts_def = 1125,
178 }, {
179 .width = 1920,
180 .height = 540,
181 .max_fps = {
182 .numerator = 10000,
183 .denominator = 600000,
184 },
185 .hts_def = 2200,
186 .vts_def = 562,
187 }, {
188 .width = 1280,
189 .height = 720,
190 .max_fps = {
191 .numerator = 10000,
192 .denominator = 600000,
193 },
194 .hts_def = 1650,
195 .vts_def = 750,
196 }, {
197 .width = 720,
198 .height = 576,
199 .max_fps = {
200 .numerator = 10000,
201 .denominator = 500000,
202 },
203 .hts_def = 864,
204 .vts_def = 625,
205 }, {
206 .width = 720,
207 .height = 480,
208 .max_fps = {
209 .numerator = 10000,
210 .denominator = 600000,
211 },
212 .hts_def = 858,
213 .vts_def = 525,
214 }, {
215 .width = 1440,
216 .height = 480,
217 .max_fps = {
218 .numerator = 10000,
219 .denominator = 600000,
220 },
221 .hts_def = 1716,
222 .vts_def = 525,
223 }, {
224 .width = 1440,
225 .height = 576,
226 .max_fps = {
227 .numerator = 10000,
228 .denominator = 500000,
229 },
230 .hts_def = 1728,
231 .vts_def = 625,
232 },
233 };
234
235 static void lt8619c_set_hpd(struct v4l2_subdev *sd, int en);
236 static void lt8619c_wait_for_signal_stable(struct v4l2_subdev *sd);
237 static void lt8619c_yuv_config(struct v4l2_subdev *sd);
238 static void lt8619c_format_change(struct v4l2_subdev *sd);
239 static void enable_stream(struct v4l2_subdev *sd, bool enable);
240 static int lt8619c_s_dv_timings(struct v4l2_subdev *sd,
241 struct v4l2_dv_timings *timings);
242 static void LVDSPLL_Lock_Det(struct v4l2_subdev *sd);
243 static void LT8619C_phase_config(struct v4l2_subdev *sd);
244 static bool lt8619c_rcv_supported_res(struct v4l2_subdev *sd,
245 struct v4l2_dv_timings *timings);
246 static bool lt8619c_timing_changed(struct v4l2_subdev *sd,
247 struct v4l2_dv_timings *timings);
248
to_lt8619c(struct v4l2_subdev * sd)249 static inline struct lt8619c *to_lt8619c(struct v4l2_subdev *sd)
250 {
251 return container_of(sd, struct lt8619c, sd);
252 }
253
tx_5v_power_present(struct v4l2_subdev * sd)254 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
255 {
256 int val;
257 struct lt8619c *lt8619c = to_lt8619c(sd);
258
259 val = gpiod_get_value(lt8619c->plugin_det_gpio);
260 v4l2_dbg(1, debug, sd, "%s 5v_present: %d!\n", __func__, val);
261 return (val > 0);
262 }
263
no_signal(struct v4l2_subdev * sd)264 static inline bool no_signal(struct v4l2_subdev *sd)
265 {
266 struct lt8619c *lt8619c = to_lt8619c(sd);
267
268 v4l2_dbg(1, debug, sd, "no signal:%d\n", lt8619c->nosignal);
269 return lt8619c->nosignal;
270 }
271
lt8619c_is_supported_interlaced_res(struct v4l2_subdev * sd,u32 hact,u32 vact)272 static bool lt8619c_is_supported_interlaced_res(struct v4l2_subdev *sd,
273 u32 hact, u32 vact)
274 {
275 if ((hact == 1920 && vact == 540) ||
276 (hact == 1440 && vact == 288) ||
277 (hact == 1440 && vact == 240))
278 return true;
279
280 return false;
281 }
282
lt8619c_get_detected_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)283 static int lt8619c_get_detected_timings(struct v4l2_subdev *sd,
284 struct v4l2_dv_timings *timings)
285 {
286 struct lt8619c *lt8619c = to_lt8619c(sd);
287 struct v4l2_bt_timings *bt = &timings->bt;
288 u32 hact, vact, htotal, vtotal, hbp, hfp, hs;
289 u32 fps, hdmi_clk_cnt;
290 u32 val, vbp, vfp, vs;
291 u32 pix_clk;
292
293 memset(timings, 0, sizeof(struct v4l2_dv_timings));
294 timings->type = V4L2_DV_BT_656_1120;
295
296 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
297 regmap_read(lt8619c->reg_map, 0x22, &val);
298 hact = val << 8;
299 regmap_read(lt8619c->reg_map, 0x23, &val);
300 hact |= val;
301
302 regmap_read(lt8619c->reg_map, 0x20, &val);
303 vact = (val & 0xf) << 8;
304 regmap_read(lt8619c->reg_map, 0x21, &val);
305 vact |= val;
306
307 regmap_read(lt8619c->reg_map, 0x1e, &val);
308 htotal = val << 8;
309 regmap_read(lt8619c->reg_map, 0x1f, &val);
310 htotal |= val;
311
312 regmap_read(lt8619c->reg_map, 0x1c, &val);
313 vtotal = (val & 0xf) << 8;
314 regmap_read(lt8619c->reg_map, 0x1d, &val);
315 vtotal |= val;
316
317 regmap_read(lt8619c->reg_map, 0x1a, &val);
318 hfp = val << 8;
319 regmap_read(lt8619c->reg_map, 0x1b, &val);
320 hfp |= val;
321
322 regmap_read(lt8619c->reg_map, 0x18, &val);
323 hbp = val << 8;
324 regmap_read(lt8619c->reg_map, 0x19, &val);
325 hbp |= val;
326
327 regmap_read(lt8619c->reg_map, 0x14, &val);
328 hs = val << 8;
329 regmap_read(lt8619c->reg_map, 0x15, &val);
330 hs |= val;
331
332 regmap_read(lt8619c->reg_map, 0x17, &vfp);
333 regmap_read(lt8619c->reg_map, 0x16, &vbp);
334 regmap_read(lt8619c->reg_map, 0x13, &vs);
335
336 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
337 regmap_read(lt8619c->reg_map, 0x44, &val);
338 hdmi_clk_cnt = (val & 0x3) << 16;
339 regmap_read(lt8619c->reg_map, 0x45, &val);
340 hdmi_clk_cnt |= val << 8;
341 regmap_read(lt8619c->reg_map, 0x46, &val);
342 hdmi_clk_cnt |= val;
343
344 bt->width = hact;
345 bt->height = vact;
346 bt->hfrontporch = hfp;
347 bt->hsync = hs;
348 bt->hbackporch = hbp;
349 bt->vfrontporch = vfp;
350 bt->vsync = vs;
351 bt->vbackporch = vbp;
352 pix_clk = hdmi_clk_cnt * 1000;
353 bt->pixelclock = pix_clk;
354
355 fps = 0;
356 if (htotal * vtotal)
357 fps = (pix_clk + (htotal * vtotal) / 2) / (htotal * vtotal);
358
359 /* for interlaced res 1080i 576i 480i */
360 if (lt8619c_is_supported_interlaced_res(sd, hact, vact)) {
361 bt->interlaced = V4L2_DV_INTERLACED;
362 bt->height *= 2;
363 bt->il_vsync = bt->vsync + 1;
364 } else {
365 bt->interlaced = V4L2_DV_PROGRESSIVE;
366 }
367
368 v4l2_dbg(1, debug, sd,
369 "%s: act:%dx%d, total:%dx%d, fps:%d, pixclk:%llu, frame mode:%s\n",
370 __func__, hact, vact, htotal, vtotal, fps, bt->pixelclock,
371 (bt->interlaced == V4L2_DV_INTERLACED) ? "I" : "P");
372 v4l2_dbg(1, debug, sd,
373 "%s: hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d\n",
374 __func__, bt->hfrontporch, bt->hsync, bt->hbackporch,
375 bt->vfrontporch, bt->vsync, bt->vbackporch);
376
377 return 0;
378 }
379
lt8619c_config_all(struct v4l2_subdev * sd)380 static void lt8619c_config_all(struct v4l2_subdev *sd)
381 {
382 lt8619c_wait_for_signal_stable(sd);
383 LVDSPLL_Lock_Det(sd);
384 lt8619c_yuv_config(sd);
385 LT8619C_phase_config(sd);
386 lt8619c_format_change(sd);
387 }
388
lt8619c_delayed_work_enable_hotplug(struct work_struct * work)389 static void lt8619c_delayed_work_enable_hotplug(struct work_struct *work)
390 {
391 struct delayed_work *dwork = to_delayed_work(work);
392 struct lt8619c *lt8619c = container_of(dwork, struct lt8619c,
393 delayed_work_enable_hotplug);
394 struct v4l2_subdev *sd = <8619c->sd;
395
396 v4l2_dbg(2, debug, sd, "%s: in\n", __func__);
397 mutex_lock(<8619c->confctl_mutex);
398 if (tx_5v_power_present(sd)) {
399 lt8619c_set_hpd(sd, 1);
400 lt8619c_config_all(sd);
401 lt8619c->nosignal = false;
402 /* monitor resolution after 100ms */
403 schedule_delayed_work(<8619c->delayed_work_monitor_resolution,
404 HZ / 10);
405 } else {
406 cancel_delayed_work(<8619c->delayed_work_monitor_resolution);
407 enable_stream(sd, false);
408 lt8619c_set_hpd(sd, 0);
409 lt8619c->nosignal = true;
410 }
411 mutex_unlock(<8619c->confctl_mutex);
412 }
413
lt8619c_delayed_work_monitor_resolution(struct work_struct * work)414 static void lt8619c_delayed_work_monitor_resolution(struct work_struct *work)
415 {
416 struct delayed_work *dwork = to_delayed_work(work);
417 struct lt8619c *lt8619c = container_of(dwork, struct lt8619c,
418 delayed_work_monitor_resolution);
419 struct v4l2_subdev *sd = <8619c->sd;
420 struct v4l2_dv_timings timings;
421 bool is_supported_res, is_timing_changed;
422
423 v4l2_dbg(1, debug, sd, "%s: in\n", __func__);
424 if (!tx_5v_power_present(sd)) {
425 v4l2_dbg(2, debug, sd, "%s: HDMI pull out, return!\n", __func__);
426 lt8619c->nosignal = true;
427 return;
428 }
429
430 mutex_lock(<8619c->confctl_mutex);
431 lt8619c_get_detected_timings(sd, &timings);
432 is_supported_res = lt8619c_rcv_supported_res(sd, &timings);
433 is_timing_changed = lt8619c_timing_changed(sd, &timings);
434 v4l2_dbg(2, debug, sd,
435 "%s: is_supported_res: %d, is_timing_changed: %d\n",
436 __func__, is_supported_res, is_timing_changed);
437
438 if (!is_supported_res) {
439 lt8619c->nosignal = true;
440 v4l2_dbg(1, debug, sd, "%s: no supported res, cfg as nosignal!\n",
441 __func__);
442 }
443
444 if (is_supported_res && is_timing_changed) {
445 lt8619c_config_all(sd);
446 lt8619c->nosignal = false;
447 }
448 mutex_unlock(<8619c->confctl_mutex);
449
450 schedule_delayed_work(<8619c->delayed_work_monitor_resolution, HZ);
451 }
452
lt8619c_load_hdcpkey(struct v4l2_subdev * sd)453 static void lt8619c_load_hdcpkey(struct v4l2_subdev *sd)
454 {
455 struct lt8619c *lt8619c = to_lt8619c(sd);
456 int wait_cnt = 5;
457 u32 val;
458
459 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
460 regmap_write(lt8619c->reg_map, 0xb2, 0x50);
461 regmap_write(lt8619c->reg_map, 0xa3, 0x77);
462 while (wait_cnt) {
463 usleep_range(50*1000, 50*1000);
464 regmap_read(lt8619c->reg_map, 0xc0, &val);
465 if (val & 0x8)
466 break;
467 wait_cnt--;
468 }
469
470 regmap_write(lt8619c->reg_map, 0xb2, 0xd0);
471 regmap_write(lt8619c->reg_map, 0xa3, 0x57);
472 if (val & 0x8)
473 v4l2_info(sd, "load hdcp key success!\n");
474 else
475 v4l2_err(sd, "load hdcp key failed!\n");
476 }
477
lt8619c_set_hdmi_hdcp(struct v4l2_subdev * sd,bool enable)478 static void lt8619c_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
479 {
480 v4l2_dbg(2, debug, sd, "%s: %sable\n", __func__, enable ? "en" : "dis");
481
482 if (enable)
483 lt8619c_load_hdcpkey(sd);
484 else
485 v4l2_info(sd, "disable hdcp function!\n");
486 }
487
lt8619c_mode_config(struct v4l2_subdev * sd)488 static void lt8619c_mode_config(struct v4l2_subdev *sd)
489 {
490 struct lt8619c *lt8619c = to_lt8619c(sd);
491
492 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
493 regmap_update_bits(lt8619c->reg_map, 0x2c, BIT(5) | BIT(4), BIT(5) | BIT(4));
494
495 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
496 regmap_write(lt8619c->reg_map, 0x80, CLK_SRC);
497 regmap_write(lt8619c->reg_map, 0x89, REF_RESISTANCE);
498 regmap_write(lt8619c->reg_map, 0x8b, 0x90);
499 /* Turn off BT output */
500 regmap_write(lt8619c->reg_map, 0xa8, 0x07);
501 /* enable PLL detect */
502 regmap_write(lt8619c->reg_map, 0x04, 0xf2);
503
504 if (lt8619c->BT656_double_clk_en) {
505 regmap_write(lt8619c->reg_map, 0x96, 0x71);
506 regmap_write(lt8619c->reg_map, 0xa0, 0x51);
507 regmap_write(lt8619c->reg_map, 0xa3, 0x44);
508 regmap_write(lt8619c->reg_map, 0xa2, 0x20);
509 } else {
510 regmap_write(lt8619c->reg_map, 0x96, 0x71);
511 regmap_write(lt8619c->reg_map, 0xa0, 0x50);
512 regmap_write(lt8619c->reg_map, 0xa3, 0x44);
513 regmap_write(lt8619c->reg_map, 0xa2, 0x20);
514 }
515 regmap_update_bits(lt8619c->reg_map, 0x60, OUTPUT_MODE_MASK,
516 lt8619c->yuv_output_mode);
517
518 if (lt8619c->clk_ddrmode_en == 1)
519 regmap_write(lt8619c->reg_map, 0xa4, 0x14);
520 else
521 regmap_write(lt8619c->reg_map, 0xa4, 0x10);
522
523 /* Vblank change reference EAV flag. */
524 regmap_write(lt8619c->reg_map, 0x6f, 0x04);
525
526 v4l2_dbg(1, debug, sd, "%s: output mode:%s, clk ddrmode en:%d\n",
527 __func__, (lt8619c->yuv_output_mode == BT656_OUTPUT) ? "BT656" :
528 "BT1120", lt8619c->clk_ddrmode_en);
529 }
530
lt8619c_set_hpd(struct v4l2_subdev * sd,int en)531 static void lt8619c_set_hpd(struct v4l2_subdev *sd, int en)
532 {
533 struct lt8619c *lt8619c = to_lt8619c(sd);
534 int level;
535
536 v4l2_dbg(2, debug, sd, "%s: %d\n", __func__, en);
537
538 level = lt8619c->hpd_output_inverted ? !en : en;
539 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
540 if (level)
541 regmap_update_bits(lt8619c->reg_map, 0x06, BIT(3), BIT(3));
542 else
543 regmap_update_bits(lt8619c->reg_map, 0x06, BIT(3), 0);
544 }
545
lt8619c_write_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)546 static void lt8619c_write_edid(struct v4l2_subdev *sd,
547 struct v4l2_subdev_edid *edid)
548 {
549 int i;
550 struct lt8619c *lt8619c = to_lt8619c(sd);
551 u32 edid_len = edid->blocks * EDID_BLOCK_SIZE;
552
553 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
554 /* Enable EDID shadow operation */
555 regmap_write(lt8619c->reg_map, 0x8e, 0x07);
556 /* EDID data write start address */
557 regmap_write(lt8619c->reg_map, 0x8f, 0x00);
558
559 for (i = 0; i < edid_len; i++)
560 regmap_write(lt8619c->reg_map, 0x90, edid->edid[i]);
561
562 regmap_write(lt8619c->reg_map, 0x8e, 0x02);
563 }
564
lt8619c_read_edid(struct v4l2_subdev * sd,u8 * edid,u32 len)565 static void lt8619c_read_edid(struct v4l2_subdev *sd, u8 *edid, u32 len)
566 {
567 struct lt8619c *lt8619c = to_lt8619c(sd);
568 int i;
569 u32 val;
570
571 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
572 /* Enable EDID shadow operation */
573 regmap_write(lt8619c->reg_map, 0x8e, 0x07);
574 /* EDID data write start address */
575 regmap_write(lt8619c->reg_map, 0x8f, 0x00);
576 for (i = 0; i < len; i++) {
577 regmap_read(lt8619c->reg_map, 0x90, &val);
578 edid[i] = val;
579 }
580 regmap_write(lt8619c->reg_map, 0x8e, 0x02);
581 }
582
lt8619c_s_ctrl_detect_tx_5v(struct v4l2_subdev * sd)583 static int lt8619c_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
584 {
585 struct lt8619c *lt8619c = to_lt8619c(sd);
586
587 return v4l2_ctrl_s_ctrl(lt8619c->detect_tx_5v_ctrl,
588 tx_5v_power_present(sd));
589 }
590
lt8619c_update_controls(struct v4l2_subdev * sd)591 static int lt8619c_update_controls(struct v4l2_subdev *sd)
592 {
593 int ret = 0;
594
595 ret = lt8619c_s_ctrl_detect_tx_5v(sd);
596
597 return ret;
598 }
599
enable_stream(struct v4l2_subdev * sd,bool enable)600 static void enable_stream(struct v4l2_subdev *sd, bool enable)
601 {
602 if (enable)
603 v4l2_info(sd, "%s: stream on!\n", __func__);
604 else
605 v4l2_info(sd, "%s: stream off!\n", __func__);
606 }
607
lt8619c_set_bt_tx_timing(struct v4l2_subdev * sd)608 static void lt8619c_set_bt_tx_timing(struct v4l2_subdev *sd)
609 {
610 struct lt8619c *lt8619c = to_lt8619c(sd);
611 struct v4l2_dv_timings timings;
612 struct v4l2_bt_timings *bt = &timings.bt;
613 u32 h_offset, v_offset, v_blank, htotal, vtotal;
614 u32 hact, hfp, hbp, hs, vact, vfp, vbp, vs;
615 u32 double_cnt = 1;
616
617 /* read timing from HDMI RX */
618 lt8619c_get_detected_timings(sd, &timings);
619
620 hact = bt->width;
621 vact = bt->height;
622 hfp = bt->hfrontporch;
623 hs = bt->hsync;
624 hbp = bt->hbackporch;
625 vfp = bt->vfrontporch;
626 vs = bt->vsync;
627 vbp = bt->vbackporch;
628 htotal = hs + hbp + hact + hfp;
629 vtotal = vs + vbp + vact + vfp;
630 h_offset = hbp + hs;
631 v_offset = vbp + vs;
632 v_blank = vtotal - vact;
633
634 if (bt->interlaced == V4L2_DV_INTERLACED) {
635 /* already *2 in lt8619c_get_detected_timings */
636 vact /= 2;
637 double_cnt = 2;
638 regmap_update_bits(lt8619c->reg_map, 0x60, IP_SEL_MASK,
639 INTERLACE_INDICATOR);
640 }
641
642 vact = vact * double_cnt;
643 vtotal = vtotal * double_cnt;
644
645 v4l2_dbg(2, debug, sd,
646 "%s: act:%dx%d, total:%dx%d, h_offset:%d, v_offset:%d, v_blank:%d\n",
647 __func__, hact, vact, htotal, vtotal, h_offset, v_offset, v_blank);
648 v4l2_dbg(2, debug, sd,
649 "%s: hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d\n",
650 __func__, hfp, hs, hbp, vfp, vs, vbp);
651
652 /* write timing to BT TX */
653 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
654 regmap_write(lt8619c->reg_map, 0x61, (h_offset >> 8) & 0xff);
655 regmap_write(lt8619c->reg_map, 0x62, h_offset & 0xff);
656 regmap_write(lt8619c->reg_map, 0x63, (hact >> 8) & 0xff);
657 regmap_write(lt8619c->reg_map, 0x64, hact & 0xff);
658 regmap_write(lt8619c->reg_map, 0x65, (htotal >> 8) & 0xff);
659 regmap_write(lt8619c->reg_map, 0x66, htotal & 0xff);
660 regmap_write(lt8619c->reg_map, 0x67, v_offset & 0xff);
661 regmap_write(lt8619c->reg_map, 0x68, v_blank & 0xff);
662 regmap_write(lt8619c->reg_map, 0x69, (vact >> 8) & 0xff);
663 regmap_write(lt8619c->reg_map, 0x6a, vact & 0xff);
664 regmap_write(lt8619c->reg_map, 0x6b, (vtotal >> 8) & 0xff);
665 regmap_write(lt8619c->reg_map, 0x6c, vtotal & 0xff);
666 }
667
lt8619c_power_on(struct lt8619c * lt8619c)668 static void lt8619c_power_on(struct lt8619c *lt8619c)
669 {
670 if (lt8619c->power_gpio) {
671 gpiod_set_value(lt8619c->power_gpio, 1);
672 usleep_range(1000, 1100);
673 }
674
675 if (lt8619c->reset_gpio) {
676 gpiod_set_value(lt8619c->reset_gpio, 1);
677 usleep_range(100*1000, 110*1000);
678 gpiod_set_value(lt8619c->reset_gpio, 0);
679 usleep_range(50*1000, 50*1000);
680 }
681 }
682
lt8619c_wait_for_signal_stable(struct v4l2_subdev * sd)683 static void lt8619c_wait_for_signal_stable(struct v4l2_subdev *sd)
684 {
685 struct lt8619c *lt8619c = to_lt8619c(sd);
686 int i;
687 u32 val;
688
689 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
690 for (i = 0; i < WAIT_MAX_TIMES; i++) {
691 usleep_range(100*1000, 110*1000);
692 regmap_read(lt8619c->reg_map, 0x43, &val);
693 if (val & 0x80)
694 break;
695 }
696
697 if (val & 0x80)
698 v4l2_info(sd, "tmds clk det success, wait cnt:%d!\n", i);
699 else
700 v4l2_err(sd, "tmds clk det failed!\n");
701
702 for (i = 0; i < WAIT_MAX_TIMES; i++) {
703 usleep_range(100*1000, 110*1000);
704 regmap_read(lt8619c->reg_map, 0x13, &val);
705 if (val & 0x01)
706 break;
707 }
708
709 if (val & 0x01)
710 v4l2_info(sd, "Hsync stable, wait cnt:%d!\n", i);
711 else
712 v4l2_err(sd, "Hsync unstable!\n");
713
714 /* reset HDMI RX logic */
715 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
716 regmap_write(lt8619c->reg_map, 0x09, 0x7f);
717 usleep_range(10*1000, 11*1000);
718 regmap_write(lt8619c->reg_map, 0x09, 0xff);
719 usleep_range(100*1000, 110*1000);
720
721 /* reset video check logic */
722 regmap_write(lt8619c->reg_map, 0x0c, 0xfb);
723 usleep_range(10*1000, 11*1000);
724 regmap_write(lt8619c->reg_map, 0x0c, 0xff);
725 usleep_range(100*1000, 110*1000);
726 }
727
LVDSPLL_Lock_Det(struct v4l2_subdev * sd)728 static void LVDSPLL_Lock_Det(struct v4l2_subdev *sd)
729 {
730 int temp = 0;
731 u32 val;
732 struct lt8619c *lt8619c = to_lt8619c(sd);
733
734 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
735 regmap_write(lt8619c->reg_map, 0x0e, 0xfd);
736 usleep_range(5*1000, 5*1000);
737 regmap_write(lt8619c->reg_map, 0x0e, 0xff);
738 usleep_range(100*1000, 100*1000);
739
740 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
741 regmap_read(lt8619c->reg_map, 0x87, &val);
742 while ((val & 0x20) == 0x00) {
743 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
744 regmap_write(lt8619c->reg_map, 0x0e, 0xfd);
745 usleep_range(5*1000, 5*1000);
746 regmap_write(lt8619c->reg_map, 0x0e, 0xff);
747
748 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
749 regmap_read(lt8619c->reg_map, 0x87, &val);
750
751 temp++;
752 if (temp > 3) {
753 v4l2_err(sd, "lvds pll lock det failed!\n");
754 break;
755 }
756 }
757 }
758
LT8619C_phase_config(struct v4l2_subdev * sd)759 static void LT8619C_phase_config(struct v4l2_subdev *sd)
760 {
761 u32 i, val;
762 int start = -1;
763 int end = -1;
764 u32 bt_clk_lag = 0;
765 struct lt8619c *lt8619c = to_lt8619c(sd);
766
767 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
768 regmap_read(lt8619c->reg_map, 0x87, &val);
769 while ((val & 0x20) == 0x00) {
770 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
771 regmap_write(lt8619c->reg_map, 0x0e, 0xfd);
772 usleep_range(5*1000, 5*1000);
773 regmap_write(lt8619c->reg_map, 0x0e, 0xff);
774
775 regmap_write(lt8619c->reg_map, 0x0a, 0x3f);
776 usleep_range(5*1000, 5*1000);
777 regmap_write(lt8619c->reg_map, 0x0a, 0x7f);
778 usleep_range(100*1000, 100*1000);
779
780 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
781 regmap_read(lt8619c->reg_map, 0x87, &val);
782 }
783
784 for (i = 0; i < ARRAY_SIZE(phase_num); i++) {
785 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
786 regmap_write(lt8619c->reg_map, 0xa2, phase_num[i]);
787 usleep_range(50*1000, 50*1000);
788 regmap_read(lt8619c->reg_map, 0x91, &val);
789
790 if (val == 0x05) {
791 bt_clk_lag = 1;
792 break;
793 } else if (val == 0x01) {
794 if (start == -1)
795 start = i;
796
797 end = i;
798 }
799 }
800
801 v4l2_info(sd, "%s: BT_clk_lag:%d, start:%d, end:%d!\n", __func__,
802 bt_clk_lag, start, end);
803 if (bt_clk_lag) {
804 regmap_write(lt8619c->reg_map, 0xa2, phase_num[i]);
805 } else {
806 if ((start != -1) && (end != -1) && (end >= start))
807 regmap_write(lt8619c->reg_map, 0xa2,
808 phase_num[start + (end - start) / 2]);
809 else
810 regmap_write(lt8619c->reg_map, 0xa2,
811 phase_num[ARRAY_SIZE(phase_num) - 1]);
812 }
813
814 /* Turn on BT output */
815 regmap_write(lt8619c->reg_map, 0xa8, 0x0f);
816 }
817
sync_polarity_config(struct v4l2_subdev * sd)818 static void sync_polarity_config(struct v4l2_subdev *sd)
819 {
820 struct lt8619c *lt8619c = to_lt8619c(sd);
821 u32 val, adj;
822
823 if (lt8619c->bt_tx_sync_pol == BT_TX_SYNC_POSITIVE) {
824 v4l2_info(sd, "%s: cfg h_vsync pol: POSITIVE\n", __func__);
825 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
826 regmap_update_bits(lt8619c->reg_map, 0x60, SYNC_POL_MASK,
827 BT_TX_SYNC_POSITIVE);
828 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
829 regmap_read(lt8619c->reg_map, 0x17, &val);
830 regmap_read(lt8619c->reg_map, 0x05, &adj);
831 if ((val & RGOD_VID_VSPOL) != RGOD_VID_VSPOL) {
832 adj ^= RGD_VS_POL_ADJ_MASK;
833 regmap_update_bits(lt8619c->reg_map, 0x05,
834 RGD_VS_POL_ADJ_MASK, adj);
835 }
836
837 if ((val & RGOD_VID_HSPOL) != RGOD_VID_HSPOL) {
838 adj ^= RGD_HS_POL_ADJ_MASK;
839 regmap_update_bits(lt8619c->reg_map, 0x05,
840 RGD_HS_POL_ADJ_MASK, adj);
841 }
842 } else {
843 v4l2_info(sd, "%s: cfg h_vsync pol: NEGATIVE\n", __func__);
844 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
845 regmap_update_bits(lt8619c->reg_map, 0x60, SYNC_POL_MASK,
846 BT_TX_SYNC_NEGATIVE);
847 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
848 regmap_read(lt8619c->reg_map, 0x17, &val);
849 regmap_read(lt8619c->reg_map, 0x05, &adj);
850 if ((val & RGOD_VID_VSPOL) == RGOD_VID_VSPOL) {
851 adj ^= RGD_VS_POL_ADJ_MASK;
852 regmap_update_bits(lt8619c->reg_map, 0x05,
853 RGD_VS_POL_ADJ_MASK, adj);
854 }
855
856 if ((val & RGOD_VID_HSPOL) == RGOD_VID_HSPOL) {
857 adj ^= RGD_HS_POL_ADJ_MASK;
858 regmap_update_bits(lt8619c->reg_map, 0x05,
859 RGD_HS_POL_ADJ_MASK, adj);
860 }
861 }
862 }
863
lt8619c_yuv_config(struct v4l2_subdev * sd)864 static void lt8619c_yuv_config(struct v4l2_subdev *sd)
865 {
866 struct lt8619c *lt8619c = to_lt8619c(sd);
867 u32 val, colorspace;
868
869 sync_polarity_config(sd);
870
871 /* softrest BT TX module */
872 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
873 regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), 0);
874 usleep_range(10*1000, 10*1000);
875 regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), BIT(1) | BIT(0));
876
877 /* ColorSpace convert */
878 regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
879 regmap_read(lt8619c->reg_map, 0x71, &val);
880 colorspace = (val & 0x60) >> 5;
881 if (colorspace == 2) {
882 /* YCbCr444 convert YCbCr422 enable */
883 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
884 regmap_write(lt8619c->reg_map, 0x07, 0xf0);
885 regmap_write(lt8619c->reg_map, 0x52, 0x02 +
886 lt8619c->cp_convert_mode);
887 v4l2_info(sd, "%s: colorspace: yuv444\n", __func__);
888 } else if (colorspace == 1) {
889 /* yuv422 */
890 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
891 regmap_write(lt8619c->reg_map, 0x07, 0x80);
892 regmap_write(lt8619c->reg_map, 0x52, 0x00);
893 v4l2_info(sd, "%s: colorspace: yuv222\n", __func__);
894 } else {
895 /* RGB convert YCbCr422 enable */
896 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
897 regmap_write(lt8619c->reg_map, 0x07, 0xf0);
898 regmap_write(lt8619c->reg_map, 0x52, 0x0a +
899 lt8619c->cp_convert_mode);
900 v4l2_info(sd, "%s: colorspace: RGB\n", __func__);
901 }
902
903 lt8619c_set_bt_tx_timing(sd);
904 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
905 regmap_write(lt8619c->reg_map, 0x6d, lt8619c->yc_swap);
906 regmap_write(lt8619c->reg_map, 0x6e, lt8619c->yuv_colordepth);
907
908 /* LVDS PLL soft reset */
909 regmap_update_bits(lt8619c->reg_map, 0x0e, BIT(1), 0);
910 usleep_range(50*1000, 50*1000);
911 regmap_update_bits(lt8619c->reg_map, 0x0e, BIT(1), BIT(1));
912
913 /* BT TX controller and afifo soft reset */
914 regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), 0);
915 usleep_range(50*1000, 50*1000);
916 regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), BIT(1) | BIT(0));
917 }
918
lt8619c_initial_setup(struct v4l2_subdev * sd)919 static void lt8619c_initial_setup(struct v4l2_subdev *sd)
920 {
921 static struct v4l2_dv_timings default_timing =
922 V4L2_DV_BT_CEA_640X480P59_94;
923 struct lt8619c *lt8619c = to_lt8619c(sd);
924 struct v4l2_subdev_edid def_edid;
925
926 def_edid.pad = 0;
927 def_edid.start_block = 0;
928 def_edid.blocks = 2;
929 def_edid.edid = edid_init_data;
930 lt8619c->enable_hdcp = false;
931 lt8619c->cp_convert_mode = CP_CONVERT_MODE;
932 lt8619c->yuv_colordepth = YUV_COLORDEPTH;
933 lt8619c->bt_tx_sync_pol = BT_TX_SYNC_POL;
934
935 if (lt8619c->yuv_output_mode == BT656_OUTPUT) {
936 lt8619c->yc_swap = YC_SWAP_DIS;
937 lt8619c->BT656_double_clk_en = true;
938 } else {
939 lt8619c->yc_swap = YC_SWAP_EN;
940 lt8619c->BT656_double_clk_en = false;
941 }
942
943 lt8619c_set_hpd(sd, 0);
944 lt8619c_write_edid(sd, &def_edid);
945 lt8619c->edid_blocks_written = def_edid.blocks;
946 lt8619c_set_hdmi_hdcp(sd, lt8619c->enable_hdcp);
947 lt8619c_mode_config(sd);
948
949 if (tx_5v_power_present(sd)) {
950 lt8619c_set_hpd(sd, 1);
951 lt8619c_config_all(sd);
952 /* monitor resolution after 100ms */
953 schedule_delayed_work(<8619c->delayed_work_monitor_resolution,
954 HZ / 10);
955 } else {
956 lt8619c_s_dv_timings(sd, &default_timing);
957 }
958
959 v4l2_dbg(1, debug, sd, "%s: init ok\n", __func__);
960 }
961
lt8619c_format_change(struct v4l2_subdev * sd)962 static void lt8619c_format_change(struct v4l2_subdev *sd)
963 {
964 struct lt8619c *lt8619c = to_lt8619c(sd);
965 struct v4l2_dv_timings timings;
966 const struct v4l2_event lt8619c_ev_fmt = {
967 .type = V4L2_EVENT_SOURCE_CHANGE,
968 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
969 };
970
971 lt8619c_get_detected_timings(sd, &timings);
972 if (!v4l2_match_dv_timings(<8619c->timings, &timings, 0, false)) {
973 /* automatically set timing rather than set by userspace */
974 lt8619c_s_dv_timings(sd, &timings);
975 v4l2_print_dv_timings(sd->name,
976 "lt8619c_format_change: New format: ", &timings, false);
977
978 }
979
980 if (sd->devnode)
981 v4l2_subdev_notify_event(sd, <8619c_ev_fmt);
982 }
983
lt8619c_timing_changed(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)984 static bool lt8619c_timing_changed(struct v4l2_subdev *sd,
985 struct v4l2_dv_timings *timings)
986 {
987 struct lt8619c *lt8619c = to_lt8619c(sd);
988 struct v4l2_bt_timings *new_bt = &timings->bt;
989 struct v4l2_bt_timings *bt = <8619c->timings.bt;
990
991 if ((bt->width != new_bt->width) |
992 (bt->height != new_bt->height) |
993 (abs(bt->hfrontporch - new_bt->hfrontporch) > 1) |
994 (abs(bt->hsync - new_bt->hsync) > 1) |
995 (abs(bt->hbackporch - new_bt->hbackporch) > 1) |
996 (abs(bt->vfrontporch - new_bt->vfrontporch) > 1) |
997 (abs(bt->vsync - new_bt->vsync) > 1) |
998 (abs(bt->vbackporch - new_bt->vbackporch) > 1) |
999 (abs(bt->pixelclock - new_bt->pixelclock) > 5000)) {
1000 v4l2_info(sd, "%s: timing changed!\n", __func__);
1001 return true;
1002 }
1003
1004 return false;
1005 }
1006
lt8619c_rcv_supported_res(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1007 static bool lt8619c_rcv_supported_res(struct v4l2_subdev *sd,
1008 struct v4l2_dv_timings *timings)
1009 {
1010 u32 i;
1011 u32 hact, vact, htotal, vtotal;
1012 struct v4l2_bt_timings *bt = &timings->bt;
1013
1014 hact = bt->width;
1015 vact = bt->height;
1016 htotal = bt->hsync + bt->hbackporch + hact + bt->hfrontporch;
1017 vtotal = bt->vsync + bt->vbackporch + vact + bt->vfrontporch;
1018
1019 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1020 if ((supported_modes[i].width == hact) &&
1021 (supported_modes[i].height == vact)) {
1022 break;
1023 }
1024 }
1025
1026 if (i == ARRAY_SIZE(supported_modes)) {
1027 v4l2_err(sd, "%s do not support res act: %dx%d, total: %dx%d\n",
1028 __func__, hact, vact, htotal, vtotal);
1029 return false;
1030 }
1031
1032 if (bt->pixelclock < 25000000) {
1033 v4l2_err(sd, "%s pixclk: %llu, err!\n", __func__, bt->pixelclock);
1034 return false;
1035 }
1036
1037 return true;
1038 }
1039
lt8619c_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)1040 static int lt8619c_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1041 struct v4l2_event_subscription *sub)
1042 {
1043 switch (sub->type) {
1044 case V4L2_EVENT_SOURCE_CHANGE:
1045 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1046 case V4L2_EVENT_CTRL:
1047 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1048 default:
1049 return -EINVAL;
1050 }
1051 }
1052
lt8619c_g_input_status(struct v4l2_subdev * sd,u32 * status)1053 static int lt8619c_g_input_status(struct v4l2_subdev *sd, u32 *status)
1054 {
1055 *status = 0;
1056 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1057
1058 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1059
1060 return 0;
1061 }
1062
lt8619c_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1063 static int lt8619c_s_dv_timings(struct v4l2_subdev *sd,
1064 struct v4l2_dv_timings *timings)
1065 {
1066 struct lt8619c *lt8619c = to_lt8619c(sd);
1067
1068 if (!timings)
1069 return -EINVAL;
1070
1071 if (debug)
1072 v4l2_print_dv_timings(sd->name, "lt8619c_s_dv_timings: ",
1073 timings, false);
1074
1075 if (v4l2_match_dv_timings(<8619c->timings, timings, 0, false)) {
1076 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1077 return 0;
1078 }
1079
1080 if (!v4l2_valid_dv_timings(timings, <8619c_timings_cap, NULL, NULL)) {
1081 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1082 return -ERANGE;
1083 }
1084
1085 lt8619c->timings = *timings;
1086 enable_stream(sd, false);
1087
1088 return 0;
1089 }
1090
lt8619c_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1091 static int lt8619c_g_dv_timings(struct v4l2_subdev *sd,
1092 struct v4l2_dv_timings *timings)
1093 {
1094 struct lt8619c *lt8619c = to_lt8619c(sd);
1095
1096 *timings = lt8619c->timings;
1097
1098 return 0;
1099 }
1100
lt8619c_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1101 static int lt8619c_enum_dv_timings(struct v4l2_subdev *sd,
1102 struct v4l2_enum_dv_timings *timings)
1103 {
1104 if (timings->pad != 0)
1105 return -EINVAL;
1106
1107 return v4l2_enum_dv_timings_cap(timings, <8619c_timings_cap, NULL, NULL);
1108 }
1109
lt8619c_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1110 static int lt8619c_query_dv_timings(struct v4l2_subdev *sd,
1111 struct v4l2_dv_timings *timings)
1112 {
1113 int ret;
1114 struct lt8619c *lt8619c = to_lt8619c(sd);
1115
1116 mutex_lock(<8619c->confctl_mutex);
1117 ret = lt8619c_get_detected_timings(sd, timings);
1118 mutex_unlock(<8619c->confctl_mutex);
1119 if (ret)
1120 return ret;
1121
1122 if (debug)
1123 v4l2_print_dv_timings(sd->name, "lt8619c_query_dv_timings: ",
1124 timings, false);
1125
1126 if (!v4l2_valid_dv_timings(timings, <8619c_timings_cap, NULL, NULL)) {
1127 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1128 return -ERANGE;
1129 }
1130
1131 return 0;
1132 }
1133
lt8619c_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1134 static int lt8619c_dv_timings_cap(struct v4l2_subdev *sd,
1135 struct v4l2_dv_timings_cap *cap)
1136 {
1137 if (cap->pad != 0)
1138 return -EINVAL;
1139
1140 *cap = lt8619c_timings_cap;
1141
1142 return 0;
1143 }
1144
lt8619c_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)1145 static int lt8619c_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1146 struct v4l2_mbus_config *cfg)
1147 {
1148 struct lt8619c *lt8619c = to_lt8619c(sd);
1149
1150 cfg->type = V4L2_MBUS_BT656;
1151 if (lt8619c->clk_ddrmode_en) {
1152 cfg->flags = RKMODULE_CAMERA_BT656_CHANNELS |
1153 V4L2_MBUS_PCLK_SAMPLE_RISING |
1154 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1155 } else {
1156 cfg->flags = RKMODULE_CAMERA_BT656_CHANNELS |
1157 V4L2_MBUS_PCLK_SAMPLE_RISING;
1158 }
1159
1160 return 0;
1161 }
1162
lt8619c_s_stream(struct v4l2_subdev * sd,int enable)1163 static int lt8619c_s_stream(struct v4l2_subdev *sd, int enable)
1164 {
1165 enable_stream(sd, enable);
1166
1167 return 0;
1168 }
1169
lt8619c_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1170 static int lt8619c_enum_mbus_code(struct v4l2_subdev *sd,
1171 struct v4l2_subdev_pad_config *cfg,
1172 struct v4l2_subdev_mbus_code_enum *code)
1173 {
1174 switch (code->index) {
1175 case 0:
1176 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
1177 break;
1178
1179 default:
1180 return -EINVAL;
1181 }
1182 return 0;
1183 }
1184
lt8619c_get_ctrl(struct v4l2_ctrl * ctrl)1185 static int lt8619c_get_ctrl(struct v4l2_ctrl *ctrl)
1186 {
1187 int ret = -1;
1188 struct lt8619c *lt8619c = container_of(ctrl->handler, struct lt8619c, hdl);
1189 struct v4l2_subdev *sd = &(lt8619c->sd);
1190
1191 if (ctrl->id == V4L2_CID_DV_RX_POWER_PRESENT) {
1192 ret = tx_5v_power_present(sd);
1193 *ctrl->p_new.p_s32 = ret;
1194 }
1195
1196 return ret;
1197 }
1198
lt8619c_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1199 static int lt8619c_enum_frame_sizes(struct v4l2_subdev *sd,
1200 struct v4l2_subdev_pad_config *cfg,
1201 struct v4l2_subdev_frame_size_enum *fse)
1202 {
1203 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1204
1205 if (fse->index >= ARRAY_SIZE(supported_modes))
1206 return -EINVAL;
1207
1208 if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
1209 return -EINVAL;
1210
1211 fse->min_width = supported_modes[fse->index].width;
1212 fse->max_width = supported_modes[fse->index].width;
1213 fse->max_height = supported_modes[fse->index].height;
1214 fse->min_height = supported_modes[fse->index].height;
1215
1216 return 0;
1217 }
1218
lt8619c_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1219 static int lt8619c_enum_frame_interval(struct v4l2_subdev *sd,
1220 struct v4l2_subdev_pad_config *cfg,
1221 struct v4l2_subdev_frame_interval_enum *fie)
1222 {
1223 if (fie->index >= ARRAY_SIZE(supported_modes))
1224 return -EINVAL;
1225
1226 fie->code = MEDIA_BUS_FMT_UYVY8_2X8;
1227
1228 fie->width = supported_modes[fie->index].width;
1229 fie->height = supported_modes[fie->index].height;
1230 fie->interval = supported_modes[fie->index].max_fps;
1231 return 0;
1232 }
1233
lt8619c_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1234 static int lt8619c_get_fmt(struct v4l2_subdev *sd,
1235 struct v4l2_subdev_pad_config *cfg,
1236 struct v4l2_subdev_format *format)
1237 {
1238 struct lt8619c *lt8619c = to_lt8619c(sd);
1239 struct v4l2_bt_timings *bt = &(lt8619c->timings.bt);
1240
1241 mutex_lock(<8619c->confctl_mutex);
1242 format->format.code = lt8619c->mbus_fmt_code;
1243 format->format.width = lt8619c->timings.bt.width;
1244 format->format.height = lt8619c->timings.bt.height;
1245 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1246 if (bt->interlaced == V4L2_DV_INTERLACED)
1247 format->format.field = V4L2_FIELD_INTERLACED;
1248 else
1249 format->format.field = V4L2_FIELD_NONE;
1250 mutex_unlock(<8619c->confctl_mutex);
1251
1252 v4l2_dbg(2, debug, sd, "fmt code:%d, w:%d, h:%d, field:%s, cosp:%d\n",
1253 format->format.code,
1254 format->format.width,
1255 format->format.height,
1256 (format->format.field == V4L2_FIELD_INTERLACED) ?
1257 "I" : "P",
1258 format->format.colorspace);
1259
1260 return 0;
1261 }
1262
lt8619c_get_reso_dist(const struct lt8619c_mode * mode,struct v4l2_mbus_framefmt * framefmt)1263 static int lt8619c_get_reso_dist(const struct lt8619c_mode *mode,
1264 struct v4l2_mbus_framefmt *framefmt)
1265 {
1266 return abs(mode->width - framefmt->width) +
1267 abs(mode->height - framefmt->height);
1268 }
1269
1270 static const struct lt8619c_mode *
lt8619c_find_best_fit(struct v4l2_subdev_format * fmt)1271 lt8619c_find_best_fit(struct v4l2_subdev_format *fmt)
1272 {
1273 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1274 int dist;
1275 int cur_best_fit = 0;
1276 int cur_best_fit_dist = -1;
1277 unsigned int i;
1278
1279 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1280 dist = lt8619c_get_reso_dist(&supported_modes[i], framefmt);
1281 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1282 cur_best_fit_dist = dist;
1283 cur_best_fit = i;
1284 }
1285 }
1286
1287 return &supported_modes[cur_best_fit];
1288 }
1289
lt8619c_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1290 static int lt8619c_set_fmt(struct v4l2_subdev *sd,
1291 struct v4l2_subdev_pad_config *cfg,
1292 struct v4l2_subdev_format *format)
1293 {
1294 struct lt8619c *lt8619c = to_lt8619c(sd);
1295 const struct lt8619c_mode *mode;
1296
1297 /* is overwritten by get_fmt */
1298 u32 code = format->format.code;
1299 int ret = lt8619c_get_fmt(sd, cfg, format);
1300
1301 format->format.code = code;
1302
1303 if (ret)
1304 return ret;
1305
1306 switch (code) {
1307 case MEDIA_BUS_FMT_UYVY8_2X8:
1308 break;
1309 default:
1310 return -EINVAL;
1311 }
1312
1313 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1314 return 0;
1315
1316 lt8619c->mbus_fmt_code = format->format.code;
1317 mode = lt8619c_find_best_fit(format);
1318 lt8619c->cur_mode = mode;
1319
1320 enable_stream(sd, false);
1321
1322 return 0;
1323 }
1324
lt8619c_g_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)1325 static int lt8619c_g_edid(struct v4l2_subdev *sd,
1326 struct v4l2_subdev_edid *edid)
1327 {
1328 struct lt8619c *lt8619c = to_lt8619c(sd);
1329
1330 memset(edid->reserved, 0, sizeof(edid->reserved));
1331
1332 if (edid->pad != 0)
1333 return -EINVAL;
1334
1335 if (edid->start_block == 0 && edid->blocks == 0) {
1336 edid->blocks = lt8619c->edid_blocks_written;
1337 return 0;
1338 }
1339
1340 if (lt8619c->edid_blocks_written == 0)
1341 return -ENODATA;
1342
1343 if (edid->start_block >= lt8619c->edid_blocks_written ||
1344 edid->blocks == 0)
1345 return -EINVAL;
1346
1347 if (edid->start_block + edid->blocks > lt8619c->edid_blocks_written)
1348 edid->blocks = lt8619c->edid_blocks_written - edid->start_block;
1349
1350 lt8619c_read_edid(sd, edid->edid, edid->blocks * EDID_BLOCK_SIZE);
1351
1352 return 0;
1353 }
1354
lt8619c_s_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)1355 static int lt8619c_s_edid(struct v4l2_subdev *sd,
1356 struct v4l2_subdev_edid *edid)
1357 {
1358 struct lt8619c *lt8619c = to_lt8619c(sd);
1359
1360 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1361 __func__, edid->pad, edid->start_block, edid->blocks);
1362
1363 memset(edid->reserved, 0, sizeof(edid->reserved));
1364
1365 if (edid->pad != 0)
1366 return -EINVAL;
1367
1368 if (edid->start_block != 0)
1369 return -EINVAL;
1370
1371 if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1372 edid->blocks = EDID_NUM_BLOCKS_MAX;
1373 return -E2BIG;
1374 }
1375
1376 lt8619c_set_hpd(sd, 0);
1377
1378 if (edid->blocks == 0) {
1379 lt8619c->edid_blocks_written = 0;
1380 return 0;
1381 }
1382
1383 lt8619c_write_edid(sd, edid);
1384 lt8619c->edid_blocks_written = edid->blocks;
1385
1386 if (tx_5v_power_present(sd))
1387 lt8619c_set_hpd(sd, 1);
1388
1389 return 0;
1390 }
1391
lt8619c_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1392 static int lt8619c_g_frame_interval(struct v4l2_subdev *sd,
1393 struct v4l2_subdev_frame_interval *fi)
1394 {
1395 struct lt8619c *lt8619c = to_lt8619c(sd);
1396 const struct lt8619c_mode *mode = lt8619c->cur_mode;
1397
1398 mutex_lock(<8619c->confctl_mutex);
1399 fi->interval = mode->max_fps;
1400 mutex_unlock(<8619c->confctl_mutex);
1401
1402 return 0;
1403 }
1404
lt8619c_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)1405 static int lt8619c_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
1406 {
1407 struct lt8619c *lt8619c = to_lt8619c(sd);
1408
1409 if (lt8619c->yuv_output_mode == BT656_OUTPUT)
1410 *std = V4L2_STD_PAL;
1411 else
1412 *std = V4L2_STD_ATSC;
1413
1414 return 0;
1415 }
1416
lt8619c_get_module_inf(struct lt8619c * lt8619c,struct rkmodule_inf * inf)1417 static void lt8619c_get_module_inf(struct lt8619c *lt8619c,
1418 struct rkmodule_inf *inf)
1419 {
1420 memset(inf, 0, sizeof(*inf));
1421 strscpy(inf->base.sensor, LT8619C_NAME, sizeof(inf->base.sensor));
1422 strscpy(inf->base.module, lt8619c->module_name,
1423 sizeof(inf->base.module));
1424 strscpy(inf->base.lens, lt8619c->len_name, sizeof(inf->base.lens));
1425 }
1426
1427 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
lt8619c_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1428 static int lt8619c_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1429 {
1430 struct lt8619c *lt8619c = to_lt8619c(sd);
1431 struct v4l2_bt_timings *bt = &(lt8619c->timings.bt);
1432 struct v4l2_mbus_framefmt *try_fmt =
1433 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1434 const struct lt8619c_mode *def_mode = &supported_modes[0];
1435
1436 mutex_lock(<8619c->confctl_mutex);
1437 try_fmt->width = def_mode->width;
1438 try_fmt->height = def_mode->height;
1439 try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
1440 if (bt->interlaced == V4L2_DV_INTERLACED)
1441 try_fmt->field = V4L2_FIELD_INTERLACED;
1442 else
1443 try_fmt->field = V4L2_FIELD_NONE;
1444 mutex_unlock(<8619c->confctl_mutex);
1445
1446 return 0;
1447 }
1448 #endif
1449
lt8619c_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1450 static long lt8619c_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1451 {
1452 struct lt8619c *lt8619c = to_lt8619c(sd);
1453 long ret = 0;
1454
1455 switch (cmd) {
1456 case RKMODULE_GET_MODULE_INFO:
1457 lt8619c_get_module_inf(lt8619c, (struct rkmodule_inf *)arg);
1458 break;
1459 default:
1460 ret = -ENOIOCTLCMD;
1461 break;
1462 }
1463
1464 return ret;
1465 }
1466
1467 #ifdef CONFIG_COMPAT
lt8619c_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1468 static long lt8619c_compat_ioctl32(struct v4l2_subdev *sd,
1469 unsigned int cmd, unsigned long arg)
1470 {
1471 void __user *up = compat_ptr(arg);
1472 struct rkmodule_inf *inf;
1473 long ret;
1474
1475 switch (cmd) {
1476 case RKMODULE_GET_MODULE_INFO:
1477 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1478 if (!inf) {
1479 ret = -ENOMEM;
1480 return ret;
1481 }
1482
1483 ret = lt8619c_ioctl(sd, cmd, inf);
1484 if (!ret) {
1485 ret = copy_to_user(up, inf, sizeof(*inf));
1486 if (ret)
1487 ret = -EFAULT;
1488 }
1489 kfree(inf);
1490 break;
1491
1492 default:
1493 ret = -ENOIOCTLCMD;
1494 break;
1495 }
1496
1497 return ret;
1498 }
1499 #endif
1500
1501 static const struct v4l2_ctrl_ops lt8619c_ctrl_ops = {
1502 .g_volatile_ctrl = lt8619c_get_ctrl,
1503 };
1504
1505 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1506 static const struct v4l2_subdev_internal_ops lt8619c_subdev_internal_ops = {
1507 .open = lt8619c_open,
1508 };
1509 #endif
1510
1511 static const struct v4l2_subdev_core_ops lt8619c_core_ops = {
1512 .subscribe_event = lt8619c_subscribe_event,
1513 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1514 .ioctl = lt8619c_ioctl,
1515 #ifdef CONFIG_COMPAT
1516 .compat_ioctl32 = lt8619c_compat_ioctl32,
1517 #endif
1518 };
1519
1520 static const struct v4l2_subdev_video_ops lt8619c_video_ops = {
1521 .g_input_status = lt8619c_g_input_status,
1522 .s_dv_timings = lt8619c_s_dv_timings,
1523 .g_dv_timings = lt8619c_g_dv_timings,
1524 .query_dv_timings = lt8619c_query_dv_timings,
1525 .s_stream = lt8619c_s_stream,
1526 .g_frame_interval = lt8619c_g_frame_interval,
1527 .querystd = lt8619c_querystd,
1528 };
1529
1530 static const struct v4l2_subdev_pad_ops lt8619c_pad_ops = {
1531 .enum_mbus_code = lt8619c_enum_mbus_code,
1532 .enum_frame_size = lt8619c_enum_frame_sizes,
1533 .enum_frame_interval = lt8619c_enum_frame_interval,
1534 .set_fmt = lt8619c_set_fmt,
1535 .get_fmt = lt8619c_get_fmt,
1536 .get_edid = lt8619c_g_edid,
1537 .set_edid = lt8619c_s_edid,
1538 .enum_dv_timings = lt8619c_enum_dv_timings,
1539 .dv_timings_cap = lt8619c_dv_timings_cap,
1540 .get_mbus_config = lt8619c_g_mbus_config,
1541 };
1542
1543 static const struct v4l2_subdev_ops lt8619c_ops = {
1544 .core = <8619c_core_ops,
1545 .video = <8619c_video_ops,
1546 .pad = <8619c_pad_ops,
1547 };
1548
plugin_detect_irq(int irq,void * dev_id)1549 static irqreturn_t plugin_detect_irq(int irq, void *dev_id)
1550 {
1551 struct lt8619c *lt8619c = dev_id;
1552 struct v4l2_subdev *sd = <8619c->sd;
1553
1554 /* enable hpd after 100ms */
1555 schedule_delayed_work(<8619c->delayed_work_enable_hotplug, HZ / 10);
1556 v4l2_dbg(2, debug, sd, "%s: plug change!\n", __func__);
1557 tx_5v_power_present(sd);
1558
1559 return IRQ_HANDLED;
1560 }
1561
lt8619c_parse_of(struct lt8619c * lt8619c)1562 static int lt8619c_parse_of(struct lt8619c *lt8619c)
1563 {
1564 struct device *dev = <8619c->i2c_client->dev;
1565 struct device_node *node = dev->of_node;
1566 int err;
1567
1568 lt8619c->hpd_output_inverted = of_property_read_bool(node,
1569 "hpd-output-inverted");
1570 err = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1571 <8619c->module_index);
1572 err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1573 <8619c->module_facing);
1574 err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1575 <8619c->module_name);
1576 err |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1577 <8619c->len_name);
1578 if (err) {
1579 dev_err(dev, "could not get module information!\n");
1580 return -EINVAL;
1581 }
1582
1583 lt8619c->xvclk = devm_clk_get(dev, "xvclk");
1584 if (IS_ERR(lt8619c->xvclk)) {
1585 dev_err(dev, "Failed to get xvclk\n");
1586 return -EINVAL;
1587 }
1588
1589 err = clk_prepare_enable(lt8619c->xvclk);
1590 if (err) {
1591 dev_err(dev, "Failed! to enable xvclk\n");
1592 return err;
1593 }
1594
1595 lt8619c->power_gpio = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_LOW);
1596 if (IS_ERR(lt8619c->power_gpio)) {
1597 dev_err(dev, "failed to get power gpio\n");
1598 err = PTR_ERR(lt8619c->power_gpio);
1599 goto disable_clk;
1600 }
1601 lt8619c->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1602 if (IS_ERR(lt8619c->reset_gpio)) {
1603 dev_err(dev, "failed to get reset gpio\n");
1604 err = PTR_ERR(lt8619c->reset_gpio);
1605 goto disable_clk;
1606 }
1607
1608 lt8619c->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det",
1609 GPIOD_IN);
1610 if (IS_ERR(lt8619c->plugin_det_gpio)) {
1611 dev_err(dev, "failed to get plugin_det gpio\n");
1612 err = PTR_ERR(lt8619c->plugin_det_gpio);
1613 goto disable_clk;
1614 }
1615
1616 if (of_property_read_u32(node, RK_CAMERA_MODULE_DUAL_EDGE,
1617 <8619c->clk_ddrmode_en)) {
1618 lt8619c->clk_ddrmode_en = LT8619C_DEFAULT_DUAL_EDGE;
1619 dev_warn(dev, "can not get module %s from dts, use default(%d)!\n",
1620 RK_CAMERA_MODULE_DUAL_EDGE, LT8619C_DEFAULT_DUAL_EDGE);
1621 } else {
1622 dev_info(dev, "get module %s from dts, dual_edge(%d)!\n",
1623 RK_CAMERA_MODULE_DUAL_EDGE, lt8619c->clk_ddrmode_en);
1624 }
1625
1626 if (of_property_read_u32(node, RK_CAMERA_MODULE_DVP_MODE,
1627 <8619c->yuv_output_mode)) {
1628 lt8619c->yuv_output_mode = LT8619C_DEFAULT_DVP_MODE;
1629 dev_warn(dev, "can not get module %s from dts, use default(BT1120)!\n",
1630 RK_CAMERA_MODULE_DVP_MODE);
1631 } else {
1632 dev_info(dev, "get module %s from dts, dvp mode(%s)!\n",
1633 RK_CAMERA_MODULE_DVP_MODE,
1634 (lt8619c->yuv_output_mode == BT656_OUTPUT) ? "BT656" : "BT1120");
1635 }
1636
1637 return 0;
1638
1639 disable_clk:
1640 clk_disable_unprepare(lt8619c->xvclk);
1641 return err;
1642 }
1643
lt8619c_init_v4l2_ctrls(struct lt8619c * lt8619c)1644 static int lt8619c_init_v4l2_ctrls(struct lt8619c *lt8619c)
1645 {
1646 struct v4l2_subdev *sd;
1647 int ret;
1648
1649 sd = <8619c->sd;
1650 ret = v4l2_ctrl_handler_init(<8619c->hdl, 2);
1651 if (ret)
1652 return ret;
1653
1654 v4l2_ctrl_new_std(<8619c->hdl, NULL, V4L2_CID_PIXEL_RATE,
1655 0, lt8619c_PIXEL_RATE, 1, lt8619c_PIXEL_RATE);
1656 lt8619c->detect_tx_5v_ctrl = v4l2_ctrl_new_std(<8619c->hdl,
1657 <8619c_ctrl_ops, V4L2_CID_DV_RX_POWER_PRESENT,
1658 0, 1, 0, 0);
1659 if (lt8619c->detect_tx_5v_ctrl)
1660 lt8619c->detect_tx_5v_ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
1661
1662 if (lt8619c->hdl.error) {
1663 ret = lt8619c->hdl.error;
1664 v4l2_err(sd, "cfg v4l2 ctrls failed! ret:%d\n", ret);
1665 return ret;
1666 }
1667 sd->ctrl_handler = <8619c->hdl;
1668
1669 if (lt8619c_update_controls(sd)) {
1670 ret = -ENODEV;
1671 v4l2_err(sd, "update v4l2 ctrls failed! ret:%d\n", ret);
1672 return ret;
1673 }
1674
1675 return 0;
1676 }
1677
lt8619c_check_chip_id(struct lt8619c * lt8619c)1678 static int lt8619c_check_chip_id(struct lt8619c *lt8619c)
1679 {
1680 struct device *dev = <8619c->i2c_client->dev;
1681 u32 id_h, id_m, id_l;
1682 int ret;
1683 u32 chipid;
1684
1685 regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
1686 ret = regmap_read(lt8619c->reg_map, CHIPID_REG_H, &id_h);
1687 ret |= regmap_read(lt8619c->reg_map, CHIPID_REG_M, &id_m);
1688 ret |= regmap_read(lt8619c->reg_map, CHIPID_REG_L, &id_l);
1689
1690 if (!ret) {
1691 chipid = (id_h << 16) | (id_m << 8) | id_l;
1692 if (chipid != LT8619C_CHIPID) {
1693 dev_err(dev,
1694 "check chipid failed, read id:%#x, we expect:%#x\n",
1695 chipid, LT8619C_CHIPID);
1696 ret = -1;
1697 }
1698 } else {
1699 dev_err(dev, "%s i2c trans failed!\n", __func__);
1700 ret = -1;
1701 }
1702
1703 return ret;
1704 }
1705
1706 static const struct regmap_range lt8619c_readable_ranges[] = {
1707 regmap_reg_range(0x00, 0xff),
1708 };
1709
1710 static const struct regmap_access_table lt8619c_readable_table = {
1711 .yes_ranges = lt8619c_readable_ranges,
1712 .n_yes_ranges = ARRAY_SIZE(lt8619c_readable_ranges),
1713 };
1714
1715 static const struct regmap_config lt8619c_hdmirx_regmap_cfg = {
1716 .name = "lt8619c",
1717 .reg_bits = 8,
1718 .val_bits = 8,
1719 .reg_stride = 1,
1720 .max_register = LT8619C_MAX_REGISTER,
1721 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
1722 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1723 .rd_table = <8619c_readable_table,
1724 };
1725
lt8619c_probe(struct i2c_client * client,const struct i2c_device_id * id)1726 static int lt8619c_probe(struct i2c_client *client,
1727 const struct i2c_device_id *id)
1728 {
1729 struct device *dev = &client->dev;
1730 struct lt8619c *lt8619c;
1731 struct v4l2_subdev *sd;
1732 char facing[2];
1733 int err;
1734
1735 dev_info(dev, "driver version: %02x.%02x.%02x",
1736 DRIVER_VERSION >> 16,
1737 (DRIVER_VERSION & 0xff00) >> 8,
1738 DRIVER_VERSION & 0x00ff);
1739
1740 lt8619c = devm_kzalloc(dev, sizeof(*lt8619c), GFP_KERNEL);
1741 if (!lt8619c)
1742 return -ENOMEM;
1743
1744 sd = <8619c->sd;
1745 lt8619c->i2c_client = client;
1746 lt8619c->cur_mode = &supported_modes[0];
1747 lt8619c->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
1748
1749 err = lt8619c_parse_of(lt8619c);
1750 if (err)
1751 return err;
1752
1753 mutex_init(<8619c->confctl_mutex);
1754 err = lt8619c_init_v4l2_ctrls(lt8619c);
1755 if (err)
1756 goto err_hdl;
1757
1758 client->flags |= I2C_CLIENT_SCCB;
1759 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1760 v4l2_i2c_subdev_init(sd, client, <8619c_ops);
1761 sd->internal_ops = <8619c_subdev_internal_ops;
1762 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1763 #endif
1764
1765 #if defined(CONFIG_MEDIA_CONTROLLER)
1766 lt8619c->pad.flags = MEDIA_PAD_FL_SOURCE;
1767 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1768 err = media_entity_pads_init(&sd->entity, 1, <8619c->pad);
1769 if (err < 0) {
1770 v4l2_err(sd, "media entity init failed! err:%d\n", err);
1771 goto err_hdl;
1772 }
1773 #endif
1774
1775 lt8619c->reg_map = devm_regmap_init_i2c(client, <8619c_hdmirx_regmap_cfg);
1776 lt8619c_power_on(lt8619c);
1777 err = lt8619c_check_chip_id(lt8619c);
1778 if (err < 0)
1779 goto err_hdl;
1780
1781 memset(facing, 0, sizeof(facing));
1782 if (strcmp(lt8619c->module_facing, "back") == 0)
1783 facing[0] = 'b';
1784 else
1785 facing[0] = 'f';
1786
1787 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1788 lt8619c->module_index, facing,
1789 LT8619C_NAME, dev_name(sd->dev));
1790 err = v4l2_async_register_subdev_sensor_common(sd);
1791 if (err < 0) {
1792 v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
1793 goto err_subdev;
1794 }
1795
1796 INIT_DELAYED_WORK(<8619c->delayed_work_enable_hotplug,
1797 lt8619c_delayed_work_enable_hotplug);
1798 INIT_DELAYED_WORK(<8619c->delayed_work_monitor_resolution,
1799 lt8619c_delayed_work_monitor_resolution);
1800 lt8619c_initial_setup(sd);
1801
1802 lt8619c->plugin_irq = gpiod_to_irq(lt8619c->plugin_det_gpio);
1803 if (lt8619c->plugin_irq < 0) {
1804 dev_err(dev, "failed to get plugin det irq\n");
1805 err = lt8619c->plugin_irq;
1806 goto err_work_queues;
1807 }
1808
1809 err = devm_request_threaded_irq(dev, lt8619c->plugin_irq, NULL,
1810 plugin_detect_irq, IRQF_TRIGGER_FALLING |
1811 IRQF_TRIGGER_RISING | IRQF_ONESHOT, "lt8619c", lt8619c);
1812 if (err) {
1813 dev_err(dev, "failed to register plugin det irq (%d)\n", err);
1814 goto err_work_queues;
1815 }
1816
1817 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1818 if (err) {
1819 v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
1820 goto err_work_queues;
1821 }
1822
1823 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1824 client->addr << 1, client->adapter->name);
1825
1826 return 0;
1827
1828 err_work_queues:
1829 cancel_delayed_work(<8619c->delayed_work_enable_hotplug);
1830 cancel_delayed_work(<8619c->delayed_work_monitor_resolution);
1831 err_subdev:
1832 #if defined(CONFIG_MEDIA_CONTROLLER)
1833 media_entity_cleanup(&sd->entity);
1834 #endif
1835 err_hdl:
1836 v4l2_ctrl_handler_free(<8619c->hdl);
1837 mutex_destroy(<8619c->confctl_mutex);
1838 clk_disable_unprepare(lt8619c->xvclk);
1839 return err;
1840 }
1841
lt8619c_remove(struct i2c_client * client)1842 static int lt8619c_remove(struct i2c_client *client)
1843 {
1844 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1845 struct lt8619c *lt8619c = to_lt8619c(sd);
1846
1847 cancel_delayed_work(<8619c->delayed_work_enable_hotplug);
1848 cancel_delayed_work(<8619c->delayed_work_monitor_resolution);
1849 v4l2_async_unregister_subdev(sd);
1850 v4l2_device_unregister_subdev(sd);
1851 #if defined(CONFIG_MEDIA_CONTROLLER)
1852 media_entity_cleanup(&sd->entity);
1853 #endif
1854 v4l2_ctrl_handler_free(<8619c->hdl);
1855 mutex_destroy(<8619c->confctl_mutex);
1856 clk_disable_unprepare(lt8619c->xvclk);
1857
1858 return 0;
1859 }
1860
1861 #if IS_ENABLED(CONFIG_OF)
1862 static const struct of_device_id lt8619c_of_match[] = {
1863 { .compatible = "lontium,lt8619c" },
1864 {},
1865 };
1866 MODULE_DEVICE_TABLE(of, lt8619c_of_match);
1867 #endif
1868
1869 static struct i2c_driver lt8619c_i2c_driver = {
1870 .driver = {
1871 .name = LT8619C_NAME,
1872 .of_match_table = of_match_ptr(lt8619c_of_match),
1873 },
1874 .probe = <8619c_probe,
1875 .remove = <8619c_remove,
1876 };
1877
lt8619c_driver_init(void)1878 static int __init lt8619c_driver_init(void)
1879 {
1880 return i2c_add_driver(<8619c_i2c_driver);
1881 }
1882
lt8619c_driver_exit(void)1883 static void __exit lt8619c_driver_exit(void)
1884 {
1885 i2c_del_driver(<8619c_i2c_driver);
1886 }
1887
1888 device_initcall_sync(lt8619c_driver_init);
1889 module_exit(lt8619c_driver_exit);
1890
1891 MODULE_DESCRIPTION("Lontium LT8619C HDMI to BT656/BT1120 bridge driver");
1892 MODULE_AUTHOR("Dingxian Wen <shawn.wen@rock-chips.com>");
1893 MODULE_LICENSE("GPL v2");
1894