1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * jx_k17 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 add enum_frame_interval function.
9 * V0.0X01.0X03 add quick stream on/off
10 * V0.0X01.0X04 add function g_mbus_config
11 */
12
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/rk-camera-module.h>
21 #include <linux/rk-preisp.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/sysfs.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/version.h>
29 #include <linux/pinctrl/consumer.h>
30
31 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
32
33 #ifndef V4L2_CID_DIGITAL_GAIN
34 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35 #endif
36
37 #define JX_K17_LANES 2
38 #define JX_K17_LINK_FREQ 198000000
39
40 #define JX_K17_PIXEL_RATE (JX_K17_LINK_FREQ * 2 * JX_K17_LANES / 10)
41
42 #define JX_K17_XVCLK_FREQ 24000000
43
44 #define CHIP_ID_H 0x0A
45 #define CHIP_ID_L 0x07
46 #define JX_K17_PIDH_ADDR 0x0a
47 #define JX_K17_PIDL_ADDR 0x0b
48
49 #define JX_K17_REG_CTRL_MODE 0x12
50 #define JX_K17_MODE_SW_STANDBY 0x40
51 #define JX_K17_MODE_STREAMING 0x00
52
53 #define JX_K17_AEC_PK_LONG_EXPO_HIGH_REG 0x02 /* Exposure Bits 8-15 */
54 #define JX_K17_AEC_PK_LONG_EXPO_LOW_REG 0x01 /* Exposure Bits 0-7 */
55 #define JX_K17_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
56 #define JX_K17_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
57 #define JX_K17_EXPOSURE_MIN 4
58 #define JX_K17_EXPOSURE_STEP 1
59 #define JX_K17_VTS_MAX 0xffff
60
61 #define JX_K17_AEC_PK_LONG_GAIN_REG 0x00 /* Bits 0 -7 */
62 #define ANALOG_GAIN_MIN 0x00
63 #define ANALOG_GAIN_MAX 0x3f
64 #define ANALOG_GAIN_STEP 1
65 #define ANALOG_GAIN_DEFAULT 0x1f
66
67 #define JX_K17_DIGI_GAIN_L_MASK 0x3f
68 #define JX_K17_DIGI_GAIN_H_SHIFT 6
69 #define JX_K17_DIGI_GAIN_MIN 0
70 #define JX_K17_DIGI_GAIN_MAX (0x4000 - 1)
71 #define JX_K17_DIGI_GAIN_STEP 1
72 #define JX_K17_DIGI_GAIN_DEFAULT 1024
73
74 #define JX_K17_REG_TEST_PATTERN 0x0c
75 #define JX_K17_TEST_PATTERN_ENABLE 0x01
76 #define JX_K17_TEST_PATTERN_DISABLE 0x0
77
78 #define JX_K17_REG_HIGH_VTS 0x23
79 #define JX_K17_REG_LOW_VTS 0X22
80 #define JX_K17_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
81 #define JX_K17_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
82
83 #define JX_K17_FLIP_MIRROR_REG 0x12
84
85 #define REG_NULL 0xFF
86 #define REG_DELAY 0xFE
87
88 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
89 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
90 #define JX_K17_NAME "jx_k17"
91
92 static const char * const jx_k17_supply_names[] = {
93 "avdd", /* Analog power */
94 "dovdd", /* Digital I/O power */
95 "dvdd", /* Digital core power */
96 };
97
98 #define JX_K17_NUM_SUPPLIES ARRAY_SIZE(jx_k17_supply_names)
99
100 struct regval {
101 u8 addr;
102 u8 val;
103 };
104
105 struct jx_k17_mode {
106 u32 bus_fmt;
107 u32 width;
108 u32 height;
109 struct v4l2_fract max_fps;
110 u32 hts_def;
111 u32 vts_def;
112 u32 exp_def;
113 const struct regval *reg_list;
114 u32 hdr_mode;
115 u32 vc[PAD_MAX];
116 };
117
118 struct jx_k17 {
119 struct i2c_client *client;
120 struct clk *xvclk;
121 struct gpio_desc *reset_gpio;
122 struct gpio_desc *pwdn_gpio;
123 struct regulator_bulk_data supplies[JX_K17_NUM_SUPPLIES];
124 struct pinctrl *pinctrl;
125 struct pinctrl_state *pins_default;
126 struct pinctrl_state *pins_sleep;
127 struct v4l2_subdev subdev;
128 struct media_pad pad;
129 struct v4l2_ctrl_handler ctrl_handler;
130 struct v4l2_ctrl *exposure;
131 struct v4l2_ctrl *anal_gain;
132 struct v4l2_ctrl *digi_gain;
133 struct v4l2_ctrl *hblank;
134 struct v4l2_ctrl *vblank;
135 struct v4l2_ctrl *test_pattern;
136 struct mutex mutex;
137 bool streaming;
138 bool power_on;
139 const struct jx_k17_mode *cur_mode;
140 u32 module_index;
141 const char *module_facing;
142 const char *module_name;
143 const char *len_name;
144 u32 cur_vts;
145 };
146
147 #define to_jx_k17(sd) container_of(sd, struct jx_k17, subdev)
148
149 /*
150 * Xclk 24Mhz
151 */
152 static const struct regval jx_k17_global_regs[] = {
153 {REG_NULL, 0x00},
154 };
155
156 /*
157 * Xclk 24Mhz
158 * lane 2
159 * linelength 880(0x370)
160 * framelength 1500(0x5dc)
161 * grabwindow_width 2560
162 * grabwindow_height 1440
163 * max_framerate 30fps
164 * mipi_datarate per lane 396Mbps
165 */
166
167 static const struct regval jx_k17_2560x1440_2lane_regs[] = {
168 {0x12, 0x40},
169 {0x48, 0x8A},
170 {0x48, 0x0A},
171 {0x0E, 0x11},
172 {0x0F, 0x04},
173 {0x10, 0x42},
174 {0x11, 0x80},
175 {0x0D, 0x50},
176 {0x57, 0xC0},
177 {0x58, 0x36},
178 {0x5F, 0x01},
179 {0x60, 0x19},
180 {0x61, 0x10},
181 {0x07, 0x08},
182 {0x20, 0x70},
183 {0x21, 0x03},
184 {0x22, 0xDC},
185 {0x23, 0x05},
186 {0x24, 0x80},
187 {0x25, 0xA0},
188 {0x26, 0x52},
189 {0x27, 0x6C},
190 {0x28, 0x15},
191 {0x29, 0x03},
192 {0x2A, 0x60},
193 {0x2B, 0x13},
194 {0x2C, 0x32},
195 {0x2D, 0x1D},
196 {0x2E, 0x8B},
197 {0x2F, 0x44},
198 {0x41, 0x84},
199 {0x42, 0x02},
200 {0x46, 0x18},
201 {0x47, 0x42},
202 {0x80, 0x03},
203 {0xAF, 0x22},
204 {0xBD, 0x00},
205 {0xBE, 0x0A},
206 {0x1D, 0x00},
207 {0x1E, 0x04},
208 {0x6C, 0x40},
209 {0x70, 0xD1},
210 {0x71, 0x8B},
211 {0x72, 0x6D},
212 {0x73, 0x49},
213 {0x75, 0x1B},
214 {0x74, 0x12},
215 {0x89, 0x10},
216 {0x0C, 0x20},
217 {0x6B, 0x10},
218 {0x86, 0x43},
219 {0x9E, 0x80},
220 {0x78, 0x14},
221 {0x30, 0x90},
222 {0x31, 0x18},
223 {0x32, 0x2A},
224 {0x33, 0xA8},
225 {0x34, 0x80},
226 {0x35, 0x70},
227 {0x3A, 0xA0},
228 {0x56, 0x12},
229 {0x59, 0xAC},
230 {0x85, 0x64},
231 {0x8A, 0x04},
232 {0x91, 0x22},
233 {0x9F, 0x0F},
234 {0xBB, 0x07},
235 {0x5B, 0xA4},
236 {0x5C, 0x82},
237 {0x5D, 0xE4},
238 {0x5E, 0x04},
239 {0x64, 0xE0},
240 {0x65, 0x07},
241 {0x66, 0x04},
242 {0x67, 0x61},
243 {0x68, 0x00},
244 {0x69, 0xF4},
245 {0x6A, 0x42},
246 {0x7A, 0x80},
247 {0x82, 0x20},
248 {0x8F, 0x90},
249 {0x9D, 0x70},
250 {0x97, 0xA2},
251 {0x13, 0x81},
252 {0x96, 0x04},
253 {0x4A, 0x05},
254 {0x7E, 0xC9},
255 {0xA7, 0x04},
256 {0x50, 0x02},
257 {0x49, 0x10},
258 {0x7B, 0x4A},
259 {0x7C, 0x0F},
260 {0x7F, 0x57},
261 {0x62, 0x21},
262 {0x90, 0x00},
263 {0x8C, 0xFF},
264 {0x8D, 0xC7},
265 {0x8E, 0x00},
266 {0x8B, 0x01},
267 {0xBF, 0x01},
268 {0x4E, 0x00},
269 {0xBF, 0x00},
270 {0xA3, 0x20},
271 {0xA0, 0x01},
272 {0xA2, 0x8D},
273 {0x81, 0x70},
274 {0x19, 0x20},
275 {REG_NULL, 0x00},
276 };
277
278 static const struct jx_k17_mode supported_modes[] = {
279 {
280 .width = 2560,
281 .height = 1440,
282 .max_fps = {
283 .numerator = 10000,
284 .denominator = 300000,
285 },
286 .exp_def = 0x001f,
287 .hts_def = 0x0370 * 4,
288 .vts_def = 0x05dc,
289 .reg_list = jx_k17_2560x1440_2lane_regs,
290 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
291 .hdr_mode = NO_HDR,
292 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
293 },
294 };
295
296 static const s64 link_freq_menu_items[] = {
297 JX_K17_LINK_FREQ
298 };
299
300 static const char * const jx_k17_test_pattern_menu[] = {
301 "Disabled",
302 "Vertical Color Bar Type 1",
303 "Vertical Color Bar Type 2",
304 "Vertical Color Bar Type 3",
305 "Vertical Color Bar Type 4"
306 };
307
308 /* Calculate the delay in us by clock rate and clock cycles */
jx_k17_cal_delay(u32 cycles)309 static inline u32 jx_k17_cal_delay(u32 cycles)
310 {
311 return DIV_ROUND_UP(cycles, JX_K17_XVCLK_FREQ / 1000 / 1000);
312 }
313
jx_k17_write_reg(struct i2c_client * client,u8 reg,u8 val)314 static int jx_k17_write_reg(struct i2c_client *client, u8 reg, u8 val)
315 {
316 struct i2c_msg msg;
317 u8 buf[2];
318 int ret;
319
320 buf[0] = reg & 0xFF;
321 buf[1] = val;
322
323 msg.addr = client->addr;
324 msg.flags = client->flags;
325 msg.buf = buf;
326 msg.len = sizeof(buf);
327
328 ret = i2c_transfer(client->adapter, &msg, 1);
329 if (ret >= 0)
330 return 0;
331
332 dev_err(&client->dev,
333 "jx_k17 write reg(0x%x val:0x%x) failed !\n", reg, val);
334
335 return ret;
336 }
337
jx_k17_write_array(struct i2c_client * client,const struct regval * regs)338 static int jx_k17_write_array(struct i2c_client *client,
339 const struct regval *regs)
340 {
341 u32 i, delay_us;
342 int ret = 0;
343
344 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
345 if (regs[i].addr == REG_DELAY) {
346 delay_us = jx_k17_cal_delay(500 * 1000);
347 usleep_range(delay_us, delay_us * 2);
348 } else {
349 ret = jx_k17_write_reg(client,
350 regs[i].addr, regs[i].val);
351 }
352 }
353
354 return ret;
355 }
356
jx_k17_read_reg(struct i2c_client * client,u8 reg,u8 * val)357 static int jx_k17_read_reg(struct i2c_client *client, u8 reg, u8 *val)
358 {
359 struct i2c_msg msg[2];
360 u8 buf[1];
361 int ret;
362
363 buf[0] = reg & 0xFF;
364
365 msg[0].addr = client->addr;
366 msg[0].flags = client->flags;
367 msg[0].buf = buf;
368 msg[0].len = sizeof(buf);
369
370 msg[1].addr = client->addr;
371 msg[1].flags = client->flags | I2C_M_RD;
372 msg[1].buf = buf;
373 msg[1].len = 1;
374
375 ret = i2c_transfer(client->adapter, msg, 2);
376 if (ret >= 0) {
377 *val = buf[0];
378 return 0;
379 }
380
381 dev_err(&client->dev,
382 "jx_k17 read reg:0x%x failed !\n", reg);
383
384 return ret;
385 }
386
jx_k17_get_reso_dist(const struct jx_k17_mode * mode,struct v4l2_mbus_framefmt * framefmt)387 static int jx_k17_get_reso_dist(const struct jx_k17_mode *mode,
388 struct v4l2_mbus_framefmt *framefmt)
389 {
390 return abs(mode->width - framefmt->width) +
391 abs(mode->height - framefmt->height);
392 }
393
394 static const struct jx_k17_mode *
jx_k17_find_best_fit(struct v4l2_subdev_format * fmt)395 jx_k17_find_best_fit(struct v4l2_subdev_format *fmt)
396 {
397 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
398 int dist;
399 int cur_best_fit = 0;
400 int cur_best_fit_dist = -1;
401 unsigned int i;
402
403 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
404 dist = jx_k17_get_reso_dist(&supported_modes[i], framefmt);
405 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
406 cur_best_fit_dist = dist;
407 cur_best_fit = i;
408 }
409 }
410
411 return &supported_modes[cur_best_fit];
412 }
413
jx_k17_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)414 static int jx_k17_set_fmt(struct v4l2_subdev *sd,
415 struct v4l2_subdev_pad_config *cfg,
416 struct v4l2_subdev_format *fmt)
417 {
418 struct jx_k17 *jx_k17 = to_jx_k17(sd);
419 const struct jx_k17_mode *mode;
420 s64 h_blank, vblank_def;
421
422 mutex_lock(&jx_k17->mutex);
423
424 mode = jx_k17_find_best_fit(fmt);
425 fmt->format.code = mode->bus_fmt;
426 fmt->format.width = mode->width;
427 fmt->format.height = mode->height;
428 fmt->format.field = V4L2_FIELD_NONE;
429 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
430 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
431 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
432 #else
433 mutex_unlock(&jx_k17->mutex);
434 return -ENOTTY;
435 #endif
436 } else {
437 jx_k17->cur_mode = mode;
438 h_blank = mode->hts_def - mode->width;
439 __v4l2_ctrl_modify_range(jx_k17->hblank, h_blank,
440 h_blank, 1, h_blank);
441 vblank_def = mode->vts_def - mode->height;
442 __v4l2_ctrl_modify_range(jx_k17->vblank, vblank_def,
443 JX_K17_VTS_MAX - mode->height,
444 1, vblank_def);
445 }
446
447 mutex_unlock(&jx_k17->mutex);
448
449 return 0;
450 }
451
jx_k17_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)452 static int jx_k17_get_fmt(struct v4l2_subdev *sd,
453 struct v4l2_subdev_pad_config *cfg,
454 struct v4l2_subdev_format *fmt)
455 {
456 struct jx_k17 *jx_k17 = to_jx_k17(sd);
457 const struct jx_k17_mode *mode = jx_k17->cur_mode;
458
459 mutex_lock(&jx_k17->mutex);
460 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
461 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
462 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
463 #else
464 mutex_unlock(&jx_k17->mutex);
465 return -ENOTTY;
466 #endif
467 } else {
468 fmt->format.width = mode->width;
469 fmt->format.height = mode->height;
470 fmt->format.code = mode->bus_fmt;
471 fmt->format.field = V4L2_FIELD_NONE;
472 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
473 fmt->reserved[0] = mode->vc[fmt->pad];
474 else
475 fmt->reserved[0] = mode->vc[PAD0];
476 }
477 mutex_unlock(&jx_k17->mutex);
478
479 return 0;
480 }
481
jx_k17_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)482 static int jx_k17_enum_mbus_code(struct v4l2_subdev *sd,
483 struct v4l2_subdev_pad_config *cfg,
484 struct v4l2_subdev_mbus_code_enum *code)
485 {
486 struct jx_k17 *jx_k17 = to_jx_k17(sd);
487
488 if (code->index != 0)
489 return -EINVAL;
490 code->code = jx_k17->cur_mode->bus_fmt;
491
492 return 0;
493 }
494
jx_k17_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)495 static int jx_k17_enum_frame_sizes(struct v4l2_subdev *sd,
496 struct v4l2_subdev_pad_config *cfg,
497 struct v4l2_subdev_frame_size_enum *fse)
498 {
499 if (fse->index >= ARRAY_SIZE(supported_modes))
500 return -EINVAL;
501
502 if (fse->code != supported_modes[0].bus_fmt)
503 return -EINVAL;
504
505 fse->min_width = supported_modes[fse->index].width;
506 fse->max_width = supported_modes[fse->index].width;
507 fse->max_height = supported_modes[fse->index].height;
508 fse->min_height = supported_modes[fse->index].height;
509
510 return 0;
511 }
512
jx_k17_enable_test_pattern(struct jx_k17 * jx_k17,u32 pattern)513 static int jx_k17_enable_test_pattern(struct jx_k17 *jx_k17, u32 pattern)
514 {
515 u8 val = 0;
516
517 jx_k17_read_reg(jx_k17->client, JX_K17_REG_TEST_PATTERN, &val);
518 if (pattern)
519 val |= (pattern - 1) | JX_K17_TEST_PATTERN_ENABLE;
520 else
521 val &= ~JX_K17_TEST_PATTERN_DISABLE;
522
523 return jx_k17_write_reg(jx_k17->client, JX_K17_REG_TEST_PATTERN, val);
524 }
525
jx_k17_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)526 static int jx_k17_g_frame_interval(struct v4l2_subdev *sd,
527 struct v4l2_subdev_frame_interval *fi)
528 {
529 struct jx_k17 *jx_k17 = to_jx_k17(sd);
530 const struct jx_k17_mode *mode = jx_k17->cur_mode;
531
532 mutex_lock(&jx_k17->mutex);
533 fi->interval = mode->max_fps;
534 mutex_unlock(&jx_k17->mutex);
535
536 return 0;
537 }
538
jx_k17_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)539 static int jx_k17_g_mbus_config(struct v4l2_subdev *sd,
540 unsigned int pad_id,
541 struct v4l2_mbus_config *config)
542 {
543 struct jx_k17 *jx_k17 = to_jx_k17(sd);
544 const struct jx_k17_mode *mode = jx_k17->cur_mode;
545 u32 val;
546
547 val = 1 << (JX_K17_LANES - 1) |
548 V4L2_MBUS_CSI2_CHANNEL_0 |
549 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
550
551 if (mode->hdr_mode != NO_HDR)
552 val |= V4L2_MBUS_CSI2_CHANNEL_1;
553 if (mode->hdr_mode == HDR_X3)
554 val |= V4L2_MBUS_CSI2_CHANNEL_2;
555
556 config->type = V4L2_MBUS_CSI2_DPHY;
557 config->flags = val;
558
559 return 0;
560 }
561
jx_k17_get_module_inf(struct jx_k17 * jx_k17,struct rkmodule_inf * inf)562 static void jx_k17_get_module_inf(struct jx_k17 *jx_k17,
563 struct rkmodule_inf *inf)
564 {
565 memset(inf, 0, sizeof(*inf));
566 strscpy(inf->base.sensor, JX_K17_NAME, sizeof(inf->base.sensor));
567 strscpy(inf->base.module, jx_k17->module_name,
568 sizeof(inf->base.module));
569 strscpy(inf->base.lens, jx_k17->len_name, sizeof(inf->base.lens));
570 }
571
jx_k17_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)572 static long jx_k17_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
573 {
574 struct jx_k17 *jx_k17 = to_jx_k17(sd);
575 struct rkmodule_hdr_cfg *hdr;
576 u32 i, h, w;
577 long ret = 0;
578 u32 stream = 0;
579
580 switch (cmd) {
581 case RKMODULE_GET_MODULE_INFO:
582 jx_k17_get_module_inf(jx_k17, (struct rkmodule_inf *)arg);
583 break;
584 case RKMODULE_GET_HDR_CFG:
585 hdr = (struct rkmodule_hdr_cfg *)arg;
586 hdr->esp.mode = HDR_NORMAL_VC;
587 hdr->hdr_mode = jx_k17->cur_mode->hdr_mode;
588 break;
589 case RKMODULE_SET_HDR_CFG:
590 hdr = (struct rkmodule_hdr_cfg *)arg;
591 w = jx_k17->cur_mode->width;
592 h = jx_k17->cur_mode->height;
593 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
594 if (w == supported_modes[i].width &&
595 h == supported_modes[i].height &&
596 supported_modes[i].hdr_mode == hdr->hdr_mode) {
597 jx_k17->cur_mode = &supported_modes[i];
598 break;
599 }
600 }
601 if (i == ARRAY_SIZE(supported_modes)) {
602 dev_err(&jx_k17->client->dev,
603 "not find hdr mode:%d %dx%d config\n",
604 hdr->hdr_mode, w, h);
605 ret = -EINVAL;
606 } else {
607 w = jx_k17->cur_mode->hts_def - jx_k17->cur_mode->width;
608 h = jx_k17->cur_mode->vts_def - jx_k17->cur_mode->height;
609 __v4l2_ctrl_modify_range(jx_k17->hblank, w, w, 1, w);
610 __v4l2_ctrl_modify_range(jx_k17->vblank, h,
611 JX_K17_VTS_MAX - jx_k17->cur_mode->height, 1, h);
612 }
613 break;
614 case PREISP_CMD_SET_HDRAE_EXP:
615 break;
616 case RKMODULE_SET_QUICK_STREAM:
617
618 stream = *((u32 *)arg);
619
620 if (stream)
621 ret = jx_k17_write_reg(jx_k17->client, JX_K17_REG_CTRL_MODE,
622 JX_K17_MODE_STREAMING);
623 else
624 ret = jx_k17_write_reg(jx_k17->client, JX_K17_REG_CTRL_MODE,
625 JX_K17_MODE_SW_STANDBY);
626 break;
627 default:
628 ret = -ENOIOCTLCMD;
629 break;
630 }
631
632 return ret;
633 }
634
635 #ifdef CONFIG_COMPAT
jx_k17_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)636 static long jx_k17_compat_ioctl32(struct v4l2_subdev *sd,
637 unsigned int cmd, unsigned long arg)
638 {
639 void __user *up = compat_ptr(arg);
640 struct rkmodule_inf *inf;
641 struct rkmodule_hdr_cfg *hdr;
642 struct preisp_hdrae_exp_s *hdrae;
643 long ret;
644 u32 stream = 0;
645
646 switch (cmd) {
647 case RKMODULE_GET_MODULE_INFO:
648 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
649 if (!inf) {
650 ret = -ENOMEM;
651 return ret;
652 }
653
654 ret = jx_k17_ioctl(sd, cmd, inf);
655 if (!ret) {
656 ret = copy_to_user(up, inf, sizeof(*inf));
657 if (ret)
658 ret = -EFAULT;
659 }
660 kfree(inf);
661 break;
662 case RKMODULE_GET_HDR_CFG:
663 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
664 if (!hdr) {
665 ret = -ENOMEM;
666 return ret;
667 }
668
669 ret = jx_k17_ioctl(sd, cmd, hdr);
670 if (!ret) {
671 ret = copy_to_user(up, hdr, sizeof(*hdr));
672 if (ret) {
673 kfree(hdr);
674 return -EFAULT;
675 }
676 }
677 kfree(hdr);
678 break;
679 case RKMODULE_SET_HDR_CFG:
680 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
681 if (!hdr) {
682 ret = -ENOMEM;
683 return ret;
684 }
685
686 ret = copy_from_user(hdr, up, sizeof(*hdr));
687 if (!ret)
688 ret = jx_k17_ioctl(sd, cmd, hdr);
689 else
690 ret = -EFAULT;
691 kfree(hdr);
692 break;
693 case PREISP_CMD_SET_HDRAE_EXP:
694 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
695 if (!hdrae) {
696 ret = -ENOMEM;
697 return ret;
698 }
699
700 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
701 if (!ret)
702 ret = jx_k17_ioctl(sd, cmd, hdrae);
703 else
704 ret = -EFAULT;
705 kfree(hdrae);
706 break;
707 case RKMODULE_SET_QUICK_STREAM:
708 ret = copy_from_user(&stream, up, sizeof(u32));
709 if (ret)
710 return -EFAULT;
711 ret = jx_k17_ioctl(sd, cmd, &stream);
712 break;
713 default:
714 ret = -ENOTTY;
715 break;
716 }
717
718 return ret;
719 }
720 #endif
721
__jx_k17_start_stream(struct jx_k17 * jx_k17)722 static int __jx_k17_start_stream(struct jx_k17 *jx_k17)
723 {
724 int ret;
725
726 ret = jx_k17_write_array(jx_k17->client, jx_k17->cur_mode->reg_list);
727 if (ret)
728 return ret;
729
730 /* In case these controls are set before streaming */
731 ret = __v4l2_ctrl_handler_setup(&jx_k17->ctrl_handler);
732 if (ret)
733 return ret;
734
735 ret = jx_k17_write_reg(jx_k17->client, JX_K17_REG_CTRL_MODE,
736 JX_K17_MODE_STREAMING);
737 return ret;
738 }
739
__jx_k17_stop_stream(struct jx_k17 * jx_k17)740 static int __jx_k17_stop_stream(struct jx_k17 *jx_k17)
741 {
742 return jx_k17_write_reg(jx_k17->client, JX_K17_REG_CTRL_MODE,
743 JX_K17_MODE_SW_STANDBY);
744 }
745
jx_k17_s_stream(struct v4l2_subdev * sd,int on)746 static int jx_k17_s_stream(struct v4l2_subdev *sd, int on)
747 {
748 struct jx_k17 *jx_k17 = to_jx_k17(sd);
749 struct i2c_client *client = jx_k17->client;
750 int ret = 0;
751
752 mutex_lock(&jx_k17->mutex);
753 on = !!on;
754 if (on == jx_k17->streaming)
755 goto unlock_and_return;
756
757 if (on) {
758 ret = pm_runtime_get_sync(&client->dev);
759 if (ret < 0) {
760 pm_runtime_put_noidle(&client->dev);
761 goto unlock_and_return;
762 }
763
764 ret = __jx_k17_start_stream(jx_k17);
765 if (ret) {
766 v4l2_err(sd, "start stream failed while write regs\n");
767 pm_runtime_put(&client->dev);
768 goto unlock_and_return;
769 }
770 } else {
771 __jx_k17_stop_stream(jx_k17);
772 pm_runtime_put(&client->dev);
773 }
774
775 jx_k17->streaming = on;
776
777 unlock_and_return:
778 mutex_unlock(&jx_k17->mutex);
779
780 return ret;
781 }
782
jx_k17_s_power(struct v4l2_subdev * sd,int on)783 static int jx_k17_s_power(struct v4l2_subdev *sd, int on)
784 {
785 struct jx_k17 *jx_k17 = to_jx_k17(sd);
786 struct i2c_client *client = jx_k17->client;
787 int ret = 0;
788
789 mutex_lock(&jx_k17->mutex);
790
791 /* If the power state is not modified - no work to do. */
792 if (jx_k17->power_on == !!on)
793 goto unlock_and_return;
794
795 if (on) {
796 ret = pm_runtime_get_sync(&client->dev);
797 if (ret < 0) {
798 pm_runtime_put_noidle(&client->dev);
799 goto unlock_and_return;
800 }
801
802 ret = jx_k17_write_array(jx_k17->client,
803 jx_k17_global_regs);
804 if (ret) {
805 v4l2_err(sd, "could not set init registers\n");
806 pm_runtime_put_noidle(&client->dev);
807 goto unlock_and_return;
808 }
809
810 jx_k17->power_on = true;
811 } else {
812 pm_runtime_put(&client->dev);
813 jx_k17->power_on = false;
814 }
815
816 unlock_and_return:
817 mutex_unlock(&jx_k17->mutex);
818
819 return ret;
820 }
821
__jx_k17_power_on(struct jx_k17 * jx_k17)822 static int __jx_k17_power_on(struct jx_k17 *jx_k17)
823 {
824 int ret;
825 u32 delay_us;
826 struct device *dev = &jx_k17->client->dev;
827
828 if (!IS_ERR_OR_NULL(jx_k17->pins_default)) {
829 ret = pinctrl_select_state(jx_k17->pinctrl,
830 jx_k17->pins_default);
831 if (ret < 0)
832 dev_err(dev, "could not set pins\n");
833 }
834
835 ret = clk_set_rate(jx_k17->xvclk, JX_K17_XVCLK_FREQ);
836 if (ret < 0) {
837 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
838 return ret;
839 }
840 if (clk_get_rate(jx_k17->xvclk) != JX_K17_XVCLK_FREQ)
841 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
842 ret = clk_prepare_enable(jx_k17->xvclk);
843 if (ret < 0) {
844 dev_err(dev, "Failed to enable xvclk\n");
845 return ret;
846 }
847
848 if (!IS_ERR(jx_k17->pwdn_gpio))
849 gpiod_set_value_cansleep(jx_k17->pwdn_gpio, 1);
850 if (!IS_ERR(jx_k17->reset_gpio))
851 gpiod_set_value_cansleep(jx_k17->reset_gpio, 1);
852 usleep_range(2 * 1000, 3 * 1000);
853 if (!IS_ERR(jx_k17->reset_gpio))
854 gpiod_set_value_cansleep(jx_k17->reset_gpio, 0);
855
856 ret = regulator_bulk_enable(JX_K17_NUM_SUPPLIES, jx_k17->supplies);
857 if (ret < 0) {
858 dev_err(dev, "Failed to enable regulators\n");
859 goto disable_clk;
860 }
861
862 /* According to datasheet, at least 10ms for reset duration */
863 usleep_range(10 * 1000, 15 * 1000);
864
865 if (!IS_ERR(jx_k17->reset_gpio))
866 gpiod_set_value_cansleep(jx_k17->reset_gpio, 1);
867
868 usleep_range(2000, 3000);
869 if (!IS_ERR(jx_k17->pwdn_gpio))
870 gpiod_set_value_cansleep(jx_k17->pwdn_gpio, 0);
871
872 if (!IS_ERR(jx_k17->reset_gpio))
873 usleep_range(6000, 8000);
874 else
875 usleep_range(12000, 16000);
876
877 /* 8192 cycles prior to first SCCB transaction */
878 delay_us = jx_k17_cal_delay(8192);
879 usleep_range(delay_us, delay_us * 2);
880
881 return 0;
882
883 disable_clk:
884 clk_disable_unprepare(jx_k17->xvclk);
885
886 return ret;
887 }
888
__jx_k17_power_off(struct jx_k17 * jx_k17)889 static void __jx_k17_power_off(struct jx_k17 *jx_k17)
890 {
891 int ret;
892 struct device *dev = &jx_k17->client->dev;
893
894 if (!IS_ERR(jx_k17->pwdn_gpio))
895 gpiod_set_value_cansleep(jx_k17->pwdn_gpio, 1);
896 clk_disable_unprepare(jx_k17->xvclk);
897 if (!IS_ERR(jx_k17->reset_gpio))
898 gpiod_set_value_cansleep(jx_k17->reset_gpio, 0);
899 if (!IS_ERR_OR_NULL(jx_k17->pins_sleep)) {
900 ret = pinctrl_select_state(jx_k17->pinctrl,
901 jx_k17->pins_sleep);
902 if (ret < 0)
903 dev_dbg(dev, "could not set pins\n");
904 }
905 regulator_bulk_disable(JX_K17_NUM_SUPPLIES, jx_k17->supplies);
906 }
907
jx_k17_runtime_resume(struct device * dev)908 static int jx_k17_runtime_resume(struct device *dev)
909 {
910 struct i2c_client *client = to_i2c_client(dev);
911 struct v4l2_subdev *sd = i2c_get_clientdata(client);
912 struct jx_k17 *jx_k17 = to_jx_k17(sd);
913
914 return __jx_k17_power_on(jx_k17);
915 }
916
jx_k17_runtime_suspend(struct device * dev)917 static int jx_k17_runtime_suspend(struct device *dev)
918 {
919 struct i2c_client *client = to_i2c_client(dev);
920 struct v4l2_subdev *sd = i2c_get_clientdata(client);
921 struct jx_k17 *jx_k17 = to_jx_k17(sd);
922
923 __jx_k17_power_off(jx_k17);
924
925 return 0;
926 }
927
928 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
jx_k17_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)929 static int jx_k17_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
930 {
931 struct jx_k17 *jx_k17 = to_jx_k17(sd);
932 struct v4l2_mbus_framefmt *try_fmt =
933 v4l2_subdev_get_try_format(sd, fh->pad, 0);
934 const struct jx_k17_mode *def_mode = &supported_modes[0];
935
936 mutex_lock(&jx_k17->mutex);
937 /* Initialize try_fmt */
938 try_fmt->width = def_mode->width;
939 try_fmt->height = def_mode->height;
940 try_fmt->code = def_mode->bus_fmt;
941 try_fmt->field = V4L2_FIELD_NONE;
942
943 mutex_unlock(&jx_k17->mutex);
944 /* No crop or compose */
945
946 return 0;
947 }
948 #endif
949
jx_k17_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)950 static int jx_k17_enum_frame_interval(struct v4l2_subdev *sd,
951 struct v4l2_subdev_pad_config *cfg,
952 struct v4l2_subdev_frame_interval_enum *fie)
953 {
954 if (fie->index >= ARRAY_SIZE(supported_modes))
955 return -EINVAL;
956
957 fie->code = supported_modes[fie->index].bus_fmt;
958 fie->width = supported_modes[fie->index].width;
959 fie->height = supported_modes[fie->index].height;
960 fie->interval = supported_modes[fie->index].max_fps;
961 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
962 return 0;
963 }
964
965 static const struct dev_pm_ops jx_k17_pm_ops = {
966 SET_RUNTIME_PM_OPS(jx_k17_runtime_suspend,
967 jx_k17_runtime_resume, NULL)
968 };
969
970 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
971 static const struct v4l2_subdev_internal_ops jx_k17_internal_ops = {
972 .open = jx_k17_open,
973 };
974 #endif
975
976 static const struct v4l2_subdev_core_ops jx_k17_core_ops = {
977 .s_power = jx_k17_s_power,
978 .ioctl = jx_k17_ioctl,
979 #ifdef CONFIG_COMPAT
980 .compat_ioctl32 = jx_k17_compat_ioctl32,
981 #endif
982 };
983
984 static const struct v4l2_subdev_video_ops jx_k17_video_ops = {
985 .s_stream = jx_k17_s_stream,
986 .g_frame_interval = jx_k17_g_frame_interval,
987 };
988
989 static const struct v4l2_subdev_pad_ops jx_k17_pad_ops = {
990 .enum_mbus_code = jx_k17_enum_mbus_code,
991 .enum_frame_size = jx_k17_enum_frame_sizes,
992 .enum_frame_interval = jx_k17_enum_frame_interval,
993 .get_fmt = jx_k17_get_fmt,
994 .set_fmt = jx_k17_set_fmt,
995 .get_mbus_config = jx_k17_g_mbus_config,
996 };
997
998 static const struct v4l2_subdev_ops jx_k17_subdev_ops = {
999 .core = &jx_k17_core_ops,
1000 .video = &jx_k17_video_ops,
1001 .pad = &jx_k17_pad_ops,
1002 };
1003
jx_k17_set_ctrl(struct v4l2_ctrl * ctrl)1004 static int jx_k17_set_ctrl(struct v4l2_ctrl *ctrl)
1005 {
1006 struct jx_k17 *jx_k17 = container_of(ctrl->handler,
1007 struct jx_k17, ctrl_handler);
1008 struct i2c_client *client = jx_k17->client;
1009 s64 max;
1010 int ret = 0;
1011
1012 /* Propagate change of current control to all related controls */
1013 switch (ctrl->id) {
1014 case V4L2_CID_VBLANK:
1015 /* Update max exposure while meeting expected vblanking */
1016 max = jx_k17->cur_mode->height + ctrl->val - 9;
1017 __v4l2_ctrl_modify_range(jx_k17->exposure,
1018 jx_k17->exposure->minimum, max,
1019 jx_k17->exposure->step,
1020 jx_k17->exposure->default_value);
1021 break;
1022 }
1023
1024 if (!pm_runtime_get_if_in_use(&client->dev))
1025 return 0;
1026
1027 switch (ctrl->id) {
1028 case V4L2_CID_EXPOSURE:
1029 dev_dbg(&client->dev, "set expo: val: %d\n", ctrl->val);
1030 /* 4 least significant bits of expsoure are fractional part */
1031 ret = jx_k17_write_reg(jx_k17->client,
1032 JX_K17_AEC_PK_LONG_EXPO_HIGH_REG,
1033 JX_K17_FETCH_HIGH_BYTE_EXP(ctrl->val));
1034 ret |= jx_k17_write_reg(jx_k17->client,
1035 JX_K17_AEC_PK_LONG_EXPO_LOW_REG,
1036 JX_K17_FETCH_LOW_BYTE_EXP(ctrl->val));
1037 break;
1038 case V4L2_CID_ANALOGUE_GAIN:
1039 dev_dbg(&client->dev, "set a-gain: val: %d\n", ctrl->val);
1040 ret |= jx_k17_write_reg(jx_k17->client,
1041 JX_K17_AEC_PK_LONG_GAIN_REG, ctrl->val);
1042 break;
1043 case V4L2_CID_VBLANK:
1044 dev_dbg(&client->dev, "set vblank: val: %d\n", ctrl->val);
1045 ret |= jx_k17_write_reg(jx_k17->client, JX_K17_REG_HIGH_VTS,
1046 JX_K17_FETCH_HIGH_BYTE_VTS((ctrl->val + jx_k17->cur_mode->height)));
1047 ret |= jx_k17_write_reg(jx_k17->client, JX_K17_REG_LOW_VTS,
1048 JX_K17_FETCH_LOW_BYTE_VTS((ctrl->val + jx_k17->cur_mode->height)));
1049 break;
1050 case V4L2_CID_TEST_PATTERN:
1051 ret = jx_k17_enable_test_pattern(jx_k17, ctrl->val);
1052 break;
1053 default:
1054 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1055 __func__, ctrl->id, ctrl->val);
1056 break;
1057 }
1058
1059 pm_runtime_put(&client->dev);
1060
1061 return ret;
1062 }
1063
1064 static const struct v4l2_ctrl_ops jx_k17_ctrl_ops = {
1065 .s_ctrl = jx_k17_set_ctrl,
1066 };
1067
jx_k17_initialize_controls(struct jx_k17 * jx_k17)1068 static int jx_k17_initialize_controls(struct jx_k17 *jx_k17)
1069 {
1070 const struct jx_k17_mode *mode;
1071 struct v4l2_ctrl_handler *handler;
1072 struct v4l2_ctrl *ctrl;
1073 s64 exposure_max, vblank_def;
1074 u32 h_blank;
1075 int ret;
1076
1077 handler = &jx_k17->ctrl_handler;
1078 mode = jx_k17->cur_mode;
1079 ret = v4l2_ctrl_handler_init(handler, 7);
1080 if (ret)
1081 return ret;
1082 handler->lock = &jx_k17->mutex;
1083
1084 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1085 0, 0, link_freq_menu_items);
1086 if (ctrl)
1087 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1088
1089 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1090 0, JX_K17_PIXEL_RATE, 1, JX_K17_PIXEL_RATE);
1091
1092 h_blank = mode->hts_def - mode->width;
1093 jx_k17->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1094 h_blank, h_blank, 1, h_blank);
1095 if (jx_k17->hblank)
1096 jx_k17->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1097
1098 vblank_def = mode->vts_def - mode->height;
1099 jx_k17->vblank = v4l2_ctrl_new_std(handler, &jx_k17_ctrl_ops,
1100 V4L2_CID_VBLANK, vblank_def,
1101 JX_K17_VTS_MAX - mode->height,
1102 1, vblank_def);
1103
1104 exposure_max = mode->vts_def - 9;
1105 jx_k17->exposure = v4l2_ctrl_new_std(handler, &jx_k17_ctrl_ops,
1106 V4L2_CID_EXPOSURE, JX_K17_EXPOSURE_MIN,
1107 exposure_max, JX_K17_EXPOSURE_STEP,
1108 mode->exp_def);
1109
1110 jx_k17->anal_gain = v4l2_ctrl_new_std(handler, &jx_k17_ctrl_ops,
1111 V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1112 ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1113 ANALOG_GAIN_DEFAULT);
1114
1115 jx_k17->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1116 &jx_k17_ctrl_ops, V4L2_CID_TEST_PATTERN,
1117 ARRAY_SIZE(jx_k17_test_pattern_menu) - 1,
1118 0, 0, jx_k17_test_pattern_menu);
1119
1120 if (handler->error) {
1121 ret = handler->error;
1122 dev_err(&jx_k17->client->dev,
1123 "Failed to init controls(%d)\n", ret);
1124 goto err_free_handler;
1125 }
1126
1127 jx_k17->subdev.ctrl_handler = handler;
1128
1129 return 0;
1130
1131 err_free_handler:
1132 v4l2_ctrl_handler_free(handler);
1133
1134 return ret;
1135 }
1136
jx_k17_check_sensor_id(struct jx_k17 * jx_k17,struct i2c_client * client)1137 static int jx_k17_check_sensor_id(struct jx_k17 *jx_k17,
1138 struct i2c_client *client)
1139 {
1140 struct device *dev = &jx_k17->client->dev;
1141 u8 id_h = 0;
1142 u8 id_l = 0;
1143 int ret;
1144
1145 ret = jx_k17_read_reg(client, JX_K17_PIDH_ADDR, &id_h);
1146 ret |= jx_k17_read_reg(client, JX_K17_PIDL_ADDR, &id_l);
1147 if (id_h != CHIP_ID_H && id_l != CHIP_ID_L) {
1148 dev_err(dev, "Wrong camera sensor id(0x%02x%02x)\n",
1149 id_h, id_l);
1150 return -EINVAL;
1151 }
1152
1153 dev_info(dev, "Detected jx_k17 (0x%02x%02x) sensor\n",
1154 id_h, id_l);
1155
1156 return ret;
1157 }
1158
jx_k17_configure_regulators(struct jx_k17 * jx_k17)1159 static int jx_k17_configure_regulators(struct jx_k17 *jx_k17)
1160 {
1161 unsigned int i;
1162
1163 for (i = 0; i < JX_K17_NUM_SUPPLIES; i++)
1164 jx_k17->supplies[i].supply = jx_k17_supply_names[i];
1165
1166 return devm_regulator_bulk_get(&jx_k17->client->dev,
1167 JX_K17_NUM_SUPPLIES,
1168 jx_k17->supplies);
1169 }
1170
jx_k17_probe(struct i2c_client * client,const struct i2c_device_id * id)1171 static int jx_k17_probe(struct i2c_client *client,
1172 const struct i2c_device_id *id)
1173 {
1174 struct device *dev = &client->dev;
1175 struct device_node *node = dev->of_node;
1176 struct jx_k17 *jx_k17;
1177 struct v4l2_subdev *sd;
1178 char facing[2];
1179 int ret;
1180
1181 dev_info(dev, "driver version: %02x.%02x.%02x",
1182 DRIVER_VERSION >> 16,
1183 (DRIVER_VERSION & 0xff00) >> 8,
1184 DRIVER_VERSION & 0x00ff);
1185
1186 jx_k17 = devm_kzalloc(dev, sizeof(*jx_k17), GFP_KERNEL);
1187 if (!jx_k17)
1188 return -ENOMEM;
1189
1190 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1191 &jx_k17->module_index);
1192 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1193 &jx_k17->module_facing);
1194 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1195 &jx_k17->module_name);
1196 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1197 &jx_k17->len_name);
1198 if (ret) {
1199 dev_err(dev, "could not get module information!\n");
1200 return -EINVAL;
1201 }
1202
1203 jx_k17->client = client;
1204 jx_k17->cur_mode = &supported_modes[0];
1205
1206 jx_k17->xvclk = devm_clk_get(dev, "xvclk");
1207 if (IS_ERR(jx_k17->xvclk)) {
1208 dev_err(dev, "Failed to get xvclk\n");
1209 return -EINVAL;
1210 }
1211
1212 jx_k17->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1213 if (IS_ERR(jx_k17->reset_gpio))
1214 dev_warn(dev, "Failed to get reset-gpios\n");
1215
1216 jx_k17->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1217 if (IS_ERR(jx_k17->pwdn_gpio))
1218 dev_warn(dev, "Failed to get pwdn-gpios\n");
1219
1220 jx_k17->pinctrl = devm_pinctrl_get(dev);
1221 if (!IS_ERR(jx_k17->pinctrl)) {
1222 jx_k17->pins_default =
1223 pinctrl_lookup_state(jx_k17->pinctrl,
1224 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1225 if (IS_ERR(jx_k17->pins_default))
1226 dev_err(dev, "could not get default pinstate\n");
1227
1228 jx_k17->pins_sleep =
1229 pinctrl_lookup_state(jx_k17->pinctrl,
1230 OF_CAMERA_PINCTRL_STATE_SLEEP);
1231 if (IS_ERR(jx_k17->pins_sleep))
1232 dev_err(dev, "could not get sleep pinstate\n");
1233 } else {
1234 dev_err(dev, "no pinctrl\n");
1235 }
1236 ret = jx_k17_configure_regulators(jx_k17);
1237 if (ret) {
1238 dev_err(dev, "Failed to get power regulators\n");
1239 return ret;
1240 }
1241
1242 mutex_init(&jx_k17->mutex);
1243
1244 sd = &jx_k17->subdev;
1245 v4l2_i2c_subdev_init(sd, client, &jx_k17_subdev_ops);
1246 ret = jx_k17_initialize_controls(jx_k17);
1247 if (ret)
1248 goto err_destroy_mutex;
1249
1250 ret = __jx_k17_power_on(jx_k17);
1251 if (ret)
1252 goto err_free_handler;
1253
1254 ret = jx_k17_check_sensor_id(jx_k17, client);
1255 if (ret)
1256 goto err_power_off;
1257
1258 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1259 sd->internal_ops = &jx_k17_internal_ops;
1260 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1261 V4L2_SUBDEV_FL_HAS_EVENTS;
1262 #endif
1263 #if defined(CONFIG_MEDIA_CONTROLLER)
1264 jx_k17->pad.flags = MEDIA_PAD_FL_SOURCE;
1265 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1266 ret = media_entity_pads_init(&sd->entity, 1, &jx_k17->pad);
1267 if (ret < 0)
1268 goto err_power_off;
1269 #endif
1270
1271 memset(facing, 0, sizeof(facing));
1272 if (strcmp(jx_k17->module_facing, "back") == 0)
1273 facing[0] = 'b';
1274 else
1275 facing[0] = 'f';
1276
1277 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1278 jx_k17->module_index, facing,
1279 JX_K17_NAME, dev_name(sd->dev));
1280
1281 ret = v4l2_async_register_subdev_sensor_common(sd);
1282 if (ret) {
1283 dev_err(dev, "v4l2 async register subdev failed\n");
1284 goto err_clean_entity;
1285 }
1286
1287 pm_runtime_set_active(dev);
1288 pm_runtime_enable(dev);
1289 pm_runtime_idle(dev);
1290
1291 return 0;
1292
1293 err_clean_entity:
1294 #if defined(CONFIG_MEDIA_CONTROLLER)
1295 media_entity_cleanup(&sd->entity);
1296 #endif
1297 err_power_off:
1298 __jx_k17_power_off(jx_k17);
1299 err_free_handler:
1300 v4l2_ctrl_handler_free(&jx_k17->ctrl_handler);
1301 err_destroy_mutex:
1302 mutex_destroy(&jx_k17->mutex);
1303
1304 return ret;
1305 }
1306
jx_k17_remove(struct i2c_client * client)1307 static int jx_k17_remove(struct i2c_client *client)
1308 {
1309 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1310 struct jx_k17 *jx_k17 = to_jx_k17(sd);
1311
1312 v4l2_async_unregister_subdev(sd);
1313 #if defined(CONFIG_MEDIA_CONTROLLER)
1314 media_entity_cleanup(&sd->entity);
1315 #endif
1316 v4l2_ctrl_handler_free(&jx_k17->ctrl_handler);
1317 mutex_destroy(&jx_k17->mutex);
1318
1319 pm_runtime_disable(&client->dev);
1320 if (!pm_runtime_status_suspended(&client->dev))
1321 __jx_k17_power_off(jx_k17);
1322 pm_runtime_set_suspended(&client->dev);
1323
1324 return 0;
1325 }
1326
1327 #if IS_ENABLED(CONFIG_OF)
1328 static const struct of_device_id jx_k17_of_match[] = {
1329 { .compatible = "soi,jx_k17" },
1330 {},
1331 };
1332 MODULE_DEVICE_TABLE(of, jx_k17_of_match);
1333 #endif
1334
1335 static const struct i2c_device_id jx_k17_match_id[] = {
1336 { "soi,jx_k17", 0 },
1337 { },
1338 };
1339
1340 static struct i2c_driver jx_k17_i2c_driver = {
1341 .driver = {
1342 .name = JX_K17_NAME,
1343 .pm = &jx_k17_pm_ops,
1344 .of_match_table = of_match_ptr(jx_k17_of_match),
1345 },
1346 .probe = &jx_k17_probe,
1347 .remove = &jx_k17_remove,
1348 .id_table = jx_k17_match_id,
1349 };
1350
sensor_mod_init(void)1351 static int __init sensor_mod_init(void)
1352 {
1353 return i2c_add_driver(&jx_k17_i2c_driver);
1354 }
1355
sensor_mod_exit(void)1356 static void __exit sensor_mod_exit(void)
1357 {
1358 i2c_del_driver(&jx_k17_i2c_driver);
1359 }
1360
1361 device_initcall_sync(sensor_mod_init);
1362 module_exit(sensor_mod_exit);
1363
1364 MODULE_DESCRIPTION("SOI jx_k17 sensor driver");
1365 MODULE_LICENSE("GPL");
1366