1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * jx_h62 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 init version.
8 * V0.0X01.0X02 add function g_mbus_config.
9 */
10
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/of.h>
19 #include <linux/of_graph.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/sysfs.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <media/media-entity.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/version.h>
29 #include <linux/rk-camera-module.h>
30
31 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
32
33 #ifndef V4L2_CID_DIGITAL_GAIN
34 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35 #endif
36
37 #define JX_H62_XVCLK_FREQ 24000000
38
39 #define CHIP_ID_H 0x0A
40 #define CHIP_ID_L 0x62
41
42 #define JX_H62_PIDH_ADDR 0x0a
43 #define JX_H62_PIDL_ADDR 0x0b
44
45 #define JX_H62_REG_CTRL_MODE 0x12
46 #define JX_H62_MODE_SW_STANDBY 0x40
47 #define JX_H62_MODE_STREAMING 0x00
48
49 #define JX_H62_AEC_PK_LONG_EXPO_HIGH_REG 0x02 /* Exposure Bits 8-15 */
50 #define JX_H62_AEC_PK_LONG_EXPO_LOW_REG 0x01 /* Exposure Bits 0-7 */
51 #define JX_H62_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
52 #define JX_H62_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
53 #define JX_H62_EXPOSURE_MIN 4
54 #define JX_H62_EXPOSURE_STEP 1
55 #define JX_H62_VTS_MAX 0xffff
56
57 #define JX_H62_AEC_PK_LONG_GAIN_REG 0x00 /* Bits 0 -7 */
58 #define ANALOG_GAIN_MIN 0x00
59 #define ANALOG_GAIN_MAX 0xf8 /* 15.5 */
60 #define ANALOG_GAIN_STEP 1
61 #define ANALOG_GAIN_DEFAULT 0x10
62
63 #define JX_H62_DIGI_GAIN_L_MASK 0x3f
64 #define JX_H62_DIGI_GAIN_H_SHIFT 6
65 #define JX_H62_DIGI_GAIN_MIN 0
66 #define JX_H62_DIGI_GAIN_MAX (0x4000 - 1)
67 #define JX_H62_DIGI_GAIN_STEP 1
68 #define JX_H62_DIGI_GAIN_DEFAULT 1024
69
70 #define JX_H62_REG_TEST_PATTERN 0x0c
71 #define JX_H62_TEST_PATTERN_ENABLE 0x80
72 #define JX_H62_TEST_PATTERN_DISABLE 0x0
73
74 #define JX_H62_REG_HIGH_VTS 0x23
75 #define JX_H62_REG_LOW_VTS 0X22
76 #define JX_H62_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
77 #define JX_H62_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
78
79 #define REG_NULL 0xFF
80 #define REG_DELAY 0xFE
81
82 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
83 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
84 #define JX_H62_NAME "jx_h62"
85 #define JX_H62_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
86
87 #define JX_H62_LANES 1
88
89 static const char * const jx_h62_supply_names[] = {
90 "vcc2v8_dvp", /* Analog power */
91 "vcc1v8_dvp", /* Digital I/O power */
92 "vdd1v5_dvp", /* Digital core power */
93 };
94
95 #define JX_H62_NUM_SUPPLIES ARRAY_SIZE(jx_h62_supply_names)
96
97 struct regval {
98 u16 addr;
99 u8 val;
100 };
101
102 struct jx_h62_mode {
103 u32 width;
104 u32 height;
105 struct v4l2_fract max_fps;
106 u32 hts_def;
107 u32 vts_def;
108 u32 exp_def;
109 const struct regval *reg_list;
110 };
111
112 struct jx_h62 {
113 struct i2c_client *client;
114 struct clk *xvclk;
115 struct gpio_desc *reset_gpio;
116 struct gpio_desc *pwdn_gpio;
117 struct regulator_bulk_data supplies[JX_H62_NUM_SUPPLIES];
118 struct pinctrl *pinctrl;
119 struct pinctrl_state *pins_default;
120 struct pinctrl_state *pins_sleep;
121 struct v4l2_subdev subdev;
122 struct media_pad pad;
123 struct v4l2_ctrl_handler ctrl_handler;
124 struct v4l2_ctrl *exposure;
125 struct v4l2_ctrl *anal_gain;
126 struct v4l2_ctrl *digi_gain;
127 struct v4l2_ctrl *hblank;
128 struct v4l2_ctrl *vblank;
129 struct v4l2_ctrl *test_pattern;
130 struct mutex mutex;
131 bool streaming;
132 bool power_on;
133 const struct jx_h62_mode *cur_mode;
134 unsigned int lane_num;
135 unsigned int cfg_num;
136 unsigned int pixel_rate;
137 u32 module_index;
138 const char *module_facing;
139 const char *module_name;
140 const char *len_name;
141 u32 old_gain;
142 };
143
144 #define to_jx_h62(sd) container_of(sd, struct jx_h62, subdev)
145
146 /*
147 * Xclk 24Mhz
148 * Pclk 45Mhz
149 * linelength 672(0x2a0)
150 * framelength 2232(0x8b8)
151 * grabwindow_width 1280
152 * grabwindow_height 720
153 * max_framerate 30fps
154 * mipi_datarate per lane 216Mbps
155 */
156
157 static const struct regval jx_h62_1280x720_regs[] = {
158 { 0x12, 0x40},
159 { 0x0E, 0x11},
160 { 0x0F, 0x09},
161 { 0x10, 0x1E},
162 { 0x11, 0x80},
163 { 0x19, 0x68},
164 { 0x20, 0x40},
165 { 0x21, 0x06},
166 { 0x22, 0xEE},
167 { 0x23, 0x02},
168 { 0x24, 0x00},
169 { 0x25, 0xD0},
170 { 0x26, 0x25},
171 { 0x27, 0x10},
172 { 0x28, 0x15},
173 { 0x29, 0x02},
174 { 0x2A, 0x01},
175 { 0x2B, 0x21},
176 { 0x2C, 0x08},
177 { 0x2D, 0x01},
178 { 0x2E, 0xBB},
179 { 0x2F, 0xC0},
180 { 0x41, 0x88},
181 { 0x42, 0x12},
182 { 0x39, 0x90},
183 { 0x1D, 0x00},
184 { 0x1E, 0x04},
185 { 0x7A, 0x4C},
186 { 0x70, 0x49},
187 { 0x71, 0x2A},
188 { 0x72, 0x48},
189 { 0x73, 0x33},
190 { 0x74, 0x52},
191 { 0x75, 0x2B},
192 { 0x76, 0x40},
193 { 0x77, 0x06},
194 { 0x78, 0x10},
195 { 0x66, 0x08},
196 { 0x1F, 0x20},
197 { 0x30, 0x90},
198 { 0x31, 0x0C},
199 { 0x32, 0xFF},
200 { 0x33, 0x0C},
201 { 0x34, 0x4B},
202 { 0x35, 0xA3},
203 { 0x36, 0x06},
204 { 0x38, 0x40},
205 { 0x3A, 0x08},
206 { 0x56, 0x02},
207 { 0x60, 0x01},
208 { 0x0D, 0x50},
209 { 0x57, 0x80},
210 { 0x58, 0x33},
211 { 0x5A, 0x04},
212 { 0x5B, 0xB6},
213 { 0x5C, 0x08},
214 { 0x5D, 0x67},
215 { 0x5E, 0x04},
216 { 0x5F, 0x08},
217 { 0x66, 0x28},
218 { 0x67, 0xF8},
219 { 0x68, 0x00},
220 { 0x69, 0x74},
221 { 0x6A, 0x1F},
222 { 0x63, 0x80},
223 { 0x6C, 0xC0},
224 { 0x6E, 0x5C},
225 { 0x82, 0x01},
226 { 0x0C, 0x00},
227 { 0x46, 0xC2},
228 { 0x48, 0x7E},
229 { 0x62, 0x40},
230 { 0x7D, 0x57},
231 { 0x7E, 0x28},
232 { 0x80, 0x00},
233 { 0x4A, 0x05},
234 { 0x49, 0x10},
235 { 0x13, 0x81},
236 { 0x59, 0x97},
237 { 0x12, 0x00},
238 { 0x47, 0x47},
239 {REG_DELAY, 0x00},
240
241 { 0x47, 0x44},
242 { 0x1F, 0x21},
243 {REG_NULL, 0x00}
244 };
245
246 static const struct jx_h62_mode supported_modes[] = {
247 {
248 .width = 1280,
249 .height = 720,
250 .max_fps = {
251 .numerator = 10000,
252 .denominator = 300000,
253 },
254 .exp_def = 0x02D0,
255 .hts_def = 0x0640,
256 .vts_def = 0x02ee,
257 .reg_list = jx_h62_1280x720_regs,
258 }
259 };
260
261 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
262 #define MIPI_FREQ 180000000
263 #define JX_H62_PIXEL_RATE (MIPI_FREQ * 2 * 1 / 10)
264 static const s64 link_freq_menu_items[] = {
265 MIPI_FREQ
266 };
267
268 static const char * const jx_h62_test_pattern_menu[] = {
269 "Disabled",
270 "Vertical Color Bar Type 1",
271 "Vertical Color Bar Type 2",
272 "Vertical Color Bar Type 3",
273 "Vertical Color Bar Type 4"
274 };
275
276 /* Calculate the delay in us by clock rate and clock cycles */
jx_h62_cal_delay(u32 cycles)277 static inline u32 jx_h62_cal_delay(u32 cycles)
278 {
279 return DIV_ROUND_UP(cycles, JX_H62_XVCLK_FREQ / 1000 / 1000);
280 }
281
jx_h62_write_reg(struct i2c_client * client,u8 reg,u8 val)282 static int jx_h62_write_reg(struct i2c_client *client, u8 reg, u8 val)
283 {
284 struct i2c_msg msg;
285 u8 buf[2];
286 int ret;
287
288 buf[0] = reg & 0xFF;
289 buf[1] = val;
290
291 msg.addr = client->addr;
292 msg.flags = client->flags;
293 msg.buf = buf;
294 msg.len = sizeof(buf);
295
296 ret = i2c_transfer(client->adapter, &msg, 1);
297 if (ret >= 0)
298 return 0;
299
300 dev_err(&client->dev,
301 "jx_h62 write reg(0x%x val:0x%x) failed !\n", reg, val);
302
303 return ret;
304 }
305
jx_h62_write_array(struct i2c_client * client,const struct regval * regs)306 static int jx_h62_write_array(struct i2c_client *client,
307 const struct regval *regs)
308 {
309 u32 i, delay_us;
310 int ret = 0;
311
312 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
313 if (regs[i].addr == REG_DELAY) {
314 delay_us = jx_h62_cal_delay(500 * 1000);
315 usleep_range(delay_us, delay_us * 2);
316 } else {
317 ret = jx_h62_write_reg(client,
318 regs[i].addr, regs[i].val);
319 }
320 }
321
322 return ret;
323 }
324
jx_h62_read_reg(struct i2c_client * client,u8 reg,u8 * val)325 static int jx_h62_read_reg(struct i2c_client *client, u8 reg, u8 *val)
326 {
327 struct i2c_msg msg[2];
328 u8 buf[1];
329 int ret;
330
331 buf[0] = reg & 0xFF;
332
333 msg[0].addr = client->addr;
334 msg[0].flags = client->flags;
335 msg[0].buf = buf;
336 msg[0].len = sizeof(buf);
337
338 msg[1].addr = client->addr;
339 msg[1].flags = client->flags | I2C_M_RD;
340 msg[1].buf = buf;
341 msg[1].len = 1;
342
343 ret = i2c_transfer(client->adapter, msg, 2);
344 if (ret >= 0) {
345 *val = buf[0];
346 return 0;
347 }
348
349 dev_err(&client->dev,
350 "jx_h62 read reg:0x%x failed !\n", reg);
351
352 return ret;
353 }
354
jx_h62_get_reso_dist(const struct jx_h62_mode * mode,struct v4l2_mbus_framefmt * framefmt)355 static int jx_h62_get_reso_dist(const struct jx_h62_mode *mode,
356 struct v4l2_mbus_framefmt *framefmt)
357 {
358 return abs(mode->width - framefmt->width) +
359 abs(mode->height - framefmt->height);
360 }
361
362 static const struct jx_h62_mode *
jx_h62_find_best_fit(struct v4l2_subdev_format * fmt)363 jx_h62_find_best_fit(struct v4l2_subdev_format *fmt)
364 {
365 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
366 int dist;
367 int cur_best_fit = 0;
368 int cur_best_fit_dist = -1;
369 unsigned int i;
370
371 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
372 dist = jx_h62_get_reso_dist(&supported_modes[i], framefmt);
373 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
374 cur_best_fit_dist = dist;
375 cur_best_fit = i;
376 }
377 }
378
379 return &supported_modes[cur_best_fit];
380 }
381
jx_h62_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)382 static int jx_h62_set_fmt(struct v4l2_subdev *sd,
383 struct v4l2_subdev_pad_config *cfg,
384 struct v4l2_subdev_format *fmt)
385 {
386 struct jx_h62 *jx_h62 = to_jx_h62(sd);
387 const struct jx_h62_mode *mode;
388 s64 h_blank, vblank_def;
389
390 mutex_lock(&jx_h62->mutex);
391
392 mode = jx_h62_find_best_fit(fmt);
393 fmt->format.code = JX_H62_MEDIA_BUS_FMT;
394 fmt->format.width = mode->width;
395 fmt->format.height = mode->height;
396 fmt->format.field = V4L2_FIELD_NONE;
397 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
398 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
399 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
400 #else
401 mutex_unlock(&jx_h62->mutex);
402 return -ENOTTY;
403 #endif
404 } else {
405 jx_h62->cur_mode = mode;
406 h_blank = mode->hts_def - mode->width;
407 __v4l2_ctrl_modify_range(jx_h62->hblank, h_blank,
408 h_blank, 1, h_blank);
409 vblank_def = mode->vts_def - mode->height;
410 __v4l2_ctrl_modify_range(jx_h62->vblank, vblank_def,
411 JX_H62_VTS_MAX - mode->height,
412 1, vblank_def);
413 }
414
415 mutex_unlock(&jx_h62->mutex);
416
417 return 0;
418 }
419
jx_h62_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)420 static int jx_h62_get_fmt(struct v4l2_subdev *sd,
421 struct v4l2_subdev_pad_config *cfg,
422 struct v4l2_subdev_format *fmt)
423 {
424 struct jx_h62 *jx_h62 = to_jx_h62(sd);
425 const struct jx_h62_mode *mode = jx_h62->cur_mode;
426
427 mutex_lock(&jx_h62->mutex);
428 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
429 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
430 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
431 #else
432 mutex_unlock(&jx_h62->mutex);
433 return -ENOTTY;
434 #endif
435 } else {
436 fmt->format.width = mode->width;
437 fmt->format.height = mode->height;
438 fmt->format.code = JX_H62_MEDIA_BUS_FMT;
439 fmt->format.field = V4L2_FIELD_NONE;
440 }
441 mutex_unlock(&jx_h62->mutex);
442
443 return 0;
444 }
445
jx_h62_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)446 static int jx_h62_enum_mbus_code(struct v4l2_subdev *sd,
447 struct v4l2_subdev_pad_config *cfg,
448 struct v4l2_subdev_mbus_code_enum *code)
449 {
450 if (code->index != 0)
451 return -EINVAL;
452 code->code = JX_H62_MEDIA_BUS_FMT;
453
454 return 0;
455 }
456
jx_h62_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)457 static int jx_h62_enum_frame_sizes(struct v4l2_subdev *sd,
458 struct v4l2_subdev_pad_config *cfg,
459 struct v4l2_subdev_frame_size_enum *fse)
460 {
461 if (fse->index >= ARRAY_SIZE(supported_modes))
462 return -EINVAL;
463
464 if (fse->code != JX_H62_MEDIA_BUS_FMT)
465 return -EINVAL;
466
467 fse->min_width = supported_modes[fse->index].width;
468 fse->max_width = supported_modes[fse->index].width;
469 fse->max_height = supported_modes[fse->index].height;
470 fse->min_height = supported_modes[fse->index].height;
471
472 return 0;
473 }
474
jx_h62_enable_test_pattern(struct jx_h62 * jx_h62,u32 pattern)475 static int jx_h62_enable_test_pattern(struct jx_h62 *jx_h62, u32 pattern)
476 {
477 u32 val;
478
479 if (pattern)
480 val = (pattern - 1) | JX_H62_TEST_PATTERN_ENABLE;
481 else
482 val = JX_H62_TEST_PATTERN_DISABLE;
483
484 return jx_h62_write_reg(jx_h62->client, JX_H62_REG_TEST_PATTERN, val);
485 }
486
jx_h62_get_module_inf(struct jx_h62 * jx_h62,struct rkmodule_inf * inf)487 static void jx_h62_get_module_inf(struct jx_h62 *jx_h62,
488 struct rkmodule_inf *inf)
489 {
490 memset(inf, 0, sizeof(*inf));
491 strlcpy(inf->base.sensor, JX_H62_NAME, sizeof(inf->base.sensor));
492 strlcpy(inf->base.module, jx_h62->module_name,
493 sizeof(inf->base.module));
494 strlcpy(inf->base.lens, jx_h62->len_name, sizeof(inf->base.lens));
495 }
496
jx_h62_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)497 static long jx_h62_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
498 {
499 struct jx_h62 *jx_h62 = to_jx_h62(sd);
500 long ret = 0;
501 u32 stream = 0;
502
503 switch (cmd) {
504 case RKMODULE_GET_MODULE_INFO:
505 jx_h62_get_module_inf(jx_h62, (struct rkmodule_inf *)arg);
506 break;
507 case RKMODULE_SET_QUICK_STREAM:
508
509 stream = *((u32 *)arg);
510
511 if (stream)
512 ret = jx_h62_write_reg(jx_h62->client, JX_H62_REG_CTRL_MODE,
513 JX_H62_MODE_STREAMING);
514 else
515 ret = jx_h62_write_reg(jx_h62->client, JX_H62_REG_CTRL_MODE,
516 JX_H62_MODE_SW_STANDBY);
517 break;
518 default:
519 ret = -ENOIOCTLCMD;
520 break;
521 }
522
523 return ret;
524 }
525
526 #ifdef CONFIG_COMPAT
jx_h62_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)527 static long jx_h62_compat_ioctl32(struct v4l2_subdev *sd,
528 unsigned int cmd, unsigned long arg)
529 {
530 void __user *up = compat_ptr(arg);
531 struct rkmodule_inf *inf;
532 struct rkmodule_awb_cfg *cfg;
533 long ret;
534 u32 stream = 0;
535
536 switch (cmd) {
537 case RKMODULE_GET_MODULE_INFO:
538 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
539 if (!inf) {
540 ret = -ENOMEM;
541 return ret;
542 }
543
544 ret = jx_h62_ioctl(sd, cmd, inf);
545 if (!ret)
546 ret = copy_to_user(up, inf, sizeof(*inf));
547 kfree(inf);
548 break;
549 case RKMODULE_AWB_CFG:
550 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
551 if (!cfg) {
552 ret = -ENOMEM;
553 return ret;
554 }
555
556 ret = copy_from_user(cfg, up, sizeof(*cfg));
557 if (!ret)
558 ret = jx_h62_ioctl(sd, cmd, cfg);
559 kfree(cfg);
560 break;
561 case RKMODULE_SET_QUICK_STREAM:
562 ret = copy_from_user(&stream, up, sizeof(u32));
563 if (!ret)
564 ret = jx_h62_ioctl(sd, cmd, &stream);
565 break;
566 default:
567 ret = -ENOIOCTLCMD;
568 break;
569 }
570
571 return ret;
572 }
573 #endif
574
jx_h62_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)575 static int jx_h62_g_frame_interval(struct v4l2_subdev *sd,
576 struct v4l2_subdev_frame_interval *fi)
577 {
578 struct jx_h62 *jx_h62 = to_jx_h62(sd);
579 const struct jx_h62_mode *mode = jx_h62->cur_mode;
580
581 mutex_lock(&jx_h62->mutex);
582 fi->interval = mode->max_fps;
583 mutex_unlock(&jx_h62->mutex);
584
585 return 0;
586 }
587
__jx_h62_start_stream(struct jx_h62 * jx_h62)588 static int __jx_h62_start_stream(struct jx_h62 *jx_h62)
589 {
590 return jx_h62_write_reg(jx_h62->client, JX_H62_REG_CTRL_MODE,
591 JX_H62_MODE_STREAMING);
592 }
593
__jx_h62_stop_stream(struct jx_h62 * jx_h62)594 static int __jx_h62_stop_stream(struct jx_h62 *jx_h62)
595 {
596 return jx_h62_write_reg(jx_h62->client, JX_H62_REG_CTRL_MODE,
597 JX_H62_MODE_SW_STANDBY);
598 }
599
jx_h62_s_stream(struct v4l2_subdev * sd,int on)600 static int jx_h62_s_stream(struct v4l2_subdev *sd, int on)
601 {
602 struct jx_h62 *jx_h62 = to_jx_h62(sd);
603 struct i2c_client *client = jx_h62->client;
604 int ret = 0;
605
606 mutex_lock(&jx_h62->mutex);
607 on = !!on;
608 if (on == jx_h62->streaming)
609 goto unlock_and_return;
610
611 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
612 jx_h62->cur_mode->width,
613 jx_h62->cur_mode->height,
614 DIV_ROUND_CLOSEST(jx_h62->cur_mode->max_fps.denominator,
615 jx_h62->cur_mode->max_fps.numerator));
616
617 if (on) {
618 ret = pm_runtime_get_sync(&client->dev);
619 if (ret < 0) {
620 pm_runtime_put_noidle(&client->dev);
621 goto unlock_and_return;
622 }
623
624 ret = __jx_h62_start_stream(jx_h62);
625 if (ret) {
626 v4l2_err(sd, " jx_h62 start stream failed while write regs\n");
627 pm_runtime_put(&client->dev);
628 goto unlock_and_return;
629 }
630 } else {
631 __jx_h62_stop_stream(jx_h62);
632 pm_runtime_put(&client->dev);
633 }
634
635 jx_h62->streaming = on;
636
637 unlock_and_return:
638 mutex_unlock(&jx_h62->mutex);
639
640 return ret;
641 }
642
jx_h62_s_power(struct v4l2_subdev * sd,int on)643 static int jx_h62_s_power(struct v4l2_subdev *sd, int on)
644 {
645 struct jx_h62 *jx_h62 = to_jx_h62(sd);
646 struct i2c_client *client = jx_h62->client;
647 int ret = 0;
648
649 mutex_lock(&jx_h62->mutex);
650
651 /* If the power state is not modified - no work to do. */
652 if (jx_h62->power_on == !!on)
653 goto unlock_and_return;
654
655 if (on) {
656 ret = pm_runtime_get_sync(&client->dev);
657 if (ret < 0) {
658 pm_runtime_put_noidle(&client->dev);
659 goto unlock_and_return;
660 }
661
662 ret = jx_h62_write_array(jx_h62->client,
663 jx_h62->cur_mode->reg_list);
664 if (ret)
665 goto unlock_and_return;
666
667 /*
668 * Enter sleep state to make sure not mipi output
669 * during rkisp init.
670 */
671 __jx_h62_stop_stream(jx_h62);
672
673 mutex_unlock(&jx_h62->mutex);
674 /* In case these controls are set before streaming */
675 ret = v4l2_ctrl_handler_setup(&jx_h62->ctrl_handler);
676 if (ret)
677 return ret;
678 mutex_lock(&jx_h62->mutex);
679
680 jx_h62->power_on = true;
681 } else {
682 pm_runtime_put(&client->dev);
683 jx_h62->power_on = false;
684 }
685
686 unlock_and_return:
687 mutex_unlock(&jx_h62->mutex);
688
689 return ret;
690 }
691
__jx_h62_power_on(struct jx_h62 * jx_h62)692 static int __jx_h62_power_on(struct jx_h62 *jx_h62)
693 {
694 int ret;
695 u32 delay_us;
696 struct device *dev = &jx_h62->client->dev;
697
698 ret = clk_set_rate(jx_h62->xvclk, JX_H62_XVCLK_FREQ);
699 if (ret < 0) {
700 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
701 return ret;
702 }
703 if (clk_get_rate(jx_h62->xvclk) != JX_H62_XVCLK_FREQ)
704 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
705 ret = clk_prepare_enable(jx_h62->xvclk);
706 if (ret < 0) {
707 dev_err(dev, "Failed to enable xvclk\n");
708 return ret;
709 }
710
711 if (!IS_ERR(jx_h62->reset_gpio))
712 gpiod_set_value_cansleep(jx_h62->reset_gpio, 1);
713
714 ret = regulator_bulk_enable(JX_H62_NUM_SUPPLIES, jx_h62->supplies);
715 if (ret < 0) {
716 dev_err(dev, "Failed to enable regulators\n");
717 goto disable_clk;
718 }
719
720 /* According to datasheet, at least 10ms for reset duration */
721 usleep_range(10 * 1000, 15 * 1000);
722
723 if (!IS_ERR(jx_h62->reset_gpio))
724 gpiod_set_value_cansleep(jx_h62->reset_gpio, 0);
725
726 if (!IS_ERR(jx_h62->pwdn_gpio))
727 gpiod_set_value_cansleep(jx_h62->pwdn_gpio, 0);
728
729 /* 8192 cycles prior to first SCCB transaction */
730 delay_us = jx_h62_cal_delay(8192);
731 usleep_range(delay_us, delay_us * 2);
732
733 return 0;
734
735 disable_clk:
736 clk_disable_unprepare(jx_h62->xvclk);
737
738 return ret;
739 }
740
__jx_h62_power_off(struct jx_h62 * jx_h62)741 static void __jx_h62_power_off(struct jx_h62 *jx_h62)
742 {
743 if (!IS_ERR(jx_h62->pwdn_gpio))
744 gpiod_set_value_cansleep(jx_h62->pwdn_gpio, 1);
745 clk_disable_unprepare(jx_h62->xvclk);
746 if (!IS_ERR(jx_h62->reset_gpio))
747 gpiod_set_value_cansleep(jx_h62->reset_gpio, 1);
748 regulator_bulk_disable(JX_H62_NUM_SUPPLIES, jx_h62->supplies);
749 }
750
jx_h62_runtime_resume(struct device * dev)751 static int jx_h62_runtime_resume(struct device *dev)
752 {
753 struct i2c_client *client = to_i2c_client(dev);
754 struct v4l2_subdev *sd = i2c_get_clientdata(client);
755 struct jx_h62 *jx_h62 = to_jx_h62(sd);
756
757 return __jx_h62_power_on(jx_h62);
758 }
759
jx_h62_runtime_suspend(struct device * dev)760 static int jx_h62_runtime_suspend(struct device *dev)
761 {
762 struct i2c_client *client = to_i2c_client(dev);
763 struct v4l2_subdev *sd = i2c_get_clientdata(client);
764 struct jx_h62 *jx_h62 = to_jx_h62(sd);
765
766 __jx_h62_power_off(jx_h62);
767
768 return 0;
769 }
770
771 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
jx_h62_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)772 static int jx_h62_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
773 {
774 struct jx_h62 *jx_h62 = to_jx_h62(sd);
775 struct v4l2_mbus_framefmt *try_fmt =
776 v4l2_subdev_get_try_format(sd, fh->pad, 0);
777 const struct jx_h62_mode *def_mode = &supported_modes[0];
778
779 mutex_lock(&jx_h62->mutex);
780 /* Initialize try_fmt */
781 try_fmt->width = def_mode->width;
782 try_fmt->height = def_mode->height;
783 try_fmt->code = JX_H62_MEDIA_BUS_FMT;
784 try_fmt->field = V4L2_FIELD_NONE;
785
786 mutex_unlock(&jx_h62->mutex);
787 /* No crop or compose */
788
789 return 0;
790 }
791 #endif
792
jx_h62_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)793 static int jx_h62_enum_frame_interval(struct v4l2_subdev *sd,
794 struct v4l2_subdev_pad_config *cfg,
795 struct v4l2_subdev_frame_interval_enum *fie)
796 {
797 if (fie->index >= ARRAY_SIZE(supported_modes))
798 return -EINVAL;
799
800 fie->code = JX_H62_MEDIA_BUS_FMT;
801 fie->width = supported_modes[fie->index].width;
802 fie->height = supported_modes[fie->index].height;
803 fie->interval = supported_modes[fie->index].max_fps;
804 return 0;
805 }
806
jx_h62_g_mbus_config(struct v4l2_subdev * sd,struct v4l2_mbus_config * config)807 static int jx_h62_g_mbus_config(struct v4l2_subdev *sd,
808 struct v4l2_mbus_config *config)
809 {
810 u32 val = 0;
811
812 val = 1 << (JX_H62_LANES - 1) |
813 V4L2_MBUS_CSI2_CHANNEL_0 |
814 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
815 config->type = V4L2_MBUS_CSI2;
816 config->flags = val;
817
818 return 0;
819 }
820
821 static const struct dev_pm_ops jx_h62_pm_ops = {
822 SET_RUNTIME_PM_OPS(jx_h62_runtime_suspend,
823 jx_h62_runtime_resume, NULL)
824 };
825
826 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
827 static const struct v4l2_subdev_internal_ops jx_h62_internal_ops = {
828 .open = jx_h62_open,
829 };
830 #endif
831
832 static const struct v4l2_subdev_core_ops jx_h62_core_ops = {
833 .s_power = jx_h62_s_power,
834 .ioctl = jx_h62_ioctl,
835 #ifdef CONFIG_COMPAT
836 .compat_ioctl32 = jx_h62_compat_ioctl32,
837 #endif
838 };
839
840 static const struct v4l2_subdev_video_ops jx_h62_video_ops = {
841 .s_stream = jx_h62_s_stream,
842 .g_frame_interval = jx_h62_g_frame_interval,
843 .g_mbus_config = jx_h62_g_mbus_config,
844 };
845
846 static const struct v4l2_subdev_pad_ops jx_h62_pad_ops = {
847 .enum_mbus_code = jx_h62_enum_mbus_code,
848 .enum_frame_size = jx_h62_enum_frame_sizes,
849 .enum_frame_interval = jx_h62_enum_frame_interval,
850 .get_fmt = jx_h62_get_fmt,
851 .set_fmt = jx_h62_set_fmt,
852 };
853
854 static const struct v4l2_subdev_ops jx_h62_subdev_ops = {
855 .core = &jx_h62_core_ops,
856 .video = &jx_h62_video_ops,
857 .pad = &jx_h62_pad_ops,
858 };
859
jx_h62_set_ctrl_gain(struct jx_h62 * jx_h62,u32 a_gain)860 static int jx_h62_set_ctrl_gain(struct jx_h62 *jx_h62, u32 a_gain)
861 {
862 int ret = 0;
863 u32 coarse_again, fine_again;
864
865 /* Total gain = 2^PGA[5:4]*(1+PGA[3:0]/16) */
866 if ( a_gain != jx_h62->old_gain) {
867 if (a_gain <= 0x20) { /*1x ~ 2x*/
868 fine_again = a_gain - 16;
869 coarse_again = (0x00 << 4);
870 } else if (a_gain <= 0x40) { /*2x ~ 4x*/
871 fine_again = (a_gain >> 1) - 16;
872 coarse_again = 0x01 << 4;
873 } else if (a_gain <= 0x80) { /*4x ~ 8x*/
874 fine_again = (a_gain >> 2) - 16;
875 coarse_again = 0x2 << 4;
876 } else { /*8x ~ 15.5x*/
877 fine_again = (a_gain >> 3) - 16;
878 coarse_again = 0x03 << 4;
879 }
880 ret = jx_h62_write_reg(jx_h62->client,
881 JX_H62_AEC_PK_LONG_GAIN_REG, coarse_again | fine_again);
882 jx_h62->old_gain = a_gain;
883 }
884 return ret;
885 }
886
jx_h62_set_ctrl(struct v4l2_ctrl * ctrl)887 static int jx_h62_set_ctrl(struct v4l2_ctrl *ctrl)
888 {
889 struct jx_h62 *jx_h62 = container_of(ctrl->handler,
890 struct jx_h62, ctrl_handler);
891 struct i2c_client *client = jx_h62->client;
892 s64 max;
893 int ret = 0;
894
895 /* Propagate change of current control to all related controls */
896 switch (ctrl->id) {
897 case V4L2_CID_VBLANK:
898 /* Update max exposure while meeting expected vblanking */
899 max = jx_h62->cur_mode->height + ctrl->val;
900 __v4l2_ctrl_modify_range(jx_h62->exposure,
901 jx_h62->exposure->minimum, max,
902 jx_h62->exposure->step,
903 jx_h62->exposure->default_value);
904 break;
905 }
906
907 if (pm_runtime_get(&client->dev) <= 0)
908 return 0;
909
910 switch (ctrl->id) {
911 case V4L2_CID_EXPOSURE:
912 dev_dbg(&client->dev, "set expo: val: %d\n", ctrl->val);
913 /* 4 least significant bits of expsoure are fractional part */
914 ret = jx_h62_write_reg(jx_h62->client,
915 JX_H62_AEC_PK_LONG_EXPO_HIGH_REG,
916 JX_H62_FETCH_HIGH_BYTE_EXP(ctrl->val));
917 ret |= jx_h62_write_reg(jx_h62->client,
918 JX_H62_AEC_PK_LONG_EXPO_LOW_REG,
919 JX_H62_FETCH_LOW_BYTE_EXP(ctrl->val));
920 break;
921 case V4L2_CID_ANALOGUE_GAIN:
922 dev_dbg(&client->dev, "set a-gain: val: %d\n", ctrl->val);
923 ret = jx_h62_set_ctrl_gain(jx_h62, ctrl->val);
924 break;
925 case V4L2_CID_DIGITAL_GAIN:
926 break;
927 case V4L2_CID_VBLANK:
928 dev_dbg(&client->dev, "set vblank: val: %d\n", ctrl->val);
929 ret |= jx_h62_write_reg(jx_h62->client, JX_H62_REG_HIGH_VTS,
930 JX_H62_FETCH_HIGH_BYTE_VTS((ctrl->val + jx_h62->cur_mode->height)));
931 ret |= jx_h62_write_reg(jx_h62->client, JX_H62_REG_LOW_VTS,
932 JX_H62_FETCH_LOW_BYTE_VTS((ctrl->val + jx_h62->cur_mode->height)));
933 break;
934 case V4L2_CID_TEST_PATTERN:
935 ret = jx_h62_enable_test_pattern(jx_h62, ctrl->val);
936 break;
937 default:
938 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
939 __func__, ctrl->id, ctrl->val);
940 break;
941 }
942
943 pm_runtime_put(&client->dev);
944
945 return ret;
946 }
947
948 static const struct v4l2_ctrl_ops jx_h62_ctrl_ops = {
949 .s_ctrl = jx_h62_set_ctrl,
950 };
951
jx_h62_initialize_controls(struct jx_h62 * jx_h62)952 static int jx_h62_initialize_controls(struct jx_h62 *jx_h62)
953 {
954 const struct jx_h62_mode *mode;
955 struct v4l2_ctrl_handler *handler;
956 struct v4l2_ctrl *ctrl;
957 s64 exposure_max, vblank_def;
958 u32 h_blank;
959 int ret;
960
961 handler = &jx_h62->ctrl_handler;
962 mode = jx_h62->cur_mode;
963 ret = v4l2_ctrl_handler_init(handler, 8);
964
965 if (ret)
966 return ret;
967 handler->lock = &jx_h62->mutex;
968
969 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
970 0, 0, link_freq_menu_items);
971
972 if (ctrl)
973 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
974
975 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
976 0, jx_h62->pixel_rate, 1, jx_h62->pixel_rate);
977
978 h_blank = mode->hts_def - mode->width;
979 jx_h62->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
980 h_blank, h_blank, 1, h_blank);
981
982 if (jx_h62->hblank)
983 jx_h62->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
984
985 vblank_def = mode->vts_def - mode->height;
986 jx_h62->vblank = v4l2_ctrl_new_std(handler, &jx_h62_ctrl_ops,
987 V4L2_CID_VBLANK, vblank_def,
988 JX_H62_VTS_MAX - mode->height,
989 1, vblank_def);
990
991 exposure_max = mode->vts_def;
992 //exposure_max = mode->vts_def - 4;
993 jx_h62->exposure = v4l2_ctrl_new_std(handler, &jx_h62_ctrl_ops,
994 V4L2_CID_EXPOSURE, JX_H62_EXPOSURE_MIN,
995 exposure_max, JX_H62_EXPOSURE_STEP,
996 mode->exp_def);
997
998 jx_h62->anal_gain = v4l2_ctrl_new_std(handler, &jx_h62_ctrl_ops,
999 V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1000 ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1001 ANALOG_GAIN_DEFAULT);
1002
1003 /* Digital gain */
1004 jx_h62->digi_gain = v4l2_ctrl_new_std(handler, &jx_h62_ctrl_ops,
1005 V4L2_CID_DIGITAL_GAIN, JX_H62_DIGI_GAIN_MIN,
1006 JX_H62_DIGI_GAIN_MAX, JX_H62_DIGI_GAIN_STEP,
1007 JX_H62_DIGI_GAIN_DEFAULT);
1008
1009 jx_h62->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1010 &jx_h62_ctrl_ops, V4L2_CID_TEST_PATTERN,
1011 ARRAY_SIZE(jx_h62_test_pattern_menu) - 1,
1012 0, 0, jx_h62_test_pattern_menu);
1013
1014 if (handler->error) {
1015 ret = handler->error;
1016 dev_err(&jx_h62->client->dev,
1017 "Failed to init controls(%d)\n", ret);
1018 goto err_free_handler;
1019 }
1020
1021 jx_h62->subdev.ctrl_handler = handler;
1022 jx_h62->old_gain = ANALOG_GAIN_DEFAULT;
1023
1024 return 0;
1025
1026 err_free_handler:
1027 v4l2_ctrl_handler_free(handler);
1028
1029 return ret;
1030 }
1031
jx_h62_check_sensor_id(struct jx_h62 * jx_h62,struct i2c_client * client)1032 static int jx_h62_check_sensor_id(struct jx_h62 *jx_h62,
1033 struct i2c_client *client)
1034 {
1035 struct device *dev = &jx_h62->client->dev;
1036 u8 id_h = 0;
1037 u8 id_l = 0;
1038 int ret;
1039
1040 ret = jx_h62_read_reg(client, JX_H62_PIDH_ADDR, &id_h);
1041 ret |= jx_h62_read_reg(client, JX_H62_PIDL_ADDR, &id_l);
1042 if (id_h != CHIP_ID_H && id_l != CHIP_ID_L) {
1043 dev_err(dev, "Wrong camera sensor id(0x%02x%02x)\n",
1044 id_h, id_l);
1045 return -EINVAL;
1046 }
1047
1048 dev_info(dev, "Detected jx_h62 (0x%02x%02x) sensor\n",
1049 id_h, id_l);
1050
1051 return ret;
1052 }
1053
jx_h62_configure_regulators(struct jx_h62 * jx_h62)1054 static int jx_h62_configure_regulators(struct jx_h62 *jx_h62)
1055 {
1056 unsigned int i;
1057
1058 for (i = 0; i < JX_H62_NUM_SUPPLIES; i++)
1059 jx_h62->supplies[i].supply = jx_h62_supply_names[i];
1060
1061 return devm_regulator_bulk_get(&jx_h62->client->dev,
1062 JX_H62_NUM_SUPPLIES,
1063 jx_h62->supplies);
1064 }
1065
jx_h62_parse_of(struct jx_h62 * jx_h62)1066 static int jx_h62_parse_of(struct jx_h62 *jx_h62)
1067 {
1068 struct device *dev = &jx_h62->client->dev;
1069 struct device_node *endpoint;
1070 struct fwnode_handle *fwnode;
1071 int rval;
1072
1073 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1074 if (!endpoint) {
1075 dev_err(dev, "Failed to get endpoint\n");
1076 return -EINVAL;
1077 }
1078 fwnode = of_fwnode_handle(endpoint);
1079 rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
1080 if (rval <= 0) {
1081 dev_warn(dev, " Get mipi lane num failed!\n");
1082 return -1;
1083 }
1084
1085 jx_h62->lane_num = rval;
1086 if (1 == jx_h62->lane_num) {
1087 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1088 jx_h62->pixel_rate = MIPI_FREQ * 2U * jx_h62->lane_num / 10U;
1089 dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
1090 jx_h62->lane_num, jx_h62->pixel_rate);
1091 } else {
1092 dev_err(dev, "unsupported lane_num(%d)\n", jx_h62->lane_num);
1093 return -1;
1094 }
1095
1096 return 0;
1097 }
1098
jx_h62_probe(struct i2c_client * client,const struct i2c_device_id * id)1099 static int jx_h62_probe(struct i2c_client *client,
1100 const struct i2c_device_id *id)
1101 {
1102 struct device *dev = &client->dev;
1103 struct device_node *node = dev->of_node;
1104 struct jx_h62 *jx_h62;
1105 struct v4l2_subdev *sd;
1106 char facing[2];
1107 int ret;
1108
1109 dev_info(dev, "driver version: %02x.%02x.%02x",
1110 DRIVER_VERSION >> 16,
1111 (DRIVER_VERSION & 0xff00) >> 8,
1112 DRIVER_VERSION & 0x00ff);
1113
1114 jx_h62 = devm_kzalloc(dev, sizeof(*jx_h62), GFP_KERNEL);
1115 if (!jx_h62)
1116 return -ENOMEM;
1117
1118 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1119 &jx_h62->module_index);
1120 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1121 &jx_h62->module_facing);
1122 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1123 &jx_h62->module_name);
1124 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1125 &jx_h62->len_name);
1126 if (ret) {
1127 dev_err(dev, "could not get module information!\n");
1128 return -EINVAL;
1129 }
1130
1131 jx_h62->client = client;
1132 jx_h62->cur_mode = &supported_modes[0];
1133
1134 jx_h62->xvclk = devm_clk_get(dev, "xvclk");
1135 if (IS_ERR(jx_h62->xvclk)) {
1136 dev_err(dev, "Failed to get xvclk\n");
1137 return -EINVAL;
1138 }
1139
1140 jx_h62->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1141 if (IS_ERR(jx_h62->reset_gpio))
1142 dev_warn(dev, "Failed to get reset-gpios\n");
1143
1144 jx_h62->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1145 if (IS_ERR(jx_h62->pwdn_gpio))
1146 dev_warn(dev, "Failed to get pwdn-gpios\n");
1147
1148 ret = jx_h62_configure_regulators(jx_h62);
1149 if (ret) {
1150 dev_err(dev, "Failed to get power regulators\n");
1151 return ret;
1152 }
1153 ret = jx_h62_parse_of(jx_h62);
1154 if (ret != 0)
1155 return -EINVAL;
1156
1157 jx_h62->pinctrl = devm_pinctrl_get(dev);
1158 if (!IS_ERR(jx_h62->pinctrl)) {
1159 jx_h62->pins_default =
1160 pinctrl_lookup_state(jx_h62->pinctrl,
1161 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1162 if (IS_ERR(jx_h62->pins_default))
1163 dev_err(dev, "could not get default pinstate\n");
1164
1165 jx_h62->pins_sleep =
1166 pinctrl_lookup_state(jx_h62->pinctrl,
1167 OF_CAMERA_PINCTRL_STATE_SLEEP);
1168 if (IS_ERR(jx_h62->pins_sleep))
1169 dev_err(dev, "could not get sleep pinstate\n");
1170 }
1171
1172 mutex_init(&jx_h62->mutex);
1173
1174 sd = &jx_h62->subdev;
1175 v4l2_i2c_subdev_init(sd, client, &jx_h62_subdev_ops);
1176 ret = jx_h62_initialize_controls(jx_h62);
1177 if (ret)
1178 goto err_destroy_mutex;
1179
1180 ret = __jx_h62_power_on(jx_h62);
1181 if (ret)
1182 goto err_free_handler;
1183
1184 ret = jx_h62_check_sensor_id(jx_h62, client);
1185 if (ret)
1186 goto err_power_off;
1187
1188 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1189 sd->internal_ops = &jx_h62_internal_ops;
1190 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1191 V4L2_SUBDEV_FL_HAS_EVENTS;
1192 #endif
1193 #if defined(CONFIG_MEDIA_CONTROLLER)
1194 jx_h62->pad.flags = MEDIA_PAD_FL_SOURCE;
1195 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1196 ret = media_entity_pads_init(&sd->entity, 1, &jx_h62->pad);
1197 if (ret < 0)
1198 goto err_power_off;
1199 #endif
1200
1201 memset(facing, 0, sizeof(facing));
1202 if (strcmp(jx_h62->module_facing, "back") == 0)
1203 facing[0] = 'b';
1204 else
1205 facing[0] = 'f';
1206
1207 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1208 jx_h62->module_index, facing,
1209 JX_H62_NAME, dev_name(sd->dev));
1210
1211 ret = v4l2_async_register_subdev(sd);
1212 if (ret) {
1213 dev_err(dev, "v4l2 async register subdev failed\n");
1214 goto err_clean_entity;
1215 }
1216
1217 pm_runtime_set_active(dev);
1218 pm_runtime_enable(dev);
1219 pm_runtime_idle(dev);
1220
1221 return 0;
1222
1223 err_clean_entity:
1224 #if defined(CONFIG_MEDIA_CONTROLLER)
1225 media_entity_cleanup(&sd->entity);
1226 #endif
1227 err_power_off:
1228 __jx_h62_power_off(jx_h62);
1229 err_free_handler:
1230 v4l2_ctrl_handler_free(&jx_h62->ctrl_handler);
1231 err_destroy_mutex:
1232 mutex_destroy(&jx_h62->mutex);
1233
1234 return ret;
1235 }
1236
jx_h62_remove(struct i2c_client * client)1237 static int jx_h62_remove(struct i2c_client *client)
1238 {
1239 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1240 struct jx_h62 *jx_h62 = to_jx_h62(sd);
1241
1242 v4l2_async_unregister_subdev(sd);
1243 #if defined(CONFIG_MEDIA_CONTROLLER)
1244 media_entity_cleanup(&sd->entity);
1245 #endif
1246 v4l2_ctrl_handler_free(&jx_h62->ctrl_handler);
1247 mutex_destroy(&jx_h62->mutex);
1248
1249 pm_runtime_disable(&client->dev);
1250 if (!pm_runtime_status_suspended(&client->dev))
1251 __jx_h62_power_off(jx_h62);
1252 pm_runtime_set_suspended(&client->dev);
1253
1254 return 0;
1255 }
1256
1257 #if IS_ENABLED(CONFIG_OF)
1258 static const struct of_device_id jx_h62_of_match[] = {
1259 { .compatible = "soi,jx_h62" },
1260 {},
1261 };
1262 MODULE_DEVICE_TABLE(of, jx_h62_of_match);
1263 #endif
1264
1265 static const struct i2c_device_id jx_h62_match_id[] = {
1266 { "soi,jx_h62", 0 },
1267 { },
1268 };
1269
1270 static struct i2c_driver jx_h62_i2c_driver = {
1271 .driver = {
1272 .name = JX_H62_NAME,
1273 .pm = &jx_h62_pm_ops,
1274 .of_match_table = of_match_ptr(jx_h62_of_match),
1275 },
1276 .probe = &jx_h62_probe,
1277 .remove = &jx_h62_remove,
1278 .id_table = jx_h62_match_id,
1279 };
1280
sensor_mod_init(void)1281 static int __init sensor_mod_init(void)
1282 {
1283 return i2c_add_driver(&jx_h62_i2c_driver);
1284 }
1285
sensor_mod_exit(void)1286 static void __exit sensor_mod_exit(void)
1287 {
1288 i2c_del_driver(&jx_h62_i2c_driver);
1289 }
1290
1291 device_initcall_sync(sensor_mod_init);
1292 module_exit(sensor_mod_exit);
1293
1294 MODULE_DESCRIPTION("SOI jx_h62 sensor driver by steven.ou");
1295 MODULE_LICENSE("GPL v2");
1296