1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /******************************************************************************** 3 * 4 * Copyright (C) 2017 NEXTCHIP Inc. All rights reserved. 5 * Module : Jaguar1 Device Driver 6 * Description : common.h 7 * Author : 8 * Date : 9 * Version : Version 1.0 10 * 11 ******************************************************************************** 12 * History : 13 * 14 * 15 ********************************************************************************/ 16 #ifndef __COMMON_H__ 17 #define __COMMON_H__ 18 19 unsigned char jaguar1_I2CReadByte8(unsigned char devaddress, unsigned char address); 20 void jaguar1_I2CWriteByte8(unsigned char devaddress, unsigned char address, unsigned char data); 21 #define gpio_i2c_read jaguar1_I2CReadByte8 22 #define gpio_i2c_write jaguar1_I2CWriteByte8 23 24 #define DRIVER_VER "1.1.7" 25 26 #define JAGUAR1_MAX_CHAN_CNT 4 27 28 extern unsigned int jaguar1_i2c_addr[4]; 29 30 #define HI_CHIPID_BASE 0x12050000 31 #define HI_CHIPID0 IO_ADDRESS(HI_CHIPID_BASE + 0xEEC) 32 #define HI_CHIPID1 IO_ADDRESS(HI_CHIPID_BASE + 0xEE8) 33 #define HI_CHIPID2 IO_ADDRESS(HI_CHIPID_BASE + 0xEE4) 34 #define HI_CHIPID3 IO_ADDRESS(HI_CHIPID_BASE + 0xEE0) 35 #define HW_REG(reg) *((volatile unsigned int *)(reg)) 36 37 #define _SET_BIT(data,bit) ((data)|=(1<<(bit))) 38 #define _CLE_BIT(data,bit) ((data)&=(~(1<<(bit)))) 39 40 #define JAGUAR1_BANK_CHANGE(bank) gpio_i2c_write(jaguar1_i2c_addr[0], 0xFF, bank ); 41 42 #define PORTA 0x00 43 #define PORTB 0x01 44 #define PORTC 0x02 45 #define PORTD 0x03 46 #define PORTAB 0x04 47 #define PORTCD 0x05 48 49 #define FUNC_ON 0x01 50 #define FUNC_OFF 0x00 51 52 #define BANK_0 0x00 53 #define BANK_1 0x01 54 #define BANK_2 0x02 55 #define BANK_3 0x03 56 #define BANK_4 0x04 57 #define BANK_5 0x05 58 #define BANK_A 0x0A 59 #define BANK_B 0x0B 60 #define BANK_11 0x11 61 #define BANK_13 0x13 62 #define BANK_20 0x20 63 #define BANK_21 0x21 64 #define BANK_22 0x22 65 66 67 typedef struct _decoder_get_information_str 68 { 69 unsigned char chip_id[4]; 70 unsigned char chip_rev[4]; 71 unsigned char chip_addr[4]; 72 73 unsigned char Total_Port_Num; 74 unsigned char Total_Chip_Cnt; 75 76 }decoder_get_information_str; 77 78 typedef struct _decoder_dev_ch_info_s 79 { 80 unsigned char ch; 81 unsigned char devnum; 82 unsigned char fmt_def; 83 }decoder_dev_ch_info_s; 84 85 86 typedef enum NC_FORMAT_FPS 87 { 88 FMT_FPS_UNKNOWN = 0, 89 FMT_NT = 1, 90 FMT_PAL, 91 FMT_12_5P, 92 FMT_7_5P, 93 FMT_30P, 94 FMT_25P, 95 FMT_50P, 96 FMT_60P, 97 FMT_15P, 98 FMT_18P, 99 FMT_18_75P, 100 FMT_20P, 101 102 FMT_FPS_MAX, 103 104 } NC_FORMAT_FPS; 105 106 //#define FMT_AUTO (-1) 107 108 typedef enum NC_FORMAT_STANDARD 109 { 110 FMT_STD_UNKNOWN = 0, 111 FMT_SD, 112 FMT_AHD20, 113 FMT_AHD30, 114 FMT_TVI, 115 FMT_CVI, 116 117 FMT_AUTO, // FIXME 118 119 FMT_STD_MAX, 120 121 } NC_FORMAT_STANDARD; 122 123 124 typedef enum NC_FORMAT_RESOLUTION 125 { 126 FMT_RESOL_UNKNOWN = 0, 127 FMT_SH720, 128 FMT_H960, 129 FMT_H1280, 130 FMT_H1440, 131 FMT_H960_EX, 132 FMT_H960_2EX, 133 FMT_H960_Btype_2EX, 134 FMT_720P, 135 FMT_720P_EX, 136 FMT_720P_Btype, 137 FMT_720P_Btype_EX, 138 FMT_1080P, 139 FMT_3M, 140 FMT_4M, 141 FMT_5M, 142 FMT_5_3M, 143 FMT_6M, 144 FMT_8M_X, 145 FMT_8M, 146 FMT_960P, 147 148 FMT_H960_Btype_2EX_SP, 149 FMT_720P_Btype_EX_SP, 150 151 FMT_RESOL_MAX, 152 } NC_FORMAT_RESOLUTION; 153 154 155 typedef enum NC_VIVO_CH_FORMATDEF 156 { 157 NC_VIVO_CH_FORMATDEF_UNKNOWN = 0, 158 NC_VIVO_CH_FORMATDEF_AUTO, 159 160 AHD20_SD_H960_NT, 161 AHD20_SD_H960_PAL, 162 AHD20_SD_SH720_NT, 163 AHD20_SD_SH720_PAL, 164 AHD20_SD_H1280_NT, 165 AHD20_SD_H1280_PAL, 166 AHD20_SD_H1440_NT, 167 AHD20_SD_H1440_PAL, 168 AHD20_SD_H960_EX_NT, 169 AHD20_SD_H960_EX_PAL, 170 AHD20_SD_H960_2EX_NT, 171 AHD20_SD_H960_2EX_PAL, 172 AHD20_SD_H960_2EX_Btype_NT, 173 AHD20_SD_H960_2EX_Btype_PAL, 174 AHD20_1080P_60P, // For Test 175 AHD20_1080P_50P, // For Test 176 AHD20_1080P_30P, 177 AHD20_1080P_25P, 178 AHD20_720P_60P, 179 AHD20_720P_50P, 180 AHD20_720P_30P, 181 AHD20_720P_25P, 182 AHD20_720P_30P_EX, 183 AHD20_720P_25P_EX, 184 AHD20_720P_30P_EX_Btype, 185 AHD20_720P_25P_EX_Btype, 186 AHD20_720P_960P_30P, 187 AHD20_720P_960P_25P, 188 189 AHD30_4M_30P, 190 AHD30_4M_25P, 191 AHD30_4M_15P, 192 AHD30_3M_30P, 193 AHD30_3M_25P, 194 AHD30_3M_18P, 195 AHD30_5M_12_5P, 196 AHD30_5M_20P, 197 AHD30_5_3M_20P, 198 AHD30_6M_18P, 199 AHD30_6M_20P, 200 AHD30_8M_X_30P, 201 AHD30_8M_X_25P, 202 AHD30_8M_7_5P, 203 AHD30_8M_12_5P, 204 AHD30_8M_15P, 205 206 TVI_FHD_30P, 207 TVI_FHD_25P, 208 TVI_HD_60P, 209 TVI_HD_50P, 210 TVI_HD_30P, 211 TVI_HD_25P, 212 TVI_HD_30P_EX, 213 TVI_HD_25P_EX, 214 TVI_HD_B_30P, 215 TVI_HD_B_25P, 216 TVI_HD_B_30P_EX, 217 TVI_HD_B_25P_EX, 218 TVI_3M_18P, 219 TVI_5M_12_5P, 220 TVI_4M_30P, 221 TVI_4M_25P, 222 TVI_4M_15P, 223 224 CVI_FHD_30P, 225 CVI_FHD_25P, 226 CVI_HD_60P, 227 CVI_HD_50P, 228 CVI_HD_30P, 229 CVI_HD_25P, 230 CVI_HD_30P_EX, 231 CVI_HD_25P_EX, 232 CVI_4M_30P, 233 CVI_4M_25P, 234 CVI_8M_15P, 235 CVI_8M_12_5P, 236 237 AHD20_SD_H960_2EX_Btype_SP_NT, 238 AHD20_SD_H960_2EX_Btype_SP_PAL, 239 240 AHD20_720P_30P_EX_Btype_SP, 241 AHD20_720P_25P_EX_Btype_SP, 242 243 NC_VIVO_CH_FORMATDEF_MAX, 244 245 } NC_VIVO_CH_FORMATDEF; 246 247 typedef enum NC_OUTPUT_MUX_MODE 248 { 249 NC_MX_MUX1 = 0, 250 NC_MX_MUX2, 251 NC_MX_MUX4, 252 } NC_OUTPUT_MUX_MODE; 253 254 typedef enum NC_OUTPUT_INTERFACE 255 { 256 NC_OI_BT656 = 0, /* ITU-R BT.656 YUV4:2:2 */ 257 NC_OI_BT601, /* ITU-R BT.601 YUV4:2:2 */ 258 NC_OI_DIGITAL_CAMERA, /* digatal camera mode */ 259 NC_OI_BT1120_STANDARD, /* BT.1120 progressive mode */ 260 NC_OI_BT1120_INTERLEAVED, /* BT.1120 interstage mode */ 261 } NC_OUTPUT_INTERFACE; 262 263 typedef enum NC_OUTPUT_EDGE 264 { 265 NC_OE_SINGLE_UP = 0, /* single-edge mode and in rising edge */ 266 NC_OE_SINGLE_DOWN, /* single-edge mode and in falling edge */ 267 NC_OE_DOUBLE , 268 } NC_OUTPUT_EDGE; 269 270 271 272 typedef enum NC_ANALOG_INPUT 273 { 274 SINGLE_ENDED = 0, 275 DIFFERENTIAL, 276 } NC_ANALOG_INPUT; 277 278 typedef enum NC_CABLE 279 { 280 CABLE_A = 0, 281 CABLE_B, 282 CABLE_C, 283 CABLE_D, 284 } NC_CABLE; 285 286 typedef enum NC_STAGE 287 { 288 STAGE_0 = 0, 289 STAGE_1, 290 STAGE_2, 291 STAGE_3, 292 STAGE_4, 293 STAGE_5, 294 } NC_STAGE; 295 296 typedef enum NC_JAGUAR1_EQ 297 { 298 NC_EQ_SETTING_FMT_UNKNOWN = 0, 299 300 AHD20_SD_H720_NT_SINGLE_ENDED, 301 AHD20_SD_H720_NT_DIFFERENTIAL, 302 AHD20_SD_H720_PAL_SINGLE_ENDED, 303 AHD20_SD_H720_PAL_DIFFERENTIAL, 304 305 AHD20_SD_H960_2EX_Btype_NT_SINGLE_ENDED, 306 AHD20_SD_H960_2EX_Btype_NT_DIFFERENTIAL, 307 AHD20_SD_H960_2EX_Btype_PAL_SINGLE_ENDED, 308 AHD20_SD_H960_2EX_Btype_PAL_DIFFERENTIAL, 309 310 AHD20_SD_H1440_NT_SINGLE_ENDED, 311 AHD20_SD_H1440_NT_DIFFERENTIAL, 312 AHD20_SD_H1440_PAL_SINGLE_ENDED, 313 AHD20_SD_H1440_PAL_DIFFERENTIAL, 314 315 AHD20_1080P_30P_SINGLE_ENDED, 316 AHD20_1080P_30P_DIFFERENTIAL, 317 AHD20_1080P_25P_SINGLE_ENDED, 318 AHD20_1080P_25P_DIFFERENTIAL, 319 320 AHD20_720P_60P_SINGLE_ENDED, 321 AHD20_720P_60P_DIFFERENTIAL, 322 AHD20_720P_50P_SINGLE_ENDED, 323 AHD20_720P_50P_DIFFERENTIAL, 324 325 AHD20_720P_30P_SINGLE_ENDED, 326 AHD20_720P_30P_DIFFERENTIAL, 327 AHD20_720P_25P_SINGLE_ENDED, 328 AHD20_720P_25P_DIFFERENTIAL, 329 330 AHD20_720P_30P_EX_SINGLE_ENDED, 331 AHD20_720P_30P_EX_DIFFERENTIAL, 332 AHD20_720P_25P_EX_SINGLE_ENDED, 333 AHD20_720P_25P_EX_DIFFERENTIAL, 334 335 AHD20_720P_30P_EX_Btype_SINGLE_ENDED, 336 AHD20_720P_30P_EX_Btype_DIFFERENTIAL, 337 AHD20_720P_25P_EX_Btype_SINGLE_ENDED, 338 AHD20_720P_25P_EX_Btype_DIFFERENTIAL, 339 340 AHD20_960P_30P_SINGLE_ENDED, 341 AHD20_960P_30P_DIFFERENTIAL, 342 AHD20_960P_25P_SINGLE_ENDED, 343 AHD20_960P_25P_DIFFERENTIAL, 344 345 TVI_FHD_30P_SINGLE_ENDED, 346 TVI_FHD_30P_DIFFERENTIAL, 347 TVI_FHD_25P_SINGLE_ENDED, 348 TVI_FHD_25P_DIFFERENTIAL, 349 350 TVI_HD_60P_SINGLE_ENDED, 351 TVI_HD_60P_DIFFERENTIAL, 352 TVI_HD_50P_SINGLE_ENDED, 353 TVI_HD_50P_DIFFERENTIAL, 354 355 TVI_HD_30P_SINGLE_ENDED, 356 TVI_HD_30P_DIFFERENTIAL, 357 TVI_HD_25P_SINGLE_ENDED, 358 TVI_HD_25P_DIFFERENTIAL, 359 360 TVI_HD_30P_EX_SINGLE_ENDED, 361 TVI_HD_30P_EX_DIFFERENTIAL, 362 TVI_HD_25P_EX_SINGLE_ENDED, 363 TVI_HD_25P_EX_DIFFERENTIAL, 364 365 TVI_HD_B_30P_SINGLE_ENDED, 366 TVI_HD_B_30P_DIFFERENTIAL, 367 TVI_HD_B_25P_SINGLE_ENDED, 368 TVI_HD_B_25P_DIFFERENTIAL, 369 370 TVI_HD_B_30P_EX_SINGLE_ENDED, 371 TVI_HD_B_30P_EX_DIFFERENTIAL, 372 TVI_HD_B_25P_EX_SINGLE_ENDED, 373 TVI_HD_B_25P_EX_DIFFERENTIAL, 374 375 CVI_FHD_30P_SINGLE_ENDED, 376 CVI_FHD_30P_DIFFERENTIAL, 377 CVI_FHD_25P_SINGLE_ENDED, 378 CVI_FHD_25P_DIFFERENTIAL, 379 380 CVI_HD_60P_SINGLE_ENDED, 381 CVI_HD_60P_DIFFERENTIAL, 382 CVI_HD_50P_SINGLE_ENDED, 383 CVI_HD_50P_DIFFERENTIAL, 384 385 CVI_HD_30P_SINGLE_ENDED, 386 CVI_HD_30P_DIFFERENTIAL, 387 CVI_HD_25P_SINGLE_ENDED, 388 CVI_HD_25P_DIFFERENTIAL, 389 390 CVI_HD_30P_EX_SINGLE_ENDED, 391 CVI_HD_30P_EX_DIFFERENTIAL, 392 CVI_HD_25P_EX_SINGLE_ENDED, 393 CVI_HD_25P_EX_DIFFERENTIAL, 394 395 NC_EQ_SETTING_FMT_MAX, 396 397 398 }NC_JAGUAR1_EQ; 399 400 typedef enum NC_D2S_OUTPUT_INTERFACE 401 { 402 DISABLE = 0, 403 YUV_422, 404 YUV_420, 405 YUV_420_LEGACY, 406 } NC_D2S_OUTPUT_INTERFACE; 407 408 typedef struct _NC_DEOCDER_SET_STR 409 { 410 NC_VIVO_CH_FORMATDEF FmtDef; 411 NC_FORMAT_STANDARD fmt_std; 412 NC_FORMAT_RESOLUTION fmt_res; 413 NC_FORMAT_FPS fmt_fps; 414 NC_ANALOG_INPUT input; 415 NC_D2S_OUTPUT_INTERFACE interface; 416 }NC_DEOCDER_SET_STR; 417 418 #define UNUSED(x) ((void)(x)) 419 420 #if 0 421 #define dbg_printk(...) _kernel_dbg_printk( __VA_ARGS__) 422 423 static void _kernel_dbg_printk(const char* s, ...) 424 { 425 unsigned char buffer[128]; 426 char *pS = buffer; 427 428 va_list args; 429 va_start(args, s); 430 vsprintf(buffer, s, args); 431 va_end(args); 432 433 434 while(*pS) { if( *pS == '\n' ) *pS= ' '; pS++; } 435 436 printk("\033[33m\033[1m [KERNEL] \033[0m:\033[32m\033[1m %s \033[0m\n", buffer); 437 } 438 #endif 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 #endif 454 455