1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * IMX492 driver
4 *
5 * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version
8 * V0.0X01.0X01 add conversion gain control
9 * V0.0X01.0X02 add debug interface for conversion gain control
10 * V0.0X01.0X03 support enum sensor fmt
11 */
12
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/sysfs.h>
22 #include <linux/slab.h>
23 #include <linux/version.h>
24 #include <linux/rk-camera-module.h>
25 #include <media/media-entity.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-subdev.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-mediabus.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/rk-preisp.h>
33 #include <linux/of_graph.h>
34
35 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x03)
36
37 #ifndef V4L2_CID_DIGITAL_GAIN
38 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
39 #endif
40
41 #define MIPI_FREQ_864M 864000000
42
43
44 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
45
46 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
47 #define IMX492_10BIT_PIXEL_RATE (MIPI_FREQ_864M * 2 / 10 * 4)
48
49
50 #define CHIP_ID 0xE6
51 #define IMX492_REG_CHIP_ID 0x3084
52
53 #define IMX492_REG_CTRL_STANDBY 0x3000
54 #define IMX492_REG_CTRL_CLKEN 0x35e5
55 #define IMX492_REG_CTRL_XMSTA 0x3033
56 #define IMX492_REG_CTRL_SYNCDRV 0x3017
57
58 #define IMX492_AGAIN_REG_L 0x300a
59 #define IMX492_AGAIN_REG_H 0x300b
60 #define IMX492_DGAIN_REG 0x3012
61 #define IMX492_GAIN_MIN 0x600
62 #define IMX492_GAIN_MAX 0x1e94
63 #define IMX492_GAIN_STEP 1
64 #define IMX492_GAIN_DEFAULT 0x600
65 #define IMX492_FETCH_GAIN_H(VAL) (((VAL) >> 8) & 0x07)
66 #define IMX492_FETCH_GAIN_L(VAL) ((VAL) & 0xFF)
67
68 #define IMX492_VTS_REG_L 0x30a9
69 #define IMX492_VTS_REG_M 0x30aA
70 #define IMX492_VTS_REG_H 0x30aB
71 #define IMX492_VTS_MAX 0x7fff
72 #define IMX492_FETCH_VTS_H(VAL) (((VAL) >> 16) & 0x07)
73 #define IMX492_FETCH_VTS_M(VAL) (((VAL) >> 8) & 0xFF)
74 #define IMX492_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
75
76
77 #define IMX492_EXPO_REG_L 0x302c
78 #define IMX492_EXPO_REG_H 0x302d
79 #define IMX492_EXPO_SVR_L 0X300e
80 #define IMX492_EXPO_SVR_H 0X300f
81 #define IMX492_EXPOSURE_MIN 12
82 #define IMX492_EXPOSURE_STEP 1
83 #define IMX492_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
84 #define IMX492_FETCH_EXP_H(VAL) (((VAL) >> 8) & 0xFF)
85
86
87 #define IMX492_GROUP_HOLD_REG 0x3001
88 #define IMX492_GROUP_HOLD_START 0x01
89 #define IMX492_GROUP_HOLD_END 0x00
90
91 #define REG_NULL 0xFFFF
92 #define DELAY_MS 0xEEEE
93
94 #define IMX492_REG_VALUE_08BIT 1
95 #define IMX492_REG_VALUE_16BIT 2
96 #define IMX492_REG_VALUE_24BIT 3
97
98 #define IMX492_VREVERSE_REG 0x304f
99 #define IMX492_HREVERSE_REG 0x304e
100
101 #define USED_SYS_DEBUG
102
103 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
104 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
105
106 #define IMX492_NAME "imx492"
107
108 static const char * const imx492_supply_names[] = {
109 "avdd", /* Analog power */
110 "dovdd", /* Digital I/O power */
111 "dvdd", /* Digital core power */
112 };
113
114 #define IMX492_NUM_SUPPLIES ARRAY_SIZE(imx492_supply_names)
115
116 struct regval {
117 u16 addr;
118 u8 val;
119 };
120
121 struct imx492_mode {
122 u32 bus_fmt;
123 u32 width;
124 u32 height;
125 struct v4l2_fract max_fps;
126 u32 hts_def;
127 u32 vts_def;
128 u32 exp_def;
129 u32 mipi_freq_idx;
130 u32 mclk;
131 u32 bpp;
132 const struct regval *reg_list;
133 u32 hdr_mode;
134 u32 vc[PAD_MAX];
135 };
136
137 struct imx492 {
138 struct i2c_client *client;
139 struct clk *xvclk;
140 struct gpio_desc *reset_gpio;
141 struct gpio_desc *pwdn_gpio;
142 struct regulator_bulk_data supplies[IMX492_NUM_SUPPLIES];
143
144 struct pinctrl *pinctrl;
145 struct pinctrl_state *pins_default;
146 struct pinctrl_state *pins_sleep;
147
148 struct v4l2_subdev subdev;
149 struct media_pad pad;
150 struct v4l2_ctrl_handler ctrl_handler;
151 struct v4l2_ctrl *exposure;
152 struct v4l2_ctrl *anal_a_gain;
153 struct v4l2_ctrl *digi_gain;
154 struct v4l2_ctrl *hblank;
155 struct v4l2_ctrl *vblank;
156 struct v4l2_ctrl *pixel_rate;
157 struct v4l2_ctrl *link_freq;
158 struct mutex mutex;
159 struct v4l2_fwnode_endpoint bus_cfg;
160 bool streaming;
161 bool power_on;
162 bool has_init_exp;
163 const struct imx492_mode *support_modes;
164 const struct imx492_mode *cur_mode;
165 u32 module_index;
166 u32 cfg_num;
167 u32 cur_vts;
168 u32 cur_mclk;
169 const char *module_facing;
170 const char *module_name;
171 const char *len_name;
172 enum rkmodule_sync_mode sync_mode;
173 struct preisp_hdrae_exp_s init_hdrae_exp;
174 bool isHCG;
175 };
176
177 #define to_IMX492(sd) container_of(sd, struct imx492, subdev)
178
179 static const struct regval imx492_linear_12bit_8192x4320_4lane_mode1_regs[] = {
180 {0x3033, 0x30},
181 {0x303C, 0x01}, //SYS_MODE[1:0]
182 {0x31E8, 0x20}, //PLRD1
183 {0x31E9, 0x01},
184 {0x3122, 0x02}, //PLRD2
185 {0x3129, 0x90}, //PLRD3
186 {0x312A, 0x02}, //PLRD4
187 {0x311F, 0x00}, //PLRD10
188 {0x3123, 0x00}, //PLRD11
189 {0x3124, 0x00}, //PLRD12
190 {0x3125, 0x01}, //PLRD13
191 {0x3127, 0x02}, //PLRD14
192 {0x312D, 0x02}, //PLRD15
193 {0x3000, 0x12},
194 {0x310b, 0x00},
195 {0x3004, 0x1C},
196 {0x3005, 0x06},
197 {0x3006, 0x00},
198 {0x3007, 0xA7},
199 {0x300A, 0xff}, //Again
200 {0x300B, 0x00},
201 {0x300E, 0x00}, //SVR
202 {0x300F, 0x00},
203 {0x3012, 0x03}, //Dgain
204 {0x3017, 0xab},
205 {0x302C, 0x0F}, //SHR
206 {0x302D, 0x00}, //SHR
207 {0x3042, 0x32},
208 {0x3043, 0x00},
209 {0x3047, 0x02},
210 {0x304E, 0x0B},
211 {0x304F, 0x2A},
212 {0x3052, 0xEE},
213 {0x3062, 0x25},
214 {0x3064, 0x78},
215 {0x3065, 0x33},
216 {0x3066, 0x64},
217 {0x3067, 0x71},
218 {0x3081, 0x00},
219 {0x3084, 0x00},
220 {0x3085, 0x00},
221 {0x3086, 0x00},
222 {0x3087, 0x00},
223 {0x3088, 0x75},
224 {0x308A, 0x09},
225 {0x308C, 0x61},
226 {0x30A9, 0x4c}, //VMA
227 {0x30AA, 0x11},
228 {0x30AB, 0x00},
229 {0x30AC, 0xb2}, //HMA
230 {0x30AD, 0x04},
231 {0x30E5, 0x00},
232 {0x30EF, 0x01},
233 {0x312F, 0x20},
234 {0x3130, 0x1C},
235 {0x3131, 0x11},
236 {0x3132, 0xFC},
237 {0x3133, 0x10},
238 {0x3134, 0xAF},
239 {0x3136, 0xC7},
240 {0x3138, 0x7F},
241 {0x313A, 0x6F},
242 {0x313C, 0x6F},
243 {0x313E, 0xCF},
244 {0x3140, 0x77},
245 {0x3142, 0x5F},
246 {0x3146, 0x00},
247 {0x31F5, 0x01},
248 {0x3234, 0x32},
249 {0x3248, 0xBC},
250 {0x3250, 0xBC},
251 {0x3258, 0xBC},
252 {0x3260, 0xBC},
253 {0x3274, 0x13},
254 {0x3276, 0x00},
255 {0x3277, 0x00},
256 {0x327C, 0x13},
257 {0x327E, 0x00},
258 {0x327F, 0x00},
259 {0x3284, 0x13},
260 {0x3286, 0x00},
261 {0x3287, 0x00},
262 {0x328C, 0x13},
263 {0x328E, 0x00},
264 {0x328F, 0x00},
265 {0x32AE, 0x00},
266 {0x32AF, 0x00},
267 {0x32CA, 0x5A},
268 {0x332C, 0x00},
269 {0x332D, 0x00},
270 {0x332F, 0x00},
271 {0x334A, 0x00},
272 {0x334B, 0x00},
273 {0x334C, 0x01},
274 {0x3352, 0x50},
275 {0x3356, 0x4F},
276 {0x335A, 0x79},
277 {0x335E, 0x56},
278 {0x3360, 0x6A},
279 {0x336A, 0x56},
280 {0x33D6, 0x79},
281 {0x340C, 0x6E},
282 {0x3448, 0x7E},
283 {0x348E, 0x6F},
284 {0x3492, 0x11},
285 {0x34C4, 0x5A},
286 {0x3506, 0x56},
287 {0x350C, 0x56},
288 {0x350E, 0x58},
289 {0x353D, 0x10},
290 {0x3549, 0x04},
291 {0x355D, 0x03},
292 {0x355E, 0x03},
293 {0x3574, 0x56},
294 {0x357F, 0x0C},
295 {0x3580, 0x0A},
296 {0x3581, 0x08},
297 {0x3583, 0x72},
298 {0x3587, 0x01},
299 {0x35D0, 0x5E},
300 {0x35D4, 0x63},
301 {0x35E5, 0x9A},
302 {0x366A, 0x04},
303 {0x366B, 0x04},
304 {0x366C, 0x00},
305 {0x366D, 0x00},
306 {0x366E, 0x00},
307 {0x366F, 0x00},
308 {0x3670, 0x00},
309 {0x3671, 0x05},
310 {0x3676, 0x83},
311 {0x3677, 0x03},
312 {0x3678, 0x00},
313 {0x3679, 0x04},
314 {0x367A, 0x2C},
315 {0x367B, 0x05},
316 {0x367D, 0x06},
317 {0x367E, 0xFF},
318 {0x367F, 0x06},
319 {0x3680, 0x4B},
320 {0x3688, 0x05},
321 {0x3690, 0x27},
322 {0x3692, 0x65},
323 {0x3694, 0x4F},
324 {0x3696, 0xA1},
325 {0x371C, 0x02},
326 {0x372F, 0x3C},
327 {0x3730, 0x01},
328 {0x3732, 0xB8},
329 {0x3734, 0x4A},
330 {0x3736, 0x57},
331 {0x3738, 0x4D},
332 {0x3744, 0x0F},
333 {0x375B, 0x01},
334 {0x382B, 0x68},
335 {0x38B3, 0x00},
336 {0x3A43, 0x00},
337 {0x3A54, 0xF0},
338 {0x3A55, 0x20},
339 {0x3AC4, 0x00},
340 {0x3C08, 0x3F},
341 {0x3C0C, 0x1B},
342 {0x3E80, 0x14},
343 {0x3E82, 0x30},
344 {0x3E84, 0x0C},
345 {0x3E85, 0x06},
346 {0x3E86, 0xFC},
347 {0x3E87, 0x10},
348 {0x3E88, 0x03},
349 {0x3E89, 0xFE},
350 {0x3E8A, 0x01},
351 {0x3E8B, 0x06},
352 {0x3E8E, 0x03},
353 {0x3E8F, 0xFE},
354 {0x3E90, 0x01},
355 {0x3E91, 0x06},
356 {0x3E94, 0x33},
357 {0x3E95, 0x01},
358 {0x3E96, 0x19},
359 {0x3E98, 0x30},
360 {0x3E9A, 0x11},
361 {0x3E9B, 0x06},
362 {0x3E9C, 0xFC},
363 {0x3E9D, 0x10},
364 {0x3E9E, 0xFE},
365 {0x3E9F, 0x03},
366 {0x3EA0, 0x06},
367 {0x3EA3, 0x01},
368 {0x3EA4, 0xFE},
369 {0x3EA5, 0x03},
370 {0x3EA6, 0x06},
371 {0x3EA9, 0x33},
372 {0x3EAA, 0x00},
373 {0x3EAB, 0x08},
374 {0x3EAC, 0x08},
375 {0x3EAD, 0x01},
376 {0x3EAE, 0x08},
377 {0x3EAF, 0x08},
378 {0x3EB0, 0x00},
379 {0x3EB1, 0x10},
380 {0x3EB2, 0x10},
381 {0x3EB3, 0x01},
382 {0x3EB4, 0x10},
383 {0x3EB5, 0x10},
384 {0x3EB6, 0x00},
385 {0x3EB7, 0x00},
386 {0x3EB8, 0x00},
387 {0x3EB9, 0x00},
388 {0x3EBA, 0x00},
389 {0x3EBB, 0x00},
390 {0x3EC0, 0x54},
391 {0x3ECC, 0x04},
392 {0x3ECD, 0x04},
393 {0x3ED0, 0xF0},
394 {0x3ED1, 0x20},
395 {0x3ED2, 0x0B},
396 {0x3ED3, 0x04},
397 {0x3ED5, 0x13},
398 {0x3ED6, 0x00},
399 {0x3ED9, 0x0F},
400 {0x3EE4, 0x02},
401 {0x3EE5, 0x02},
402 {0x3EE7, 0x00},
403 {0x3EF6, 0x00},
404 {0x3EF8, 0x10},
405 {0x3EFA, 0x00},
406 {0x3EFC, 0x10},
407 {DELAY_MS, 20},
408 {0x3000, 0x02},
409 {0x35E5, 0x92},
410 {0x35E5, 0x9a},
411 {REG_NULL, 0x00},
412 };
413
414 static const struct regval imx492_linear_10bit_8192x4320_4lane_mode2_regs[] = {
415 {0x3033, 0x30},
416 {0x303C, 0x01}, //SYS_MODE[1:0]
417 {0x31E8, 0x20}, //PLRD1
418 {0x31E9, 0x01},
419 {0x3122, 0x02}, //PLRD2
420 {0x3129, 0x90}, //PLRD3
421 {0x312A, 0x02}, //PLRD4
422 {0x311F, 0x00}, //PLRD10
423 {0x3123, 0x00}, //PLRD11
424 {0x3124, 0x00}, //PLRD12
425 {0x3125, 0x01}, //PLRD13
426 {0x3127, 0x02}, //PLRD14
427 {0x312D, 0x02}, //PLRD15
428 {0x3000, 0x12},
429 {0x310b, 0x00},
430 {0x3004, 0x1C},
431 {0x3005, 0x01},
432 {0x3006, 0x00},
433 {0x3007, 0xA7},
434 {0x300A, 0xfa}, //Again
435 {0x300B, 0x00},
436 {0x300E, 0x00}, //SVR
437 {0x300F, 0x00},
438 {0x3012, 0x03}, //Dgain
439 {0x3017, 0xab},
440 {0x302C, 0x0F}, //SHR
441 {0x302D, 0x00}, //SHR
442 {0x3042, 0x32},
443 {0x3043, 0x00},
444 {0x3047, 0x01},
445 {0x304E, 0x0B},
446 {0x304F, 0x24},
447 {0x3062, 0x25},
448 {0x3064, 0x78},
449 {0x3065, 0x33},
450 {0x3067, 0x71},
451 {0x3068, 0x44},
452 {0x3081, 0x00},
453 {0x3084, 0x00},
454 {0x3085, 0x00},
455 {0x3086, 0x00},
456 {0x3087, 0x00},
457 {0x3088, 0x75},
458 {0x308A, 0x09},
459 {0x308C, 0x61},
460 {0x30A9, 0x4c}, //VMAX
461 {0x30AA, 0x11},
462 {0x30AB, 0x00},
463 {0x30AC, 0x98}, //HMAX
464 {0x30AD, 0x03},
465 {0x30E5, 0x00},
466 {0x30EF, 0x01},
467 {0x312F, 0x20},
468 {0x3130, 0x1C},
469 {0x3131, 0x11},
470 {0x3132, 0xFC},
471 {0x3133, 0x10},
472 {0x3134, 0xAF},
473 {0x3136, 0xC7},
474 {0x3138, 0x7F},
475 {0x313A, 0x6F},
476 {0x313C, 0x6F},
477 {0x313E, 0xCF},
478 {0x3140, 0x77},
479 {0x3142, 0x5F},
480 {0x3146, 0x00},
481 {0x31F5, 0x01},
482 {0x3234, 0x32},
483 {0x3248, 0xBC},
484 {0x3250, 0xBC},
485 {0x3258, 0xBC},
486 {0x3260, 0xBC},
487 {0x3274, 0x13},
488 {0x3276, 0x00},
489 {0x3277, 0x00},
490 {0x327C, 0x13},
491 {0x327E, 0x00},
492 {0x327F, 0x00},
493 {0x3284, 0x13},
494 {0x3286, 0x00},
495 {0x3287, 0x00},
496 {0x328C, 0x13},
497 {0x328E, 0x00},
498 {0x328F, 0x00},
499 {0x32AE, 0x00},
500 {0x32AF, 0x00},
501 {0x32CA, 0x5A},
502 {0x332C, 0x00}, //PSSLVS1
503 {0x332D, 0x00},
504 {0x332F, 0x00},
505 {0x334A, 0x00}, //PSSLVS2
506 {0x334B, 0x00},
507 {0x334C, 0x01},
508 {0x335A, 0x79},
509 {0x335E, 0x56},
510 {0x3360, 0x6A},
511 {0x336A, 0x56},
512 {0x33D6, 0x79},
513 {0x340C, 0x6E},
514 {0x3448, 0x7E},
515 {0x348E, 0x6F},
516 {0x3492, 0x11},
517 {0x34C4, 0x5A},
518 {0x3506, 0x56},
519 {0x350C, 0x56},
520 {0x350E, 0x58},
521 {0x353D, 0x10},
522 {0x3549, 0x04},
523 {0x355D, 0x03},
524 {0x355E, 0x03},
525 {0x3574, 0x56},
526 {0x357F, 0x0C},
527 {0x3580, 0x0A},
528 {0x3581, 0x0A},
529 {0x3583, 0x75},
530 {0x3587, 0x01},
531 {0x35D0, 0x5E},
532 {0x35D4, 0x63},
533 {0x35E5, 0x9A},
534 {0x366A, 0x1A},
535 {0x366B, 0x16},
536 {0x366C, 0x10},
537 {0x366D, 0x09},
538 {0x366E, 0x00},
539 {0x366F, 0x00},
540 {0x3670, 0x00},
541 {0x3671, 0x00},
542 {0x3676, 0x83},
543 {0x3677, 0x03},
544 {0x3678, 0x00},
545 {0x3679, 0x04},
546 {0x367A, 0x2C},
547 {0x367B, 0x05},
548 {0x367D, 0x06},
549 {0x367E, 0x00},
550 {0x3680, 0x4B},
551 {0x3690, 0x27},
552 {0x3692, 0x65},
553 {0x3694, 0x4F},
554 {0x3696, 0xA1},
555 {0x36BC, 0x00}, //PSSLVS0
556 {0x36BD, 0x00},
557 {0x371C, 0x02},
558 {0x372F, 0x3C},
559 {0x3730, 0x01},
560 {0x3732, 0xB8},
561 {0x3744, 0x0F},
562 {0x375B, 0x01},
563 {0x382B, 0x68},
564 {0x38B3, 0x00},
565 {0x3A43, 0x00},
566 {0x3A54, 0xF0},
567 {0x3A55, 0x20},
568 {0x3AC4, 0x00},
569 {0x3C00, 0x01},
570 {0x3C01, 0x01},
571 {0x3E80, 0x14},
572 {0x3E82, 0x30},
573 {0x3E84, 0x0C},
574 {0x3E85, 0x06},
575 {0x3E86, 0xFC},
576 {0x3E87, 0x10},
577 {0x3E88, 0x03},
578 {0x3E89, 0xFE},
579 {0x3E8A, 0x01},
580 {0x3E8B, 0x06},
581 {0x3E8E, 0x03},
582 {0x3E8F, 0xFE},
583 {0x3E90, 0x01},
584 {0x3E91, 0x06},
585 {0x3E94, 0x33},
586 {0x3E95, 0x01},
587 {0x3E96, 0x19},
588 {0x3E98, 0x30},
589 {0x3E9A, 0x11},
590 {0x3E9B, 0x06},
591 {0x3E9C, 0xFC},
592 {0x3E9D, 0x10},
593 {0x3E9E, 0xFE},
594 {0x3E9F, 0x03},
595 {0x3EA0, 0x06},
596 {0x3EA3, 0x01},
597 {0x3EA4, 0xFE},
598 {0x3EA5, 0x03},
599 {0x3EA6, 0x06},
600 {0x3EA9, 0x33},
601 {0x3EAA, 0x00},
602 {0x3EAB, 0x08},
603 {0x3EAC, 0x08},
604 {0x3EAD, 0x01},
605 {0x3EAE, 0x08},
606 {0x3EAF, 0x08},
607 {0x3EB0, 0x00},
608 {0x3EB1, 0x10},
609 {0x3EB2, 0x10},
610 {0x3EB3, 0x01},
611 {0x3EB4, 0x10},
612 {0x3EB5, 0x10},
613 {0x3EB6, 0x00},
614 {0x3EB7, 0x00},
615 {0x3EB8, 0x00},
616 {0x3EB9, 0x00},
617 {0x3EBA, 0x00},
618 {0x3EBB, 0x00},
619 {0x3EC0, 0x54},
620 {0x3ECC, 0x04},
621 {0x3ECD, 0x04},
622 {0x3ED0, 0xF0},
623 {0x3ED1, 0x20},
624 {0x3ED2, 0x0B},
625 {0x3ED3, 0x04},
626 {0x3ED5, 0x13},
627 {0x3ED6, 0x00},
628 {0x3ED9, 0x0F},
629 {0x3EE4, 0x02},
630 {0x3EE5, 0x02},
631 {0x3EE7, 0x00},
632 {0x3EF6, 0x00},
633 {0x3EF8, 0x10},
634 {0x3EFA, 0x00},
635 {0x3EFC, 0x10},
636 {DELAY_MS, 20},
637 {0x3000, 0x02},
638 {0x35E5, 0x92},
639 {0x35E5, 0x9a},
640 {REG_NULL, 0x00},
641 };
642
643 static __maybe_unused const struct regval imx492_pllsetting_regs[] = {
644 {0x31E8, 0x20}, //PLRD1
645 {0x31E9, 0x01},
646 {0x3122, 0x02}, //PLRD2
647 {0x3129, 0x90}, //PLRD3
648 {0x312A, 0x02}, //PLRD4
649 {0x311F, 0x00}, //PLRD10
650 {0x3123, 0x00}, //PLRD11
651 {0x3124, 0x00}, //PLRD12
652 {0x3125, 0x01}, //PLRD13
653 {0x3127, 0x02}, //PLRD14
654 {0x312D, 0x02}, //PLRD15
655 {REG_NULL, 0x00},
656 };
657 /*
658 * The width and height must be configured to be
659 * the same as the current output resolution of the sensor.
660 * The input width of the isp needs to be 16 aligned.
661 * The input height of the isp needs to be 8 aligned.
662 * If the width or height does not meet the alignment rules,
663 * you can configure the cropping parameters with the following function to
664 * crop out the appropriate resolution.
665 * struct v4l2_subdev_pad_ops {
666 * .get_selection
667 * }
668 */
669 static const struct imx492_mode supported_modes[] = {
670 {
671 .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
672 .width = 8360,
673 .height = 4320,
674 .max_fps = {
675 .numerator = 10000,
676 .denominator = 135200,
677 },
678 .exp_def = 0x0906,
679 .hts_def = 0x04b2 * 7,
680 .vts_def = 0x114c,
681 .mipi_freq_idx = 0,
682 .bpp = 12,
683 .mclk = 24000000,
684 .reg_list = imx492_linear_12bit_8192x4320_4lane_mode1_regs,
685 .hdr_mode = NO_HDR,
686 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
687 },
688 {
689 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
690 .width = 8360,
691 .height = 4320,
692 .max_fps = {
693 .numerator = 10000,
694 .denominator = 176200,
695 },
696 .exp_def = 0x0906,
697 .hts_def = 0x0398 * 9,
698 .vts_def = 0x114c,
699 .mipi_freq_idx = 0,
700 .bpp = 10,
701 .mclk = 24000000,
702 .reg_list = imx492_linear_10bit_8192x4320_4lane_mode2_regs,
703 .hdr_mode = NO_HDR,
704 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
705 }
706 };
707
708 static const s64 link_freq_menu_items[] = {
709 MIPI_FREQ_864M
710 };
711
712 /* Write registers up to 4 at a time */
imx492_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)713 static int imx492_write_reg(struct i2c_client *client, u16 reg,
714 u32 len, u32 val)
715 {
716 u32 buf_i, val_i;
717 u8 buf[6];
718 u8 *val_p;
719 __be32 val_be;
720
721 if (len > 4)
722 return -EINVAL;
723
724 buf[0] = reg >> 8;
725 buf[1] = reg & 0xff;
726
727 val_be = cpu_to_be32(val);
728 val_p = (u8 *)&val_be;
729 buf_i = 2;
730 val_i = 4 - len;
731
732 while (val_i < 4)
733 buf[buf_i++] = val_p[val_i++];
734
735 if (i2c_master_send(client, buf, len + 2) != len + 2)
736 return -EIO;
737
738 return 0;
739 }
740
imx492_write_array(struct i2c_client * client,const struct regval * regs)741 static int imx492_write_array(struct i2c_client *client,
742 const struct regval *regs)
743 {
744 u32 i, delay_ms;
745 int ret = 0;
746
747 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
748 if (regs[i].addr == DELAY_MS) {
749 delay_ms = regs[i].val;
750 dev_info(&client->dev, "delay(%d) ms !\n", delay_ms);
751 usleep_range(1000 * delay_ms, 1000 * delay_ms + 100);
752 continue;
753 }
754 ret = imx492_write_reg(client, regs[i].addr,
755 IMX492_REG_VALUE_08BIT, regs[i].val);
756 }
757 return ret;
758 }
759
760 /* Read registers up to 4 at a time */
imx492_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)761 static int imx492_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
762 u32 *val)
763 {
764 struct i2c_msg msgs[2];
765 u8 *data_be_p;
766 __be32 data_be = 0;
767 __be16 reg_addr_be = cpu_to_be16(reg);
768 int ret;
769
770 if (len > 4 || !len)
771 return -EINVAL;
772
773 data_be_p = (u8 *)&data_be;
774 /* Write register address */
775 msgs[0].addr = client->addr;
776 msgs[0].flags = 0;
777 msgs[0].len = 2;
778 msgs[0].buf = (u8 *)®_addr_be;
779
780 /* Read data from register */
781 msgs[1].addr = client->addr;
782 msgs[1].flags = I2C_M_RD;
783 msgs[1].len = len;
784 msgs[1].buf = &data_be_p[4 - len];
785
786 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
787 if (ret != ARRAY_SIZE(msgs))
788 return -EIO;
789
790 *val = be32_to_cpu(data_be);
791
792 return 0;
793 }
794
imx492_get_reso_dist(const struct imx492_mode * mode,struct v4l2_mbus_framefmt * framefmt)795 static int imx492_get_reso_dist(const struct imx492_mode *mode,
796 struct v4l2_mbus_framefmt *framefmt)
797 {
798 return abs(mode->width - framefmt->width) +
799 abs(mode->height - framefmt->height);
800 }
801
802 static const struct imx492_mode *
imx492_find_best_fit(struct imx492 * imx492,struct v4l2_subdev_format * fmt)803 imx492_find_best_fit(struct imx492 *imx492, struct v4l2_subdev_format *fmt)
804 {
805 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
806 int dist;
807 int cur_best_fit = 0;
808 int cur_best_fit_dist = -1;
809 unsigned int i;
810
811 for (i = 0; i < imx492->cfg_num; i++) {
812 dist = imx492_get_reso_dist(&imx492->support_modes[i], framefmt);
813 if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
814 imx492->support_modes[i].bus_fmt == framefmt->code) {
815 cur_best_fit_dist = dist;
816 cur_best_fit = i;
817 }
818 }
819
820 return &imx492->support_modes[cur_best_fit];
821 }
822
imx492_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)823 static int imx492_set_fmt(struct v4l2_subdev *sd,
824 struct v4l2_subdev_pad_config *cfg,
825 struct v4l2_subdev_format *fmt)
826 {
827 struct imx492 *imx492 = to_IMX492(sd);
828 const struct imx492_mode *mode;
829 s64 h_blank, vblank_def;
830 u64 pixel_rate = 0;
831
832 mutex_lock(&imx492->mutex);
833
834 mode = imx492_find_best_fit(imx492, fmt);
835 fmt->format.code = mode->bus_fmt;
836 fmt->format.width = mode->width;
837 fmt->format.height = mode->height;
838 fmt->format.field = V4L2_FIELD_NONE;
839 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
840 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
841 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
842 #else
843 mutex_unlock(&imx492->mutex);
844 return -ENOTTY;
845 #endif
846 } else {
847 imx492->cur_mode = mode;
848 h_blank = mode->hts_def - mode->width;
849 __v4l2_ctrl_modify_range(imx492->hblank, h_blank,
850 h_blank, 1, h_blank);
851 vblank_def = mode->vts_def - mode->height;
852 __v4l2_ctrl_modify_range(imx492->vblank, vblank_def,
853 IMX492_VTS_MAX - mode->height, 1,
854 vblank_def);
855 imx492->cur_vts = imx492->cur_mode->vts_def;
856 pixel_rate = (u32)link_freq_menu_items[mode->mipi_freq_idx] /
857 mode->bpp * 2 * 4;
858 __v4l2_ctrl_s_ctrl_int64(imx492->pixel_rate, pixel_rate);
859 __v4l2_ctrl_s_ctrl(imx492->link_freq, mode->mipi_freq_idx);
860 }
861
862 mutex_unlock(&imx492->mutex);
863
864 return 0;
865 }
866
imx492_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)867 static int imx492_get_fmt(struct v4l2_subdev *sd,
868 struct v4l2_subdev_pad_config *cfg,
869 struct v4l2_subdev_format *fmt)
870 {
871 struct imx492 *imx492 = to_IMX492(sd);
872 const struct imx492_mode *mode = imx492->cur_mode;
873
874 mutex_lock(&imx492->mutex);
875 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
876 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
877 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
878 #else
879 mutex_unlock(&imx492->mutex);
880 return -ENOTTY;
881 #endif
882 } else {
883 fmt->format.width = mode->width;
884 fmt->format.height = mode->height;
885 fmt->format.code = mode->bus_fmt;
886 fmt->format.field = V4L2_FIELD_NONE;
887 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
888 fmt->reserved[0] = mode->vc[fmt->pad];
889 else
890 fmt->reserved[0] = mode->vc[PAD0];
891 }
892 mutex_unlock(&imx492->mutex);
893
894 return 0;
895 }
896
imx492_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)897 static int imx492_enum_mbus_code(struct v4l2_subdev *sd,
898 struct v4l2_subdev_pad_config *cfg,
899 struct v4l2_subdev_mbus_code_enum *code)
900 {
901 struct imx492 *imx492 = to_IMX492(sd);
902
903 if (code->index != 0)
904 return -EINVAL;
905 code->code = imx492->cur_mode->bus_fmt;
906
907 return 0;
908 }
909
imx492_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)910 static int imx492_enum_frame_sizes(struct v4l2_subdev *sd,
911 struct v4l2_subdev_pad_config *cfg,
912 struct v4l2_subdev_frame_size_enum *fse)
913 {
914 struct imx492 *imx492 = to_IMX492(sd);
915
916 if (fse->index >= imx492->cfg_num)
917 return -EINVAL;
918
919 if (fse->code != imx492->support_modes[fse->index].bus_fmt)
920 return -EINVAL;
921
922 fse->min_width = imx492->support_modes[fse->index].width;
923 fse->max_width = imx492->support_modes[fse->index].width;
924 fse->max_height = imx492->support_modes[fse->index].height;
925 fse->min_height = imx492->support_modes[fse->index].height;
926
927 return 0;
928 }
929
imx492_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)930 static int imx492_g_frame_interval(struct v4l2_subdev *sd,
931 struct v4l2_subdev_frame_interval *fi)
932 {
933 struct imx492 *imx492 = to_IMX492(sd);
934 const struct imx492_mode *mode = imx492->cur_mode;
935
936 fi->interval = mode->max_fps;
937
938 return 0;
939 }
940
imx492_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)941 static int imx492_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
942 struct v4l2_mbus_config *config)
943 {
944 struct imx492 *imx492 = to_IMX492(sd);
945 const struct imx492_mode *mode = imx492->cur_mode;
946 u32 val = 0;
947 u32 lane_num = imx492->bus_cfg.bus.mipi_csi2.num_data_lanes;
948
949 if (mode->hdr_mode == NO_HDR) {
950 val = 1 << (lane_num - 1) |
951 V4L2_MBUS_CSI2_CHANNEL_0 |
952 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
953 }
954 if (mode->hdr_mode == HDR_X2)
955 val = 1 << (lane_num - 1) |
956 V4L2_MBUS_CSI2_CHANNEL_0 |
957 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
958 V4L2_MBUS_CSI2_CHANNEL_1;
959 if (mode->hdr_mode == HDR_X3)
960 val = 1 << (lane_num - 1) |
961 V4L2_MBUS_CSI2_CHANNEL_0 |
962 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
963 V4L2_MBUS_CSI2_CHANNEL_1 |
964 V4L2_MBUS_CSI2_CHANNEL_2;
965
966 config->type = V4L2_MBUS_CSI2_DPHY;
967 config->flags = val;
968
969 return 0;
970 }
971
imx492_get_module_inf(struct imx492 * imx492,struct rkmodule_inf * inf)972 static void imx492_get_module_inf(struct imx492 *imx492,
973 struct rkmodule_inf *inf)
974 {
975 memset(inf, 0, sizeof(*inf));
976 strscpy(inf->base.sensor, IMX492_NAME, sizeof(inf->base.sensor));
977 strscpy(inf->base.module, imx492->module_name, sizeof(inf->base.module));
978 strscpy(inf->base.lens, imx492->len_name, sizeof(inf->base.lens));
979 }
980
981
imx492_get_channel_info(struct imx492 * imx492,struct rkmodule_channel_info * ch_info)982 static int imx492_get_channel_info(struct imx492 *imx492,
983 struct rkmodule_channel_info *ch_info)
984 {
985 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
986 return -EINVAL;
987 ch_info->vc = imx492->cur_mode->vc[ch_info->index];
988 ch_info->width = imx492->cur_mode->width;
989 ch_info->height = imx492->cur_mode->height;
990 ch_info->bus_fmt = imx492->cur_mode->bus_fmt;
991 return 0;
992 }
993
imx492_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)994 static long imx492_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
995 {
996 struct imx492 *imx492 = to_IMX492(sd);
997 struct rkmodule_hdr_cfg *hdr;
998 struct rkmodule_channel_info *ch_info;
999 u32 i, h, w, stream;
1000 long ret = 0;
1001 u64 pixel_rate = 0;
1002 u32 *sync_mode = NULL;
1003
1004 switch (cmd) {
1005 case PREISP_CMD_SET_HDRAE_EXP:
1006 break;
1007 case RKMODULE_GET_MODULE_INFO:
1008 imx492_get_module_inf(imx492, (struct rkmodule_inf *)arg);
1009 break;
1010 case RKMODULE_GET_HDR_CFG:
1011 hdr = (struct rkmodule_hdr_cfg *)arg;
1012 hdr->esp.mode = HDR_NORMAL_VC;
1013 hdr->hdr_mode = imx492->cur_mode->hdr_mode;
1014 break;
1015 case RKMODULE_SET_HDR_CFG:
1016 hdr = (struct rkmodule_hdr_cfg *)arg;
1017 w = imx492->cur_mode->width;
1018 h = imx492->cur_mode->height;
1019 for (i = 0; i < imx492->cfg_num; i++) {
1020 if (w == imx492->support_modes[i].width &&
1021 h == imx492->support_modes[i].height &&
1022 imx492->support_modes[i].hdr_mode == hdr->hdr_mode) {
1023 imx492->cur_mode = &imx492->support_modes[i];
1024 break;
1025 }
1026 }
1027 if (i == imx492->cfg_num) {
1028 dev_err(&imx492->client->dev,
1029 "not find hdr mode:%d %dx%d config\n",
1030 hdr->hdr_mode, w, h);
1031 ret = -EINVAL;
1032 } else {
1033 w = imx492->cur_mode->hts_def - imx492->cur_mode->width;
1034 h = imx492->cur_mode->vts_def - imx492->cur_mode->height;
1035 __v4l2_ctrl_modify_range(imx492->hblank, w, w, 1, w);
1036 __v4l2_ctrl_modify_range(imx492->vblank, h,
1037 IMX492_VTS_MAX - imx492->cur_mode->height,
1038 1, h);
1039 imx492->cur_vts = imx492->cur_mode->vts_def;
1040 pixel_rate = (u32)link_freq_menu_items[imx492->cur_mode->mipi_freq_idx]
1041 / imx492->cur_mode->bpp * 2 *
1042 imx492->bus_cfg.bus.mipi_csi2.num_data_lanes;
1043 __v4l2_ctrl_s_ctrl_int64(imx492->pixel_rate,
1044 pixel_rate);
1045 __v4l2_ctrl_s_ctrl(imx492->link_freq,
1046 imx492->cur_mode->mipi_freq_idx);
1047 }
1048 break;
1049 case RKMODULE_SET_QUICK_STREAM:
1050 stream = *((u32 *)arg);
1051
1052 if (stream) {
1053 ret |= imx492_write_reg(imx492->client, IMX492_REG_CTRL_STANDBY,
1054 IMX492_REG_VALUE_08BIT, 0x00);
1055 } else {
1056 ret |= imx492_write_reg(imx492->client, IMX492_REG_CTRL_STANDBY,
1057 IMX492_REG_VALUE_08BIT, 0x11);
1058 }
1059 break;
1060 case RKMODULE_GET_CHANNEL_INFO:
1061 ch_info = (struct rkmodule_channel_info *)arg;
1062 ret = imx492_get_channel_info(imx492, ch_info);
1063 break;
1064 case RKMODULE_GET_SYNC_MODE:
1065 sync_mode = (u32 *)arg;
1066 *sync_mode = imx492->sync_mode;
1067 break;
1068 case RKMODULE_SET_SYNC_MODE:
1069 sync_mode = (u32 *)arg;
1070 imx492->sync_mode = *sync_mode;
1071 break;
1072 default:
1073 ret = -ENOIOCTLCMD;
1074 break;
1075 }
1076
1077 return ret;
1078 }
1079
1080 #ifdef CONFIG_COMPAT
imx492_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1081 static long imx492_compat_ioctl32(struct v4l2_subdev *sd,
1082 unsigned int cmd, unsigned long arg)
1083 {
1084 void __user *up = compat_ptr(arg);
1085 struct rkmodule_inf *inf;
1086 struct rkmodule_awb_cfg *cfg;
1087 struct rkmodule_hdr_cfg *hdr;
1088 struct preisp_hdrae_exp_s *hdrae;
1089 struct rkmodule_channel_info *ch_info;
1090 long ret;
1091 u32 cg = 0;
1092 u32 stream;
1093 u32 sync_mode;
1094
1095 switch (cmd) {
1096 case RKMODULE_GET_MODULE_INFO:
1097 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1098 if (!inf) {
1099 ret = -ENOMEM;
1100 return ret;
1101 }
1102
1103 ret = imx492_ioctl(sd, cmd, inf);
1104 if (!ret) {
1105 ret = copy_to_user(up, inf, sizeof(*inf));
1106 if (ret)
1107 ret = -EFAULT;
1108 }
1109 kfree(inf);
1110 break;
1111 case RKMODULE_AWB_CFG:
1112 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1113 if (!cfg) {
1114 ret = -ENOMEM;
1115 return ret;
1116 }
1117
1118 ret = copy_from_user(cfg, up, sizeof(*cfg));
1119 if (!ret)
1120 ret = imx492_ioctl(sd, cmd, cfg);
1121 else
1122 ret = -EFAULT;
1123 kfree(cfg);
1124 break;
1125 case RKMODULE_GET_HDR_CFG:
1126 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1127 if (!hdr) {
1128 ret = -ENOMEM;
1129 return ret;
1130 }
1131
1132 ret = imx492_ioctl(sd, cmd, hdr);
1133 if (!ret) {
1134 ret = copy_to_user(up, hdr, sizeof(*hdr));
1135 if (ret)
1136 ret = -EFAULT;
1137 }
1138 kfree(hdr);
1139 break;
1140 case RKMODULE_SET_HDR_CFG:
1141 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1142 if (!hdr) {
1143 ret = -ENOMEM;
1144 return ret;
1145 }
1146
1147 ret = copy_from_user(hdr, up, sizeof(*hdr));
1148 if (!ret)
1149 ret = imx492_ioctl(sd, cmd, hdr);
1150 else
1151 ret = -EFAULT;
1152 kfree(hdr);
1153 break;
1154 case PREISP_CMD_SET_HDRAE_EXP:
1155 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1156 if (!hdrae) {
1157 ret = -ENOMEM;
1158 return ret;
1159 }
1160
1161 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1162 if (!ret)
1163 ret = imx492_ioctl(sd, cmd, hdrae);
1164 else
1165 ret = -EFAULT;
1166 kfree(hdrae);
1167 break;
1168 case RKMODULE_SET_CONVERSION_GAIN:
1169 ret = copy_from_user(&cg, up, sizeof(cg));
1170 if (!ret)
1171 ret = imx492_ioctl(sd, cmd, &cg);
1172 else
1173 ret = -EFAULT;
1174 break;
1175 case RKMODULE_SET_QUICK_STREAM:
1176 ret = copy_from_user(&stream, up, sizeof(u32));
1177 if (!ret)
1178 ret = imx492_ioctl(sd, cmd, &stream);
1179 else
1180 ret = -EFAULT;
1181
1182 break;
1183 case RKMODULE_GET_CHANNEL_INFO:
1184 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1185 if (!ch_info) {
1186 ret = -ENOMEM;
1187 return ret;
1188 }
1189
1190 ret = imx492_ioctl(sd, cmd, ch_info);
1191 if (!ret) {
1192 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1193 if (ret)
1194 ret = -EFAULT;
1195 }
1196 kfree(ch_info);
1197 break;
1198 case RKMODULE_GET_SYNC_MODE:
1199 ret = imx492_ioctl(sd, cmd, &sync_mode);
1200 if (!ret) {
1201 ret = copy_to_user(up, &sync_mode, sizeof(u32));
1202 if (ret)
1203 ret = -EFAULT;
1204 }
1205 break;
1206 case RKMODULE_SET_SYNC_MODE:
1207 ret = copy_from_user(&sync_mode, up, sizeof(u32));
1208 if (!ret)
1209 ret = imx492_ioctl(sd, cmd, &sync_mode);
1210 else
1211 ret = -EFAULT;
1212 break;
1213 default:
1214 ret = -ENOIOCTLCMD;
1215 break;
1216 }
1217
1218 return ret;
1219 }
1220 #endif
1221
1222
__imx492_start_stream(struct imx492 * imx492)1223 static int __imx492_start_stream(struct imx492 *imx492)
1224 {
1225 int ret;
1226
1227 ret = imx492_write_array(imx492->client, imx492->cur_mode->reg_list);
1228 if (ret)
1229 return ret;
1230 /* In case these controls are set before streaming */
1231 ret = __v4l2_ctrl_handler_setup(&imx492->ctrl_handler);
1232 if (ret)
1233 return ret;
1234 if (imx492->has_init_exp && imx492->cur_mode->hdr_mode != NO_HDR) {
1235 ret = imx492_ioctl(&imx492->subdev, PREISP_CMD_SET_HDRAE_EXP,
1236 &imx492->init_hdrae_exp);
1237 if (ret) {
1238 dev_err(&imx492->client->dev,
1239 "init exp fail in hdr mode\n");
1240 return ret;
1241 }
1242 }
1243 ret |= imx492_write_reg(imx492->client, IMX492_REG_CTRL_STANDBY,
1244 IMX492_REG_VALUE_08BIT, 0x00);
1245 usleep_range(1000, 1100);
1246 ret |= imx492_write_reg(imx492->client, IMX492_REG_CTRL_XMSTA,
1247 IMX492_REG_VALUE_08BIT, 0x20);
1248 ret |= imx492_write_reg(imx492->client, IMX492_REG_CTRL_SYNCDRV,
1249 IMX492_REG_VALUE_08BIT, 0xa8);
1250
1251 return ret;
1252 }
1253
__imx492_stop_stream(struct imx492 * imx492)1254 static int __imx492_stop_stream(struct imx492 *imx492)
1255 {
1256 int ret = 0;
1257
1258 imx492->has_init_exp = false;
1259 ret = imx492_write_reg(imx492->client, IMX492_REG_CTRL_STANDBY,
1260 IMX492_REG_VALUE_08BIT, 0x11);
1261 return ret;
1262 }
1263
imx492_s_stream(struct v4l2_subdev * sd,int on)1264 static int imx492_s_stream(struct v4l2_subdev *sd, int on)
1265 {
1266 struct imx492 *imx492 = to_IMX492(sd);
1267 struct i2c_client *client = imx492->client;
1268 int ret = 0;
1269
1270 mutex_lock(&imx492->mutex);
1271 on = !!on;
1272 if (on == imx492->streaming)
1273 goto unlock_and_return;
1274
1275 if (on) {
1276 ret = pm_runtime_get_sync(&client->dev);
1277 if (ret < 0) {
1278 pm_runtime_put_noidle(&client->dev);
1279 goto unlock_and_return;
1280 }
1281
1282 ret = __imx492_start_stream(imx492);
1283 if (ret) {
1284 v4l2_err(sd, "start stream failed while write regs\n");
1285 pm_runtime_put(&client->dev);
1286 goto unlock_and_return;
1287 }
1288 } else {
1289 __imx492_stop_stream(imx492);
1290 pm_runtime_put(&client->dev);
1291 }
1292
1293 imx492->streaming = on;
1294
1295 unlock_and_return:
1296 mutex_unlock(&imx492->mutex);
1297
1298 return ret;
1299 }
1300
imx492_s_power(struct v4l2_subdev * sd,int on)1301 static int imx492_s_power(struct v4l2_subdev *sd, int on)
1302 {
1303 struct imx492 *imx492 = to_IMX492(sd);
1304 struct i2c_client *client = imx492->client;
1305 int ret = 0;
1306
1307 mutex_lock(&imx492->mutex);
1308
1309 /* If the power state is not modified - no work to do. */
1310 if (imx492->power_on == !!on)
1311 goto unlock_and_return;
1312
1313 if (on) {
1314 ret = pm_runtime_get_sync(&client->dev);
1315 if (ret < 0) {
1316 pm_runtime_put_noidle(&client->dev);
1317 goto unlock_and_return;
1318 }
1319 imx492->power_on = true;
1320 } else {
1321 pm_runtime_put(&client->dev);
1322 imx492->power_on = false;
1323 }
1324
1325 unlock_and_return:
1326 mutex_unlock(&imx492->mutex);
1327
1328 return ret;
1329 }
1330
1331 /* Calculate the delay in us by clock rate and clock cycles */
1332
__imx492_power_on(struct imx492 * imx492)1333 static int __imx492_power_on(struct imx492 *imx492)
1334 {
1335 int ret;
1336 struct device *dev = &imx492->client->dev;
1337
1338 if (!IS_ERR_OR_NULL(imx492->pins_default)) {
1339 ret = pinctrl_select_state(imx492->pinctrl,
1340 imx492->pins_default);
1341 if (ret < 0)
1342 dev_err(dev, "could not set pins\n");
1343 }
1344
1345 ret = clk_set_rate(imx492->xvclk, imx492->cur_mode->mclk);
1346 if (ret < 0)
1347 dev_warn(dev, "Failed to set xvclk rate\n");
1348 if (clk_get_rate(imx492->xvclk) != imx492->cur_mode->mclk)
1349 dev_warn(dev, "xvclk mismatched, %lu\n", clk_get_rate(imx492->xvclk));
1350 else
1351 imx492->cur_mclk = imx492->cur_mode->mclk;
1352 ret = clk_prepare_enable(imx492->xvclk);
1353 if (ret < 0) {
1354 dev_err(dev, "Failed to enable xvclk\n");
1355 return ret;
1356 }
1357
1358 ret = regulator_bulk_enable(IMX492_NUM_SUPPLIES, imx492->supplies);
1359 if (ret < 0) {
1360 dev_err(dev, "Failed to enable regulators\n");
1361 goto disable_clk;
1362 }
1363 if (!IS_ERR(imx492->pwdn_gpio))
1364 gpiod_set_value_cansleep(imx492->pwdn_gpio, 0);
1365 if (!IS_ERR(imx492->reset_gpio))
1366 gpiod_set_value_cansleep(imx492->reset_gpio, 0);
1367
1368 usleep_range(3000, 3100);
1369 return 0;
1370
1371 disable_clk:
1372 clk_disable_unprepare(imx492->xvclk);
1373
1374 return ret;
1375 }
1376
__imx492_power_off(struct imx492 * imx492)1377 static void __imx492_power_off(struct imx492 *imx492)
1378 {
1379 int ret;
1380 struct device *dev = &imx492->client->dev;
1381
1382 if (!IS_ERR(imx492->pwdn_gpio))
1383 gpiod_set_value_cansleep(imx492->pwdn_gpio, 1);
1384 clk_disable_unprepare(imx492->xvclk);
1385 if (!IS_ERR(imx492->reset_gpio))
1386 gpiod_set_value_cansleep(imx492->reset_gpio, 1);
1387 if (!IS_ERR_OR_NULL(imx492->pins_sleep)) {
1388 ret = pinctrl_select_state(imx492->pinctrl, imx492->pins_sleep);
1389 if (ret < 0)
1390 dev_err(dev, "could not set pins\n");
1391 }
1392 regulator_bulk_disable(IMX492_NUM_SUPPLIES, imx492->supplies);
1393 usleep_range(15000, 16000);
1394 }
1395
imx492_runtime_resume(struct device * dev)1396 static int imx492_runtime_resume(struct device *dev)
1397 {
1398 struct i2c_client *client = to_i2c_client(dev);
1399 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1400 struct imx492 *imx492 = to_IMX492(sd);
1401
1402 return __imx492_power_on(imx492);
1403 }
1404
imx492_runtime_suspend(struct device * dev)1405 static int imx492_runtime_suspend(struct device *dev)
1406 {
1407 struct i2c_client *client = to_i2c_client(dev);
1408 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1409 struct imx492 *imx492 = to_IMX492(sd);
1410
1411 __imx492_power_off(imx492);
1412
1413 return 0;
1414 }
1415
1416 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx492_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1417 static int imx492_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1418 {
1419 struct imx492 *imx492 = to_IMX492(sd);
1420 struct v4l2_mbus_framefmt *try_fmt =
1421 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1422 const struct imx492_mode *def_mode = &imx492->support_modes[0];
1423
1424 mutex_lock(&imx492->mutex);
1425 /* Initialize try_fmt */
1426 try_fmt->width = def_mode->width;
1427 try_fmt->height = def_mode->height;
1428 try_fmt->code = def_mode->bus_fmt;
1429 try_fmt->field = V4L2_FIELD_NONE;
1430
1431 mutex_unlock(&imx492->mutex);
1432 /* No crop or compose */
1433
1434 return 0;
1435 }
1436 #endif
1437
imx492_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1438 static int imx492_enum_frame_interval(struct v4l2_subdev *sd,
1439 struct v4l2_subdev_pad_config *cfg,
1440 struct v4l2_subdev_frame_interval_enum *fie)
1441 {
1442 struct imx492 *imx492 = to_IMX492(sd);
1443
1444 if (fie->index >= imx492->cfg_num)
1445 return -EINVAL;
1446
1447 fie->code = imx492->support_modes[fie->index].bus_fmt;
1448 fie->width = imx492->support_modes[fie->index].width;
1449 fie->height = imx492->support_modes[fie->index].height;
1450 fie->interval = imx492->support_modes[fie->index].max_fps;
1451 fie->reserved[0] = imx492->support_modes[fie->index].hdr_mode;
1452 return 0;
1453 }
1454
1455 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1456 #define DST_WIDTH_8192 8192
1457 #define DST_HEIGHT_4320 4320
1458 #define DST_WIDTH_3840 3840
1459 #define DST_HEIGHT_2160 2160
1460 #define DST_WIDTH_1920 1920
1461 #define DST_HEIGHT_1080 1080
1462 /*
1463 * The resolution of the driver configuration needs to be exactly
1464 * the same as the current output resolution of the sensor,
1465 * the input width of the isp needs to be 16 aligned,
1466 * the input height of the isp needs to be 8 aligned.
1467 * Can be cropped to standard resolution by this function,
1468 * otherwise it will crop out strange resolution according
1469 * to the alignment rules.
1470 */
imx492_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1471 static int imx492_get_selection(struct v4l2_subdev *sd,
1472 struct v4l2_subdev_pad_config *cfg,
1473 struct v4l2_subdev_selection *sel)
1474 {
1475 struct imx492 *imx492 = to_IMX492(sd);
1476
1477 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1478 sel->r.left = 168;// CROP_START(imx492->cur_mode->width, DST_WIDTH_8192);
1479 sel->r.width = DST_WIDTH_8192;
1480 sel->r.top = CROP_START(imx492->cur_mode->height, DST_HEIGHT_4320);
1481 sel->r.height = DST_HEIGHT_4320;
1482 dev_info(&imx492->client->dev, "sel->r.left %d sel->r.top %d\n",
1483 sel->r.left, sel->r.top);
1484 return 0;
1485 }
1486 return -EINVAL;
1487 }
1488
1489 static const struct dev_pm_ops imx492_pm_ops = {
1490 SET_RUNTIME_PM_OPS(imx492_runtime_suspend, imx492_runtime_resume, NULL)
1491 };
1492
1493 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1494 static const struct v4l2_subdev_internal_ops imx492_internal_ops = {
1495 .open = imx492_open,
1496 };
1497 #endif
1498
1499 static const struct v4l2_subdev_core_ops imx492_core_ops = {
1500 .s_power = imx492_s_power,
1501 .ioctl = imx492_ioctl,
1502 #ifdef CONFIG_COMPAT
1503 .compat_ioctl32 = imx492_compat_ioctl32,
1504 #endif
1505 };
1506
1507 static const struct v4l2_subdev_video_ops imx492_video_ops = {
1508 .s_stream = imx492_s_stream,
1509 .g_frame_interval = imx492_g_frame_interval,
1510 };
1511
1512 static const struct v4l2_subdev_pad_ops imx492_pad_ops = {
1513 .enum_mbus_code = imx492_enum_mbus_code,
1514 .enum_frame_size = imx492_enum_frame_sizes,
1515 .enum_frame_interval = imx492_enum_frame_interval,
1516 .get_fmt = imx492_get_fmt,
1517 .set_fmt = imx492_set_fmt,
1518 .get_selection = imx492_get_selection,
1519 .get_mbus_config = imx492_g_mbus_config,
1520 };
1521
1522 static const struct v4l2_subdev_ops imx492_subdev_ops = {
1523 .core = &imx492_core_ops,
1524 .video = &imx492_video_ops,
1525 .pad = &imx492_pad_ops,
1526 };
1527
1528
imx492_set_ctrl(struct v4l2_ctrl * ctrl)1529 static int imx492_set_ctrl(struct v4l2_ctrl *ctrl)
1530 {
1531 struct imx492 *imx492 = container_of(ctrl->handler,
1532 struct imx492, ctrl_handler);
1533 struct i2c_client *client = imx492->client;
1534 const struct imx492_mode *mode = imx492->cur_mode;
1535 s64 max;
1536 u32 vts = 0;
1537 int ret = 0;
1538 u16 reg_val = 0;
1539 u16 SHR = 12;
1540
1541
1542 /* Propagate change of current control to all related controls */
1543 switch (ctrl->id) {
1544 case V4L2_CID_VBLANK:
1545 /* Update max exposure while meeting expected vblanking */
1546 if (mode->hdr_mode == NO_HDR) {
1547 max = imx492->cur_mode->height + ctrl->val - 3;
1548 __v4l2_ctrl_modify_range(imx492->exposure,
1549 imx492->exposure->minimum, max,
1550 imx492->exposure->step,
1551 imx492->exposure->default_value);
1552 }
1553 break;
1554 }
1555
1556 if (!pm_runtime_get_if_in_use(&client->dev))
1557 return 0;
1558
1559 switch (ctrl->id) {
1560 case V4L2_CID_EXPOSURE:
1561 if (mode->hdr_mode == NO_HDR) {
1562 SHR = mode->vts_def - ctrl->val;
1563 ret |= imx492_write_reg(imx492->client, IMX492_EXPO_REG_L,
1564 IMX492_REG_VALUE_08BIT,
1565 IMX492_FETCH_EXP_L(SHR));
1566 ret |= imx492_write_reg(imx492->client, IMX492_EXPO_REG_H,
1567 IMX492_REG_VALUE_08BIT,
1568 IMX492_FETCH_EXP_H(SHR));
1569 dev_info(&client->dev, "ctr_val 0x%x set exposure 0x%x\n",
1570 ctrl->val, SHR);
1571 }
1572 break;
1573 case V4L2_CID_ANALOGUE_GAIN:
1574 if (mode->hdr_mode == NO_HDR) {
1575 if (ctrl->val <= 1957) {
1576 reg_val = ctrl->val;
1577 ret |= imx492_write_reg(imx492->client, IMX492_AGAIN_REG_H,
1578 IMX492_REG_VALUE_08BIT,
1579 IMX492_FETCH_GAIN_H(reg_val));
1580 ret |= imx492_write_reg(imx492->client, IMX492_AGAIN_REG_L,
1581 IMX492_REG_VALUE_08BIT,
1582 IMX492_FETCH_GAIN_L(reg_val));
1583 ret |= imx492_write_reg(imx492->client, IMX492_DGAIN_REG,
1584 IMX492_REG_VALUE_08BIT, 0x0);
1585 } else if (ctrl->val <= 3914) {
1586 reg_val = ctrl->val - 1957;
1587 ret |= imx492_write_reg(imx492->client, IMX492_AGAIN_REG_H,
1588 IMX492_REG_VALUE_08BIT,
1589 IMX492_FETCH_GAIN_H(reg_val));
1590 ret |= imx492_write_reg(imx492->client, IMX492_AGAIN_REG_L,
1591 IMX492_REG_VALUE_08BIT,
1592 IMX492_FETCH_GAIN_L(reg_val));
1593 ret |= imx492_write_reg(imx492->client, IMX492_DGAIN_REG,
1594 IMX492_REG_VALUE_08BIT, 0x1);
1595 } else if (ctrl->val <= 5871) {
1596 reg_val = ctrl->val - 3914;
1597 ret |= imx492_write_reg(imx492->client, IMX492_AGAIN_REG_H,
1598 IMX492_REG_VALUE_08BIT,
1599 IMX492_FETCH_GAIN_H(reg_val));
1600 ret |= imx492_write_reg(imx492->client, IMX492_AGAIN_REG_L,
1601 IMX492_REG_VALUE_08BIT,
1602 IMX492_FETCH_GAIN_L(reg_val));
1603 ret |= imx492_write_reg(imx492->client, IMX492_DGAIN_REG,
1604 IMX492_REG_VALUE_08BIT, 0x2);
1605 } else if (ctrl->val <= 7828) {
1606 reg_val = ctrl->val - 5871;
1607 ret |= imx492_write_reg(imx492->client, IMX492_AGAIN_REG_H,
1608 IMX492_REG_VALUE_08BIT,
1609 IMX492_FETCH_GAIN_H(reg_val));
1610 ret |= imx492_write_reg(imx492->client, IMX492_AGAIN_REG_L,
1611 IMX492_REG_VALUE_08BIT,
1612 IMX492_FETCH_GAIN_L(reg_val));
1613 ret |= imx492_write_reg(imx492->client, IMX492_DGAIN_REG,
1614 IMX492_REG_VALUE_08BIT, 0x3);
1615 }
1616 dev_err(&client->dev, "set analog gain 0x%x\n",
1617 ctrl->val);
1618 }
1619 break;
1620 case V4L2_CID_VBLANK:
1621 vts = ctrl->val + imx492->cur_mode->height;
1622
1623 imx492->cur_vts = vts;
1624 ret |= imx492_write_reg(imx492->client, IMX492_VTS_REG_L,
1625 IMX492_REG_VALUE_08BIT,
1626 IMX492_FETCH_VTS_L(vts));
1627 ret |= imx492_write_reg(imx492->client, IMX492_VTS_REG_M,
1628 IMX492_REG_VALUE_08BIT,
1629 IMX492_FETCH_VTS_M(vts));
1630 ret |= imx492_write_reg(imx492->client, IMX492_VTS_REG_H,
1631 IMX492_REG_VALUE_08BIT,
1632 IMX492_FETCH_VTS_H(vts));
1633
1634 dev_info(&client->dev, "set vts 0x%x\n",
1635 vts);
1636 break;
1637 case V4L2_CID_HFLIP:
1638 break;
1639 case V4L2_CID_VFLIP:
1640 break;
1641 default:
1642 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1643 __func__, ctrl->id, ctrl->val);
1644 break;
1645 }
1646
1647 pm_runtime_put(&client->dev);
1648
1649 return ret;
1650 }
1651
1652 static const struct v4l2_ctrl_ops imx492_ctrl_ops = {
1653 .s_ctrl = imx492_set_ctrl,
1654 };
1655
imx492_initialize_controls(struct imx492 * imx492)1656 static int imx492_initialize_controls(struct imx492 *imx492)
1657 {
1658 const struct imx492_mode *mode;
1659 struct v4l2_ctrl_handler *handler;
1660 s64 exposure_max, vblank_def;
1661 u32 h_blank;
1662 u64 pixel_rate = 0;
1663 int ret;
1664
1665 handler = &imx492->ctrl_handler;
1666 mode = imx492->cur_mode;
1667 ret = v4l2_ctrl_handler_init(handler, 8);
1668 if (ret)
1669 return ret;
1670 handler->lock = &imx492->mutex;
1671
1672 imx492->link_freq = v4l2_ctrl_new_int_menu(handler,
1673 NULL, V4L2_CID_LINK_FREQ,
1674 1, 0, link_freq_menu_items);
1675 __v4l2_ctrl_s_ctrl(imx492->link_freq, imx492->cur_mode->mipi_freq_idx);
1676 pixel_rate = (u32)link_freq_menu_items[mode->mipi_freq_idx] / mode->bpp
1677 * 2 * imx492->bus_cfg.bus.mipi_csi2.num_data_lanes;
1678 imx492->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1679 0, IMX492_10BIT_PIXEL_RATE,
1680 1, pixel_rate);
1681
1682 h_blank = mode->hts_def - mode->width;
1683 imx492->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1684 h_blank, h_blank, 1, h_blank);
1685 if (imx492->hblank)
1686 imx492->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1687
1688 vblank_def = mode->vts_def - mode->height;
1689 imx492->vblank = v4l2_ctrl_new_std(handler, &imx492_ctrl_ops,
1690 V4L2_CID_VBLANK, vblank_def,
1691 IMX492_VTS_MAX - mode->height,
1692 1, vblank_def);
1693 imx492->cur_vts = mode->vts_def;
1694
1695 exposure_max = mode->vts_def - 4;
1696 imx492->exposure = v4l2_ctrl_new_std(handler, &imx492_ctrl_ops,
1697 V4L2_CID_EXPOSURE, IMX492_EXPOSURE_MIN,
1698 exposure_max, IMX492_EXPOSURE_STEP,
1699 mode->exp_def);
1700
1701 imx492->anal_a_gain = v4l2_ctrl_new_std(handler, &imx492_ctrl_ops,
1702 V4L2_CID_ANALOGUE_GAIN, IMX492_GAIN_MIN,
1703 IMX492_GAIN_MAX, IMX492_GAIN_STEP,
1704 IMX492_GAIN_DEFAULT);
1705 v4l2_ctrl_new_std(handler, &imx492_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1706 v4l2_ctrl_new_std(handler, &imx492_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1707
1708 if (handler->error) {
1709 ret = handler->error;
1710 dev_err(&imx492->client->dev, "Failed to init controls(%d)\n", ret);
1711 goto err_free_handler;
1712 }
1713
1714 imx492->subdev.ctrl_handler = handler;
1715 imx492->has_init_exp = false;
1716 imx492->isHCG = false;
1717
1718 return 0;
1719
1720 err_free_handler:
1721 v4l2_ctrl_handler_free(handler);
1722
1723 return ret;
1724 }
1725
imx492_check_sensor_id(struct imx492 * imx492,struct i2c_client * client)1726 static int imx492_check_sensor_id(struct imx492 *imx492,
1727 struct i2c_client *client)
1728 {
1729 struct device *dev = &imx492->client->dev;
1730 u32 id = 0;
1731 int ret;
1732
1733 ret = imx492_read_reg(client, IMX492_REG_CHIP_ID,
1734 IMX492_REG_VALUE_08BIT, &id);
1735 if (id != CHIP_ID) {
1736 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1737 return -ENODEV;
1738 }
1739
1740 dev_info(dev, "Detected imx492 id %06x\n", CHIP_ID);
1741
1742 return 0;
1743 }
1744
imx492_configure_regulators(struct imx492 * imx492)1745 static int imx492_configure_regulators(struct imx492 *imx492)
1746 {
1747 unsigned int i;
1748
1749 for (i = 0; i < IMX492_NUM_SUPPLIES; i++)
1750 imx492->supplies[i].supply = imx492_supply_names[i];
1751
1752 return devm_regulator_bulk_get(&imx492->client->dev,
1753 IMX492_NUM_SUPPLIES,
1754 imx492->supplies);
1755 }
1756
imx492_probe(struct i2c_client * client,const struct i2c_device_id * id)1757 static int imx492_probe(struct i2c_client *client,
1758 const struct i2c_device_id *id)
1759 {
1760 struct device *dev = &client->dev;
1761 struct device_node *node = dev->of_node;
1762 struct imx492 *imx492;
1763 struct v4l2_subdev *sd;
1764 struct device_node *endpoint;
1765 char facing[2];
1766 int ret;
1767 int i;
1768 u32 hdr_mode = 0;
1769 const char *sync_mode_name = NULL;
1770
1771
1772 dev_info(dev, "driver version: %02x.%02x.%02x",
1773 DRIVER_VERSION >> 16,
1774 (DRIVER_VERSION & 0xff00) >> 8,
1775 DRIVER_VERSION & 0x00ff);
1776
1777 imx492 = devm_kzalloc(dev, sizeof(*imx492), GFP_KERNEL);
1778 if (!imx492)
1779 return -ENOMEM;
1780
1781 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1782 &imx492->module_index);
1783 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1784 &imx492->module_facing);
1785 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1786 &imx492->module_name);
1787 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1788 &imx492->len_name);
1789 if (ret) {
1790 dev_err(dev, "could not get module information!\n");
1791 return -EINVAL;
1792 }
1793
1794 ret = of_property_read_string(node, RKMODULE_CAMERA_SYNC_MODE,
1795 &sync_mode_name);
1796 if (ret) {
1797 imx492->sync_mode = NO_SYNC_MODE;
1798 dev_err(dev, "could not get sync mode!\n");
1799 } else {
1800 if (strcmp(sync_mode_name, RKMODULE_EXTERNAL_MASTER_MODE) == 0)
1801 imx492->sync_mode = EXTERNAL_MASTER_MODE;
1802 else if (strcmp(sync_mode_name, RKMODULE_INTERNAL_MASTER_MODE) == 0)
1803 imx492->sync_mode = INTERNAL_MASTER_MODE;
1804 else if (strcmp(sync_mode_name, RKMODULE_SLAVE_MODE) == 0)
1805 imx492->sync_mode = SLAVE_MODE;
1806 }
1807
1808 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1809 if (ret) {
1810 hdr_mode = NO_HDR;
1811 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
1812 }
1813 imx492->client = client;
1814 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1815 if (!endpoint) {
1816 dev_err(dev, "Failed to get endpoint\n");
1817 return -EINVAL;
1818 }
1819 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
1820 &imx492->bus_cfg);
1821 if (ret) {
1822 dev_err(dev, "Failed to get bus cfg\n");
1823 return ret;
1824 }
1825 imx492->support_modes = supported_modes;
1826 imx492->cfg_num = ARRAY_SIZE(supported_modes);
1827
1828 for (i = 0; i < imx492->cfg_num; i++) {
1829 if (hdr_mode == imx492->support_modes[i].hdr_mode) {
1830 imx492->cur_mode = &imx492->support_modes[i];
1831 break;
1832 }
1833 }
1834 imx492->xvclk = devm_clk_get(dev, "xvclk");
1835 if (IS_ERR(imx492->xvclk)) {
1836 dev_err(dev, "Failed to get xvclk\n");
1837 return -EINVAL;
1838 }
1839
1840 imx492->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1841 if (IS_ERR(imx492->reset_gpio))
1842 dev_warn(dev, "Failed to get reset-gpios\n");
1843
1844 imx492->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1845 if (IS_ERR(imx492->pwdn_gpio))
1846 dev_warn(dev, "Failed to get pwdn-gpios\n");
1847
1848 imx492->pinctrl = devm_pinctrl_get(dev);
1849 if (!IS_ERR(imx492->pinctrl)) {
1850 imx492->pins_default =
1851 pinctrl_lookup_state(imx492->pinctrl,
1852 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1853 if (IS_ERR(imx492->pins_default))
1854 dev_err(dev, "could not get default pinstate\n");
1855
1856 imx492->pins_sleep =
1857 pinctrl_lookup_state(imx492->pinctrl,
1858 OF_CAMERA_PINCTRL_STATE_SLEEP);
1859 if (IS_ERR(imx492->pins_sleep))
1860 dev_err(dev, "could not get sleep pinstate\n");
1861 } else {
1862 dev_err(dev, "no pinctrl\n");
1863 }
1864
1865 ret = imx492_configure_regulators(imx492);
1866 if (ret) {
1867 dev_err(dev, "Failed to get power regulators\n");
1868 return ret;
1869 }
1870
1871 mutex_init(&imx492->mutex);
1872
1873 sd = &imx492->subdev;
1874 v4l2_i2c_subdev_init(sd, client, &imx492_subdev_ops);
1875 ret = imx492_initialize_controls(imx492);
1876 if (ret)
1877 goto err_destroy_mutex;
1878
1879 ret = __imx492_power_on(imx492);
1880 if (ret)
1881 goto err_free_handler;
1882
1883 ret = imx492_check_sensor_id(imx492, client);
1884 if (ret)
1885 goto err_power_off;
1886
1887 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1888 sd->internal_ops = &imx492_internal_ops;
1889 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1890 #endif
1891 #if defined(CONFIG_MEDIA_CONTROLLER)
1892 imx492->pad.flags = MEDIA_PAD_FL_SOURCE;
1893 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1894 ret = media_entity_pads_init(&sd->entity, 1, &imx492->pad);
1895 if (ret < 0)
1896 goto err_power_off;
1897 #endif
1898
1899 memset(facing, 0, sizeof(facing));
1900 if (strcmp(imx492->module_facing, "back") == 0)
1901 facing[0] = 'b';
1902 else
1903 facing[0] = 'f';
1904
1905 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1906 imx492->module_index, facing,
1907 IMX492_NAME, dev_name(sd->dev));
1908 ret = v4l2_async_register_subdev_sensor_common(sd);
1909 if (ret) {
1910 dev_err(dev, "v4l2 async register subdev failed\n");
1911 goto err_clean_entity;
1912 }
1913
1914 pm_runtime_set_active(dev);
1915 pm_runtime_enable(dev);
1916 pm_runtime_idle(dev);
1917
1918 return 0;
1919
1920 err_clean_entity:
1921 #if defined(CONFIG_MEDIA_CONTROLLER)
1922 media_entity_cleanup(&sd->entity);
1923 #endif
1924 err_power_off:
1925 __imx492_power_off(imx492);
1926 err_free_handler:
1927 v4l2_ctrl_handler_free(&imx492->ctrl_handler);
1928 err_destroy_mutex:
1929 mutex_destroy(&imx492->mutex);
1930
1931 return ret;
1932 }
1933
imx492_remove(struct i2c_client * client)1934 static int imx492_remove(struct i2c_client *client)
1935 {
1936 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1937 struct imx492 *imx492 = to_IMX492(sd);
1938
1939 v4l2_async_unregister_subdev(sd);
1940 #if defined(CONFIG_MEDIA_CONTROLLER)
1941 media_entity_cleanup(&sd->entity);
1942 #endif
1943 v4l2_ctrl_handler_free(&imx492->ctrl_handler);
1944 mutex_destroy(&imx492->mutex);
1945
1946 pm_runtime_disable(&client->dev);
1947 if (!pm_runtime_status_suspended(&client->dev))
1948 __imx492_power_off(imx492);
1949 pm_runtime_set_suspended(&client->dev);
1950
1951 return 0;
1952 }
1953
1954 #if IS_ENABLED(CONFIG_OF)
1955 static const struct of_device_id imx492_of_match[] = {
1956 { .compatible = "sony,imx492" },
1957 {},
1958 };
1959 MODULE_DEVICE_TABLE(of, imx492_of_match);
1960 #endif
1961
1962 static const struct i2c_device_id imx492_match_id[] = {
1963 { "sony,imx492", 0 },
1964 { },
1965 };
1966
1967 static struct i2c_driver imx492_i2c_driver = {
1968 .driver = {
1969 .name = IMX492_NAME,
1970 .pm = &imx492_pm_ops,
1971 .of_match_table = of_match_ptr(imx492_of_match),
1972 },
1973 .probe = &imx492_probe,
1974 .remove = &imx492_remove,
1975 .id_table = imx492_match_id,
1976 };
1977
sensor_mod_init(void)1978 static int __init sensor_mod_init(void)
1979 {
1980 return i2c_add_driver(&imx492_i2c_driver);
1981 }
1982
sensor_mod_exit(void)1983 static void __exit sensor_mod_exit(void)
1984 {
1985 i2c_del_driver(&imx492_i2c_driver);
1986 }
1987
1988 device_initcall_sync(sensor_mod_init);
1989 module_exit(sensor_mod_exit);
1990
1991 MODULE_DESCRIPTION("Sony IMX492 sensor driver");
1992 MODULE_LICENSE("GPL");
1993