1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx415 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01
9 * 1. fix hdr ae ratio error,
10 * 0x3260 should be set 0x01 in normal mode,
11 * should be 0x00 in hdr mode.
12 * 2. rhs1 should be 4n+1 when set hdr ae.
13 * V0.0X01.0X02
14 * 1. shr0 should be greater than (rsh1 + 9).
15 * 2. rhs1 should be ceil to 4n + 1.
16 * V0.0X01.0X03
17 * 1. support 12bit HDR DOL3
18 * 2. support HDR/Linear quick switch
19 * V0.0X01.0X04
20 * 1. support enum format info by aiq
21 * V0.0X01.0X05
22 * 1. fixed 10bit hdr2/hdr3 frame rate issue
23 * V0.0X01.0X06
24 * 1. support DOL3 10bit 20fps 1485Mbps
25 * 2. fixed linkfreq error
26 * V0.0X01.0X07
27 * 1. fix set_fmt & ioctl get mode unmatched issue.
28 * 2. need to set default vblank when change format.
29 * 3. enum all supported mode mbus_code, not just cur_mode.
30 * V0.0X01.0X08
31 * 1. add dcphy param for hdrx2 mode.
32 */
33
34 #define DEBUG
35 #include <linux/clk.h>
36 #include <linux/device.h>
37 #include <linux/delay.h>
38 #include <linux/gpio/consumer.h>
39 #include <linux/i2c.h>
40 #include <linux/module.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/sysfs.h>
44 #include <linux/slab.h>
45 #include <linux/version.h>
46 #include <linux/rk-camera-module.h>
47 #include <media/media-entity.h>
48 #include <media/v4l2-async.h>
49 #include <media/v4l2-ctrls.h>
50 #include <media/v4l2-subdev.h>
51 #include <linux/pinctrl/consumer.h>
52 #include <linux/rk-preisp.h>
53 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
54
55 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x08)
56
57 #ifndef V4L2_CID_DIGITAL_GAIN
58 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
59 #endif
60
61 #define MIPI_FREQ_891M 891000000
62 #define MIPI_FREQ_446M 446000000
63 #define MIPI_FREQ_743M 743000000
64 #define MIPI_FREQ_297M 297000000
65
66 #define IMX415_4LANES 4
67
68 #define IMX415_MAX_PIXEL_RATE (MIPI_FREQ_891M / 10 * 2 * IMX415_4LANES)
69 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
70
71 #define IMX415_XVCLK_FREQ_37M 37125000
72
73 /* TODO: Get the real chip id from reg */
74 #define CHIP_ID 0xE0
75 #define IMX415_REG_CHIP_ID 0x311A
76
77 #define IMX415_REG_CTRL_MODE 0x3000
78 #define IMX415_MODE_SW_STANDBY BIT(0)
79 #define IMX415_MODE_STREAMING 0x0
80
81 #define IMX415_LF_GAIN_REG_H 0x3091
82 #define IMX415_LF_GAIN_REG_L 0x3090
83
84 #define IMX415_SF1_GAIN_REG_H 0x3093
85 #define IMX415_SF1_GAIN_REG_L 0x3092
86
87 #define IMX415_SF2_GAIN_REG_H 0x3095
88 #define IMX415_SF2_GAIN_REG_L 0x3094
89
90 #define IMX415_LF_EXPO_REG_H 0x3052
91 #define IMX415_LF_EXPO_REG_M 0x3051
92 #define IMX415_LF_EXPO_REG_L 0x3050
93
94 #define IMX415_SF1_EXPO_REG_H 0x3056
95 #define IMX415_SF1_EXPO_REG_M 0x3055
96 #define IMX415_SF1_EXPO_REG_L 0x3054
97
98 #define IMX415_SF2_EXPO_REG_H 0x305A
99 #define IMX415_SF2_EXPO_REG_M 0x3059
100 #define IMX415_SF2_EXPO_REG_L 0x3058
101
102 #define IMX415_RHS1_REG_H 0x3062
103 #define IMX415_RHS1_REG_M 0x3061
104 #define IMX415_RHS1_REG_L 0x3060
105 #define IMX415_RHS1_DEFAULT 0x004D
106
107 #define IMX415_RHS2_REG_H 0x3066
108 #define IMX415_RHS2_REG_M 0x3065
109 #define IMX415_RHS2_REG_L 0x3064
110 #define IMX415_RHS2_DEFAULT 0x004D
111
112 #define IMX415_EXPOSURE_MIN 4
113 #define IMX415_EXPOSURE_STEP 1
114 #define IMX415_VTS_MAX 0x7fff
115
116 #define IMX415_GAIN_MIN 0x00
117 #define IMX415_GAIN_MAX 0xf0
118 #define IMX415_GAIN_STEP 1
119 #define IMX415_GAIN_DEFAULT 0x00
120
121 #define IMX415_FETCH_GAIN_H(VAL) (((VAL) >> 8) & 0x07)
122 #define IMX415_FETCH_GAIN_L(VAL) ((VAL) & 0xFF)
123
124 #define IMX415_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0x0F)
125 #define IMX415_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF)
126 #define IMX415_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
127
128 #define IMX415_FETCH_RHS1_H(VAL) (((VAL) >> 16) & 0x0F)
129 #define IMX415_FETCH_RHS1_M(VAL) (((VAL) >> 8) & 0xFF)
130 #define IMX415_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
131
132 #define IMX415_FETCH_VTS_H(VAL) (((VAL) >> 16) & 0x0F)
133 #define IMX415_FETCH_VTS_M(VAL) (((VAL) >> 8) & 0xFF)
134 #define IMX415_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
135
136 #define IMX415_VTS_REG_L 0x3024
137 #define IMX415_VTS_REG_M 0x3025
138 #define IMX415_VTS_REG_H 0x3026
139
140 #define IMX415_MIRROR_BIT_MASK BIT(0)
141 #define IMX415_FLIP_BIT_MASK BIT(1)
142 #define IMX415_FLIP_REG 0x3030
143
144 #define REG_NULL 0xFFFF
145
146 #define IMX415_REG_VALUE_08BIT 1
147 #define IMX415_REG_VALUE_16BIT 2
148 #define IMX415_REG_VALUE_24BIT 3
149
150 #define IMX415_GROUP_HOLD_REG 0x3001
151 #define IMX415_GROUP_HOLD_START 0x01
152 #define IMX415_GROUP_HOLD_END 0x00
153
154 /* Basic Readout Lines. Number of necessary readout lines in sensor */
155 #define BRL_ALL 2228u
156 #define BRL_BINNING 1115u
157 /* Readout timing setting of SEF1(DOL2): RHS1 < 2 * BRL and should be 4n + 1 */
158 #define RHS1_MAX_X2(VAL) (((VAL) * 2 - 1) / 4 * 4 + 1)
159 #define SHR1_MIN_X2 9u
160
161 /* Readout timing setting of SEF1(DOL3): RHS1 < 3 * BRL and should be 6n + 1 */
162 #define RHS1_MAX_X3(VAL) (((VAL) * 3 - 1) / 6 * 6 + 1)
163 #define SHR1_MIN_X3 13u
164
165 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
166 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
167
168 #define IMX415_NAME "imx415"
169
170 static const char * const imx415_supply_names[] = {
171 "dvdd", /* Digital core power */
172 "dovdd", /* Digital I/O power */
173 "avdd", /* Analog power */
174 };
175
176 #define IMX415_NUM_SUPPLIES ARRAY_SIZE(imx415_supply_names)
177
178 struct regval {
179 u16 addr;
180 u8 val;
181 };
182
183 struct imx415_mode {
184 u32 bus_fmt;
185 u32 width;
186 u32 height;
187 struct v4l2_fract max_fps;
188 u32 hts_def;
189 u32 vts_def;
190 u32 exp_def;
191 u32 mipi_freq_idx;
192 u32 bpp;
193 const struct regval *global_reg_list;
194 const struct regval *reg_list;
195 u32 hdr_mode;
196 u32 vc[PAD_MAX];
197 };
198
199 struct imx415 {
200 struct i2c_client *client;
201 struct clk *xvclk;
202 struct gpio_desc *reset_gpio;
203 struct gpio_desc *power_gpio;
204 struct regulator_bulk_data supplies[IMX415_NUM_SUPPLIES];
205
206 struct pinctrl *pinctrl;
207 struct pinctrl_state *pins_default;
208 struct pinctrl_state *pins_sleep;
209
210 struct v4l2_subdev subdev;
211 struct media_pad pad;
212 struct v4l2_ctrl_handler ctrl_handler;
213 struct v4l2_ctrl *exposure;
214 struct v4l2_ctrl *anal_a_gain;
215 struct v4l2_ctrl *digi_gain;
216 struct v4l2_ctrl *hblank;
217 struct v4l2_ctrl *vblank;
218 struct v4l2_ctrl *pixel_rate;
219 struct v4l2_ctrl *link_freq;
220 struct mutex mutex;
221 bool streaming;
222 bool power_on;
223 bool is_thunderboot;
224 bool is_thunderboot_ng;
225 bool is_first_streamoff;
226 const struct imx415_mode *cur_mode;
227 u32 module_index;
228 u32 cfg_num;
229 const char *module_facing;
230 const char *module_name;
231 const char *len_name;
232 u32 cur_vts;
233 bool has_init_exp;
234 struct preisp_hdrae_exp_s init_hdrae_exp;
235 };
236
237 static struct rkmodule_csi_dphy_param dcphy_param = {
238 .vendor = PHY_VENDOR_SAMSUNG,
239 .lp_vol_ref = 6,
240 .lp_hys_sw = {3, 0, 0, 0},
241 .lp_escclk_pol_sel = {1, 1, 1, 1},
242 .skew_data_cal_clk = {0, 3, 3, 3},
243 .clk_hs_term_sel = 2,
244 .data_hs_term_sel = {2, 2, 2, 2},
245 .reserved = {0},
246 };
247
248 #define to_imx415(sd) container_of(sd, struct imx415, subdev)
249
250 /*
251 * Xclk 37.125Mhz
252 */
253 static __maybe_unused const struct regval imx415_global_12bit_3864x2192_regs[] = {
254 {0x3002, 0x00},
255 {0x3008, 0x7F},
256 {0x300A, 0x5B},
257 {0x30C1, 0x00},
258 {0x3031, 0x01},
259 {0x3032, 0x01},
260 {0x30D9, 0x06},
261 {0x3116, 0x24},
262 {0x3118, 0xC0},
263 {0x311E, 0x24},
264 {0x32D4, 0x21},
265 {0x32EC, 0xA1},
266 {0x3452, 0x7F},
267 {0x3453, 0x03},
268 {0x358A, 0x04},
269 {0x35A1, 0x02},
270 {0x36BC, 0x0C},
271 {0x36CC, 0x53},
272 {0x36CD, 0x00},
273 {0x36CE, 0x3C},
274 {0x36D0, 0x8C},
275 {0x36D1, 0x00},
276 {0x36D2, 0x71},
277 {0x36D4, 0x3C},
278 {0x36D6, 0x53},
279 {0x36D7, 0x00},
280 {0x36D8, 0x71},
281 {0x36DA, 0x8C},
282 {0x36DB, 0x00},
283 {0x3701, 0x03},
284 {0x3724, 0x02},
285 {0x3726, 0x02},
286 {0x3732, 0x02},
287 {0x3734, 0x03},
288 {0x3736, 0x03},
289 {0x3742, 0x03},
290 {0x3862, 0xE0},
291 {0x38CC, 0x30},
292 {0x38CD, 0x2F},
293 {0x395C, 0x0C},
294 {0x3A42, 0xD1},
295 {0x3A4C, 0x77},
296 {0x3AE0, 0x02},
297 {0x3AEC, 0x0C},
298 {0x3B00, 0x2E},
299 {0x3B06, 0x29},
300 {0x3B98, 0x25},
301 {0x3B99, 0x21},
302 {0x3B9B, 0x13},
303 {0x3B9C, 0x13},
304 {0x3B9D, 0x13},
305 {0x3B9E, 0x13},
306 {0x3BA1, 0x00},
307 {0x3BA2, 0x06},
308 {0x3BA3, 0x0B},
309 {0x3BA4, 0x10},
310 {0x3BA5, 0x14},
311 {0x3BA6, 0x18},
312 {0x3BA7, 0x1A},
313 {0x3BA8, 0x1A},
314 {0x3BA9, 0x1A},
315 {0x3BAC, 0xED},
316 {0x3BAD, 0x01},
317 {0x3BAE, 0xF6},
318 {0x3BAF, 0x02},
319 {0x3BB0, 0xA2},
320 {0x3BB1, 0x03},
321 {0x3BB2, 0xE0},
322 {0x3BB3, 0x03},
323 {0x3BB4, 0xE0},
324 {0x3BB5, 0x03},
325 {0x3BB6, 0xE0},
326 {0x3BB7, 0x03},
327 {0x3BB8, 0xE0},
328 {0x3BBA, 0xE0},
329 {0x3BBC, 0xDA},
330 {0x3BBE, 0x88},
331 {0x3BC0, 0x44},
332 {0x3BC2, 0x7B},
333 {0x3BC4, 0xA2},
334 {0x3BC8, 0xBD},
335 {0x3BCA, 0xBD},
336 {0x4004, 0x48},
337 {0x4005, 0x09},
338 {REG_NULL, 0x00},
339 };
340
341 static __maybe_unused const struct regval imx415_linear_12bit_3864x2192_891M_regs[] = {
342 {0x3020, 0x00},
343 {0x3021, 0x00},
344 {0x3022, 0x00},
345 {0x3024, 0xCA},
346 {0x3025, 0x08},
347 {0x3028, 0x4C},
348 {0x3029, 0x04},
349 {0x302C, 0x00},
350 {0x302D, 0x00},
351 {0x3033, 0x05},
352 {0x3050, 0x08},
353 {0x3051, 0x00},
354 {0x3054, 0x19},
355 {0x3058, 0x3E},
356 {0x3060, 0x25},
357 {0x3064, 0x4A},
358 {0x30CF, 0x00},
359 {0x3260, 0x01},
360 {0x400C, 0x00},
361 {0x4018, 0x7F},
362 {0x401A, 0x37},
363 {0x401C, 0x37},
364 {0x401E, 0xF7},
365 {0x401F, 0x00},
366 {0x4020, 0x3F},
367 {0x4022, 0x6F},
368 {0x4024, 0x3F},
369 {0x4026, 0x5F},
370 {0x4028, 0x2F},
371 {0x4074, 0x01},
372 {REG_NULL, 0x00},
373 };
374
375 static __maybe_unused const struct regval imx415_hdr2_12bit_3864x2192_1782M_regs[] = {
376 {0x3020, 0x00},
377 {0x3021, 0x00},
378 {0x3022, 0x00},
379 {0x3024, 0xCA},
380 {0x3025, 0x08},
381 {0x3028, 0x26},
382 {0x3029, 0x02},
383 {0x302C, 0x01},
384 {0x302D, 0x01},
385 {0x3033, 0x04},
386 {0x3050, 0x90},
387 {0x3051, 0x0D},
388 {0x3054, 0x09},
389 {0x3058, 0x3E},
390 {0x3060, 0x4D},
391 {0x3064, 0x4A},
392 {0x30CF, 0x01},
393 {0x3260, 0x00},
394 {0x400C, 0x01},
395 {0x4018, 0xB7},
396 {0x401A, 0x67},
397 {0x401C, 0x6F},
398 {0x401E, 0xDF},
399 {0x401F, 0x01},
400 {0x4020, 0x6F},
401 {0x4022, 0xCF},
402 {0x4024, 0x6F},
403 {0x4026, 0xB7},
404 {0x4028, 0x5F},
405 {0x4074, 0x00},
406 {REG_NULL, 0x00},
407 };
408
409 static __maybe_unused const struct regval imx415_hdr3_12bit_3864x2192_1782M_regs[] = {
410 {0x3020, 0x00},
411 {0x3021, 0x00},
412 {0x3022, 0x00},
413 {0x3024, 0x96},
414 {0x3025, 0x06},
415 {0x3028, 0x26},
416 {0x3029, 0x02},
417 {0x302C, 0x01},
418 {0x302D, 0x02},
419 {0x3033, 0x04},
420 {0x3050, 0x14},
421 {0x3051, 0x01},
422 {0x3054, 0x0D},
423 {0x3058, 0x26},
424 {0x3060, 0x19},
425 {0x3064, 0x32},
426 {0x30CF, 0x03},
427 {0x3260, 0x00},
428 {0x400C, 0x01},
429 {0x4018, 0xB7},
430 {0x401A, 0x67},
431 {0x401C, 0x6F},
432 {0x401E, 0xDF},
433 {0x401F, 0x01},
434 {0x4020, 0x6F},
435 {0x4022, 0xCF},
436 {0x4024, 0x6F},
437 {0x4026, 0xB7},
438 {0x4028, 0x5F},
439 {0x4074, 0x00},
440 {REG_NULL, 0x00},
441 };
442
443 static __maybe_unused const struct regval imx415_global_10bit_3864x2192_regs[] = {
444 {0x3002, 0x00},
445 {0x3008, 0x7F},
446 {0x300A, 0x5B},
447 {0x3031, 0x00},
448 {0x3032, 0x00},
449 {0x30C1, 0x00},
450 {0x30D9, 0x06},
451 {0x3116, 0x24},
452 {0x311E, 0x24},
453 {0x32D4, 0x21},
454 {0x32EC, 0xA1},
455 {0x3452, 0x7F},
456 {0x3453, 0x03},
457 {0x358A, 0x04},
458 {0x35A1, 0x02},
459 {0x36BC, 0x0C},
460 {0x36CC, 0x53},
461 {0x36CD, 0x00},
462 {0x36CE, 0x3C},
463 {0x36D0, 0x8C},
464 {0x36D1, 0x00},
465 {0x36D2, 0x71},
466 {0x36D4, 0x3C},
467 {0x36D6, 0x53},
468 {0x36D7, 0x00},
469 {0x36D8, 0x71},
470 {0x36DA, 0x8C},
471 {0x36DB, 0x00},
472 {0x3701, 0x00},
473 {0x3724, 0x02},
474 {0x3726, 0x02},
475 {0x3732, 0x02},
476 {0x3734, 0x03},
477 {0x3736, 0x03},
478 {0x3742, 0x03},
479 {0x3862, 0xE0},
480 {0x38CC, 0x30},
481 {0x38CD, 0x2F},
482 {0x395C, 0x0C},
483 {0x3A42, 0xD1},
484 {0x3A4C, 0x77},
485 {0x3AE0, 0x02},
486 {0x3AEC, 0x0C},
487 {0x3B00, 0x2E},
488 {0x3B06, 0x29},
489 {0x3B98, 0x25},
490 {0x3B99, 0x21},
491 {0x3B9B, 0x13},
492 {0x3B9C, 0x13},
493 {0x3B9D, 0x13},
494 {0x3B9E, 0x13},
495 {0x3BA1, 0x00},
496 {0x3BA2, 0x06},
497 {0x3BA3, 0x0B},
498 {0x3BA4, 0x10},
499 {0x3BA5, 0x14},
500 {0x3BA6, 0x18},
501 {0x3BA7, 0x1A},
502 {0x3BA8, 0x1A},
503 {0x3BA9, 0x1A},
504 {0x3BAC, 0xED},
505 {0x3BAD, 0x01},
506 {0x3BAE, 0xF6},
507 {0x3BAF, 0x02},
508 {0x3BB0, 0xA2},
509 {0x3BB1, 0x03},
510 {0x3BB2, 0xE0},
511 {0x3BB3, 0x03},
512 {0x3BB4, 0xE0},
513 {0x3BB5, 0x03},
514 {0x3BB6, 0xE0},
515 {0x3BB7, 0x03},
516 {0x3BB8, 0xE0},
517 {0x3BBA, 0xE0},
518 {0x3BBC, 0xDA},
519 {0x3BBE, 0x88},
520 {0x3BC0, 0x44},
521 {0x3BC2, 0x7B},
522 {0x3BC4, 0xA2},
523 {0x3BC8, 0xBD},
524 {0x3BCA, 0xBD},
525 {0x4004, 0x48},
526 {0x4005, 0x09},
527 {REG_NULL, 0x00},
528 };
529
530 static __maybe_unused const struct regval imx415_hdr3_10bit_3864x2192_1485M_regs[] = {
531 {0x3020, 0x00},
532 {0x3021, 0x00},
533 {0x3022, 0x00},
534 {0x3024, 0xBD},
535 {0x3025, 0x06},
536 {0x3028, 0x1A},
537 {0x3029, 0x02},
538 {0x302C, 0x01},
539 {0x302D, 0x02},
540 {0x3033, 0x08},
541 {0x3050, 0x90},
542 {0x3051, 0x15},
543 {0x3054, 0x0D},
544 {0x3058, 0xA4},
545 {0x3060, 0x97},
546 {0x3064, 0xB6},
547 {0x30CF, 0x03},
548 {0x3118, 0xA0},
549 {0x3260, 0x00},
550 {0x400C, 0x01},
551 {0x4018, 0xA7},
552 {0x401A, 0x57},
553 {0x401C, 0x5F},
554 {0x401E, 0x97},
555 {0x401F, 0x01},
556 {0x4020, 0x5F},
557 {0x4022, 0xAF},
558 {0x4024, 0x5F},
559 {0x4026, 0x9F},
560 {0x4028, 0x4F},
561 {0x4074, 0x00},
562 {REG_NULL, 0x00},
563 };
564
565 static __maybe_unused const struct regval imx415_hdr3_10bit_3864x2192_1782M_regs[] = {
566 {0x3020, 0x00},
567 {0x3021, 0x00},
568 {0x3022, 0x00},
569 {0x3024, 0xEA},
570 {0x3025, 0x07},
571 {0x3028, 0xCA},
572 {0x3029, 0x01},
573 {0x302C, 0x01},
574 {0x302D, 0x02},
575 {0x3033, 0x04},
576 {0x3050, 0x3E},
577 {0x3051, 0x01},
578 {0x3054, 0x0D},
579 {0x3058, 0x9E},
580 {0x3060, 0x91},
581 {0x3064, 0xC2},
582 {0x30CF, 0x03},
583 {0x3118, 0xC0},
584 {0x3260, 0x00},
585 {0x400C, 0x01},
586 {0x4018, 0xB7},
587 {0x401A, 0x67},
588 {0x401C, 0x6F},
589 {0x401E, 0xDF},
590 {0x401F, 0x01},
591 {0x4020, 0x6F},
592 {0x4022, 0xCF},
593 {0x4024, 0x6F},
594 {0x4026, 0xB7},
595 {0x4028, 0x5F},
596 {0x4074, 0x00},
597 {REG_NULL, 0x00},
598 };
599
600 static __maybe_unused const struct regval imx415_hdr2_10bit_3864x2192_1485M_regs[] = {
601 {0x3020, 0x00},
602 {0x3021, 0x00},
603 {0x3022, 0x00},
604 {0x3024, 0xFC},
605 {0x3025, 0x08},
606 {0x3028, 0x1A},
607 {0x3029, 0x02},
608 {0x302C, 0x01},
609 {0x302D, 0x01},
610 {0x3033, 0x08},
611 {0x3050, 0xA8},
612 {0x3051, 0x0D},
613 {0x3054, 0x09},
614 {0x3058, 0x3E},
615 {0x3060, 0x4D},
616 {0x3064, 0x4a},
617 {0x30CF, 0x01},
618 {0x3118, 0xA0},
619 {0x3260, 0x00},
620 {0x400C, 0x01},
621 {0x4018, 0xA7},
622 {0x401A, 0x57},
623 {0x401C, 0x5F},
624 {0x401E, 0x97},
625 {0x401F, 0x01},
626 {0x4020, 0x5F},
627 {0x4022, 0xAF},
628 {0x4024, 0x5F},
629 {0x4026, 0x9F},
630 {0x4028, 0x4F},
631 {0x4074, 0x00},
632 {REG_NULL, 0x00},
633 };
634
635 static __maybe_unused const struct regval imx415_linear_10bit_3864x2192_891M_regs[] = {
636 {0x3020, 0x00},
637 {0x3021, 0x00},
638 {0x3022, 0x00},
639 {0x3024, 0xCA},
640 {0x3025, 0x08},
641 {0x3028, 0x4C},
642 {0x3029, 0x04},
643 {0x302C, 0x00},
644 {0x302D, 0x00},
645 {0x3033, 0x05},
646 {0x3050, 0x08},
647 {0x3051, 0x00},
648 {0x3054, 0x19},
649 {0x3058, 0x3E},
650 {0x3060, 0x25},
651 {0x3064, 0x4a},
652 {0x30CF, 0x00},
653 {0x3118, 0xC0},
654 {0x3260, 0x01},
655 {0x400C, 0x00},
656 {0x4018, 0x7F},
657 {0x401A, 0x37},
658 {0x401C, 0x37},
659 {0x401E, 0xF7},
660 {0x401F, 0x00},
661 {0x4020, 0x3F},
662 {0x4022, 0x6F},
663 {0x4024, 0x3F},
664 {0x4026, 0x5F},
665 {0x4028, 0x2F},
666 {0x4074, 0x01},
667 {REG_NULL, 0x00},
668 };
669
670 static __maybe_unused const struct regval imx415_linear_12bit_1932x1096_594M_regs[] = {
671 {0x3020, 0x01},
672 {0x3021, 0x01},
673 {0x3022, 0x01},
674 {0x3024, 0x5D},
675 {0x3025, 0x0C},
676 {0x3028, 0x0E},
677 {0x3029, 0x03},
678 {0x302C, 0x00},
679 {0x302D, 0x00},
680 {0x3031, 0x00},
681 {0x3033, 0x07},
682 {0x3050, 0x08},
683 {0x3051, 0x00},
684 {0x3054, 0x19},
685 {0x3058, 0x3E},
686 {0x3060, 0x25},
687 {0x3064, 0x4A},
688 {0x30CF, 0x00},
689 {0x30D9, 0x02},
690 {0x30DA, 0x01},
691 {0x3118, 0x80},
692 {0x3260, 0x01},
693 {0x3701, 0x00},
694 {0x400C, 0x00},
695 {0x4018, 0x67},
696 {0x401A, 0x27},
697 {0x401C, 0x27},
698 {0x401E, 0xB7},
699 {0x401F, 0x00},
700 {0x4020, 0x2F},
701 {0x4022, 0x4F},
702 {0x4024, 0x2F},
703 {0x4026, 0x47},
704 {0x4028, 0x27},
705 {0x4074, 0x01},
706 {REG_NULL, 0x00},
707 };
708
709 static __maybe_unused const struct regval imx415_hdr2_12bit_1932x1096_891M_regs[] = {
710 {0x3020, 0x01},
711 {0x3021, 0x01},
712 {0x3022, 0x01},
713 {0x3024, 0xFC},
714 {0x3025, 0x08},
715 {0x3028, 0x1A},
716 {0x3029, 0x02},
717 {0x302C, 0x01},
718 {0x302D, 0x01},
719 {0x3031, 0x00},
720 {0x3033, 0x05},
721 {0x3050, 0xB8},
722 {0x3051, 0x00},
723 {0x3054, 0x09},
724 {0x3058, 0x3E},
725 {0x3060, 0x25},
726 {0x3064, 0x4A},
727 {0x30CF, 0x01},
728 {0x30D9, 0x02},
729 {0x30DA, 0x01},
730 {0x3118, 0xC0},
731 {0x3260, 0x00},
732 {0x3701, 0x00},
733 {0x400C, 0x00},
734 {0x4018, 0xA7},
735 {0x401A, 0x57},
736 {0x401C, 0x5F},
737 {0x401E, 0x97},
738 {0x401F, 0x01},
739 {0x4020, 0x5F},
740 {0x4022, 0xAF},
741 {0x4024, 0x5F},
742 {0x4026, 0x9F},
743 {0x4028, 0x4F},
744 {0x4074, 0x01},
745 {REG_NULL, 0x00},
746 };
747
748 /*
749 * The width and height must be configured to be
750 * the same as the current output resolution of the sensor.
751 * The input width of the isp needs to be 16 aligned.
752 * The input height of the isp needs to be 8 aligned.
753 * If the width or height does not meet the alignment rules,
754 * you can configure the cropping parameters with the following function to
755 * crop out the appropriate resolution.
756 * struct v4l2_subdev_pad_ops {
757 * .get_selection
758 * }
759 */
760 static const struct imx415_mode supported_modes[] = {
761 /*
762 * frame rate = 1 / (Vtt * 1H) = 1 / (VMAX * 1H)
763 * VMAX >= (PIX_VWIDTH / 2) + 46 = height + 46
764 */
765 {
766 .bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
767 .width = 3864,
768 .height = 2192,
769 .max_fps = {
770 .numerator = 10000,
771 .denominator = 300000,
772 },
773 .exp_def = 0x08ca - 0x08,
774 .hts_def = 0x044c * IMX415_4LANES * 2,
775 .vts_def = 0x08ca,
776 .global_reg_list = imx415_global_10bit_3864x2192_regs,
777 .reg_list = imx415_linear_10bit_3864x2192_891M_regs,
778 .hdr_mode = NO_HDR,
779 .mipi_freq_idx = 1,
780 .bpp = 10,
781 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
782 },
783 {
784 .bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
785 .width = 3864,
786 .height = 2192,
787 .max_fps = {
788 .numerator = 10000,
789 .denominator = 300000,
790 },
791 .exp_def = 0x08fc * 2 - 0x0da8,
792 .hts_def = 0x0226 * IMX415_4LANES * 2,
793 /*
794 * IMX415 HDR mode T-line is half of Linear mode,
795 * make vts double to workaround.
796 */
797 .vts_def = 0x08fc * 2,
798 .global_reg_list = imx415_global_10bit_3864x2192_regs,
799 .reg_list = imx415_hdr2_10bit_3864x2192_1485M_regs,
800 .hdr_mode = HDR_X2,
801 .mipi_freq_idx = 2,
802 .bpp = 10,
803 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
804 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
805 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
806 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
807 },
808 {
809 .bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
810 .width = 3864,
811 .height = 2192,
812 .max_fps = {
813 .numerator = 10000,
814 .denominator = 200000,
815 },
816 .exp_def = 0x13e,
817 .hts_def = 0x021A * IMX415_4LANES * 2,
818 /*
819 * IMX415 HDR mode T-line is half of Linear mode,
820 * make vts double to workaround.
821 */
822 .vts_def = 0x06BD * 4,
823 .global_reg_list = imx415_global_10bit_3864x2192_regs,
824 .reg_list = imx415_hdr3_10bit_3864x2192_1485M_regs,
825 .hdr_mode = HDR_X3,
826 .mipi_freq_idx = 2,
827 .bpp = 10,
828 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
829 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
830 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
831 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
832 },
833 {
834 .bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
835 .width = 3864,
836 .height = 2192,
837 .max_fps = {
838 .numerator = 10000,
839 .denominator = 200000,
840 },
841 .exp_def = 0x13e,
842 .hts_def = 0x01ca * IMX415_4LANES * 2,
843 /*
844 * IMX415 HDR mode T-line is half of Linear mode,
845 * make vts double to workaround.
846 */
847 .vts_def = 0x07ea * 4,
848 .global_reg_list = imx415_global_10bit_3864x2192_regs,
849 .reg_list = imx415_hdr3_10bit_3864x2192_1782M_regs,
850 .hdr_mode = HDR_X3,
851 .mipi_freq_idx = 3,
852 .bpp = 10,
853 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
854 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
855 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
856 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
857 },
858 {
859 /* 1H period = (1100 clock) = (1100 * 1 / 74.25MHz) */
860 .bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
861 .width = 3864,
862 .height = 2192,
863 .max_fps = {
864 .numerator = 10000,
865 .denominator = 300000,
866 },
867 .exp_def = 0x08ca - 0x08,
868 .hts_def = 0x044c * IMX415_4LANES * 2,
869 .vts_def = 0x08ca,
870 .global_reg_list = imx415_global_12bit_3864x2192_regs,
871 .reg_list = imx415_linear_12bit_3864x2192_891M_regs,
872 .hdr_mode = NO_HDR,
873 .mipi_freq_idx = 1,
874 .bpp = 12,
875 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
876 },
877 {
878 .bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
879 .width = 3864,
880 .height = 2192,
881 .max_fps = {
882 .numerator = 10000,
883 .denominator = 300000,
884 },
885 .exp_def = 0x08CA * 2 - 0x0d90,
886 .hts_def = 0x0226 * IMX415_4LANES * 2,
887 /*
888 * IMX415 HDR mode T-line is half of Linear mode,
889 * make vts double(that is FSC) to workaround.
890 */
891 .vts_def = 0x08CA * 2,
892 .global_reg_list = imx415_global_12bit_3864x2192_regs,
893 .reg_list = imx415_hdr2_12bit_3864x2192_1782M_regs,
894 .hdr_mode = HDR_X2,
895 .mipi_freq_idx = 3,
896 .bpp = 12,
897 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
898 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
899 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
900 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
901 },
902 {
903 .bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
904 .width = 3864,
905 .height = 2192,
906 .max_fps = {
907 .numerator = 10000,
908 .denominator = 200000,
909 },
910 .exp_def = 0x114,
911 .hts_def = 0x0226 * IMX415_4LANES * 2,
912 /*
913 * IMX415 HDR mode T-line is half of Linear mode,
914 * make vts double(that is FSC) to workaround.
915 */
916 .vts_def = 0x0696 * 4,
917 .global_reg_list = imx415_global_12bit_3864x2192_regs,
918 .reg_list = imx415_hdr3_12bit_3864x2192_1782M_regs,
919 .hdr_mode = HDR_X3,
920 .mipi_freq_idx = 3,
921 .bpp = 12,
922 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
923 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
924 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
925 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
926 },
927 {
928 .bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
929 .width = 1944,
930 .height = 1097,
931 .max_fps = {
932 .numerator = 10000,
933 .denominator = 300000,
934 },
935 .exp_def = 0x05dc - 0x08,
936 .hts_def = 0x030e * 3,
937 .vts_def = 0x0c5d,
938 .global_reg_list = imx415_global_12bit_3864x2192_regs,
939 .reg_list = imx415_linear_12bit_1932x1096_594M_regs,
940 .hdr_mode = NO_HDR,
941 .mipi_freq_idx = 0,
942 .bpp = 12,
943 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
944 },
945 {
946 .bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
947 .width = 1944,
948 .height = 1097,
949 .max_fps = {
950 .numerator = 10000,
951 .denominator = 300000,
952 },
953 .exp_def = 0x08FC / 4,
954 .hts_def = 0x021A * 4,
955 /*
956 * IMX415 HDR mode T-line is half of Linear mode,
957 * make vts double(that is FSC) to workaround.
958 */
959 .vts_def = 0x08FC * 2,
960 .global_reg_list = imx415_global_12bit_3864x2192_regs,
961 .reg_list = imx415_hdr2_12bit_1932x1096_891M_regs,
962 .hdr_mode = HDR_X2,
963 .mipi_freq_idx = 1,
964 .bpp = 12,
965 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
966 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
967 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
968 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
969 },
970 };
971
972 static const s64 link_freq_items[] = {
973 MIPI_FREQ_297M,
974 MIPI_FREQ_446M,
975 MIPI_FREQ_743M,
976 MIPI_FREQ_891M,
977 };
978
979 /* Write registers up to 4 at a time */
imx415_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)980 static int imx415_write_reg(struct i2c_client *client, u16 reg,
981 u32 len, u32 val)
982 {
983 u32 buf_i, val_i;
984 u8 buf[6];
985 u8 *val_p;
986 __be32 val_be;
987
988 if (len > 4)
989 return -EINVAL;
990
991 buf[0] = reg >> 8;
992 buf[1] = reg & 0xff;
993
994 val_be = cpu_to_be32(val);
995 val_p = (u8 *)&val_be;
996 buf_i = 2;
997 val_i = 4 - len;
998
999 while (val_i < 4)
1000 buf[buf_i++] = val_p[val_i++];
1001
1002 if (i2c_master_send(client, buf, len + 2) != len + 2)
1003 return -EIO;
1004
1005 return 0;
1006 }
1007
imx415_write_array(struct i2c_client * client,const struct regval * regs)1008 static int imx415_write_array(struct i2c_client *client,
1009 const struct regval *regs)
1010 {
1011 u32 i;
1012 int ret = 0;
1013
1014 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
1015 ret = imx415_write_reg(client, regs[i].addr,
1016 IMX415_REG_VALUE_08BIT, regs[i].val);
1017 }
1018 return ret;
1019 }
1020
1021 /* Read registers up to 4 at a time */
imx415_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)1022 static int imx415_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
1023 u32 *val)
1024 {
1025 struct i2c_msg msgs[2];
1026 u8 *data_be_p;
1027 __be32 data_be = 0;
1028 __be16 reg_addr_be = cpu_to_be16(reg);
1029 int ret;
1030
1031 if (len > 4 || !len)
1032 return -EINVAL;
1033
1034 data_be_p = (u8 *)&data_be;
1035 /* Write register address */
1036 msgs[0].addr = client->addr;
1037 msgs[0].flags = 0;
1038 msgs[0].len = 2;
1039 msgs[0].buf = (u8 *)®_addr_be;
1040
1041 /* Read data from register */
1042 msgs[1].addr = client->addr;
1043 msgs[1].flags = I2C_M_RD;
1044 msgs[1].len = len;
1045 msgs[1].buf = &data_be_p[4 - len];
1046
1047 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1048 if (ret != ARRAY_SIZE(msgs))
1049 return -EIO;
1050
1051 *val = be32_to_cpu(data_be);
1052
1053 return 0;
1054 }
1055
imx415_get_reso_dist(const struct imx415_mode * mode,struct v4l2_mbus_framefmt * framefmt)1056 static int imx415_get_reso_dist(const struct imx415_mode *mode,
1057 struct v4l2_mbus_framefmt *framefmt)
1058 {
1059 return abs(mode->width - framefmt->width) +
1060 abs(mode->height - framefmt->height);
1061 }
1062
1063 static const struct imx415_mode *
imx415_find_best_fit(struct imx415 * imx415,struct v4l2_subdev_format * fmt)1064 imx415_find_best_fit(struct imx415 *imx415, struct v4l2_subdev_format *fmt)
1065 {
1066 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1067 int dist;
1068 int cur_best_fit = 0;
1069 int cur_best_fit_dist = -1;
1070 unsigned int i;
1071
1072 for (i = 0; i < imx415->cfg_num; i++) {
1073 dist = imx415_get_reso_dist(&supported_modes[i], framefmt);
1074 if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
1075 supported_modes[i].bus_fmt == framefmt->code) {
1076 cur_best_fit_dist = dist;
1077 cur_best_fit = i;
1078 }
1079 }
1080 dev_info(&imx415->client->dev, "%s: cur_best_fit(%d)",
1081 __func__, cur_best_fit);
1082
1083 return &supported_modes[cur_best_fit];
1084 }
1085
1086 static int __imx415_power_on(struct imx415 *imx415);
1087
imx415_change_mode(struct imx415 * imx415,const struct imx415_mode * mode)1088 static void imx415_change_mode(struct imx415 *imx415, const struct imx415_mode *mode)
1089 {
1090 if (imx415->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1091 imx415->is_thunderboot = false;
1092 imx415->is_thunderboot_ng = true;
1093 __imx415_power_on(imx415);
1094 }
1095 imx415->cur_mode = mode;
1096 imx415->cur_vts = imx415->cur_mode->vts_def;
1097 dev_dbg(&imx415->client->dev, "set fmt: cur_mode: %dx%d, hdr: %d\n",
1098 mode->width, mode->height, mode->hdr_mode);
1099 }
1100
imx415_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1101 static int imx415_set_fmt(struct v4l2_subdev *sd,
1102 struct v4l2_subdev_pad_config *cfg,
1103 struct v4l2_subdev_format *fmt)
1104 {
1105 struct imx415 *imx415 = to_imx415(sd);
1106 const struct imx415_mode *mode;
1107 s64 h_blank, vblank_def, vblank_min;
1108 u64 pixel_rate = 0;
1109
1110 mutex_lock(&imx415->mutex);
1111
1112 mode = imx415_find_best_fit(imx415, fmt);
1113 fmt->format.code = mode->bus_fmt;
1114 fmt->format.width = mode->width;
1115 fmt->format.height = mode->height;
1116 fmt->format.field = V4L2_FIELD_NONE;
1117 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1118 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1119 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1120 #else
1121 mutex_unlock(&imx415->mutex);
1122 return -ENOTTY;
1123 #endif
1124 } else {
1125 imx415_change_mode(imx415, mode);
1126 h_blank = mode->hts_def - mode->width;
1127 __v4l2_ctrl_modify_range(imx415->hblank, h_blank,
1128 h_blank, 1, h_blank);
1129 vblank_def = mode->vts_def - mode->height;
1130 /* VMAX >= (PIX_VWIDTH / 2) + 46 = height + 46 */
1131 vblank_min = (mode->height + 46) - mode->height;
1132 __v4l2_ctrl_modify_range(imx415->vblank, vblank_min,
1133 IMX415_VTS_MAX - mode->height,
1134 1, vblank_def);
1135 __v4l2_ctrl_s_ctrl(imx415->vblank, vblank_def);
1136 __v4l2_ctrl_s_ctrl(imx415->link_freq, mode->mipi_freq_idx);
1137 pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * IMX415_4LANES;
1138 __v4l2_ctrl_s_ctrl_int64(imx415->pixel_rate,
1139 pixel_rate);
1140 }
1141 dev_info(&imx415->client->dev, "%s: mode->mipi_freq_idx(%d)",
1142 __func__, mode->mipi_freq_idx);
1143
1144 mutex_unlock(&imx415->mutex);
1145
1146 return 0;
1147 }
1148
imx415_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1149 static int imx415_get_fmt(struct v4l2_subdev *sd,
1150 struct v4l2_subdev_pad_config *cfg,
1151 struct v4l2_subdev_format *fmt)
1152 {
1153 struct imx415 *imx415 = to_imx415(sd);
1154 const struct imx415_mode *mode = imx415->cur_mode;
1155
1156 mutex_lock(&imx415->mutex);
1157 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1158 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1159 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1160 #else
1161 mutex_unlock(&imx415->mutex);
1162 return -ENOTTY;
1163 #endif
1164 } else {
1165 fmt->format.width = mode->width;
1166 fmt->format.height = mode->height;
1167 fmt->format.code = mode->bus_fmt;
1168 fmt->format.field = V4L2_FIELD_NONE;
1169 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
1170 fmt->reserved[0] = mode->vc[fmt->pad];
1171 else
1172 fmt->reserved[0] = mode->vc[PAD0];
1173 }
1174 mutex_unlock(&imx415->mutex);
1175
1176 return 0;
1177 }
1178
imx415_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1179 static int imx415_enum_mbus_code(struct v4l2_subdev *sd,
1180 struct v4l2_subdev_pad_config *cfg,
1181 struct v4l2_subdev_mbus_code_enum *code)
1182 {
1183 struct imx415 *imx415 = to_imx415(sd);
1184
1185 if (code->index >= imx415->cfg_num)
1186 return -EINVAL;
1187
1188 code->code = supported_modes[code->index].bus_fmt;
1189
1190 return 0;
1191 }
1192
imx415_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1193 static int imx415_enum_frame_sizes(struct v4l2_subdev *sd,
1194 struct v4l2_subdev_pad_config *cfg,
1195 struct v4l2_subdev_frame_size_enum *fse)
1196 {
1197 struct imx415 *imx415 = to_imx415(sd);
1198
1199 if (fse->index >= imx415->cfg_num)
1200 return -EINVAL;
1201
1202 if (fse->code != supported_modes[fse->index].bus_fmt)
1203 return -EINVAL;
1204
1205 fse->min_width = supported_modes[fse->index].width;
1206 fse->max_width = supported_modes[fse->index].width;
1207 fse->max_height = supported_modes[fse->index].height;
1208 fse->min_height = supported_modes[fse->index].height;
1209
1210 return 0;
1211 }
1212
imx415_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1213 static int imx415_g_frame_interval(struct v4l2_subdev *sd,
1214 struct v4l2_subdev_frame_interval *fi)
1215 {
1216 struct imx415 *imx415 = to_imx415(sd);
1217 const struct imx415_mode *mode = imx415->cur_mode;
1218
1219 fi->interval = mode->max_fps;
1220
1221 return 0;
1222 }
1223
imx415_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1224 static int imx415_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1225 struct v4l2_mbus_config *config)
1226 {
1227 struct imx415 *imx415 = to_imx415(sd);
1228 const struct imx415_mode *mode = imx415->cur_mode;
1229 u32 val = 0;
1230
1231 val = 1 << (IMX415_4LANES - 1) |
1232 V4L2_MBUS_CSI2_CHANNEL_0 |
1233 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1234 if (mode->hdr_mode != NO_HDR)
1235 val |= V4L2_MBUS_CSI2_CHANNEL_1;
1236 if (mode->hdr_mode == HDR_X3)
1237 val |= V4L2_MBUS_CSI2_CHANNEL_2;
1238 config->type = V4L2_MBUS_CSI2_DPHY;
1239 config->flags = val;
1240
1241 return 0;
1242 }
1243
imx415_get_module_inf(struct imx415 * imx415,struct rkmodule_inf * inf)1244 static void imx415_get_module_inf(struct imx415 *imx415,
1245 struct rkmodule_inf *inf)
1246 {
1247 memset(inf, 0, sizeof(*inf));
1248 strlcpy(inf->base.sensor, IMX415_NAME, sizeof(inf->base.sensor));
1249 strlcpy(inf->base.module, imx415->module_name,
1250 sizeof(inf->base.module));
1251 strlcpy(inf->base.lens, imx415->len_name, sizeof(inf->base.lens));
1252 }
1253
imx415_set_hdrae_3frame(struct imx415 * imx415,struct preisp_hdrae_exp_s * ae)1254 static int imx415_set_hdrae_3frame(struct imx415 *imx415,
1255 struct preisp_hdrae_exp_s *ae)
1256 {
1257 struct i2c_client *client = imx415->client;
1258 u32 l_exp_time, m_exp_time, s_exp_time;
1259 u32 l_a_gain, m_a_gain, s_a_gain;
1260 int shr2, shr1, shr0, rhs2, rhs1 = 0;
1261 int rhs1_change_limit, rhs2_change_limit = 0;
1262 static int rhs1_old = IMX415_RHS1_DEFAULT;
1263 static int rhs2_old = IMX415_RHS2_DEFAULT;
1264 int ret = 0;
1265 u32 fsc;
1266 int rhs1_max = 0;
1267 int shr2_min = 0;
1268
1269 if (!imx415->has_init_exp && !imx415->streaming) {
1270 imx415->init_hdrae_exp = *ae;
1271 imx415->has_init_exp = true;
1272 dev_dbg(&imx415->client->dev, "imx415 is not streaming, save hdr ae!\n");
1273 return ret;
1274 }
1275 l_exp_time = ae->long_exp_reg;
1276 m_exp_time = ae->middle_exp_reg;
1277 s_exp_time = ae->short_exp_reg;
1278 l_a_gain = ae->long_gain_reg;
1279 m_a_gain = ae->middle_gain_reg;
1280 s_a_gain = ae->short_gain_reg;
1281 dev_dbg(&client->dev,
1282 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
1283 l_exp_time, m_exp_time, s_exp_time,
1284 l_a_gain, m_a_gain, s_a_gain);
1285
1286 ret = imx415_write_reg(client, IMX415_GROUP_HOLD_REG,
1287 IMX415_REG_VALUE_08BIT, IMX415_GROUP_HOLD_START);
1288 /* gain effect n+1 */
1289 ret |= imx415_write_reg(client, IMX415_LF_GAIN_REG_H,
1290 IMX415_REG_VALUE_08BIT, IMX415_FETCH_GAIN_H(l_a_gain));
1291 ret |= imx415_write_reg(client, IMX415_LF_GAIN_REG_L,
1292 IMX415_REG_VALUE_08BIT, IMX415_FETCH_GAIN_L(l_a_gain));
1293 ret |= imx415_write_reg(client, IMX415_SF1_GAIN_REG_H,
1294 IMX415_REG_VALUE_08BIT, IMX415_FETCH_GAIN_H(m_a_gain));
1295 ret |= imx415_write_reg(client, IMX415_SF1_GAIN_REG_L,
1296 IMX415_REG_VALUE_08BIT, IMX415_FETCH_GAIN_L(m_a_gain));
1297 ret |= imx415_write_reg(client, IMX415_SF2_GAIN_REG_H,
1298 IMX415_REG_VALUE_08BIT, IMX415_FETCH_GAIN_H(s_a_gain));
1299 ret |= imx415_write_reg(client, IMX415_SF2_GAIN_REG_L,
1300 IMX415_REG_VALUE_08BIT, IMX415_FETCH_GAIN_L(s_a_gain));
1301
1302 /* Restrictions
1303 * FSC = 4 * VMAX and FSC should be 6n;
1304 * exp_l = FSC - SHR0 + Toffset;
1305 *
1306 * SHR0 = FSC - exp_l + Toffset;
1307 * SHR0 <= (FSC -12);
1308 * SHR0 >= RHS2 + 13;
1309 * SHR0 should be 3n;
1310 *
1311 * exp_m = RHS1 - SHR1 + Toffset;
1312 *
1313 * RHS1 < BRL * 3;
1314 * RHS1 <= SHR2 - 13;
1315 * RHS1 >= SHR1 + 12;
1316 * SHR1 >= 13;
1317 * SHR1 <= RHS1 - 12;
1318 * RHS1(n+1) >= RHS1(n) + BRL * 3 -FSC + 3;
1319 *
1320 * SHR1 should be 3n+1 and RHS1 should be 6n+1;
1321 *
1322 * exp_s = RHS2 - SHR2 + Toffset;
1323 *
1324 * RHS2 < BRL * 3 + RHS1;
1325 * RHS2 <= SHR0 - 13;
1326 * RHS2 >= SHR2 + 12;
1327 * SHR2 >= RHS1 + 13;
1328 * SHR2 <= RHS2 - 12;
1329 * RHS1(n+1) >= RHS1(n) + BRL * 3 -FSC + 3;
1330 *
1331 * SHR2 should be 3n+2 and RHS2 should be 6n+2;
1332 */
1333
1334 /* The HDR mode vts is double by default to workaround T-line */
1335 fsc = imx415->cur_vts;
1336 fsc = fsc / 6 * 6;
1337 shr0 = fsc - l_exp_time;
1338 dev_dbg(&client->dev,
1339 "line(%d) shr0 %d, l_exp_time %d, fsc %d\n",
1340 __LINE__, shr0, l_exp_time, fsc);
1341
1342 rhs1 = (SHR1_MIN_X3 + m_exp_time + 5) / 6 * 6 + 1;
1343 if (imx415->cur_mode->height == 2192)
1344 rhs1_max = RHS1_MAX_X3(BRL_ALL);
1345 else
1346 rhs1_max = RHS1_MAX_X3(BRL_BINNING);
1347 if (rhs1 < 25)
1348 rhs1 = 25;
1349 else if (rhs1 > rhs1_max)
1350 rhs1 = rhs1_max;
1351 dev_dbg(&client->dev,
1352 "line(%d) rhs1 %d, m_exp_time %d rhs1_old %d\n",
1353 __LINE__, rhs1, m_exp_time, rhs1_old);
1354
1355 //Dynamic adjustment rhs2 must meet the following conditions
1356 if (imx415->cur_mode->height == 2192)
1357 rhs1_change_limit = rhs1_old + 3 * BRL_ALL - fsc + 3;
1358 else
1359 rhs1_change_limit = rhs1_old + 3 * BRL_BINNING - fsc + 3;
1360 rhs1_change_limit = (rhs1_change_limit < 25) ? 25 : rhs1_change_limit;
1361 rhs1_change_limit = (rhs1_change_limit + 5) / 6 * 6 + 1;
1362 if (rhs1_max < rhs1_change_limit) {
1363 dev_err(&client->dev,
1364 "The total exposure limit makes rhs1 max is %d,but old rhs1 limit makes rhs1 min is %d\n",
1365 rhs1_max, rhs1_change_limit);
1366 return -EINVAL;
1367 }
1368 if (rhs1 < rhs1_change_limit)
1369 rhs1 = rhs1_change_limit;
1370
1371 dev_dbg(&client->dev,
1372 "line(%d) m_exp_time %d rhs1_old %d, rhs1_new %d\n",
1373 __LINE__, m_exp_time, rhs1_old, rhs1);
1374
1375 rhs1_old = rhs1;
1376
1377 /* shr1 = rhs1 - s_exp_time */
1378 if (rhs1 - m_exp_time <= SHR1_MIN_X3) {
1379 shr1 = SHR1_MIN_X3;
1380 m_exp_time = rhs1 - shr1;
1381 } else {
1382 shr1 = rhs1 - m_exp_time;
1383 }
1384
1385 shr2_min = rhs1 + 13;
1386 rhs2 = (shr2_min + s_exp_time + 5) / 6 * 6 + 2;
1387 if (rhs2 > (shr0 - 13))
1388 rhs2 = shr0 - 13;
1389 else if (rhs2 < 50)
1390 rhs2 = 50;
1391 dev_dbg(&client->dev,
1392 "line(%d) rhs2 %d, s_exp_time %d, rhs2_old %d\n",
1393 __LINE__, rhs2, s_exp_time, rhs2_old);
1394
1395 //Dynamic adjustment rhs2 must meet the following conditions
1396 if (imx415->cur_mode->height == 2192)
1397 rhs2_change_limit = rhs2_old + 3 * BRL_ALL - fsc + 3;
1398 else
1399 rhs2_change_limit = rhs2_old + 3 * BRL_BINNING - fsc + 3;
1400 rhs2_change_limit = (rhs2_change_limit < 50) ? 50 : rhs2_change_limit;
1401 rhs2_change_limit = (rhs2_change_limit + 5) / 6 * 6 + 2;
1402 if ((shr0 - 13) < rhs2_change_limit) {
1403 dev_err(&client->dev,
1404 "The total exposure limit makes rhs2 max is %d,but old rhs1 limit makes rhs2 min is %d\n",
1405 shr0 - 13, rhs2_change_limit);
1406 return -EINVAL;
1407 }
1408 if (rhs2 < rhs2_change_limit)
1409 rhs2 = rhs2_change_limit;
1410
1411 rhs2_old = rhs2;
1412
1413 /* shr2 = rhs2 - s_exp_time */
1414 if (rhs2 - s_exp_time <= shr2_min) {
1415 shr2 = shr2_min;
1416 s_exp_time = rhs2 - shr2;
1417 } else {
1418 shr2 = rhs2 - s_exp_time;
1419 }
1420 dev_dbg(&client->dev,
1421 "line(%d) rhs2_new %d, s_exp_time %d shr2 %d, rhs2_change_limit %d\n",
1422 __LINE__, rhs2, s_exp_time, shr2, rhs2_change_limit);
1423
1424 if (shr0 < rhs2 + 13)
1425 shr0 = rhs2 + 13;
1426 else if (shr0 > fsc - 12)
1427 shr0 = fsc - 12;
1428
1429 dev_dbg(&client->dev,
1430 "long exposure: l_exp_time=%d, fsc=%d, shr0=%d, l_a_gain=%d\n",
1431 l_exp_time, fsc, shr0, l_a_gain);
1432 dev_dbg(&client->dev,
1433 "middle exposure(SEF1): m_exp_time=%d, rhs1=%d, shr1=%d, m_a_gain=%d\n",
1434 m_exp_time, rhs1, shr1, m_a_gain);
1435 dev_dbg(&client->dev,
1436 "short exposure(SEF2): s_exp_time=%d, rhs2=%d, shr2=%d, s_a_gain=%d\n",
1437 s_exp_time, rhs2, shr2, s_a_gain);
1438 /* time effect n+1 */
1439 /* write SEF2 exposure RHS2 regs*/
1440 ret |= imx415_write_reg(client,
1441 IMX415_RHS2_REG_L,
1442 IMX415_REG_VALUE_08BIT,
1443 IMX415_FETCH_RHS1_L(rhs2));
1444 ret |= imx415_write_reg(client,
1445 IMX415_RHS2_REG_M,
1446 IMX415_REG_VALUE_08BIT,
1447 IMX415_FETCH_RHS1_M(rhs2));
1448 ret |= imx415_write_reg(client,
1449 IMX415_RHS2_REG_H,
1450 IMX415_REG_VALUE_08BIT,
1451 IMX415_FETCH_RHS1_H(rhs2));
1452 /* write SEF2 exposure SHR2 regs*/
1453 ret |= imx415_write_reg(client,
1454 IMX415_SF2_EXPO_REG_L,
1455 IMX415_REG_VALUE_08BIT,
1456 IMX415_FETCH_EXP_L(shr2));
1457 ret |= imx415_write_reg(client,
1458 IMX415_SF2_EXPO_REG_M,
1459 IMX415_REG_VALUE_08BIT,
1460 IMX415_FETCH_EXP_M(shr2));
1461 ret |= imx415_write_reg(client,
1462 IMX415_SF2_EXPO_REG_H,
1463 IMX415_REG_VALUE_08BIT,
1464 IMX415_FETCH_EXP_H(shr2));
1465 /* write SEF1 exposure RHS1 regs*/
1466 ret |= imx415_write_reg(client,
1467 IMX415_RHS1_REG_L,
1468 IMX415_REG_VALUE_08BIT,
1469 IMX415_FETCH_RHS1_L(rhs1));
1470 ret |= imx415_write_reg(client,
1471 IMX415_RHS1_REG_M,
1472 IMX415_REG_VALUE_08BIT,
1473 IMX415_FETCH_RHS1_M(rhs1));
1474 ret |= imx415_write_reg(client,
1475 IMX415_RHS1_REG_H,
1476 IMX415_REG_VALUE_08BIT,
1477 IMX415_FETCH_RHS1_H(rhs1));
1478 /* write SEF1 exposure SHR1 regs*/
1479 ret |= imx415_write_reg(client,
1480 IMX415_SF1_EXPO_REG_L,
1481 IMX415_REG_VALUE_08BIT,
1482 IMX415_FETCH_EXP_L(shr1));
1483 ret |= imx415_write_reg(client,
1484 IMX415_SF1_EXPO_REG_M,
1485 IMX415_REG_VALUE_08BIT,
1486 IMX415_FETCH_EXP_M(shr1));
1487 ret |= imx415_write_reg(client,
1488 IMX415_SF1_EXPO_REG_H,
1489 IMX415_REG_VALUE_08BIT,
1490 IMX415_FETCH_EXP_H(shr1));
1491 /* write LF exposure SHR0 regs*/
1492 ret |= imx415_write_reg(client,
1493 IMX415_LF_EXPO_REG_L,
1494 IMX415_REG_VALUE_08BIT,
1495 IMX415_FETCH_EXP_L(shr0));
1496 ret |= imx415_write_reg(client,
1497 IMX415_LF_EXPO_REG_M,
1498 IMX415_REG_VALUE_08BIT,
1499 IMX415_FETCH_EXP_M(shr0));
1500 ret |= imx415_write_reg(client,
1501 IMX415_LF_EXPO_REG_H,
1502 IMX415_REG_VALUE_08BIT,
1503 IMX415_FETCH_EXP_H(shr0));
1504
1505 ret |= imx415_write_reg(client, IMX415_GROUP_HOLD_REG,
1506 IMX415_REG_VALUE_08BIT, IMX415_GROUP_HOLD_END);
1507 return ret;
1508 }
1509
imx415_set_hdrae(struct imx415 * imx415,struct preisp_hdrae_exp_s * ae)1510 static int imx415_set_hdrae(struct imx415 *imx415,
1511 struct preisp_hdrae_exp_s *ae)
1512 {
1513 struct i2c_client *client = imx415->client;
1514 u32 l_exp_time, m_exp_time, s_exp_time;
1515 u32 l_a_gain, m_a_gain, s_a_gain;
1516 int shr1, shr0, rhs1, rhs1_max, rhs1_min;
1517 static int rhs1_old = IMX415_RHS1_DEFAULT;
1518 int ret = 0;
1519 u32 fsc;
1520
1521 if (!imx415->has_init_exp && !imx415->streaming) {
1522 imx415->init_hdrae_exp = *ae;
1523 imx415->has_init_exp = true;
1524 dev_dbg(&imx415->client->dev, "imx415 is not streaming, save hdr ae!\n");
1525 return ret;
1526 }
1527 l_exp_time = ae->long_exp_reg;
1528 m_exp_time = ae->middle_exp_reg;
1529 s_exp_time = ae->short_exp_reg;
1530 l_a_gain = ae->long_gain_reg;
1531 m_a_gain = ae->middle_gain_reg;
1532 s_a_gain = ae->short_gain_reg;
1533 dev_dbg(&client->dev,
1534 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
1535 l_exp_time, m_exp_time, s_exp_time,
1536 l_a_gain, m_a_gain, s_a_gain);
1537
1538 if (imx415->cur_mode->hdr_mode == HDR_X2) {
1539 l_a_gain = m_a_gain;
1540 l_exp_time = m_exp_time;
1541 }
1542
1543 ret = imx415_write_reg(client, IMX415_GROUP_HOLD_REG,
1544 IMX415_REG_VALUE_08BIT, IMX415_GROUP_HOLD_START);
1545 /* gain effect n+1 */
1546 ret |= imx415_write_reg(client, IMX415_LF_GAIN_REG_H,
1547 IMX415_REG_VALUE_08BIT, IMX415_FETCH_GAIN_H(l_a_gain));
1548 ret |= imx415_write_reg(client, IMX415_LF_GAIN_REG_L,
1549 IMX415_REG_VALUE_08BIT, IMX415_FETCH_GAIN_L(l_a_gain));
1550 ret |= imx415_write_reg(client, IMX415_SF1_GAIN_REG_H,
1551 IMX415_REG_VALUE_08BIT, IMX415_FETCH_GAIN_H(s_a_gain));
1552 ret |= imx415_write_reg(client, IMX415_SF1_GAIN_REG_L,
1553 IMX415_REG_VALUE_08BIT, IMX415_FETCH_GAIN_L(s_a_gain));
1554
1555 /* Restrictions
1556 * FSC = 2 * VMAX and FSC should be 4n;
1557 * exp_l = FSC - SHR0 + Toffset;
1558 * exp_l should be even value;
1559 *
1560 * SHR0 = FSC - exp_l + Toffset;
1561 * SHR0 <= (FSC -8);
1562 * SHR0 >= RHS1 + 9;
1563 * SHR0 should be 2n;
1564 *
1565 * exp_s = RHS1 - SHR1 + Toffset;
1566 * exp_s should be even value;
1567 *
1568 * RHS1 < BRL * 2;
1569 * RHS1 <= SHR0 - 9;
1570 * RHS1 >= SHR1 + 8;
1571 * SHR1 >= 9;
1572 * RHS1(n+1) >= RHS1(n) + BRL * 2 -FSC + 2;
1573 *
1574 * SHR1 should be 2n+1 and RHS1 should be 4n+1;
1575 */
1576
1577 /* The HDR mode vts is double by default to workaround T-line */
1578 fsc = imx415->cur_vts;
1579 shr0 = fsc - l_exp_time;
1580
1581 if (imx415->cur_mode->height == 2192) {
1582 rhs1_max = min(RHS1_MAX_X2(BRL_ALL), ((shr0 - 9u) / 4 * 4 + 1));
1583 rhs1_min = max(SHR1_MIN_X2 + 8u, rhs1_old + 2 * BRL_ALL - fsc + 2);
1584 } else {
1585 rhs1_max = min(RHS1_MAX_X2(BRL_BINNING), ((shr0 - 9u) / 4 * 4 + 1));
1586 rhs1_min = max(SHR1_MIN_X2 + 8u, rhs1_old + 2 * BRL_BINNING - fsc + 2);
1587 }
1588 rhs1_min = (rhs1_min + 3) / 4 * 4 + 1;
1589 rhs1 = (SHR1_MIN_X2 + s_exp_time + 3) / 4 * 4 + 1;/* shall be 4n + 1 */
1590 dev_dbg(&client->dev,
1591 "line(%d) rhs1 %d, rhs1 min %d rhs1 max %d\n",
1592 __LINE__, rhs1, rhs1_min, rhs1_max);
1593 if (rhs1_max < rhs1_min) {
1594 dev_err(&client->dev,
1595 "The total exposure limit makes rhs1 max is %d,but old rhs1 limit makes rhs1 min is %d\n",
1596 rhs1_max, rhs1_min);
1597 return -EINVAL;
1598 }
1599 rhs1 = clamp(rhs1, rhs1_min, rhs1_max);
1600 dev_dbg(&client->dev,
1601 "line(%d) rhs1 %d, short time %d rhs1_old %d, rhs1_new %d\n",
1602 __LINE__, rhs1, s_exp_time, rhs1_old, rhs1);
1603
1604 rhs1_old = rhs1;
1605
1606 /* shr1 = rhs1 - s_exp_time */
1607 if (rhs1 - s_exp_time <= SHR1_MIN_X2) {
1608 shr1 = SHR1_MIN_X2;
1609 s_exp_time = rhs1 - shr1;
1610 } else {
1611 shr1 = rhs1 - s_exp_time;
1612 }
1613
1614 if (shr0 < rhs1 + 9)
1615 shr0 = rhs1 + 9;
1616 else if (shr0 > fsc - 8)
1617 shr0 = fsc - 8;
1618
1619 dev_dbg(&client->dev,
1620 "fsc=%d,RHS1_MAX=%d,SHR1_MIN=%d,rhs1_max=%d\n",
1621 fsc, RHS1_MAX_X2(BRL_ALL), SHR1_MIN_X2, rhs1_max);
1622 dev_dbg(&client->dev,
1623 "l_exp_time=%d,s_exp_time=%d,shr0=%d,shr1=%d,rhs1=%d,l_a_gain=%d,s_a_gain=%d\n",
1624 l_exp_time, s_exp_time, shr0, shr1, rhs1, l_a_gain, s_a_gain);
1625 /* time effect n+2 */
1626 ret |= imx415_write_reg(client,
1627 IMX415_RHS1_REG_L,
1628 IMX415_REG_VALUE_08BIT,
1629 IMX415_FETCH_RHS1_L(rhs1));
1630 ret |= imx415_write_reg(client,
1631 IMX415_RHS1_REG_M,
1632 IMX415_REG_VALUE_08BIT,
1633 IMX415_FETCH_RHS1_M(rhs1));
1634 ret |= imx415_write_reg(client,
1635 IMX415_RHS1_REG_H,
1636 IMX415_REG_VALUE_08BIT,
1637 IMX415_FETCH_RHS1_H(rhs1));
1638
1639 ret |= imx415_write_reg(client,
1640 IMX415_SF1_EXPO_REG_L,
1641 IMX415_REG_VALUE_08BIT,
1642 IMX415_FETCH_EXP_L(shr1));
1643 ret |= imx415_write_reg(client,
1644 IMX415_SF1_EXPO_REG_M,
1645 IMX415_REG_VALUE_08BIT,
1646 IMX415_FETCH_EXP_M(shr1));
1647 ret |= imx415_write_reg(client,
1648 IMX415_SF1_EXPO_REG_H,
1649 IMX415_REG_VALUE_08BIT,
1650 IMX415_FETCH_EXP_H(shr1));
1651 ret |= imx415_write_reg(client,
1652 IMX415_LF_EXPO_REG_L,
1653 IMX415_REG_VALUE_08BIT,
1654 IMX415_FETCH_EXP_L(shr0));
1655 ret |= imx415_write_reg(client,
1656 IMX415_LF_EXPO_REG_M,
1657 IMX415_REG_VALUE_08BIT,
1658 IMX415_FETCH_EXP_M(shr0));
1659 ret |= imx415_write_reg(client,
1660 IMX415_LF_EXPO_REG_H,
1661 IMX415_REG_VALUE_08BIT,
1662 IMX415_FETCH_EXP_H(shr0));
1663
1664 ret |= imx415_write_reg(client, IMX415_GROUP_HOLD_REG,
1665 IMX415_REG_VALUE_08BIT, IMX415_GROUP_HOLD_END);
1666 return ret;
1667 }
1668
imx415_get_channel_info(struct imx415 * imx415,struct rkmodule_channel_info * ch_info)1669 static int imx415_get_channel_info(struct imx415 *imx415, struct rkmodule_channel_info *ch_info)
1670 {
1671 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1672 return -EINVAL;
1673 ch_info->vc = imx415->cur_mode->vc[ch_info->index];
1674 ch_info->width = imx415->cur_mode->width;
1675 ch_info->height = imx415->cur_mode->height;
1676 ch_info->bus_fmt = imx415->cur_mode->bus_fmt;
1677 return 0;
1678 }
1679
imx415_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1680 static long imx415_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1681 {
1682 struct imx415 *imx415 = to_imx415(sd);
1683 struct rkmodule_hdr_cfg *hdr;
1684 struct rkmodule_channel_info *ch_info;
1685 u32 i, h, w, stream;
1686 long ret = 0;
1687 const struct imx415_mode *mode;
1688 u64 pixel_rate = 0;
1689 struct rkmodule_csi_dphy_param *dphy_param;
1690
1691 switch (cmd) {
1692 case PREISP_CMD_SET_HDRAE_EXP:
1693 if (imx415->cur_mode->hdr_mode == HDR_X2)
1694 ret = imx415_set_hdrae(imx415, arg);
1695 else if (imx415->cur_mode->hdr_mode == HDR_X3)
1696 ret = imx415_set_hdrae_3frame(imx415, arg);
1697 break;
1698 case RKMODULE_GET_MODULE_INFO:
1699 imx415_get_module_inf(imx415, (struct rkmodule_inf *)arg);
1700 break;
1701 case RKMODULE_GET_HDR_CFG:
1702 hdr = (struct rkmodule_hdr_cfg *)arg;
1703 hdr->esp.mode = HDR_NORMAL_VC;
1704 hdr->hdr_mode = imx415->cur_mode->hdr_mode;
1705 break;
1706 case RKMODULE_SET_HDR_CFG:
1707 hdr = (struct rkmodule_hdr_cfg *)arg;
1708 w = imx415->cur_mode->width;
1709 h = imx415->cur_mode->height;
1710 for (i = 0; i < imx415->cfg_num; i++) {
1711 if (w == supported_modes[i].width &&
1712 h == supported_modes[i].height &&
1713 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1714 imx415_change_mode(imx415, &supported_modes[i]);
1715 break;
1716 }
1717 }
1718 if (i == imx415->cfg_num) {
1719 dev_err(&imx415->client->dev,
1720 "not find hdr mode:%d %dx%d config\n",
1721 hdr->hdr_mode, w, h);
1722 ret = -EINVAL;
1723 } else {
1724 mode = imx415->cur_mode;
1725 if (imx415->streaming) {
1726 ret = imx415_write_reg(imx415->client, IMX415_GROUP_HOLD_REG,
1727 IMX415_REG_VALUE_08BIT, IMX415_GROUP_HOLD_START);
1728
1729 ret |= imx415_write_array(imx415->client, imx415->cur_mode->reg_list);
1730
1731 ret |= imx415_write_reg(imx415->client, IMX415_GROUP_HOLD_REG,
1732 IMX415_REG_VALUE_08BIT, IMX415_GROUP_HOLD_END);
1733 if (ret)
1734 return ret;
1735 }
1736 w = mode->hts_def - imx415->cur_mode->width;
1737 h = mode->vts_def - mode->height;
1738 mutex_lock(&imx415->mutex);
1739 __v4l2_ctrl_modify_range(imx415->hblank, w, w, 1, w);
1740 __v4l2_ctrl_modify_range(imx415->vblank, h,
1741 IMX415_VTS_MAX - mode->height,
1742 1, h);
1743 __v4l2_ctrl_s_ctrl(imx415->link_freq, mode->mipi_freq_idx);
1744 pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * IMX415_4LANES;
1745 __v4l2_ctrl_s_ctrl_int64(imx415->pixel_rate,
1746 pixel_rate);
1747 mutex_unlock(&imx415->mutex);
1748 }
1749 break;
1750 case RKMODULE_SET_QUICK_STREAM:
1751
1752 stream = *((u32 *)arg);
1753
1754 if (stream)
1755 ret = imx415_write_reg(imx415->client, IMX415_REG_CTRL_MODE,
1756 IMX415_REG_VALUE_08BIT, IMX415_MODE_STREAMING);
1757 else
1758 ret = imx415_write_reg(imx415->client, IMX415_REG_CTRL_MODE,
1759 IMX415_REG_VALUE_08BIT, IMX415_MODE_SW_STANDBY);
1760 break;
1761 case RKMODULE_GET_SONY_BRL:
1762 if (imx415->cur_mode->width == 3864 && imx415->cur_mode->height == 2192)
1763 *((u32 *)arg) = BRL_ALL;
1764 else
1765 *((u32 *)arg) = BRL_BINNING;
1766 break;
1767 case RKMODULE_GET_CHANNEL_INFO:
1768 ch_info = (struct rkmodule_channel_info *)arg;
1769 ret = imx415_get_channel_info(imx415, ch_info);
1770 break;
1771 case RKMODULE_GET_CSI_DPHY_PARAM:
1772 if (imx415->cur_mode->hdr_mode == HDR_X2) {
1773 dphy_param = (struct rkmodule_csi_dphy_param *)arg;
1774 if (dphy_param->vendor == dcphy_param.vendor)
1775 *dphy_param = dcphy_param;
1776 dev_info(&imx415->client->dev,
1777 "get sensor dphy param\n");
1778 } else
1779 ret = -EINVAL;
1780 break;
1781 default:
1782 ret = -ENOIOCTLCMD;
1783 break;
1784 }
1785
1786 return ret;
1787 }
1788
1789 #ifdef CONFIG_COMPAT
imx415_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1790 static long imx415_compat_ioctl32(struct v4l2_subdev *sd,
1791 unsigned int cmd, unsigned long arg)
1792 {
1793 void __user *up = compat_ptr(arg);
1794 struct rkmodule_inf *inf;
1795 struct rkmodule_awb_cfg *cfg;
1796 struct rkmodule_hdr_cfg *hdr;
1797 struct preisp_hdrae_exp_s *hdrae;
1798 struct rkmodule_channel_info *ch_info;
1799 long ret;
1800 u32 stream;
1801 u32 brl = 0;
1802 struct rkmodule_csi_dphy_param *dphy_param;
1803
1804 switch (cmd) {
1805 case RKMODULE_GET_MODULE_INFO:
1806 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1807 if (!inf) {
1808 ret = -ENOMEM;
1809 return ret;
1810 }
1811
1812 ret = imx415_ioctl(sd, cmd, inf);
1813 if (!ret) {
1814 if (copy_to_user(up, inf, sizeof(*inf))) {
1815 kfree(inf);
1816 return -EFAULT;
1817 }
1818 }
1819 kfree(inf);
1820 break;
1821 case RKMODULE_AWB_CFG:
1822 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1823 if (!cfg) {
1824 ret = -ENOMEM;
1825 return ret;
1826 }
1827
1828 if (copy_from_user(cfg, up, sizeof(*cfg))) {
1829 kfree(cfg);
1830 return -EFAULT;
1831 }
1832 ret = imx415_ioctl(sd, cmd, cfg);
1833 kfree(cfg);
1834 break;
1835 case RKMODULE_GET_HDR_CFG:
1836 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1837 if (!hdr) {
1838 ret = -ENOMEM;
1839 return ret;
1840 }
1841
1842 ret = imx415_ioctl(sd, cmd, hdr);
1843 if (!ret) {
1844 if (copy_to_user(up, hdr, sizeof(*hdr))) {
1845 kfree(hdr);
1846 return -EFAULT;
1847 }
1848 }
1849 kfree(hdr);
1850 break;
1851 case RKMODULE_SET_HDR_CFG:
1852 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1853 if (!hdr) {
1854 ret = -ENOMEM;
1855 return ret;
1856 }
1857
1858 if (copy_from_user(hdr, up, sizeof(*hdr))) {
1859 kfree(hdr);
1860 return -EFAULT;
1861 }
1862 ret = imx415_ioctl(sd, cmd, hdr);
1863 kfree(hdr);
1864 break;
1865 case PREISP_CMD_SET_HDRAE_EXP:
1866 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1867 if (!hdrae) {
1868 ret = -ENOMEM;
1869 return ret;
1870 }
1871
1872 if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
1873 kfree(hdrae);
1874 return -EFAULT;
1875 }
1876 ret = imx415_ioctl(sd, cmd, hdrae);
1877 kfree(hdrae);
1878 break;
1879 case RKMODULE_SET_QUICK_STREAM:
1880 if (copy_from_user(&stream, up, sizeof(u32)))
1881 return -EFAULT;
1882 ret = imx415_ioctl(sd, cmd, &stream);
1883 break;
1884 case RKMODULE_GET_SONY_BRL:
1885 ret = imx415_ioctl(sd, cmd, &brl);
1886 if (!ret) {
1887 if (copy_to_user(up, &brl, sizeof(u32)))
1888 return -EFAULT;
1889 }
1890 break;
1891 case RKMODULE_GET_CHANNEL_INFO:
1892 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1893 if (!ch_info) {
1894 ret = -ENOMEM;
1895 return ret;
1896 }
1897
1898 ret = imx415_ioctl(sd, cmd, ch_info);
1899 if (!ret) {
1900 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1901 if (ret)
1902 ret = -EFAULT;
1903 }
1904 kfree(ch_info);
1905 break;
1906 case RKMODULE_GET_CSI_DPHY_PARAM:
1907 dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
1908 if (!dphy_param) {
1909 ret = -ENOMEM;
1910 return ret;
1911 }
1912
1913 ret = imx415_ioctl(sd, cmd, dphy_param);
1914 if (!ret) {
1915 ret = copy_to_user(up, dphy_param, sizeof(*dphy_param));
1916 if (ret)
1917 ret = -EFAULT;
1918 }
1919 kfree(dphy_param);
1920 break;
1921
1922 default:
1923 ret = -ENOIOCTLCMD;
1924 break;
1925 }
1926
1927 return ret;
1928 }
1929 #endif
1930
1931
__imx415_start_stream(struct imx415 * imx415)1932 static int __imx415_start_stream(struct imx415 *imx415)
1933 {
1934 int ret;
1935
1936 if (!imx415->is_thunderboot) {
1937 ret = imx415_write_array(imx415->client, imx415->cur_mode->global_reg_list);
1938 if (ret)
1939 return ret;
1940 ret = imx415_write_array(imx415->client, imx415->cur_mode->reg_list);
1941 if (ret)
1942 return ret;
1943 }
1944
1945 /* In case these controls are set before streaming */
1946 ret = __v4l2_ctrl_handler_setup(&imx415->ctrl_handler);
1947 if (ret)
1948 return ret;
1949 if (imx415->has_init_exp && imx415->cur_mode->hdr_mode != NO_HDR) {
1950 ret = imx415_ioctl(&imx415->subdev, PREISP_CMD_SET_HDRAE_EXP,
1951 &imx415->init_hdrae_exp);
1952 if (ret) {
1953 dev_err(&imx415->client->dev,
1954 "init exp fail in hdr mode\n");
1955 return ret;
1956 }
1957 }
1958 return imx415_write_reg(imx415->client, IMX415_REG_CTRL_MODE,
1959 IMX415_REG_VALUE_08BIT, 0);
1960 }
1961
__imx415_stop_stream(struct imx415 * imx415)1962 static int __imx415_stop_stream(struct imx415 *imx415)
1963 {
1964 imx415->has_init_exp = false;
1965 if (imx415->is_thunderboot)
1966 imx415->is_first_streamoff = true;
1967 return imx415_write_reg(imx415->client, IMX415_REG_CTRL_MODE,
1968 IMX415_REG_VALUE_08BIT, 1);
1969 }
1970
imx415_s_stream(struct v4l2_subdev * sd,int on)1971 static int imx415_s_stream(struct v4l2_subdev *sd, int on)
1972 {
1973 struct imx415 *imx415 = to_imx415(sd);
1974 struct i2c_client *client = imx415->client;
1975 int ret = 0;
1976
1977 dev_info(&imx415->client->dev, "s_stream: %d. %dx%d, hdr: %d, bpp: %d\n",
1978 on, imx415->cur_mode->width, imx415->cur_mode->height,
1979 imx415->cur_mode->hdr_mode, imx415->cur_mode->bpp);
1980
1981 mutex_lock(&imx415->mutex);
1982 on = !!on;
1983 if (on == imx415->streaming)
1984 goto unlock_and_return;
1985
1986 if (on) {
1987 if (imx415->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1988 imx415->is_thunderboot = false;
1989 __imx415_power_on(imx415);
1990 }
1991 ret = pm_runtime_get_sync(&client->dev);
1992 if (ret < 0) {
1993 pm_runtime_put_noidle(&client->dev);
1994 goto unlock_and_return;
1995 }
1996
1997 ret = __imx415_start_stream(imx415);
1998 if (ret) {
1999 v4l2_err(sd, "start stream failed while write regs\n");
2000 pm_runtime_put(&client->dev);
2001 goto unlock_and_return;
2002 }
2003 } else {
2004 __imx415_stop_stream(imx415);
2005 pm_runtime_put(&client->dev);
2006 }
2007
2008 imx415->streaming = on;
2009
2010 unlock_and_return:
2011 mutex_unlock(&imx415->mutex);
2012
2013 return ret;
2014 }
2015
imx415_s_power(struct v4l2_subdev * sd,int on)2016 static int imx415_s_power(struct v4l2_subdev *sd, int on)
2017 {
2018 struct imx415 *imx415 = to_imx415(sd);
2019 struct i2c_client *client = imx415->client;
2020 int ret = 0;
2021
2022 mutex_lock(&imx415->mutex);
2023
2024 if (imx415->power_on == !!on)
2025 goto unlock_and_return;
2026
2027 if (on) {
2028 ret = pm_runtime_get_sync(&client->dev);
2029 if (ret < 0) {
2030 pm_runtime_put_noidle(&client->dev);
2031 goto unlock_and_return;
2032 }
2033 imx415->power_on = true;
2034 } else {
2035 pm_runtime_put(&client->dev);
2036 imx415->power_on = false;
2037 }
2038
2039 unlock_and_return:
2040 mutex_unlock(&imx415->mutex);
2041
2042 return ret;
2043 }
2044
__imx415_power_on(struct imx415 * imx415)2045 int __imx415_power_on(struct imx415 *imx415)
2046 {
2047 int ret;
2048 struct device *dev = &imx415->client->dev;
2049
2050 if (imx415->is_thunderboot)
2051 return 0;
2052
2053 if (!IS_ERR_OR_NULL(imx415->pins_default)) {
2054 ret = pinctrl_select_state(imx415->pinctrl,
2055 imx415->pins_default);
2056 if (ret < 0)
2057 dev_err(dev, "could not set pins\n");
2058 }
2059
2060 ret = regulator_bulk_enable(IMX415_NUM_SUPPLIES, imx415->supplies);
2061 if (ret < 0) {
2062 dev_err(dev, "Failed to enable regulators\n");
2063 goto err_pinctrl;
2064 }
2065 if (!IS_ERR(imx415->power_gpio))
2066 gpiod_direction_output(imx415->power_gpio, 1);
2067 /* At least 500ns between power raising and XCLR */
2068 /* fix power on timing if insmod this ko */
2069 usleep_range(10 * 1000, 20 * 1000);
2070 if (!IS_ERR(imx415->reset_gpio))
2071 gpiod_direction_output(imx415->reset_gpio, 0);
2072
2073 /* At least 1us between XCLR and clk */
2074 /* fix power on timing if insmod this ko */
2075 usleep_range(10 * 1000, 20 * 1000);
2076 ret = clk_set_rate(imx415->xvclk, IMX415_XVCLK_FREQ_37M);
2077 if (ret < 0)
2078 dev_warn(dev, "Failed to set xvclk rate\n");
2079 if (clk_get_rate(imx415->xvclk) != IMX415_XVCLK_FREQ_37M)
2080 dev_warn(dev, "xvclk mismatched\n");
2081 ret = clk_prepare_enable(imx415->xvclk);
2082 if (ret < 0) {
2083 dev_err(dev, "Failed to enable xvclk\n");
2084 goto err_clk;
2085 }
2086
2087 /* At least 20us between XCLR and I2C communication */
2088 usleep_range(20*1000, 30*1000);
2089
2090 return 0;
2091
2092 err_clk:
2093 if (!IS_ERR(imx415->reset_gpio))
2094 gpiod_direction_output(imx415->reset_gpio, 1);
2095 regulator_bulk_disable(IMX415_NUM_SUPPLIES, imx415->supplies);
2096
2097 err_pinctrl:
2098 if (!IS_ERR_OR_NULL(imx415->pins_sleep))
2099 pinctrl_select_state(imx415->pinctrl, imx415->pins_sleep);
2100
2101 return ret;
2102 }
2103
__imx415_power_off(struct imx415 * imx415)2104 static void __imx415_power_off(struct imx415 *imx415)
2105 {
2106 int ret;
2107 struct device *dev = &imx415->client->dev;
2108
2109 if (imx415->is_thunderboot) {
2110 if (imx415->is_first_streamoff) {
2111 imx415->is_thunderboot = false;
2112 imx415->is_first_streamoff = false;
2113 } else {
2114 return;
2115 }
2116 }
2117
2118 if (!IS_ERR(imx415->reset_gpio))
2119 gpiod_direction_output(imx415->reset_gpio, 1);
2120 clk_disable_unprepare(imx415->xvclk);
2121 if (!IS_ERR_OR_NULL(imx415->pins_sleep)) {
2122 ret = pinctrl_select_state(imx415->pinctrl,
2123 imx415->pins_sleep);
2124 if (ret < 0)
2125 dev_dbg(dev, "could not set pins\n");
2126 }
2127 if (!IS_ERR(imx415->power_gpio))
2128 gpiod_direction_output(imx415->power_gpio, 0);
2129 regulator_bulk_disable(IMX415_NUM_SUPPLIES, imx415->supplies);
2130 }
2131
imx415_runtime_resume(struct device * dev)2132 static int __maybe_unused imx415_runtime_resume(struct device *dev)
2133 {
2134 struct i2c_client *client = to_i2c_client(dev);
2135 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2136 struct imx415 *imx415 = to_imx415(sd);
2137
2138 return __imx415_power_on(imx415);
2139 }
2140
imx415_runtime_suspend(struct device * dev)2141 static int __maybe_unused imx415_runtime_suspend(struct device *dev)
2142 {
2143 struct i2c_client *client = to_i2c_client(dev);
2144 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2145 struct imx415 *imx415 = to_imx415(sd);
2146
2147 __imx415_power_off(imx415);
2148
2149 return 0;
2150 }
2151
2152 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx415_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)2153 static int imx415_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2154 {
2155 struct imx415 *imx415 = to_imx415(sd);
2156 struct v4l2_mbus_framefmt *try_fmt =
2157 v4l2_subdev_get_try_format(sd, fh->pad, 0);
2158 const struct imx415_mode *def_mode = &supported_modes[0];
2159
2160 mutex_lock(&imx415->mutex);
2161 /* Initialize try_fmt */
2162 try_fmt->width = def_mode->width;
2163 try_fmt->height = def_mode->height;
2164 try_fmt->code = def_mode->bus_fmt;
2165 try_fmt->field = V4L2_FIELD_NONE;
2166
2167 mutex_unlock(&imx415->mutex);
2168 /* No crop or compose */
2169
2170 return 0;
2171 }
2172 #endif
2173
imx415_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)2174 static int imx415_enum_frame_interval(struct v4l2_subdev *sd,
2175 struct v4l2_subdev_pad_config *cfg,
2176 struct v4l2_subdev_frame_interval_enum *fie)
2177 {
2178 struct imx415 *imx415 = to_imx415(sd);
2179
2180 if (fie->index >= imx415->cfg_num)
2181 return -EINVAL;
2182
2183 fie->code = supported_modes[fie->index].bus_fmt;
2184 fie->width = supported_modes[fie->index].width;
2185 fie->height = supported_modes[fie->index].height;
2186 fie->interval = supported_modes[fie->index].max_fps;
2187 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
2188 return 0;
2189 }
2190
2191 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
2192 #define DST_WIDTH_3840 3840
2193 #define DST_HEIGHT_2160 2160
2194 #define DST_WIDTH_1920 1920
2195 #define DST_HEIGHT_1080 1080
2196
2197 /*
2198 * The resolution of the driver configuration needs to be exactly
2199 * the same as the current output resolution of the sensor,
2200 * the input width of the isp needs to be 16 aligned,
2201 * the input height of the isp needs to be 8 aligned.
2202 * Can be cropped to standard resolution by this function,
2203 * otherwise it will crop out strange resolution according
2204 * to the alignment rules.
2205 */
imx415_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)2206 static int imx415_get_selection(struct v4l2_subdev *sd,
2207 struct v4l2_subdev_pad_config *cfg,
2208 struct v4l2_subdev_selection *sel)
2209 {
2210 struct imx415 *imx415 = to_imx415(sd);
2211
2212 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
2213 if (imx415->cur_mode->width == 3864) {
2214 sel->r.left = CROP_START(imx415->cur_mode->width, DST_WIDTH_3840);
2215 sel->r.width = DST_WIDTH_3840;
2216 sel->r.top = CROP_START(imx415->cur_mode->height, DST_HEIGHT_2160);
2217 sel->r.height = DST_HEIGHT_2160;
2218 } else if (imx415->cur_mode->width == 1944) {
2219 sel->r.left = CROP_START(imx415->cur_mode->width, DST_WIDTH_1920);
2220 sel->r.width = DST_WIDTH_1920;
2221 sel->r.top = CROP_START(imx415->cur_mode->height, DST_HEIGHT_1080);
2222 sel->r.height = DST_HEIGHT_1080;
2223 } else {
2224 sel->r.left = CROP_START(imx415->cur_mode->width, imx415->cur_mode->width);
2225 sel->r.width = imx415->cur_mode->width;
2226 sel->r.top = CROP_START(imx415->cur_mode->height, imx415->cur_mode->height);
2227 sel->r.height = imx415->cur_mode->height;
2228 }
2229 return 0;
2230 }
2231 return -EINVAL;
2232 }
2233
2234 static const struct dev_pm_ops imx415_pm_ops = {
2235 SET_RUNTIME_PM_OPS(imx415_runtime_suspend,
2236 imx415_runtime_resume, NULL)
2237 };
2238
2239 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2240 static const struct v4l2_subdev_internal_ops imx415_internal_ops = {
2241 .open = imx415_open,
2242 };
2243 #endif
2244
2245 static const struct v4l2_subdev_core_ops imx415_core_ops = {
2246 .s_power = imx415_s_power,
2247 .ioctl = imx415_ioctl,
2248 #ifdef CONFIG_COMPAT
2249 .compat_ioctl32 = imx415_compat_ioctl32,
2250 #endif
2251 };
2252
2253 static const struct v4l2_subdev_video_ops imx415_video_ops = {
2254 .s_stream = imx415_s_stream,
2255 .g_frame_interval = imx415_g_frame_interval,
2256 };
2257
2258 static const struct v4l2_subdev_pad_ops imx415_pad_ops = {
2259 .enum_mbus_code = imx415_enum_mbus_code,
2260 .enum_frame_size = imx415_enum_frame_sizes,
2261 .enum_frame_interval = imx415_enum_frame_interval,
2262 .get_fmt = imx415_get_fmt,
2263 .set_fmt = imx415_set_fmt,
2264 .get_selection = imx415_get_selection,
2265 .get_mbus_config = imx415_g_mbus_config,
2266 };
2267
2268 static const struct v4l2_subdev_ops imx415_subdev_ops = {
2269 .core = &imx415_core_ops,
2270 .video = &imx415_video_ops,
2271 .pad = &imx415_pad_ops,
2272 };
2273
imx415_set_ctrl(struct v4l2_ctrl * ctrl)2274 static int imx415_set_ctrl(struct v4l2_ctrl *ctrl)
2275 {
2276 struct imx415 *imx415 = container_of(ctrl->handler,
2277 struct imx415, ctrl_handler);
2278 struct i2c_client *client = imx415->client;
2279 s64 max;
2280 u32 vts = 0, val;
2281 int ret = 0;
2282 u32 shr0 = 0;
2283
2284 /* Propagate change of current control to all related controls */
2285 switch (ctrl->id) {
2286 case V4L2_CID_VBLANK:
2287 if (imx415->cur_mode->hdr_mode == NO_HDR) {
2288 /* Update max exposure while meeting expected vblanking */
2289 max = imx415->cur_mode->height + ctrl->val - 8;
2290 __v4l2_ctrl_modify_range(imx415->exposure,
2291 imx415->exposure->minimum, max,
2292 imx415->exposure->step,
2293 imx415->exposure->default_value);
2294 }
2295 break;
2296 }
2297
2298 if (!pm_runtime_get_if_in_use(&client->dev))
2299 return 0;
2300
2301 switch (ctrl->id) {
2302 case V4L2_CID_EXPOSURE:
2303 if (imx415->cur_mode->hdr_mode != NO_HDR)
2304 goto ctrl_end;
2305 shr0 = imx415->cur_vts - ctrl->val;
2306 ret = imx415_write_reg(imx415->client, IMX415_LF_EXPO_REG_L,
2307 IMX415_REG_VALUE_08BIT,
2308 IMX415_FETCH_EXP_L(shr0));
2309 ret |= imx415_write_reg(imx415->client, IMX415_LF_EXPO_REG_M,
2310 IMX415_REG_VALUE_08BIT,
2311 IMX415_FETCH_EXP_M(shr0));
2312 ret |= imx415_write_reg(imx415->client, IMX415_LF_EXPO_REG_H,
2313 IMX415_REG_VALUE_08BIT,
2314 IMX415_FETCH_EXP_H(shr0));
2315 dev_dbg(&client->dev, "set exposure(shr0) %d = cur_vts(%d) - val(%d)\n",
2316 shr0, imx415->cur_vts, ctrl->val);
2317 break;
2318 case V4L2_CID_ANALOGUE_GAIN:
2319 if (imx415->cur_mode->hdr_mode != NO_HDR)
2320 goto ctrl_end;
2321 ret = imx415_write_reg(imx415->client, IMX415_LF_GAIN_REG_H,
2322 IMX415_REG_VALUE_08BIT,
2323 IMX415_FETCH_GAIN_H(ctrl->val));
2324 ret |= imx415_write_reg(imx415->client, IMX415_LF_GAIN_REG_L,
2325 IMX415_REG_VALUE_08BIT,
2326 IMX415_FETCH_GAIN_L(ctrl->val));
2327 dev_dbg(&client->dev, "set analog gain 0x%x\n",
2328 ctrl->val);
2329 break;
2330 case V4L2_CID_VBLANK:
2331 vts = ctrl->val + imx415->cur_mode->height;
2332 /*
2333 * vts of hdr mode is double to correct T-line calculation.
2334 * Restore before write to reg.
2335 */
2336 if (imx415->cur_mode->hdr_mode == HDR_X2) {
2337 vts = (vts + 3) / 4 * 4;
2338 imx415->cur_vts = vts;
2339 vts /= 2;
2340 } else if (imx415->cur_mode->hdr_mode == HDR_X3) {
2341 vts = (vts + 11) / 12 * 12;
2342 imx415->cur_vts = vts;
2343 vts /= 4;
2344 } else {
2345 imx415->cur_vts = vts;
2346 }
2347 ret = imx415_write_reg(imx415->client, IMX415_VTS_REG_L,
2348 IMX415_REG_VALUE_08BIT,
2349 IMX415_FETCH_VTS_L(vts));
2350 ret |= imx415_write_reg(imx415->client, IMX415_VTS_REG_M,
2351 IMX415_REG_VALUE_08BIT,
2352 IMX415_FETCH_VTS_M(vts));
2353 ret |= imx415_write_reg(imx415->client, IMX415_VTS_REG_H,
2354 IMX415_REG_VALUE_08BIT,
2355 IMX415_FETCH_VTS_H(vts));
2356 dev_dbg(&client->dev, "set vblank 0x%x vts %d\n",
2357 ctrl->val, vts);
2358 break;
2359 case V4L2_CID_HFLIP:
2360 ret = imx415_read_reg(imx415->client, IMX415_FLIP_REG,
2361 IMX415_REG_VALUE_08BIT, &val);
2362 if (ret)
2363 break;
2364 if (ctrl->val)
2365 val |= IMX415_MIRROR_BIT_MASK;
2366 else
2367 val &= ~IMX415_MIRROR_BIT_MASK;
2368 ret = imx415_write_reg(imx415->client, IMX415_FLIP_REG,
2369 IMX415_REG_VALUE_08BIT, val);
2370 break;
2371 case V4L2_CID_VFLIP:
2372 ret = imx415_read_reg(imx415->client, IMX415_FLIP_REG,
2373 IMX415_REG_VALUE_08BIT, &val);
2374 if (ret)
2375 break;
2376 if (ctrl->val)
2377 val |= IMX415_FLIP_BIT_MASK;
2378 else
2379 val &= ~IMX415_FLIP_BIT_MASK;
2380 ret = imx415_write_reg(imx415->client, IMX415_FLIP_REG,
2381 IMX415_REG_VALUE_08BIT, val);
2382 break;
2383 default:
2384 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
2385 __func__, ctrl->id, ctrl->val);
2386 break;
2387 }
2388
2389 ctrl_end:
2390 pm_runtime_put(&client->dev);
2391
2392 return ret;
2393 }
2394
2395 static const struct v4l2_ctrl_ops imx415_ctrl_ops = {
2396 .s_ctrl = imx415_set_ctrl,
2397 };
2398
imx415_initialize_controls(struct imx415 * imx415)2399 static int imx415_initialize_controls(struct imx415 *imx415)
2400 {
2401 const struct imx415_mode *mode;
2402 struct v4l2_ctrl_handler *handler;
2403 s64 exposure_max, vblank_def;
2404 u64 pixel_rate;
2405 u32 h_blank;
2406 int ret;
2407
2408 handler = &imx415->ctrl_handler;
2409 mode = imx415->cur_mode;
2410 ret = v4l2_ctrl_handler_init(handler, 8);
2411 if (ret)
2412 return ret;
2413 handler->lock = &imx415->mutex;
2414
2415 imx415->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
2416 V4L2_CID_LINK_FREQ,
2417 ARRAY_SIZE(link_freq_items) - 1, 0,
2418 link_freq_items);
2419 v4l2_ctrl_s_ctrl(imx415->link_freq, mode->mipi_freq_idx);
2420
2421 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
2422 pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * IMX415_4LANES;
2423 imx415->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
2424 V4L2_CID_PIXEL_RATE, 0, IMX415_MAX_PIXEL_RATE,
2425 1, pixel_rate);
2426
2427 h_blank = mode->hts_def - mode->width;
2428 imx415->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
2429 h_blank, h_blank, 1, h_blank);
2430 if (imx415->hblank)
2431 imx415->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2432
2433 vblank_def = mode->vts_def - mode->height;
2434 imx415->vblank = v4l2_ctrl_new_std(handler, &imx415_ctrl_ops,
2435 V4L2_CID_VBLANK, vblank_def,
2436 IMX415_VTS_MAX - mode->height,
2437 1, vblank_def);
2438 imx415->cur_vts = mode->vts_def;
2439
2440 exposure_max = mode->vts_def - 8;
2441 imx415->exposure = v4l2_ctrl_new_std(handler, &imx415_ctrl_ops,
2442 V4L2_CID_EXPOSURE, IMX415_EXPOSURE_MIN,
2443 exposure_max, IMX415_EXPOSURE_STEP,
2444 mode->exp_def);
2445
2446 imx415->anal_a_gain = v4l2_ctrl_new_std(handler, &imx415_ctrl_ops,
2447 V4L2_CID_ANALOGUE_GAIN, IMX415_GAIN_MIN,
2448 IMX415_GAIN_MAX, IMX415_GAIN_STEP,
2449 IMX415_GAIN_DEFAULT);
2450
2451 v4l2_ctrl_new_std(handler, &imx415_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
2452 v4l2_ctrl_new_std(handler, &imx415_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
2453
2454 if (handler->error) {
2455 ret = handler->error;
2456 dev_err(&imx415->client->dev,
2457 "Failed to init controls(%d)\n", ret);
2458 goto err_free_handler;
2459 }
2460
2461 imx415->subdev.ctrl_handler = handler;
2462 imx415->has_init_exp = false;
2463
2464 return 0;
2465
2466 err_free_handler:
2467 v4l2_ctrl_handler_free(handler);
2468
2469 return ret;
2470 }
2471
imx415_check_sensor_id(struct imx415 * imx415,struct i2c_client * client)2472 static int imx415_check_sensor_id(struct imx415 *imx415,
2473 struct i2c_client *client)
2474 {
2475 struct device *dev = &imx415->client->dev;
2476 u32 id = 0;
2477 int ret;
2478
2479 if (imx415->is_thunderboot) {
2480 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
2481 return 0;
2482 }
2483
2484 ret = imx415_read_reg(client, IMX415_REG_CHIP_ID,
2485 IMX415_REG_VALUE_08BIT, &id);
2486 if (id != CHIP_ID) {
2487 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
2488 return -ENODEV;
2489 }
2490
2491 dev_info(dev, "Detected imx415 id %06x\n", CHIP_ID);
2492
2493 return 0;
2494 }
2495
imx415_configure_regulators(struct imx415 * imx415)2496 static int imx415_configure_regulators(struct imx415 *imx415)
2497 {
2498 unsigned int i;
2499
2500 for (i = 0; i < IMX415_NUM_SUPPLIES; i++)
2501 imx415->supplies[i].supply = imx415_supply_names[i];
2502
2503 return devm_regulator_bulk_get(&imx415->client->dev,
2504 IMX415_NUM_SUPPLIES,
2505 imx415->supplies);
2506 }
2507
imx415_probe(struct i2c_client * client,const struct i2c_device_id * id)2508 static int imx415_probe(struct i2c_client *client,
2509 const struct i2c_device_id *id)
2510 {
2511 struct device *dev = &client->dev;
2512 struct device_node *node = dev->of_node;
2513 struct imx415 *imx415;
2514 struct v4l2_subdev *sd;
2515 char facing[2];
2516 int ret;
2517 u32 i, hdr_mode = 0;
2518
2519 dev_info(dev, "driver version: %02x.%02x.%02x",
2520 DRIVER_VERSION >> 16,
2521 (DRIVER_VERSION & 0xff00) >> 8,
2522 DRIVER_VERSION & 0x00ff);
2523
2524 imx415 = devm_kzalloc(dev, sizeof(*imx415), GFP_KERNEL);
2525 if (!imx415)
2526 return -ENOMEM;
2527
2528 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2529 &imx415->module_index);
2530 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2531 &imx415->module_facing);
2532 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2533 &imx415->module_name);
2534 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2535 &imx415->len_name);
2536 if (ret) {
2537 dev_err(dev, "could not get module information!\n");
2538 return -EINVAL;
2539 }
2540
2541 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
2542 if (ret) {
2543 hdr_mode = NO_HDR;
2544 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
2545 }
2546 imx415->client = client;
2547 imx415->cfg_num = ARRAY_SIZE(supported_modes);
2548 for (i = 0; i < imx415->cfg_num; i++) {
2549 if (hdr_mode == supported_modes[i].hdr_mode) {
2550 imx415->cur_mode = &supported_modes[i];
2551 break;
2552 }
2553 }
2554
2555 imx415->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
2556
2557 imx415->xvclk = devm_clk_get(dev, "xvclk");
2558 if (IS_ERR(imx415->xvclk)) {
2559 dev_err(dev, "Failed to get xvclk\n");
2560 return -EINVAL;
2561 }
2562
2563 imx415->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
2564 if (IS_ERR(imx415->reset_gpio))
2565 dev_warn(dev, "Failed to get reset-gpios\n");
2566 imx415->power_gpio = devm_gpiod_get(dev, "power", GPIOD_ASIS);
2567 if (IS_ERR(imx415->power_gpio))
2568 dev_warn(dev, "Failed to get power-gpios\n");
2569 imx415->pinctrl = devm_pinctrl_get(dev);
2570 if (!IS_ERR(imx415->pinctrl)) {
2571 imx415->pins_default =
2572 pinctrl_lookup_state(imx415->pinctrl,
2573 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2574 if (IS_ERR(imx415->pins_default))
2575 dev_info(dev, "could not get default pinstate\n");
2576
2577 imx415->pins_sleep =
2578 pinctrl_lookup_state(imx415->pinctrl,
2579 OF_CAMERA_PINCTRL_STATE_SLEEP);
2580 if (IS_ERR(imx415->pins_sleep))
2581 dev_info(dev, "could not get sleep pinstate\n");
2582 } else {
2583 dev_info(dev, "no pinctrl\n");
2584 }
2585
2586 ret = imx415_configure_regulators(imx415);
2587 if (ret) {
2588 dev_err(dev, "Failed to get power regulators\n");
2589 return ret;
2590 }
2591
2592 mutex_init(&imx415->mutex);
2593
2594 sd = &imx415->subdev;
2595 v4l2_i2c_subdev_init(sd, client, &imx415_subdev_ops);
2596 ret = imx415_initialize_controls(imx415);
2597 if (ret)
2598 goto err_destroy_mutex;
2599
2600 ret = __imx415_power_on(imx415);
2601 if (ret)
2602 goto err_free_handler;
2603
2604 ret = imx415_check_sensor_id(imx415, client);
2605 if (ret)
2606 goto err_power_off;
2607
2608 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2609 sd->internal_ops = &imx415_internal_ops;
2610 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2611 V4L2_SUBDEV_FL_HAS_EVENTS;
2612 #endif
2613 #if defined(CONFIG_MEDIA_CONTROLLER)
2614 imx415->pad.flags = MEDIA_PAD_FL_SOURCE;
2615 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2616 ret = media_entity_pads_init(&sd->entity, 1, &imx415->pad);
2617 if (ret < 0)
2618 goto err_power_off;
2619 #endif
2620
2621 memset(facing, 0, sizeof(facing));
2622 if (strcmp(imx415->module_facing, "back") == 0)
2623 facing[0] = 'b';
2624 else
2625 facing[0] = 'f';
2626
2627 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2628 imx415->module_index, facing,
2629 IMX415_NAME, dev_name(sd->dev));
2630 ret = v4l2_async_register_subdev_sensor_common(sd);
2631 if (ret) {
2632 dev_err(dev, "v4l2 async register subdev failed\n");
2633 goto err_clean_entity;
2634 }
2635
2636 pm_runtime_set_active(dev);
2637 pm_runtime_enable(dev);
2638 pm_runtime_idle(dev);
2639
2640 return 0;
2641
2642 err_clean_entity:
2643 #if defined(CONFIG_MEDIA_CONTROLLER)
2644 media_entity_cleanup(&sd->entity);
2645 #endif
2646 err_power_off:
2647 __imx415_power_off(imx415);
2648 err_free_handler:
2649 v4l2_ctrl_handler_free(&imx415->ctrl_handler);
2650 err_destroy_mutex:
2651 mutex_destroy(&imx415->mutex);
2652
2653 return ret;
2654 }
2655
imx415_remove(struct i2c_client * client)2656 static int imx415_remove(struct i2c_client *client)
2657 {
2658 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2659 struct imx415 *imx415 = to_imx415(sd);
2660
2661 v4l2_async_unregister_subdev(sd);
2662 #if defined(CONFIG_MEDIA_CONTROLLER)
2663 media_entity_cleanup(&sd->entity);
2664 #endif
2665 v4l2_ctrl_handler_free(&imx415->ctrl_handler);
2666 mutex_destroy(&imx415->mutex);
2667
2668 pm_runtime_disable(&client->dev);
2669 if (!pm_runtime_status_suspended(&client->dev))
2670 __imx415_power_off(imx415);
2671 pm_runtime_set_suspended(&client->dev);
2672
2673 return 0;
2674 }
2675
2676 #if IS_ENABLED(CONFIG_OF)
2677 static const struct of_device_id imx415_of_match[] = {
2678 { .compatible = "sony,imx415" },
2679 {},
2680 };
2681 MODULE_DEVICE_TABLE(of, imx415_of_match);
2682 #endif
2683
2684 static const struct i2c_device_id imx415_match_id[] = {
2685 { "sony,imx415", 0 },
2686 { },
2687 };
2688
2689 static struct i2c_driver imx415_i2c_driver = {
2690 .driver = {
2691 .name = IMX415_NAME,
2692 .pm = &imx415_pm_ops,
2693 .of_match_table = of_match_ptr(imx415_of_match),
2694 },
2695 .probe = &imx415_probe,
2696 .remove = &imx415_remove,
2697 .id_table = imx415_match_id,
2698 };
2699
sensor_mod_init(void)2700 static int __init sensor_mod_init(void)
2701 {
2702 return i2c_add_driver(&imx415_i2c_driver);
2703 }
2704
sensor_mod_exit(void)2705 static void __exit sensor_mod_exit(void)
2706 {
2707 i2c_del_driver(&imx415_i2c_driver);
2708 }
2709
2710 device_initcall_sync(sensor_mod_init);
2711 module_exit(sensor_mod_exit);
2712
2713 MODULE_DESCRIPTION("Sony imx415 sensor driver");
2714 MODULE_LICENSE("GPL v2");
2715