1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx347 driver
4 *
5 * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version
8 * V0.0X01.0X01 add conversion gain control
9 * V0.0X01.0X02 add debug interface for conversion gain control
10 * V0.0X01.0X03 support enum sensor fmt
11 * V0.0X01.0X04 fix setting flow error according to datasheet and fix hdr gain error
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/sysfs.h>
23 #include <linux/slab.h>
24 #include <linux/version.h>
25 #include <linux/rk-camera-module.h>
26 #include <media/media-entity.h>
27 #include <media/v4l2-async.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-subdev.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/rk-preisp.h>
32
33 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
34
35 #ifndef V4L2_CID_DIGITAL_GAIN
36 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
37 #endif
38
39 #define MIPI_FREQ_360M 360000000
40 #define MIPI_FREQ_594M 594000000
41
42 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
43
44 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
45 #define IMX347_10BIT_LINEAR_PIXEL_RATE (MIPI_FREQ_594M * 2 / 10 * 2)
46 #define IMX347_10BIT_HDR2_PIXEL_RATE (MIPI_FREQ_594M * 2 / 10 * 4)
47 #define IMX347_12BIT_PIXEL_RATE (MIPI_FREQ_360M * 2 / 12 * 4)
48 #define IMX347_XVCLK_FREQ_37M 37125000
49 #define IMX347_XVCLK_FREQ_24M 24000000
50
51 #define CHIP_ID 0x06
52 #define IMX347_REG_CHIP_ID 0x3057
53
54 #define IMX347_REG_CTRL_MODE 0x3000
55 #define IMX347_MODE_SW_STANDBY BIT(0)
56 #define IMX347_MODE_STREAMING 0x0
57
58 #define IMX347_REG_MASTER_MODE 0x3002
59 #define IMX347_MASTER_MODE_STOP BIT(0)
60 #define IMX347_MASTER_MODE_START 0x0
61
62 #define IMX347_REG_RESTART_MODE 0x3004
63 #define IMX347_RESTART_MODE_START 0x04
64 #define IMX347_RESTART_MODE_STOP 0x0
65
66 #define IMX347_GAIN_SWITCH_REG 0x3019
67
68 #define IMX347_LF_GAIN_REG_H 0x30E9
69 #define IMX347_LF_GAIN_REG_L 0x30E8
70
71 #define IMX347_SF1_GAIN_REG_H 0x30EB
72 #define IMX347_SF1_GAIN_REG_L 0x30EA
73
74 #define IMX347_LF_EXPO_REG_H 0x305A
75 #define IMX347_LF_EXPO_REG_M 0x3059
76 #define IMX347_LF_EXPO_REG_L 0x3058
77
78 #define IMX347_SF1_EXPO_REG_H 0x305E
79 #define IMX347_SF1_EXPO_REG_M 0x305D
80 #define IMX347_SF1_EXPO_REG_L 0x305C
81
82 #define IMX347_RHS1_REG_H 0x306a
83 #define IMX347_RHS1_REG_M 0x3069
84 #define IMX347_RHS1_REG_L 0x3068
85
86 #define IMX347_EXPOSURE_MIN 2
87 #define IMX347_EXPOSURE_STEP 1
88 #define IMX347_VTS_MAX 0x7fff
89
90 #define IMX347_GAIN_MIN 0x00
91 #define IMX347_GAIN_MAX 0xee
92 #define IMX347_GAIN_STEP 1
93 #define IMX347_GAIN_DEFAULT 0x00
94
95 #define IMX347_FETCH_GAIN_H(VAL) (((VAL) >> 8) & 0x07)
96 #define IMX347_FETCH_GAIN_L(VAL) ((VAL) & 0xFF)
97
98 #define IMX347_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0x0F)
99 #define IMX347_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF)
100 #define IMX347_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
101
102 #define IMX347_FETCH_RHS1_H(VAL) (((VAL) >> 16) & 0x0F)
103 #define IMX347_FETCH_RHS1_M(VAL) (((VAL) >> 8) & 0xFF)
104 #define IMX347_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
105
106 #define IMX347_FETCH_VTS_H(VAL) (((VAL) >> 16) & 0x0F)
107 #define IMX347_FETCH_VTS_M(VAL) (((VAL) >> 8) & 0xFF)
108 #define IMX347_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
109
110 #define IMX347_GROUP_HOLD_REG 0x3001
111 #define IMX347_GROUP_HOLD_START 0x01
112 #define IMX347_GROUP_HOLD_END 0x00
113
114 #define IMX347_VTS_REG_L 0x3030
115 #define IMX347_VTS_REG_M 0x3031
116 #define IMX347_VTS_REG_H 0x3032
117
118 #define REG_NULL 0xFFFF
119
120 #define IMX347_REG_VALUE_08BIT 1
121 #define IMX347_REG_VALUE_16BIT 2
122 #define IMX347_REG_VALUE_24BIT 3
123
124 #define IMX347_2LANES 2
125 #define IMX347_4LANES 4
126 #define IMX347_BITS_PER_SAMPLE 10
127
128 #define IMX347_VREVERSE_REG 0x304f
129 #define IMX347_HREVERSE_REG 0x304e
130
131 #define RHS1_MAX 3113 // <2*BRL=2*1556 && 4n+1
132 #define SHR1_MIN 9
133 #define BRL 1556
134
135 #define USED_SYS_DEBUG
136
137 static bool g_isHCG;
138
139 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
140 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
141
142 #define IMX347_NAME "imx347"
143
144 static const char * const imx347_supply_names[] = {
145 "avdd", /* Analog power */
146 "dovdd", /* Digital I/O power */
147 "dvdd", /* Digital core power */
148 };
149
150 #define IMX347_NUM_SUPPLIES ARRAY_SIZE(imx347_supply_names)
151
152 struct regval {
153 u16 addr;
154 u8 val;
155 };
156
157 struct imx347_mode {
158 u32 bus_fmt;
159 u32 width;
160 u32 height;
161 struct v4l2_fract max_fps;
162 u32 hts_def;
163 u32 vts_def;
164 u32 exp_def;
165 const struct regval *reg_list;
166 u32 hdr_mode;
167 u32 vc[PAD_MAX];
168 u8 bpp;
169 };
170
171 struct imx347 {
172 struct i2c_client *client;
173 struct clk *xvclk;
174 struct gpio_desc *reset_gpio;
175 struct gpio_desc *pwdn_gpio;
176 struct regulator_bulk_data supplies[IMX347_NUM_SUPPLIES];
177 struct pinctrl *pinctrl;
178 struct pinctrl_state *pins_default;
179 struct pinctrl_state *pins_sleep;
180 struct v4l2_subdev subdev;
181 struct media_pad pad;
182 struct v4l2_ctrl_handler ctrl_handler;
183 struct v4l2_ctrl *exposure;
184 struct v4l2_ctrl *anal_a_gain;
185 struct v4l2_ctrl *digi_gain;
186 struct v4l2_ctrl *hblank;
187 struct v4l2_ctrl *vblank;
188 struct v4l2_ctrl *pixel_rate;
189 struct v4l2_ctrl *link_freq;
190 struct mutex mutex;
191 bool streaming;
192 bool power_on;
193 const struct imx347_mode *cur_mode;
194 u32 module_index;
195 u32 cfg_num;
196 u32 cur_pixel_rate;
197 u32 cur_link_freq;
198 const char *module_facing;
199 const char *module_name;
200 const char *len_name;
201 u32 cur_vts;
202 bool has_init_exp;
203 struct preisp_hdrae_exp_s init_hdrae_exp;
204 };
205
206 #define to_imx347(sd) container_of(sd, struct imx347, subdev)
207
208 /*
209 * Xclk 37.125Mhz
210 */
211 static const struct regval imx347_global_regs[] = {
212 {REG_NULL, 0x00},
213 };
214
215 static const struct regval imx347_linear_10bit_2688x1520_regs[] = {
216 {0x300C, 0x5B},
217 {0x300D, 0x40},
218 {0x3018, 0x00},
219 {0x302C, 0x24},
220 {0x302E, 0x98},
221 {0x302F, 0x0A},
222 {0x3030, 0xBC},
223 {0x3031, 0x07},
224 {0x3032, 0x00},
225 {0x3034, 0xDC},
226 {0x3035, 0x05},
227 {0x3048, 0x00},
228 {0x3049, 0x00},
229 {0x304A, 0x03},
230 {0x304B, 0x02},
231 {0x304C, 0x14},
232 {0x3050, 0x00},
233 {0x3056, 0x00},
234 {0x3057, 0x06},
235 {0x3058, 0x03},
236 {0x3059, 0x00},
237 {0x3068, 0xc9},
238 {0x3069, 0x00},
239 {0x30BE, 0x5E},
240 {0x30C6, 0x06},
241 {0x30CE, 0x04},
242 {0x30D8, 0x44},
243 {0x30D9, 0x06},
244 {0x3110, 0x02},
245 {0x314C, 0x80},
246 {0x315A, 0x02},
247 {0x3168, 0x68},
248 {0x316A, 0x7E},
249 {0x319D, 0x00},
250 {0x319E, 0x01},
251 {0x31A1, 0x00},
252 {0x31D7, 0x00},
253 {0x3200, 0x11},/* Each frame gain adjustment disabed in linear mode */
254 {0x3202, 0x02},
255 {0x3288, 0x22},
256 {0x328A, 0x02},
257 {0x328C, 0xA2},
258 {0x328E, 0x22},
259 {0x3415, 0x27},
260 {0x3418, 0x27},
261 {0x3428, 0xFE},
262 {0x349E, 0x6A},
263 {0x34A2, 0x9A},
264 {0x34A4, 0x8A},
265 {0x34A6, 0x8E},
266 {0x34AA, 0xD8},
267 {0x3648, 0x01},
268 {0x3678, 0x01},
269 {0x367C, 0x69},
270 {0x367E, 0x69},
271 {0x3680, 0x69},
272 {0x3682, 0x69},
273 {0x371D, 0x05},
274 {0x375D, 0x11},
275 {0x375E, 0x43},
276 {0x375F, 0x76},
277 {0x3760, 0x07},
278 {0x3768, 0x1B},
279 {0x3769, 0x1B},
280 {0x376A, 0x1A},
281 {0x376B, 0x19},
282 {0x376C, 0x17},
283 {0x376D, 0x0F},
284 {0x376E, 0x0B},
285 {0x376F, 0x0B},
286 {0x3770, 0x0B},
287 {0x3776, 0x89},
288 {0x3777, 0x00},
289 {0x3778, 0xCA},
290 {0x3779, 0x00},
291 {0x377A, 0x45},
292 {0x377B, 0x01},
293 {0x377C, 0x56},
294 {0x377D, 0x02},
295 {0x377E, 0xFE},
296 {0x377F, 0x03},
297 {0x3780, 0xFE},
298 {0x3781, 0x05},
299 {0x3782, 0xFE},
300 {0x3783, 0x06},
301 {0x3784, 0x7F},
302 {0x3788, 0x1F},
303 {0x378A, 0xCA},
304 {0x378B, 0x00},
305 {0x378C, 0x45},
306 {0x378D, 0x01},
307 {0x378E, 0x56},
308 {0x378F, 0x02},
309 {0x3790, 0xFE},
310 {0x3791, 0x03},
311 {0x3792, 0xFE},
312 {0x3793, 0x05},
313 {0x3794, 0xFE},
314 {0x3795, 0x06},
315 {0x3796, 0x7F},
316 {0x3798, 0xBF},
317 {0x3A01, 0x01},
318 {0x3A18, 0x8F},
319 {0x3A1A, 0x4F},
320 {0x3A1C, 0x47},
321 {0x3A1E, 0x37},
322 {0x3A1F, 0x01},
323 {0x3A20, 0x4F},
324 {0x3A22, 0x87},
325 {0x3A24, 0x4F},
326 {0x3A26, 0x7f},
327 {0x3A28, 0x3f},
328 {REG_NULL, 0x00},
329 };
330
331 static const struct regval imx347_hdr_2x_10bit_2688x1520_regs[] = {
332 {0x300C, 0x5B},
333 {0x300D, 0x40},
334 {0x3018, 0x00},
335 {0x302C, 0x24},
336 {0x302E, 0x98},
337 {0x302F, 0x0A},
338 {0x3030, 0xbc},
339 {0x3031, 0x07},
340 {0x3032, 0x00},
341 {0x3034, 0xEE},
342 {0x3035, 0x02},
343 {0x3048, 0x01},
344 {0x3049, 0x01},
345 {0x304A, 0x04},
346 {0x304B, 0x04},
347 {0x304C, 0x13},
348 {0x3050, 0x00},
349 {0x3056, 0x00},
350 {0x3057, 0x06},
351 {0x3058, 0x4A},
352 {0x3059, 0x01},
353 {0x3068, 0xD1},
354 {0x3069, 0x00},
355 {0x30BE, 0x5E},
356 {0x30C6, 0x06},
357 {0x30CE, 0x04},
358 {0x30D8, 0x44},
359 {0x30D9, 0x06},
360 {0x3110, 0x02},
361 {0x314C, 0x80},
362 {0x315A, 0x02},
363 {0x3168, 0x68},
364 {0x316A, 0x7E},
365 {0x319D, 0x00},
366 {0x319E, 0x01},
367 {0x31A1, 0x00},
368 {0x31D7, 0x01},
369 {0x3200, 0x10},/* Each frame gain adjustment EN in hdr mode */
370 {0x3202, 0x02},
371 {0x3288, 0x22},
372 {0x328A, 0x02},
373 {0x328C, 0xA2},
374 {0x328E, 0x22},
375 {0x3415, 0x27},
376 {0x3418, 0x27},
377 {0x3428, 0xFE},
378 {0x349E, 0x6A},
379 {0x34A2, 0x9A},
380 {0x34A4, 0x8A},
381 {0x34A6, 0x8E},
382 {0x34AA, 0xD8},
383 {0x3648, 0x01},
384 {0x3678, 0x01},
385 {0x367C, 0x69},
386 {0x367E, 0x69},
387 {0x3680, 0x69},
388 {0x3682, 0x69},
389 {0x371D, 0x05},
390 {0x375D, 0x11},
391 {0x375E, 0x43},
392 {0x375F, 0x76},
393 {0x3760, 0x07},
394 {0x3768, 0x1B},
395 {0x3769, 0x1B},
396 {0x376A, 0x1A},
397 {0x376B, 0x19},
398 {0x376C, 0x17},
399 {0x376D, 0x0F},
400 {0x376E, 0x0B},
401 {0x376F, 0x0B},
402 {0x3770, 0x0B},
403 {0x3776, 0x89},
404 {0x3777, 0x00},
405 {0x3778, 0xCA},
406 {0x3779, 0x00},
407 {0x377A, 0x45},
408 {0x377B, 0x01},
409 {0x377C, 0x56},
410 {0x377D, 0x02},
411 {0x377E, 0xFE},
412 {0x377F, 0x03},
413 {0x3780, 0xFE},
414 {0x3781, 0x05},
415 {0x3782, 0xFE},
416 {0x3783, 0x06},
417 {0x3784, 0x7F},
418 {0x3788, 0x1F},
419 {0x378A, 0xCA},
420 {0x378B, 0x00},
421 {0x378C, 0x45},
422 {0x378D, 0x01},
423 {0x378E, 0x56},
424 {0x378F, 0x02},
425 {0x3790, 0xFE},
426 {0x3791, 0x03},
427 {0x3792, 0xFE},
428 {0x3793, 0x05},
429 {0x3794, 0xFE},
430 {0x3795, 0x06},
431 {0x3796, 0x7F},
432 {0x3798, 0xBF},
433 {0x3A01, 0x03},
434 {0x3A18, 0x8F},
435 {0x3A1A, 0x4F},
436 {0x3A1C, 0x47},
437 {0x3A1E, 0x37},
438 {0x3A1F, 0x01},
439 {0x3A20, 0x4F},
440 {0x3A22, 0x87},
441 {0x3A24, 0x4F},
442 {0x3A26, 0x7f},
443 {0x3A28, 0x3f},
444 {REG_NULL, 0x00},
445 };
446
447 static const struct regval imx347_linear_12bit_2688x1520_regs[] = {
448 {0x300C, 0x3B},
449 {0x300D, 0x2A},
450 {0x3018, 0x04},
451 {0x302C, 0x30},
452 {0x302E, 0x80},
453 {0x302F, 0x0A},
454 {0x3030, 0x6B},
455 {0x3031, 0x0A},
456 {0x3032, 0x00},
457 {0x3034, 0xee},
458 {0x3035, 0x02},
459 {0x3048, 0x00},
460 {0x3049, 0x00},
461 {0x304A, 0x03},
462 {0x304B, 0x02},
463 {0x304C, 0x14},
464 {0x3050, 0x01},
465 {0x3056, 0x02},
466 {0x3057, 0x06},
467 {0x3058, 0x03},
468 {0x3059, 0x00},
469 {0x3068, 0xc9},
470 {0x3069, 0x00},
471 {0x30BE, 0x5E},
472 {0x30C6, 0x00},
473 {0x30CE, 0x00},
474 {0x30D8, 0x4F},
475 {0x30D9, 0x64},
476 {0x3110, 0x02},
477 {0x314C, 0xF0},
478 {0x315A, 0x06},
479 {0x3168, 0x82},
480 {0x316A, 0x7E},
481 {0x319D, 0x01},
482 {0x319E, 0x02},
483 {0x31A1, 0x00},
484 {0x31D7, 0x00},
485 {0x3200, 0x11},/* Each frame gain adjustment disabed in linear mode */
486 {0x3202, 0x02},
487 {0x3288, 0x22},
488 {0x328A, 0x02},
489 {0x328C, 0xA2},
490 {0x328E, 0x22},
491 {0x3415, 0x27},
492 {0x3418, 0x27},
493 {0x3428, 0xFE},
494 {0x349E, 0x6A},
495 {0x34A2, 0x9A},
496 {0x34A4, 0x8A},
497 {0x34A6, 0x8E},
498 {0x34AA, 0xD8},
499 {0x3648, 0x01},
500 {0x3678, 0x01},
501 {0x367C, 0x69},
502 {0x367E, 0x69},
503 {0x3680, 0x69},
504 {0x3682, 0x69},
505 {0x371D, 0x05},
506 {0x375D, 0x11},
507 {0x375E, 0x43},
508 {0x375F, 0x76},
509 {0x3760, 0x07},
510 {0x3768, 0x1B},
511 {0x3769, 0x1B},
512 {0x376A, 0x1A},
513 {0x376B, 0x19},
514 {0x376C, 0x17},
515 {0x376D, 0x0F},
516 {0x376E, 0x0B},
517 {0x376F, 0x0B},
518 {0x3770, 0x0B},
519 {0x3776, 0x89},
520 {0x3777, 0x00},
521 {0x3778, 0xCA},
522 {0x3779, 0x00},
523 {0x377A, 0x45},
524 {0x377B, 0x01},
525 {0x377C, 0x56},
526 {0x377D, 0x02},
527 {0x377E, 0xFE},
528 {0x377F, 0x03},
529 {0x3780, 0xFE},
530 {0x3781, 0x05},
531 {0x3782, 0xFE},
532 {0x3783, 0x06},
533 {0x3784, 0x7F},
534 {0x3788, 0x1F},
535 {0x378A, 0xCA},
536 {0x378B, 0x00},
537 {0x378C, 0x45},
538 {0x378D, 0x01},
539 {0x378E, 0x56},
540 {0x378F, 0x02},
541 {0x3790, 0xFE},
542 {0x3791, 0x03},
543 {0x3792, 0xFE},
544 {0x3793, 0x05},
545 {0x3794, 0xFE},
546 {0x3795, 0x06},
547 {0x3796, 0x7F},
548 {0x3798, 0xBF},
549 {0x3A01, 0x03},
550 {0x3A18, 0x6F},
551 {0x3A1A, 0x2F},
552 {0x3A1C, 0x2F},
553 {0x3A1E, 0xBF},
554 {0x3A1F, 0x00},
555 {0x3A20, 0x2F},
556 {0x3A22, 0x57},
557 {0x3A24, 0x2F},
558 {0x3A26, 0x4F},
559 {0x3A28, 0x27},
560 {REG_NULL, 0x00},
561 };
562
563 static const struct regval imx347_hdr_2x_12bit_2688x1520_regs[] = {
564 {0x300C, 0x3B},
565 {0x300D, 0x2A},
566 {0x3018, 0x04},
567 {0x302C, 0x30},
568 {0x302E, 0x80},
569 {0x302F, 0x0A},
570 {0x3030, 0x40},
571 {0x3031, 0x06},
572 {0x3032, 0x00},
573 {0x3034, 0xee},
574 {0x3035, 0x02},
575 {0x3048, 0x01},
576 {0x3049, 0x01},
577 {0x304A, 0x04},
578 {0x304B, 0x04},
579 {0x304C, 0x13},
580 {0x3050, 0x01},
581 {0x3056, 0x02},
582 {0x3057, 0x06},
583 {0x3058, 0x20},
584 {0x3059, 0x03},
585 {0x3068, 0xD9},
586 {0x3069, 0x02},
587 {0x30BE, 0x5E},
588 {0x30C6, 0x00},
589 {0x30CE, 0x00},
590 {0x30D8, 0x4F},
591 {0x30D9, 0x64},
592 {0x3110, 0x02},
593 {0x314C, 0xF0},
594 {0x315A, 0x06},
595 {0x3168, 0x82},
596 {0x316A, 0x7E},
597 {0x319D, 0x01},
598 {0x319E, 0x02},
599 {0x31A1, 0x00},
600 {0x31D7, 0x01},
601 {0x3200, 0x10},/* Each frame gain adjustment EN in hdr mode */
602 {0x3202, 0x02},
603 {0x3288, 0x22},
604 {0x328A, 0x02},
605 {0x328C, 0xA2},
606 {0x328E, 0x22},
607 {0x3415, 0x27},
608 {0x3418, 0x27},
609 {0x3428, 0xFE},
610 {0x349E, 0x6A},
611 {0x34A2, 0x9A},
612 {0x34A4, 0x8A},
613 {0x34A6, 0x8E},
614 {0x34AA, 0xD8},
615 {0x3648, 0x01},
616 {0x3678, 0x01},
617 {0x367C, 0x69},
618 {0x367E, 0x69},
619 {0x3680, 0x69},
620 {0x3682, 0x69},
621 {0x371D, 0x05},
622 {0x375D, 0x11},
623 {0x375E, 0x43},
624 {0x375F, 0x76},
625 {0x3760, 0x07},
626 {0x3768, 0x1B},
627 {0x3769, 0x1B},
628 {0x376A, 0x1A},
629 {0x376B, 0x19},
630 {0x376C, 0x17},
631 {0x376D, 0x0F},
632 {0x376E, 0x0B},
633 {0x376F, 0x0B},
634 {0x3770, 0x0B},
635 {0x3776, 0x89},
636 {0x3777, 0x00},
637 {0x3778, 0xCA},
638 {0x3779, 0x00},
639 {0x377A, 0x45},
640 {0x377B, 0x01},
641 {0x377C, 0x56},
642 {0x377D, 0x02},
643 {0x377E, 0xFE},
644 {0x377F, 0x03},
645 {0x3780, 0xFE},
646 {0x3781, 0x05},
647 {0x3782, 0xFE},
648 {0x3783, 0x06},
649 {0x3784, 0x7F},
650 {0x3788, 0x1F},
651 {0x378A, 0xCA},
652 {0x378B, 0x00},
653 {0x378C, 0x45},
654 {0x378D, 0x01},
655 {0x378E, 0x56},
656 {0x378F, 0x02},
657 {0x3790, 0xFE},
658 {0x3791, 0x03},
659 {0x3792, 0xFE},
660 {0x3793, 0x05},
661 {0x3794, 0xFE},
662 {0x3795, 0x06},
663 {0x3796, 0x7F},
664 {0x3798, 0xBF},
665 {0x3A01, 0x03},
666 {0x3A18, 0x6F},
667 {0x3A1A, 0x2F},
668 {0x3A1C, 0x2F},
669 {0x3A1E, 0xBF},
670 {0x3A1F, 0x00},
671 {0x3A20, 0x2F},
672 {0x3A22, 0x57},
673 {0x3A24, 0x2F},
674 {0x3A26, 0x4F},
675 {0x3A28, 0x27},
676 {REG_NULL, 0x00},
677 };
678
679 /*
680 * The width and height must be configured to be
681 * the same as the current output resolution of the sensor.
682 * The input width of the isp needs to be 16 aligned.
683 * The input height of the isp needs to be 8 aligned.
684 * If the width or height does not meet the alignment rules,
685 * you can configure the cropping parameters with the following function to
686 * crop out the appropriate resolution.
687 * struct v4l2_subdev_pad_ops {
688 * .get_selection
689 * }
690 */
691 static const struct imx347_mode supported_modes[] = {
692 {
693 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
694 .width = 2712,
695 .height = 1536,
696 .max_fps = {
697 .numerator = 10000,
698 .denominator = 250000,
699 },
700 .exp_def = 0x0240,
701 .hts_def = 0x05dc * 2,
702 .vts_def = 0x07bc,
703 .reg_list = imx347_linear_10bit_2688x1520_regs,
704 .hdr_mode = NO_HDR,
705 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
706 .bpp = 10,
707 },
708 {
709 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
710 .width = 2712,
711 .height = 1536,
712 .max_fps = {
713 .numerator = 10000,
714 .denominator = 250000,
715 },
716 .exp_def = 0x0240,
717 .hts_def = 0x02ee * 4,
718 .vts_def = 0x07bc * 2,
719 .reg_list = imx347_hdr_2x_10bit_2688x1520_regs,
720 .hdr_mode = HDR_X2,
721 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
722 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
723 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
724 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
725 .bpp = 10,
726 },
727 {
728 .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
729 .width = 2688,
730 .height = 1538,
731 .max_fps = {
732 .numerator = 10000,
733 .denominator = 299960,
734 },
735 .exp_def = 0x0240,
736 .hts_def = 0x02EE * 4,
737 .vts_def = 0x0A6B,
738 .reg_list = imx347_linear_12bit_2688x1520_regs,
739 .hdr_mode = NO_HDR,
740 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
741 .bpp = 12,
742 },
743 {
744 .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
745 .width = 2688,
746 .height = 1538,
747 .max_fps = {
748 .numerator = 10000,
749 .denominator = 250000,
750 },
751 .exp_def = 0x0240,
752 .hts_def = 0x02ee * 4,
753 .vts_def = 0x0640 * 2,
754 .reg_list = imx347_hdr_2x_12bit_2688x1520_regs,
755 .hdr_mode = HDR_X2,
756 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
757 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
758 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
759 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
760 .bpp = 12,
761 },
762 };
763
764 static const s64 link_freq_menu_items[] = {
765 MIPI_FREQ_360M,
766 MIPI_FREQ_594M,
767 };
768
769 /* Write registers up to 4 at a time */
imx347_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)770 static int imx347_write_reg(struct i2c_client *client, u16 reg,
771 u32 len, u32 val)
772 {
773 u32 buf_i, val_i;
774 u8 buf[6];
775 u8 *val_p;
776 __be32 val_be;
777
778 if (len > 4)
779 return -EINVAL;
780
781 buf[0] = reg >> 8;
782 buf[1] = reg & 0xff;
783
784 val_be = cpu_to_be32(val);
785 val_p = (u8 *)&val_be;
786 buf_i = 2;
787 val_i = 4 - len;
788
789 while (val_i < 4)
790 buf[buf_i++] = val_p[val_i++];
791
792 if (i2c_master_send(client, buf, len + 2) != len + 2)
793 return -EIO;
794
795 return 0;
796 }
797
imx347_write_array(struct i2c_client * client,const struct regval * regs)798 static int imx347_write_array(struct i2c_client *client,
799 const struct regval *regs)
800 {
801 u32 i;
802 int ret = 0;
803
804 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
805 ret = imx347_write_reg(client, regs[i].addr,
806 IMX347_REG_VALUE_08BIT, regs[i].val);
807 }
808 return ret;
809 }
810
811 /* Read registers up to 4 at a time */
imx347_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)812 static int imx347_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
813 u32 *val)
814 {
815 struct i2c_msg msgs[2];
816 u8 *data_be_p;
817 __be32 data_be = 0;
818 __be16 reg_addr_be = cpu_to_be16(reg);
819 int ret;
820
821 if (len > 4 || !len)
822 return -EINVAL;
823
824 data_be_p = (u8 *)&data_be;
825 /* Write register address */
826 msgs[0].addr = client->addr;
827 msgs[0].flags = 0;
828 msgs[0].len = 2;
829 msgs[0].buf = (u8 *)®_addr_be;
830
831 /* Read data from register */
832 msgs[1].addr = client->addr;
833 msgs[1].flags = I2C_M_RD;
834 msgs[1].len = len;
835 msgs[1].buf = &data_be_p[4 - len];
836
837 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
838 if (ret != ARRAY_SIZE(msgs))
839 return -EIO;
840
841 *val = be32_to_cpu(data_be);
842
843 return 0;
844 }
845
imx347_get_reso_dist(const struct imx347_mode * mode,struct v4l2_mbus_framefmt * framefmt)846 static int imx347_get_reso_dist(const struct imx347_mode *mode,
847 struct v4l2_mbus_framefmt *framefmt)
848 {
849 return abs(mode->width - framefmt->width) +
850 abs(mode->height - framefmt->height);
851 }
852
853 static const struct imx347_mode *
imx347_find_best_fit(struct imx347 * imx347,struct v4l2_subdev_format * fmt)854 imx347_find_best_fit(struct imx347 *imx347, struct v4l2_subdev_format *fmt)
855 {
856 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
857 int dist;
858 int cur_best_fit = 0;
859 int cur_best_fit_dist = -1;
860 unsigned int i;
861
862 for (i = 0; i < imx347->cfg_num; i++) {
863 dist = imx347_get_reso_dist(&supported_modes[i], framefmt);
864 if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
865 supported_modes[i].bus_fmt == framefmt->code) {
866 cur_best_fit_dist = dist;
867 cur_best_fit = i;
868 }
869 }
870
871 return &supported_modes[cur_best_fit];
872 }
873
imx347_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)874 static int imx347_set_fmt(struct v4l2_subdev *sd,
875 struct v4l2_subdev_pad_config *cfg,
876 struct v4l2_subdev_format *fmt)
877 {
878 struct imx347 *imx347 = to_imx347(sd);
879 const struct imx347_mode *mode;
880 s64 h_blank, vblank_def;
881 struct device *dev = &imx347->client->dev;
882 int ret = 0;
883
884 mutex_lock(&imx347->mutex);
885
886 mode = imx347_find_best_fit(imx347, fmt);
887 fmt->format.code = mode->bus_fmt;
888 fmt->format.width = mode->width;
889 fmt->format.height = mode->height;
890 fmt->format.field = V4L2_FIELD_NONE;
891 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
892 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
893 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
894 #else
895 mutex_unlock(&imx347->mutex);
896 return -ENOTTY;
897 #endif
898 } else {
899 imx347->cur_mode = mode;
900 h_blank = mode->hts_def - mode->width;
901 __v4l2_ctrl_modify_range(imx347->hblank, h_blank,
902 h_blank, 1, h_blank);
903 vblank_def = mode->vts_def - mode->height;
904 __v4l2_ctrl_modify_range(imx347->vblank, vblank_def,
905 IMX347_VTS_MAX - mode->height,
906 1, vblank_def);
907 imx347->cur_vts = imx347->cur_mode->vts_def;
908 if (mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10) {
909 if (mode->hdr_mode == NO_HDR)
910 imx347->cur_pixel_rate = IMX347_10BIT_LINEAR_PIXEL_RATE;
911 else if (mode->hdr_mode == HDR_X2)
912 imx347->cur_pixel_rate = IMX347_10BIT_HDR2_PIXEL_RATE;
913 imx347->cur_link_freq = 1;
914 clk_disable_unprepare(imx347->xvclk);
915 ret = clk_set_rate(imx347->xvclk, IMX347_XVCLK_FREQ_37M);
916 if (ret < 0)
917 dev_err(dev, "Failed to set xvclk rate\n");
918 if (clk_get_rate(imx347->xvclk) != IMX347_XVCLK_FREQ_37M)
919 dev_err(dev, "xvclk mismatched\n");
920 ret = clk_prepare_enable(imx347->xvclk);
921 if (ret < 0)
922 dev_err(dev, "Failed to enable xvclk\n");
923 } else {
924 imx347->cur_pixel_rate = IMX347_12BIT_PIXEL_RATE;
925 imx347->cur_link_freq = 0;
926 clk_disable_unprepare(imx347->xvclk);
927 ret = clk_set_rate(imx347->xvclk, IMX347_XVCLK_FREQ_24M);
928 if (ret < 0)
929 dev_err(dev, "Failed to set xvclk rate\n");
930 if (clk_get_rate(imx347->xvclk) != IMX347_XVCLK_FREQ_24M)
931 dev_err(dev, "xvclk mismatched\n");
932 ret = clk_prepare_enable(imx347->xvclk);
933 if (ret < 0)
934 dev_err(dev, "Failed to enable xvclk\n");
935 }
936 __v4l2_ctrl_s_ctrl_int64(imx347->pixel_rate,
937 imx347->cur_pixel_rate);
938 __v4l2_ctrl_s_ctrl(imx347->link_freq,
939 imx347->cur_link_freq);
940 }
941
942 mutex_unlock(&imx347->mutex);
943
944 return 0;
945 }
946
imx347_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)947 static int imx347_get_fmt(struct v4l2_subdev *sd,
948 struct v4l2_subdev_pad_config *cfg,
949 struct v4l2_subdev_format *fmt)
950 {
951 struct imx347 *imx347 = to_imx347(sd);
952 const struct imx347_mode *mode = imx347->cur_mode;
953
954 mutex_lock(&imx347->mutex);
955 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
956 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
957 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
958 #else
959 mutex_unlock(&imx347->mutex);
960 return -ENOTTY;
961 #endif
962 } else {
963 fmt->format.width = mode->width;
964 fmt->format.height = mode->height;
965 fmt->format.code = mode->bus_fmt;
966 fmt->format.field = V4L2_FIELD_NONE;
967 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
968 fmt->reserved[0] = mode->vc[fmt->pad];
969 else
970 fmt->reserved[0] = mode->vc[PAD0];
971 }
972 mutex_unlock(&imx347->mutex);
973
974 return 0;
975 }
976
imx347_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)977 static int imx347_enum_mbus_code(struct v4l2_subdev *sd,
978 struct v4l2_subdev_pad_config *cfg,
979 struct v4l2_subdev_mbus_code_enum *code)
980 {
981 struct imx347 *imx347 = to_imx347(sd);
982
983 if (code->index != 0)
984 return -EINVAL;
985 code->code = imx347->cur_mode->bus_fmt;
986
987 return 0;
988 }
989
imx347_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)990 static int imx347_enum_frame_sizes(struct v4l2_subdev *sd,
991 struct v4l2_subdev_pad_config *cfg,
992 struct v4l2_subdev_frame_size_enum *fse)
993 {
994 struct imx347 *imx347 = to_imx347(sd);
995
996 if (fse->index >= imx347->cfg_num)
997 return -EINVAL;
998
999 if (fse->code != supported_modes[fse->index].bus_fmt)
1000 return -EINVAL;
1001
1002 fse->min_width = supported_modes[fse->index].width;
1003 fse->max_width = supported_modes[fse->index].width;
1004 fse->max_height = supported_modes[fse->index].height;
1005 fse->min_height = supported_modes[fse->index].height;
1006
1007 return 0;
1008 }
1009
imx347_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1010 static int imx347_g_frame_interval(struct v4l2_subdev *sd,
1011 struct v4l2_subdev_frame_interval *fi)
1012 {
1013 struct imx347 *imx347 = to_imx347(sd);
1014 const struct imx347_mode *mode = imx347->cur_mode;
1015
1016 fi->interval = mode->max_fps;
1017
1018 return 0;
1019 }
1020
imx347_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1021 static int imx347_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1022 struct v4l2_mbus_config *config)
1023 {
1024 struct imx347 *imx347 = to_imx347(sd);
1025 const struct imx347_mode *mode = imx347->cur_mode;
1026 u32 val = 0;
1027
1028 if (mode->hdr_mode == NO_HDR) {
1029 if (mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10)
1030 val = 1 << (IMX347_2LANES - 1) |
1031 V4L2_MBUS_CSI2_CHANNEL_0 |
1032 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1033 else
1034 val = 1 << (IMX347_4LANES - 1) |
1035 V4L2_MBUS_CSI2_CHANNEL_0 |
1036 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1037 }
1038 if (mode->hdr_mode == HDR_X2)
1039 val = 1 << (IMX347_4LANES - 1) |
1040 V4L2_MBUS_CSI2_CHANNEL_0 |
1041 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
1042 V4L2_MBUS_CSI2_CHANNEL_1;
1043
1044 config->type = V4L2_MBUS_CSI2_DPHY;
1045 config->flags = val;
1046
1047 return 0;
1048 }
1049
imx347_get_module_inf(struct imx347 * imx347,struct rkmodule_inf * inf)1050 static void imx347_get_module_inf(struct imx347 *imx347,
1051 struct rkmodule_inf *inf)
1052 {
1053 memset(inf, 0, sizeof(*inf));
1054 strscpy(inf->base.sensor, IMX347_NAME, sizeof(inf->base.sensor));
1055 strscpy(inf->base.module, imx347->module_name,
1056 sizeof(inf->base.module));
1057 strscpy(inf->base.lens, imx347->len_name, sizeof(inf->base.lens));
1058 }
1059
imx347_set_hdrae(struct imx347 * imx347,struct preisp_hdrae_exp_s * ae)1060 static int imx347_set_hdrae(struct imx347 *imx347,
1061 struct preisp_hdrae_exp_s *ae)
1062 {
1063 struct i2c_client *client = imx347->client;
1064 u32 l_exp_time, m_exp_time, s_exp_time;
1065 u32 l_a_gain, m_a_gain, s_a_gain;
1066 u32 gain_switch = 0;
1067 u32 shr1 = 0;
1068 u32 shr0 = 0;
1069 u32 rhs1 = 0;
1070 u32 rhs1_max = 0;
1071 static int rhs1_old = 209;
1072 int rhs1_change_limit;
1073 int ret = 0;
1074 u32 fsc = imx347->cur_vts;
1075 u8 cg_mode = 0;
1076
1077 if (!imx347->has_init_exp && !imx347->streaming) {
1078 imx347->init_hdrae_exp = *ae;
1079 imx347->has_init_exp = true;
1080 dev_dbg(&imx347->client->dev, "imx347 don't stream, record exp for hdr!\n");
1081 return ret;
1082 }
1083 l_exp_time = ae->long_exp_reg;
1084 m_exp_time = ae->middle_exp_reg;
1085 s_exp_time = ae->short_exp_reg;
1086 l_a_gain = ae->long_gain_reg;
1087 m_a_gain = ae->middle_gain_reg;
1088 s_a_gain = ae->short_gain_reg;
1089 dev_dbg(&client->dev,
1090 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
1091 l_exp_time, m_exp_time, s_exp_time,
1092 l_a_gain, m_a_gain, s_a_gain);
1093
1094 if (imx347->cur_mode->hdr_mode == HDR_X2) {
1095 //2 stagger
1096 l_a_gain = m_a_gain;
1097 l_exp_time = m_exp_time;
1098 cg_mode = ae->middle_cg_mode;
1099 }
1100 if (!g_isHCG && cg_mode == GAIN_MODE_HCG) {
1101 gain_switch = 0x01 | 0x100;
1102 g_isHCG = true;
1103 } else if (g_isHCG && cg_mode == GAIN_MODE_LCG) {
1104 gain_switch = 0x00 | 0x100;
1105 g_isHCG = false;
1106 }
1107 ret = imx347_write_reg(client,
1108 IMX347_GROUP_HOLD_REG,
1109 IMX347_REG_VALUE_08BIT,
1110 IMX347_GROUP_HOLD_START);
1111 //gain effect n+1
1112 ret |= imx347_write_reg(client,
1113 IMX347_LF_GAIN_REG_H,
1114 IMX347_REG_VALUE_08BIT,
1115 IMX347_FETCH_GAIN_H(l_a_gain));
1116 ret |= imx347_write_reg(client,
1117 IMX347_LF_GAIN_REG_L,
1118 IMX347_REG_VALUE_08BIT,
1119 IMX347_FETCH_GAIN_L(l_a_gain));
1120 ret |= imx347_write_reg(client,
1121 IMX347_SF1_GAIN_REG_H,
1122 IMX347_REG_VALUE_08BIT,
1123 IMX347_FETCH_GAIN_H(s_a_gain));
1124 ret |= imx347_write_reg(client,
1125 IMX347_SF1_GAIN_REG_L,
1126 IMX347_REG_VALUE_08BIT,
1127 IMX347_FETCH_GAIN_L(s_a_gain));
1128 if (gain_switch & 0x100)
1129 ret |= imx347_write_reg(client,
1130 IMX347_GAIN_SWITCH_REG,
1131 IMX347_REG_VALUE_08BIT,
1132 gain_switch & 0xff);
1133
1134 //long exposure and short exposure
1135 shr0 = fsc - l_exp_time;
1136 rhs1_max = (RHS1_MAX > (shr0 - 9)) ? (shr0 - 9) : RHS1_MAX;
1137 rhs1 = SHR1_MIN + s_exp_time;
1138 dev_dbg(&client->dev, "line(%d) rhs1 %d\n", __LINE__, rhs1);
1139 if (rhs1 < 13)
1140 rhs1 = 13;
1141 else if (rhs1 > rhs1_max)
1142 rhs1 = rhs1_max;
1143 dev_dbg(&client->dev, "line(%d) rhs1 %d\n", __LINE__, rhs1);
1144
1145 //Dynamic adjustment rhs1 must meet the following conditions
1146 rhs1_change_limit = rhs1_old + 2 * BRL - fsc + 2;
1147 rhs1_change_limit = (rhs1_change_limit < 13) ? 13 : rhs1_change_limit;
1148 if (rhs1 < rhs1_change_limit)
1149 rhs1 = rhs1_change_limit;
1150
1151 dev_dbg(&client->dev,
1152 "line(%d) rhs1 %d,short time %d rhs1_old %d test %d\n",
1153 __LINE__, rhs1, s_exp_time, rhs1_old,
1154 (rhs1_old + 2 * BRL - fsc + 2));
1155
1156 rhs1 = (rhs1 >> 2) * 4 + 1;
1157 rhs1_old = rhs1;
1158
1159 if (rhs1 < s_exp_time) {
1160 shr1 = 9;
1161 s_exp_time = rhs1 - shr1;
1162 } else {
1163 shr1 = rhs1 - s_exp_time;
1164 }
1165
1166 if (shr1 < 9)
1167 shr1 = 9;
1168 else if (shr1 > (rhs1 - 2))
1169 shr1 = rhs1 - 2;
1170
1171 if (shr0 < (rhs1 + 9))
1172 shr0 = rhs1 + 9;
1173 else if (shr0 > (fsc - 2))
1174 shr0 = fsc - 2;
1175
1176 dev_dbg(&client->dev,
1177 "fsc=%d,RHS1_MAX=%d,SHR1_MIN=%d,rhs1_max=%d\n",
1178 fsc, RHS1_MAX, SHR1_MIN, rhs1_max);
1179 dev_dbg(&client->dev,
1180 "l_exp_time=%d,s_exp_time=%d,shr0=%d,shr1=%d,rhs1=%d,l_a_gain=%d,s_a_gain=%d\n",
1181 l_exp_time, s_exp_time, shr0, shr1, rhs1, l_a_gain, s_a_gain);
1182 //time effect n+2
1183 ret |= imx347_write_reg(client,
1184 IMX347_RHS1_REG_L,
1185 IMX347_REG_VALUE_08BIT,
1186 IMX347_FETCH_RHS1_L(rhs1));
1187 ret |= imx347_write_reg(client,
1188 IMX347_RHS1_REG_M,
1189 IMX347_REG_VALUE_08BIT,
1190 IMX347_FETCH_RHS1_M(rhs1));
1191 ret |= imx347_write_reg(client,
1192 IMX347_RHS1_REG_H,
1193 IMX347_REG_VALUE_08BIT,
1194 IMX347_FETCH_RHS1_H(rhs1));
1195
1196 ret |= imx347_write_reg(client,
1197 IMX347_SF1_EXPO_REG_L,
1198 IMX347_REG_VALUE_08BIT,
1199 IMX347_FETCH_EXP_L(shr1));
1200 ret |= imx347_write_reg(client,
1201 IMX347_SF1_EXPO_REG_M,
1202 IMX347_REG_VALUE_08BIT,
1203 IMX347_FETCH_EXP_M(shr1));
1204 ret |= imx347_write_reg(client,
1205 IMX347_SF1_EXPO_REG_H,
1206 IMX347_REG_VALUE_08BIT,
1207 IMX347_FETCH_EXP_H(shr1));
1208 ret |= imx347_write_reg(client,
1209 IMX347_LF_EXPO_REG_L,
1210 IMX347_REG_VALUE_08BIT,
1211 IMX347_FETCH_EXP_L(shr0));
1212 ret |= imx347_write_reg(client,
1213 IMX347_LF_EXPO_REG_M,
1214 IMX347_REG_VALUE_08BIT,
1215 IMX347_FETCH_EXP_M(shr0));
1216 ret |= imx347_write_reg(client,
1217 IMX347_LF_EXPO_REG_H,
1218 IMX347_REG_VALUE_08BIT,
1219 IMX347_FETCH_EXP_H(shr0));
1220 ret |= imx347_write_reg(client,
1221 IMX347_GROUP_HOLD_REG,
1222 IMX347_REG_VALUE_08BIT,
1223 IMX347_GROUP_HOLD_END);
1224 return ret;
1225 }
1226
imx347_set_conversion_gain(struct imx347 * imx347,u32 * cg)1227 static int imx347_set_conversion_gain(struct imx347 *imx347, u32 *cg)
1228 {
1229 int ret = 0;
1230 struct i2c_client *client = imx347->client;
1231 int cur_cg = *cg;
1232 u32 gain_switch = 0;
1233
1234 if (g_isHCG && cur_cg == GAIN_MODE_LCG) {
1235 gain_switch = 0x00 | 0x100;
1236 g_isHCG = false;
1237 } else if (!g_isHCG && cur_cg == GAIN_MODE_HCG) {
1238 gain_switch = 0x01 | 0x100;
1239 g_isHCG = true;
1240 }
1241 ret = imx347_write_reg(client,
1242 IMX347_GROUP_HOLD_REG,
1243 IMX347_REG_VALUE_08BIT,
1244 IMX347_GROUP_HOLD_START);
1245 if (gain_switch & 0x100)
1246 ret |= imx347_write_reg(client,
1247 IMX347_GAIN_SWITCH_REG,
1248 IMX347_REG_VALUE_08BIT,
1249 gain_switch & 0xff);
1250 ret |= imx347_write_reg(client,
1251 IMX347_GROUP_HOLD_REG,
1252 IMX347_REG_VALUE_08BIT,
1253 IMX347_GROUP_HOLD_END);
1254 return ret;
1255 }
1256
1257 #ifdef USED_SYS_DEBUG
1258 //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0037/cam_s_cg
set_conversion_gain_status(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1259 static ssize_t set_conversion_gain_status(struct device *dev,
1260 struct device_attribute *attr,
1261 const char *buf,
1262 size_t count)
1263 {
1264 struct i2c_client *client = to_i2c_client(dev);
1265 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1266 struct imx347 *imx347 = to_imx347(sd);
1267 int status = 0;
1268 int ret = 0;
1269
1270 ret = kstrtoint(buf, 0, &status);
1271 if (!ret && status >= 0 && status < 2)
1272 imx347_set_conversion_gain(imx347, &status);
1273 else
1274 dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
1275 return count;
1276 }
1277
1278 static struct device_attribute attributes[] = {
1279 __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
1280 };
1281
add_sysfs_interfaces(struct device * dev)1282 static int add_sysfs_interfaces(struct device *dev)
1283 {
1284 int i;
1285
1286 for (i = 0; i < ARRAY_SIZE(attributes); i++)
1287 if (device_create_file(dev, attributes + i))
1288 goto undo;
1289 return 0;
1290 undo:
1291 for (i--; i >= 0 ; i--)
1292 device_remove_file(dev, attributes + i);
1293 dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
1294 return -ENODEV;
1295 }
1296 #endif
1297
imx347_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1298 static long imx347_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1299 {
1300 struct imx347 *imx347 = to_imx347(sd);
1301 struct rkmodule_hdr_cfg *hdr;
1302 u32 i, h, w, stream;
1303 long ret = 0;
1304
1305 switch (cmd) {
1306 case PREISP_CMD_SET_HDRAE_EXP:
1307 ret = imx347_set_hdrae(imx347, arg);
1308 break;
1309 case RKMODULE_GET_MODULE_INFO:
1310 imx347_get_module_inf(imx347, (struct rkmodule_inf *)arg);
1311 break;
1312 case RKMODULE_GET_HDR_CFG:
1313 hdr = (struct rkmodule_hdr_cfg *)arg;
1314 hdr->esp.mode = HDR_NORMAL_VC;
1315 hdr->hdr_mode = imx347->cur_mode->hdr_mode;
1316 break;
1317 case RKMODULE_SET_HDR_CFG:
1318 hdr = (struct rkmodule_hdr_cfg *)arg;
1319 w = imx347->cur_mode->width;
1320 h = imx347->cur_mode->height;
1321 for (i = 0; i < imx347->cfg_num; i++) {
1322 if (w == supported_modes[i].width &&
1323 h == supported_modes[i].height &&
1324 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1325 imx347->cur_mode = &supported_modes[i];
1326 break;
1327 }
1328 }
1329 if (i == imx347->cfg_num) {
1330 dev_err(&imx347->client->dev,
1331 "not find hdr mode:%d %dx%d config\n",
1332 hdr->hdr_mode, w, h);
1333 ret = -EINVAL;
1334 } else {
1335 w = imx347->cur_mode->hts_def - imx347->cur_mode->width;
1336 h = imx347->cur_mode->vts_def - imx347->cur_mode->height;
1337 __v4l2_ctrl_modify_range(imx347->hblank, w, w, 1, w);
1338 __v4l2_ctrl_modify_range(imx347->vblank, h,
1339 IMX347_VTS_MAX - imx347->cur_mode->height,
1340 1, h);
1341 imx347->cur_vts = imx347->cur_mode->vts_def;
1342 if (imx347->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10) {
1343 if (imx347->cur_mode->hdr_mode == NO_HDR)
1344 imx347->cur_pixel_rate = IMX347_10BIT_LINEAR_PIXEL_RATE;
1345 else if (imx347->cur_mode->hdr_mode == HDR_X2)
1346 imx347->cur_pixel_rate = IMX347_10BIT_HDR2_PIXEL_RATE;
1347 __v4l2_ctrl_s_ctrl_int64(imx347->pixel_rate,
1348 imx347->cur_pixel_rate);
1349 }
1350 }
1351 break;
1352 case RKMODULE_SET_CONVERSION_GAIN:
1353 ret = imx347_set_conversion_gain(imx347, (u32 *)arg);
1354 break;
1355 case RKMODULE_SET_QUICK_STREAM:
1356
1357 stream = *((u32 *)arg);
1358
1359 if (stream)
1360 ret = imx347_write_reg(imx347->client, IMX347_REG_CTRL_MODE,
1361 IMX347_REG_VALUE_08BIT, IMX347_MODE_STREAMING);
1362 else
1363 ret = imx347_write_reg(imx347->client, IMX347_REG_CTRL_MODE,
1364 IMX347_REG_VALUE_08BIT, IMX347_MODE_SW_STANDBY);
1365 break;
1366 default:
1367 ret = -ENOIOCTLCMD;
1368 break;
1369 }
1370
1371 return ret;
1372 }
1373
1374 #ifdef CONFIG_COMPAT
imx347_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1375 static long imx347_compat_ioctl32(struct v4l2_subdev *sd,
1376 unsigned int cmd, unsigned long arg)
1377 {
1378 void __user *up = compat_ptr(arg);
1379 struct rkmodule_inf *inf;
1380 struct rkmodule_hdr_cfg *hdr;
1381 struct preisp_hdrae_exp_s *hdrae;
1382 long ret;
1383 u32 cg = 0;
1384 u32 stream;
1385
1386 switch (cmd) {
1387 case RKMODULE_GET_MODULE_INFO:
1388 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1389 if (!inf) {
1390 ret = -ENOMEM;
1391 return ret;
1392 }
1393
1394 ret = imx347_ioctl(sd, cmd, inf);
1395 if (!ret) {
1396 ret = copy_to_user(up, inf, sizeof(*inf));
1397 if (ret)
1398 ret = -EFAULT;
1399 }
1400 kfree(inf);
1401 break;
1402 case RKMODULE_GET_HDR_CFG:
1403 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1404 if (!hdr) {
1405 ret = -ENOMEM;
1406 return ret;
1407 }
1408
1409 ret = imx347_ioctl(sd, cmd, hdr);
1410 if (!ret) {
1411 ret = copy_to_user(up, hdr, sizeof(*hdr));
1412 if (ret)
1413 ret = -EFAULT;
1414 }
1415 kfree(hdr);
1416 break;
1417 case RKMODULE_SET_HDR_CFG:
1418 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1419 if (!hdr) {
1420 ret = -ENOMEM;
1421 return ret;
1422 }
1423
1424 if (copy_from_user(hdr, up, sizeof(*hdr))) {
1425 kfree(hdr);
1426 return -EFAULT;
1427 }
1428
1429 ret = imx347_ioctl(sd, cmd, hdr);
1430 kfree(hdr);
1431 break;
1432 case PREISP_CMD_SET_HDRAE_EXP:
1433 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1434 if (!hdrae) {
1435 ret = -ENOMEM;
1436 return ret;
1437 }
1438
1439 if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
1440 kfree(hdrae);
1441 return -EFAULT;
1442 }
1443
1444 ret = imx347_ioctl(sd, cmd, hdrae);
1445 kfree(hdrae);
1446 break;
1447 case RKMODULE_SET_CONVERSION_GAIN:
1448 if (copy_from_user(&cg, up, sizeof(cg)))
1449 return -EFAULT;
1450
1451 ret = imx347_ioctl(sd, cmd, &cg);
1452 break;
1453 case RKMODULE_SET_QUICK_STREAM:
1454 if (copy_from_user(&stream, up, sizeof(u32)))
1455 return -EFAULT;
1456
1457 ret = imx347_ioctl(sd, cmd, &stream);
1458 break;
1459 default:
1460 ret = -ENOIOCTLCMD;
1461 break;
1462 }
1463
1464 return ret;
1465 }
1466 #endif
1467
imx347_init_conversion_gain(struct imx347 * imx347)1468 static int imx347_init_conversion_gain(struct imx347 *imx347)
1469 {
1470 int ret = 0;
1471 struct i2c_client *client = imx347->client;
1472
1473 ret = imx347_write_reg(client, IMX347_GAIN_SWITCH_REG,
1474 IMX347_REG_VALUE_08BIT, 0x00);
1475 if (!ret)
1476 g_isHCG = false;
1477 return ret;
1478 }
1479
__imx347_start_stream(struct imx347 * imx347)1480 static int __imx347_start_stream(struct imx347 *imx347)
1481 {
1482 int ret;
1483
1484 ret = imx347_write_array(imx347->client, imx347->cur_mode->reg_list);
1485 if (ret)
1486 return ret;
1487 ret = imx347_init_conversion_gain(imx347);
1488 if (ret)
1489 return ret;
1490 /* In case these controls are set before streaming */
1491 ret = __v4l2_ctrl_handler_setup(&imx347->ctrl_handler);
1492 if (ret)
1493 return ret;
1494 if (imx347->has_init_exp && imx347->cur_mode->hdr_mode != NO_HDR) {
1495 ret = imx347_ioctl(&imx347->subdev, PREISP_CMD_SET_HDRAE_EXP,
1496 &imx347->init_hdrae_exp);
1497 if (ret) {
1498 dev_err(&imx347->client->dev,
1499 "init exp fail in hdr mode\n");
1500 return ret;
1501 }
1502 }
1503
1504 ret = imx347_write_reg(imx347->client, IMX347_REG_CTRL_MODE,
1505 IMX347_REG_VALUE_08BIT, IMX347_MODE_STREAMING);
1506 ret |= imx347_write_reg(imx347->client, IMX347_REG_MASTER_MODE,
1507 IMX347_REG_VALUE_08BIT, IMX347_MASTER_MODE_START);
1508 return ret;
1509 }
1510
__imx347_stop_stream(struct imx347 * imx347)1511 static int __imx347_stop_stream(struct imx347 *imx347)
1512 {
1513 int ret = 0;
1514 u32 value = 0;
1515
1516 imx347->has_init_exp = false;
1517 ret = imx347_write_reg(imx347->client, IMX347_REG_CTRL_MODE,
1518 IMX347_REG_VALUE_08BIT, IMX347_MODE_SW_STANDBY);
1519 ret |= imx347_write_reg(imx347->client, IMX347_REG_MASTER_MODE,
1520 IMX347_REG_VALUE_08BIT, IMX347_MASTER_MODE_STOP);
1521
1522 ret |= imx347_read_reg(imx347->client, IMX347_REG_RESTART_MODE,
1523 IMX347_REG_VALUE_08BIT, &value);
1524 dev_dbg(&imx347->client->dev, "reg 0x3004 = 0x%x\n", value);
1525 if (value == 0x00) {
1526 ret |= imx347_write_reg(imx347->client, IMX347_REG_RESTART_MODE,
1527 IMX347_REG_VALUE_08BIT, IMX347_RESTART_MODE_START);
1528 ret |= imx347_write_reg(imx347->client, IMX347_REG_RESTART_MODE,
1529 IMX347_REG_VALUE_08BIT, IMX347_RESTART_MODE_STOP);
1530 }
1531
1532 return ret;
1533 }
1534
imx347_s_stream(struct v4l2_subdev * sd,int on)1535 static int imx347_s_stream(struct v4l2_subdev *sd, int on)
1536 {
1537 struct imx347 *imx347 = to_imx347(sd);
1538 struct i2c_client *client = imx347->client;
1539 int ret = 0;
1540
1541 dev_dbg(&imx347->client->dev, "s_stream: %d. %dx%d, hdr: %d, bpp: %d\n",
1542 on, imx347->cur_mode->width, imx347->cur_mode->height,
1543 imx347->cur_mode->hdr_mode, imx347->cur_mode->bpp);
1544
1545 mutex_lock(&imx347->mutex);
1546 on = !!on;
1547 if (on == imx347->streaming)
1548 goto unlock_and_return;
1549
1550 if (on) {
1551 ret = pm_runtime_get_sync(&client->dev);
1552 if (ret < 0) {
1553 pm_runtime_put_noidle(&client->dev);
1554 goto unlock_and_return;
1555 }
1556
1557 ret = __imx347_start_stream(imx347);
1558 if (ret) {
1559 v4l2_err(sd, "start stream failed while write regs\n");
1560 pm_runtime_put(&client->dev);
1561 goto unlock_and_return;
1562 }
1563 } else {
1564 __imx347_stop_stream(imx347);
1565 pm_runtime_put(&client->dev);
1566 }
1567
1568 imx347->streaming = on;
1569
1570 unlock_and_return:
1571 mutex_unlock(&imx347->mutex);
1572
1573 return ret;
1574 }
1575
imx347_s_power(struct v4l2_subdev * sd,int on)1576 static int imx347_s_power(struct v4l2_subdev *sd, int on)
1577 {
1578 struct imx347 *imx347 = to_imx347(sd);
1579 struct i2c_client *client = imx347->client;
1580 int ret = 0;
1581
1582 mutex_lock(&imx347->mutex);
1583
1584 /* If the power state is not modified - no work to do. */
1585 if (imx347->power_on == !!on)
1586 goto unlock_and_return;
1587
1588 if (on) {
1589 ret = pm_runtime_get_sync(&client->dev);
1590 if (ret < 0) {
1591 pm_runtime_put_noidle(&client->dev);
1592 goto unlock_and_return;
1593 }
1594
1595 ret = imx347_write_array(imx347->client, imx347_global_regs);
1596 if (ret) {
1597 v4l2_err(sd, "could not set init registers\n");
1598 pm_runtime_put_noidle(&client->dev);
1599 goto unlock_and_return;
1600 }
1601
1602 imx347->power_on = true;
1603 } else {
1604 pm_runtime_put(&client->dev);
1605 imx347->power_on = false;
1606 }
1607
1608 unlock_and_return:
1609 mutex_unlock(&imx347->mutex);
1610
1611 return ret;
1612 }
1613
1614 /* Calculate the delay in us by clock rate and clock cycles */
imx347_cal_delay(u32 cycles)1615 static inline u32 imx347_cal_delay(u32 cycles)
1616 {
1617 return DIV_ROUND_UP(cycles, IMX347_XVCLK_FREQ_37M / 1000 / 1000);
1618 }
1619
__imx347_power_on(struct imx347 * imx347)1620 static int __imx347_power_on(struct imx347 *imx347)
1621 {
1622 int ret;
1623 u32 delay_us;
1624 struct device *dev = &imx347->client->dev;
1625 unsigned long mclk = 0;
1626
1627 if (!IS_ERR_OR_NULL(imx347->pins_default)) {
1628 ret = pinctrl_select_state(imx347->pinctrl,
1629 imx347->pins_default);
1630 if (ret < 0)
1631 dev_err(dev, "could not set pins\n");
1632 }
1633 if (imx347->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10)
1634 mclk = IMX347_XVCLK_FREQ_37M;
1635 else
1636 mclk = IMX347_XVCLK_FREQ_24M;
1637 ret = clk_set_rate(imx347->xvclk, mclk);
1638 if (ret < 0)
1639 dev_warn(dev, "Failed to set xvclk rate\n");
1640 if (clk_get_rate(imx347->xvclk) != mclk)
1641 dev_warn(dev, "xvclk mismatched\n");
1642 ret = clk_prepare_enable(imx347->xvclk);
1643 if (ret < 0) {
1644 dev_err(dev, "Failed to enable xvclk\n");
1645 return ret;
1646 }
1647 if (!IS_ERR(imx347->reset_gpio))
1648 gpiod_set_value_cansleep(imx347->reset_gpio, 0);
1649
1650 ret = regulator_bulk_enable(IMX347_NUM_SUPPLIES, imx347->supplies);
1651 if (ret < 0) {
1652 dev_err(dev, "Failed to enable regulators\n");
1653 goto disable_clk;
1654 }
1655
1656 if (!IS_ERR(imx347->reset_gpio))
1657 gpiod_set_value_cansleep(imx347->reset_gpio, 1);
1658
1659 usleep_range(500, 1000);
1660 if (!IS_ERR(imx347->pwdn_gpio))
1661 gpiod_set_value_cansleep(imx347->pwdn_gpio, 1);
1662
1663 /* 8192 cycles prior to first SCCB transaction */
1664 delay_us = imx347_cal_delay(8192);
1665 usleep_range(delay_us, delay_us * 2);
1666
1667 return 0;
1668
1669 disable_clk:
1670 clk_disable_unprepare(imx347->xvclk);
1671
1672 return ret;
1673 }
1674
__imx347_power_off(struct imx347 * imx347)1675 static void __imx347_power_off(struct imx347 *imx347)
1676 {
1677 int ret;
1678 struct device *dev = &imx347->client->dev;
1679
1680 if (!IS_ERR(imx347->pwdn_gpio))
1681 gpiod_set_value_cansleep(imx347->pwdn_gpio, 0);
1682 clk_disable_unprepare(imx347->xvclk);
1683 if (!IS_ERR(imx347->reset_gpio))
1684 gpiod_set_value_cansleep(imx347->reset_gpio, 0);
1685 if (!IS_ERR_OR_NULL(imx347->pins_sleep)) {
1686 ret = pinctrl_select_state(imx347->pinctrl,
1687 imx347->pins_sleep);
1688 if (ret < 0)
1689 dev_dbg(dev, "could not set pins\n");
1690 }
1691 regulator_bulk_disable(IMX347_NUM_SUPPLIES, imx347->supplies);
1692 }
1693
imx347_runtime_resume(struct device * dev)1694 static int imx347_runtime_resume(struct device *dev)
1695 {
1696 struct i2c_client *client = to_i2c_client(dev);
1697 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1698 struct imx347 *imx347 = to_imx347(sd);
1699
1700 return __imx347_power_on(imx347);
1701 }
1702
imx347_runtime_suspend(struct device * dev)1703 static int imx347_runtime_suspend(struct device *dev)
1704 {
1705 struct i2c_client *client = to_i2c_client(dev);
1706 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1707 struct imx347 *imx347 = to_imx347(sd);
1708
1709 __imx347_power_off(imx347);
1710
1711 return 0;
1712 }
1713
1714 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx347_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1715 static int imx347_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1716 {
1717 struct imx347 *imx347 = to_imx347(sd);
1718 struct v4l2_mbus_framefmt *try_fmt =
1719 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1720 const struct imx347_mode *def_mode = &supported_modes[0];
1721
1722 mutex_lock(&imx347->mutex);
1723 /* Initialize try_fmt */
1724 try_fmt->width = def_mode->width;
1725 try_fmt->height = def_mode->height;
1726 try_fmt->code = def_mode->bus_fmt;
1727 try_fmt->field = V4L2_FIELD_NONE;
1728
1729 mutex_unlock(&imx347->mutex);
1730 /* No crop or compose */
1731
1732 return 0;
1733 }
1734 #endif
1735
imx347_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1736 static int imx347_enum_frame_interval(struct v4l2_subdev *sd,
1737 struct v4l2_subdev_pad_config *cfg,
1738 struct v4l2_subdev_frame_interval_enum *fie)
1739 {
1740 struct imx347 *imx347 = to_imx347(sd);
1741
1742 if (fie->index >= imx347->cfg_num)
1743 return -EINVAL;
1744
1745 fie->code = supported_modes[fie->index].bus_fmt;
1746 fie->width = supported_modes[fie->index].width;
1747 fie->height = supported_modes[fie->index].height;
1748 fie->interval = supported_modes[fie->index].max_fps;
1749 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1750 return 0;
1751 }
1752
1753 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1754 #define DST_WIDTH 2688
1755 #define DST_HEIGHT 1520
1756
1757 /*
1758 * The resolution of the driver configuration needs to be exactly
1759 * the same as the current output resolution of the sensor,
1760 * the input width of the isp needs to be 16 aligned,
1761 * the input height of the isp needs to be 8 aligned.
1762 * Can be cropped to standard resolution by this function,
1763 * otherwise it will crop out strange resolution according
1764 * to the alignment rules.
1765 */
imx347_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1766 static int imx347_get_selection(struct v4l2_subdev *sd,
1767 struct v4l2_subdev_pad_config *cfg,
1768 struct v4l2_subdev_selection *sel)
1769 {
1770 struct imx347 *imx347 = to_imx347(sd);
1771
1772 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1773 sel->r.left = CROP_START(imx347->cur_mode->width, DST_WIDTH);
1774 sel->r.width = DST_WIDTH;
1775 sel->r.top = CROP_START(imx347->cur_mode->height, DST_HEIGHT);
1776 sel->r.height = DST_HEIGHT;
1777 return 0;
1778 }
1779 return -EINVAL;
1780 }
1781
1782 static const struct dev_pm_ops imx347_pm_ops = {
1783 SET_RUNTIME_PM_OPS(imx347_runtime_suspend,
1784 imx347_runtime_resume, NULL)
1785 };
1786
1787 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1788 static const struct v4l2_subdev_internal_ops imx347_internal_ops = {
1789 .open = imx347_open,
1790 };
1791 #endif
1792
1793 static const struct v4l2_subdev_core_ops imx347_core_ops = {
1794 .s_power = imx347_s_power,
1795 .ioctl = imx347_ioctl,
1796 #ifdef CONFIG_COMPAT
1797 .compat_ioctl32 = imx347_compat_ioctl32,
1798 #endif
1799 };
1800
1801 static const struct v4l2_subdev_video_ops imx347_video_ops = {
1802 .s_stream = imx347_s_stream,
1803 .g_frame_interval = imx347_g_frame_interval,
1804 };
1805
1806 static const struct v4l2_subdev_pad_ops imx347_pad_ops = {
1807 .enum_mbus_code = imx347_enum_mbus_code,
1808 .enum_frame_size = imx347_enum_frame_sizes,
1809 .enum_frame_interval = imx347_enum_frame_interval,
1810 .get_fmt = imx347_get_fmt,
1811 .set_fmt = imx347_set_fmt,
1812 .get_selection = imx347_get_selection,
1813 .get_mbus_config = imx347_g_mbus_config,
1814 };
1815
1816 static const struct v4l2_subdev_ops imx347_subdev_ops = {
1817 .core = &imx347_core_ops,
1818 .video = &imx347_video_ops,
1819 .pad = &imx347_pad_ops,
1820 };
1821
imx347_set_ctrl(struct v4l2_ctrl * ctrl)1822 static int imx347_set_ctrl(struct v4l2_ctrl *ctrl)
1823 {
1824 struct imx347 *imx347 = container_of(ctrl->handler,
1825 struct imx347, ctrl_handler);
1826 struct i2c_client *client = imx347->client;
1827 const struct imx347_mode *mode = imx347->cur_mode;
1828 s64 max;
1829 u32 vts = 0;
1830 int ret = 0;
1831 u32 shr0 = 0;
1832 u32 flip = 0;
1833
1834 /* Propagate change of current control to all related controls */
1835 switch (ctrl->id) {
1836 case V4L2_CID_VBLANK:
1837 /* Update max exposure while meeting expected vblanking */
1838 if (mode->hdr_mode == NO_HDR) {
1839 max = imx347->cur_mode->height + ctrl->val - 3;
1840 __v4l2_ctrl_modify_range(imx347->exposure,
1841 imx347->exposure->minimum, max,
1842 imx347->exposure->step,
1843 imx347->exposure->default_value);
1844 }
1845 break;
1846 }
1847
1848 if (!pm_runtime_get_if_in_use(&client->dev))
1849 return 0;
1850
1851 switch (ctrl->id) {
1852 case V4L2_CID_EXPOSURE:
1853 if (mode->hdr_mode == NO_HDR) {
1854 shr0 = imx347->cur_vts - ctrl->val;
1855 ret = imx347_write_reg(imx347->client, IMX347_LF_EXPO_REG_L,
1856 IMX347_REG_VALUE_08BIT,
1857 IMX347_FETCH_EXP_L(shr0));
1858 ret |= imx347_write_reg(imx347->client, IMX347_LF_EXPO_REG_M,
1859 IMX347_REG_VALUE_08BIT,
1860 IMX347_FETCH_EXP_M(shr0));
1861 ret |= imx347_write_reg(imx347->client, IMX347_LF_EXPO_REG_H,
1862 IMX347_REG_VALUE_08BIT,
1863 IMX347_FETCH_EXP_H(shr0));
1864 dev_dbg(&client->dev, "set exposure 0x%x\n",
1865 ctrl->val);
1866 }
1867 break;
1868 case V4L2_CID_ANALOGUE_GAIN:
1869 if (mode->hdr_mode == NO_HDR) {
1870 ret = imx347_write_reg(imx347->client, IMX347_LF_GAIN_REG_H,
1871 IMX347_REG_VALUE_08BIT,
1872 IMX347_FETCH_GAIN_H(ctrl->val));
1873 ret |= imx347_write_reg(imx347->client, IMX347_LF_GAIN_REG_L,
1874 IMX347_REG_VALUE_08BIT,
1875 IMX347_FETCH_GAIN_L(ctrl->val));
1876 dev_dbg(&client->dev, "set analog gain 0x%x\n",
1877 ctrl->val);
1878 }
1879 break;
1880 case V4L2_CID_VBLANK:
1881 vts = ctrl->val + imx347->cur_mode->height;
1882 imx347->cur_vts = vts;
1883 if (imx347->cur_mode->hdr_mode == HDR_X2)
1884 vts /= 2;
1885 ret = imx347_write_reg(imx347->client, IMX347_VTS_REG_L,
1886 IMX347_REG_VALUE_08BIT,
1887 IMX347_FETCH_VTS_L(vts));
1888 ret |= imx347_write_reg(imx347->client, IMX347_VTS_REG_M,
1889 IMX347_REG_VALUE_08BIT,
1890 IMX347_FETCH_VTS_M(vts));
1891 ret |= imx347_write_reg(imx347->client, IMX347_VTS_REG_H,
1892 IMX347_REG_VALUE_08BIT,
1893 IMX347_FETCH_VTS_H(vts));
1894
1895 dev_dbg(&client->dev, "set vblank 0x%x\n",
1896 ctrl->val);
1897 break;
1898 case V4L2_CID_HFLIP:
1899 ret = imx347_write_reg(imx347->client, IMX347_HREVERSE_REG,
1900 IMX347_REG_VALUE_08BIT, !!ctrl->val);
1901 break;
1902 case V4L2_CID_VFLIP:
1903 flip = ctrl->val;
1904 ret = imx347_write_reg(imx347->client, IMX347_VREVERSE_REG,
1905 IMX347_REG_VALUE_08BIT, !!flip);
1906 if (flip) {
1907 ret |= imx347_write_reg(imx347->client, 0x3074,
1908 IMX347_REG_VALUE_08BIT, 0x40);
1909 ret |= imx347_write_reg(imx347->client, 0x3075,
1910 IMX347_REG_VALUE_08BIT, 0x06);
1911 ret |= imx347_write_reg(imx347->client, 0x3080,
1912 IMX347_REG_VALUE_08BIT, 0xff);
1913 ret |= imx347_write_reg(imx347->client, 0x30ad,
1914 IMX347_REG_VALUE_08BIT, 0x7e);
1915 ret |= imx347_write_reg(imx347->client, 0x30b6,
1916 IMX347_REG_VALUE_08BIT, 0xff);
1917 ret |= imx347_write_reg(imx347->client, 0x30b7,
1918 IMX347_REG_VALUE_08BIT, 0x01);
1919 ret |= imx347_write_reg(imx347->client, 0x30d8,
1920 IMX347_REG_VALUE_08BIT, 0x45);
1921 ret |= imx347_write_reg(imx347->client, 0x3114,
1922 IMX347_REG_VALUE_08BIT, 0x01);
1923 } else {
1924 ret |= imx347_write_reg(imx347->client, 0x3074,
1925 IMX347_REG_VALUE_08BIT, 0x3c);
1926 ret |= imx347_write_reg(imx347->client, 0x3075,
1927 IMX347_REG_VALUE_08BIT, 0x00);
1928 ret |= imx347_write_reg(imx347->client, 0x3080,
1929 IMX347_REG_VALUE_08BIT, 0x01);
1930 ret |= imx347_write_reg(imx347->client, 0x30ad,
1931 IMX347_REG_VALUE_08BIT, 0x02);
1932 ret |= imx347_write_reg(imx347->client, 0x30b6,
1933 IMX347_REG_VALUE_08BIT, 0x00);
1934 ret |= imx347_write_reg(imx347->client, 0x30b7,
1935 IMX347_REG_VALUE_08BIT, 0x00);
1936 ret |= imx347_write_reg(imx347->client, 0x30d8,
1937 IMX347_REG_VALUE_08BIT, 0x44);
1938 ret |= imx347_write_reg(imx347->client, 0x3114,
1939 IMX347_REG_VALUE_08BIT, 0x02);
1940 }
1941 break;
1942 default:
1943 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1944 __func__, ctrl->id, ctrl->val);
1945 break;
1946 }
1947
1948 pm_runtime_put(&client->dev);
1949
1950 return ret;
1951 }
1952
1953 static const struct v4l2_ctrl_ops imx347_ctrl_ops = {
1954 .s_ctrl = imx347_set_ctrl,
1955 };
1956
imx347_initialize_controls(struct imx347 * imx347)1957 static int imx347_initialize_controls(struct imx347 *imx347)
1958 {
1959 const struct imx347_mode *mode;
1960 struct v4l2_ctrl_handler *handler;
1961 s64 exposure_max, vblank_def;
1962 u32 h_blank;
1963 int ret;
1964
1965 handler = &imx347->ctrl_handler;
1966 mode = imx347->cur_mode;
1967 ret = v4l2_ctrl_handler_init(handler, 8);
1968 if (ret)
1969 return ret;
1970 handler->lock = &imx347->mutex;
1971
1972 imx347->link_freq = v4l2_ctrl_new_int_menu(handler,
1973 NULL, V4L2_CID_LINK_FREQ,
1974 1, 0, link_freq_menu_items);
1975 if (imx347->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10) {
1976 imx347->cur_link_freq = 1;
1977 if (imx347->cur_mode->hdr_mode == NO_HDR)
1978 imx347->cur_pixel_rate =
1979 IMX347_10BIT_LINEAR_PIXEL_RATE;
1980 else if (imx347->cur_mode->hdr_mode == HDR_X2)
1981 imx347->cur_pixel_rate =
1982 IMX347_10BIT_HDR2_PIXEL_RATE;
1983 } else {
1984 imx347->cur_link_freq = 0;
1985 imx347->cur_pixel_rate =
1986 IMX347_12BIT_PIXEL_RATE;
1987 }
1988 __v4l2_ctrl_s_ctrl(imx347->link_freq,
1989 imx347->cur_link_freq);
1990 imx347->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1991 V4L2_CID_PIXEL_RATE, 0, IMX347_10BIT_HDR2_PIXEL_RATE,
1992 1, imx347->cur_pixel_rate);
1993
1994 h_blank = mode->hts_def - mode->width;
1995 imx347->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1996 h_blank, h_blank, 1, h_blank);
1997 if (imx347->hblank)
1998 imx347->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1999
2000 vblank_def = mode->vts_def - mode->height;
2001 imx347->vblank = v4l2_ctrl_new_std(handler, &imx347_ctrl_ops,
2002 V4L2_CID_VBLANK, vblank_def,
2003 IMX347_VTS_MAX - mode->height,
2004 1, vblank_def);
2005 imx347->cur_vts = mode->vts_def;
2006
2007 exposure_max = mode->vts_def - 3;
2008 imx347->exposure = v4l2_ctrl_new_std(handler, &imx347_ctrl_ops,
2009 V4L2_CID_EXPOSURE, IMX347_EXPOSURE_MIN,
2010 exposure_max, IMX347_EXPOSURE_STEP,
2011 mode->exp_def);
2012
2013 imx347->anal_a_gain = v4l2_ctrl_new_std(handler, &imx347_ctrl_ops,
2014 V4L2_CID_ANALOGUE_GAIN, IMX347_GAIN_MIN,
2015 IMX347_GAIN_MAX, IMX347_GAIN_STEP,
2016 IMX347_GAIN_DEFAULT);
2017 v4l2_ctrl_new_std(handler, &imx347_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
2018 v4l2_ctrl_new_std(handler, &imx347_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
2019
2020 if (handler->error) {
2021 ret = handler->error;
2022 dev_err(&imx347->client->dev,
2023 "Failed to init controls(%d)\n", ret);
2024 goto err_free_handler;
2025 }
2026
2027 imx347->subdev.ctrl_handler = handler;
2028 imx347->has_init_exp = false;
2029
2030 return 0;
2031
2032 err_free_handler:
2033 v4l2_ctrl_handler_free(handler);
2034
2035 return ret;
2036 }
2037
imx347_check_sensor_id(struct imx347 * imx347,struct i2c_client * client)2038 static int imx347_check_sensor_id(struct imx347 *imx347,
2039 struct i2c_client *client)
2040 {
2041 struct device *dev = &imx347->client->dev;
2042 u32 id = 0;
2043 int ret;
2044
2045 ret = imx347_read_reg(client, IMX347_REG_CHIP_ID,
2046 IMX347_REG_VALUE_08BIT, &id);
2047 if (id != CHIP_ID) {
2048 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
2049 return -ENODEV;
2050 }
2051
2052 dev_info(dev, "Detected imx347 id %06x\n", CHIP_ID);
2053
2054 return 0;
2055 }
2056
imx347_configure_regulators(struct imx347 * imx347)2057 static int imx347_configure_regulators(struct imx347 *imx347)
2058 {
2059 unsigned int i;
2060
2061 for (i = 0; i < IMX347_NUM_SUPPLIES; i++)
2062 imx347->supplies[i].supply = imx347_supply_names[i];
2063
2064 return devm_regulator_bulk_get(&imx347->client->dev,
2065 IMX347_NUM_SUPPLIES,
2066 imx347->supplies);
2067 }
2068
imx347_probe(struct i2c_client * client,const struct i2c_device_id * id)2069 static int imx347_probe(struct i2c_client *client,
2070 const struct i2c_device_id *id)
2071 {
2072 struct device *dev = &client->dev;
2073 struct device_node *node = dev->of_node;
2074 struct imx347 *imx347;
2075 struct v4l2_subdev *sd;
2076 char facing[2];
2077 int ret;
2078 u32 i, hdr_mode = 0;
2079
2080 dev_info(dev, "driver version: %02x.%02x.%02x",
2081 DRIVER_VERSION >> 16,
2082 (DRIVER_VERSION & 0xff00) >> 8,
2083 DRIVER_VERSION & 0x00ff);
2084
2085 imx347 = devm_kzalloc(dev, sizeof(*imx347), GFP_KERNEL);
2086 if (!imx347)
2087 return -ENOMEM;
2088
2089 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2090 &imx347->module_index);
2091 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2092 &imx347->module_facing);
2093 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2094 &imx347->module_name);
2095 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2096 &imx347->len_name);
2097 if (ret) {
2098 dev_err(dev, "could not get module information!\n");
2099 return -EINVAL;
2100 }
2101
2102 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
2103 &hdr_mode);
2104 if (ret) {
2105 hdr_mode = NO_HDR;
2106 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
2107 }
2108 imx347->client = client;
2109 imx347->cfg_num = ARRAY_SIZE(supported_modes);
2110 for (i = 0; i < imx347->cfg_num; i++) {
2111 if (hdr_mode == supported_modes[i].hdr_mode) {
2112 imx347->cur_mode = &supported_modes[i];
2113 break;
2114 }
2115 }
2116
2117 imx347->xvclk = devm_clk_get(dev, "xvclk");
2118 if (IS_ERR(imx347->xvclk)) {
2119 dev_err(dev, "Failed to get xvclk\n");
2120 return -EINVAL;
2121 }
2122
2123 imx347->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2124 if (IS_ERR(imx347->reset_gpio))
2125 dev_warn(dev, "Failed to get reset-gpios\n");
2126
2127 imx347->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
2128 if (IS_ERR(imx347->pwdn_gpio))
2129 dev_warn(dev, "Failed to get pwdn-gpios\n");
2130
2131 imx347->pinctrl = devm_pinctrl_get(dev);
2132 if (!IS_ERR(imx347->pinctrl)) {
2133 imx347->pins_default =
2134 pinctrl_lookup_state(imx347->pinctrl,
2135 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2136 if (IS_ERR(imx347->pins_default))
2137 dev_err(dev, "could not get default pinstate\n");
2138
2139 imx347->pins_sleep =
2140 pinctrl_lookup_state(imx347->pinctrl,
2141 OF_CAMERA_PINCTRL_STATE_SLEEP);
2142 if (IS_ERR(imx347->pins_sleep))
2143 dev_err(dev, "could not get sleep pinstate\n");
2144 } else {
2145 dev_err(dev, "no pinctrl\n");
2146 }
2147
2148 ret = imx347_configure_regulators(imx347);
2149 if (ret) {
2150 dev_err(dev, "Failed to get power regulators\n");
2151 return ret;
2152 }
2153
2154 mutex_init(&imx347->mutex);
2155
2156 sd = &imx347->subdev;
2157 v4l2_i2c_subdev_init(sd, client, &imx347_subdev_ops);
2158 ret = imx347_initialize_controls(imx347);
2159 if (ret)
2160 goto err_destroy_mutex;
2161
2162 ret = __imx347_power_on(imx347);
2163 if (ret)
2164 goto err_free_handler;
2165
2166 ret = imx347_check_sensor_id(imx347, client);
2167 if (ret)
2168 goto err_power_off;
2169
2170 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2171 sd->internal_ops = &imx347_internal_ops;
2172 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2173 V4L2_SUBDEV_FL_HAS_EVENTS;
2174 #endif
2175 #if defined(CONFIG_MEDIA_CONTROLLER)
2176 imx347->pad.flags = MEDIA_PAD_FL_SOURCE;
2177 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2178 ret = media_entity_pads_init(&sd->entity, 1, &imx347->pad);
2179 if (ret < 0)
2180 goto err_power_off;
2181 #endif
2182
2183 memset(facing, 0, sizeof(facing));
2184 if (strcmp(imx347->module_facing, "back") == 0)
2185 facing[0] = 'b';
2186 else
2187 facing[0] = 'f';
2188
2189 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2190 imx347->module_index, facing,
2191 IMX347_NAME, dev_name(sd->dev));
2192 ret = v4l2_async_register_subdev_sensor_common(sd);
2193 if (ret) {
2194 dev_err(dev, "v4l2 async register subdev failed\n");
2195 goto err_clean_entity;
2196 }
2197
2198 pm_runtime_set_active(dev);
2199 pm_runtime_enable(dev);
2200 pm_runtime_idle(dev);
2201
2202 g_isHCG = false;
2203 #ifdef USED_SYS_DEBUG
2204 add_sysfs_interfaces(dev);
2205 #endif
2206 return 0;
2207
2208 err_clean_entity:
2209 #if defined(CONFIG_MEDIA_CONTROLLER)
2210 media_entity_cleanup(&sd->entity);
2211 #endif
2212 err_power_off:
2213 __imx347_power_off(imx347);
2214 err_free_handler:
2215 v4l2_ctrl_handler_free(&imx347->ctrl_handler);
2216 err_destroy_mutex:
2217 mutex_destroy(&imx347->mutex);
2218
2219 return ret;
2220 }
2221
imx347_remove(struct i2c_client * client)2222 static int imx347_remove(struct i2c_client *client)
2223 {
2224 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2225 struct imx347 *imx347 = to_imx347(sd);
2226
2227 v4l2_async_unregister_subdev(sd);
2228 #if defined(CONFIG_MEDIA_CONTROLLER)
2229 media_entity_cleanup(&sd->entity);
2230 #endif
2231 v4l2_ctrl_handler_free(&imx347->ctrl_handler);
2232 mutex_destroy(&imx347->mutex);
2233
2234 pm_runtime_disable(&client->dev);
2235 if (!pm_runtime_status_suspended(&client->dev))
2236 __imx347_power_off(imx347);
2237 pm_runtime_set_suspended(&client->dev);
2238
2239 return 0;
2240 }
2241
2242 #if IS_ENABLED(CONFIG_OF)
2243 static const struct of_device_id imx347_of_match[] = {
2244 { .compatible = "sony,imx347" },
2245 {},
2246 };
2247 MODULE_DEVICE_TABLE(of, imx347_of_match);
2248 #endif
2249
2250 static const struct i2c_device_id imx347_match_id[] = {
2251 { "sony,imx347", 0 },
2252 { },
2253 };
2254
2255 static struct i2c_driver imx347_i2c_driver = {
2256 .driver = {
2257 .name = IMX347_NAME,
2258 .pm = &imx347_pm_ops,
2259 .of_match_table = of_match_ptr(imx347_of_match),
2260 },
2261 .probe = &imx347_probe,
2262 .remove = &imx347_remove,
2263 .id_table = imx347_match_id,
2264 };
2265
sensor_mod_init(void)2266 static int __init sensor_mod_init(void)
2267 {
2268 return i2c_add_driver(&imx347_i2c_driver);
2269 }
2270
sensor_mod_exit(void)2271 static void __exit sensor_mod_exit(void)
2272 {
2273 i2c_del_driver(&imx347_i2c_driver);
2274 }
2275
2276 device_initcall_sync(sensor_mod_init);
2277 module_exit(sensor_mod_exit);
2278
2279 MODULE_DESCRIPTION("Sony imx347 sensor driver");
2280 MODULE_LICENSE("GPL v2");
2281