1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx334 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 * V0.0X01.0X03 add enum_frame_interval function.
7 * V0.0X01.0X04
8 * 1.add parse mclk pinctrl.
9 * 2.add set flip ctrl.
10 * V0.0X01.0X05 add quick stream on/off
11 */
12
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/sysfs.h>
22 #include <linux/slab.h>
23 #include <linux/version.h>
24 #include <linux/rk-camera-module.h>
25 #include <media/media-entity.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-subdev.h>
29 #include <media/v4l2-fwnode.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/of_graph.h>
34 #include <linux/of_platform.h>
35 #include <linux/of_gpio.h>
36 #include <linux/mfd/syscon.h>
37 #include <linux/rk-preisp.h>
38
39 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
40
41 #ifndef V4L2_CID_DIGITAL_GAIN
42 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
43 #endif
44
45 #define IMX334_LINK_FREQ_445 445500000// 891Mbps
46 #define IMX334_LINK_FREQ_594 594000000// 1188Mbps
47 #define IMX334_LINK_FREQ_891 891000000// 1782Mbps
48
49 #define IMX334_LANES 4
50
51 #define PIXEL_RATE_WITH_445M_10BIT (IMX334_LINK_FREQ_445 * 2 / 10 * 4)
52 #define PIXEL_RATE_WITH_594M_12BIT (IMX334_LINK_FREQ_594 * 2 / 12 * 4)
53 #define PIXEL_RATE_WITH_891M_10BIT (IMX334_LINK_FREQ_891 * 2 / 10 * 4)
54 #define PIXEL_RATE_WITH_891M_12BIT (IMX334_LINK_FREQ_891 * 2 / 12 * 4)
55
56 #define IMX334_XVCLK_FREQ_37 37125000
57 #define IMX334_XVCLK_FREQ_74 74250000
58
59 #define CHIP_ID 0x30
60 #define IMX334_REG_CHIP_ID 0x302c
61
62 #define IMX334_REG_CTRL_MODE 0x3000
63 #define IMX334_MODE_SW_STANDBY 0x1
64 #define IMX334_MODE_STREAMING 0x0
65
66 #define IMX334_LF_GAIN_REG_L 0x30E8
67
68 #define IMX334_SF1_GAIN_REG_L 0x30EA
69
70 #define IMX334_LF_EXPO_REG_H 0x305A
71 #define IMX334_LF_EXPO_REG_M 0x3059
72 #define IMX334_LF_EXPO_REG_L 0x3058
73
74 #define IMX334_SF1_EXPO_REG_H 0x305E
75 #define IMX334_SF1_EXPO_REG_M 0x305D
76 #define IMX334_SF1_EXPO_REG_L 0x305C
77
78 #define IMX334_RHS1_REG_H 0x306a
79 #define IMX334_RHS1_REG_M 0x3069
80 #define IMX334_RHS1_REG_L 0x3068
81
82 #define IMX334_EXPOSURE_MIN 5
83 #define IMX334_EXPOSURE_STEP 1
84 #define IMX334_VTS_MAX 0xfffff
85
86 #define IMX334_REG_GAIN 0x30e8
87 #define IMX334_GAIN_MIN 0x00
88 #define IMX334_GAIN_MAX 0xf0
89 #define IMX334_GAIN_STEP 1
90 #define IMX334_GAIN_DEFAULT 0x30
91
92 #define IMX334_REG_TEST_PATTERN 0x5e00
93 #define IMX334_TEST_PATTERN_ENABLE 0x80
94 #define IMX334_TEST_PATTERN_DISABLE 0x0
95
96 #define IMX334_REG_VTS_H 0x3032
97 #define IMX334_REG_VTS_M 0x3031
98 #define IMX334_REG_VTS_L 0x3030
99
100 #define IMX334_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0x0F)
101 #define IMX334_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF)
102 #define IMX334_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
103
104 #define IMX334_FETCH_RHS1_H(VAL) (((VAL) >> 16) & 0x0F)
105 #define IMX334_FETCH_RHS1_M(VAL) (((VAL) >> 8) & 0xFF)
106 #define IMX334_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
107
108 #define IMX334_FETCH_VTS_H(VAL) (((VAL) >> 16) & 0x0F)
109 #define IMX334_FETCH_VTS_M(VAL) (((VAL) >> 8) & 0xFF)
110 #define IMX334_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
111
112 #define IMX334_VREVERSE_REG 0x304f
113 #define IMX334_HREVERSE_REG 0x304e
114
115 #define REG_DELAY 0xFFFE
116 #define REG_NULL 0xFFFF
117
118 #define IMX334_REG_VALUE_08BIT 1
119 #define IMX334_REG_VALUE_16BIT 2
120 #define IMX334_REG_VALUE_24BIT 3
121
122 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
123 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
124 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
125
126 #define IMX334_NAME "imx334"
127
128 #define BRL 2200
129 #define RHS1_MAX 4397 // <2*BRL && 4n+1
130 #define SHR1_MIN 9
131
132 static const char * const imx334_supply_names[] = {
133 "avdd", /* Analog power */
134 "dovdd", /* Digital I/O power */
135 "dvdd", /* Digital core power */
136 };
137
138 #define IMX334_NUM_SUPPLIES ARRAY_SIZE(imx334_supply_names)
139
140 struct regval {
141 u16 addr;
142 u8 val;
143 };
144
145 struct imx334_mode {
146 u32 bus_fmt;
147 u32 width;
148 u32 height;
149 struct v4l2_fract max_fps;
150 u32 hts_def;
151 u32 vts_def;
152 u32 exp_def;
153 const struct regval *global_reg_list;
154 const struct regval *reg_list;
155 u32 hdr_mode;
156 u32 vclk_freq;
157 u32 bpp;
158 u32 mipi_freq_idx;
159 u32 vc[PAD_MAX];
160 };
161
162 struct imx334 {
163 struct i2c_client *client;
164 struct clk *xvclk;
165 struct gpio_desc *reset_gpio;
166 struct gpio_desc *pwdn_gpio;
167 struct regulator_bulk_data supplies[IMX334_NUM_SUPPLIES];
168
169 struct pinctrl *pinctrl;
170 struct pinctrl_state *pins_default;
171 struct pinctrl_state *pins_sleep;
172
173 struct v4l2_subdev subdev;
174 struct media_pad pad;
175 struct v4l2_ctrl_handler ctrl_handler;
176 struct v4l2_ctrl *exposure;
177 struct v4l2_ctrl *anal_gain;
178 struct v4l2_ctrl *digi_gain;
179 struct v4l2_ctrl *hblank;
180 struct v4l2_ctrl *vblank;
181 struct v4l2_ctrl *test_pattern;
182 struct v4l2_ctrl *pixel_rate;
183 struct v4l2_ctrl *link_freq;
184 struct mutex mutex;
185 bool streaming;
186 bool power_on;
187 const struct imx334_mode *cur_mode;
188 u32 module_index;
189 const char *module_facing;
190 const char *module_name;
191 const char *len_name;
192 u32 cur_vts;
193 bool has_init_exp;
194 struct preisp_hdrae_exp_s init_hdrae_exp;
195 u32 cur_vclk_freq;
196 u32 cur_mipi_freq_idx;
197 };
198
199 #define to_imx334(sd) container_of(sd, struct imx334, subdev)
200
201 static const struct regval imx334_10_3840x2160_global_regs[] = {
202 {0x3001, 0x00},
203 {0x3002, 0x00},
204 {0x300C, 0x5B},// BCWAIT_TIME[7:0]
205 {0x300D, 0x40},// CPWAIT_TIME[7:0]
206 {0x3050, 0x00},// ADBIT[0]
207 {0x316A, 0x7E},// INCKSEL4[1:0]
208 {0x319D, 0x00},// MDBIT
209 {0x31A1, 0x00},// XVS_DRV[1:0]
210 {0x3288, 0x21},// -
211 {0x328A, 0x02},// -
212 {0x3414, 0x05},// -
213 {0x3416, 0x18},// -
214 {0x341D, 0x01},//
215 {0x35AC, 0x0E},// -
216 {0x3648, 0x01},// -
217 {0x364A, 0x04},// -
218 {0x364C, 0x04},// -
219 {0x3678, 0x01},// -
220 {0x367C, 0x31},// -
221 {0x367E, 0x31},// -
222 {0x3708, 0x02},// -
223 {0x3714, 0x01},// -
224 {0x3715, 0x02},// -
225 {0x3716, 0x02},// -
226 {0x3717, 0x02},// -
227 {0x371C, 0x3D},// -
228 {0x371D, 0x3F},// -
229 {0x372C, 0x00},// -
230 {0x372D, 0x00},// -
231 {0x372E, 0x46},// -
232 {0x372F, 0x00},// -
233 {0x3730, 0x89},// -
234 {0x3731, 0x00},// -
235 {0x3732, 0x08},// -
236 {0x3733, 0x01},// -
237 {0x3734, 0xFE},// -
238 {0x3735, 0x05},// -
239 {0x375D, 0x00},// -
240 {0x375E, 0x00},// -
241 {0x375F, 0x61},// -
242 {0x3760, 0x06},// -
243 {0x3768, 0x1B},// -
244 {0x3769, 0x1B},// -
245 {0x376A, 0x1A},// -
246 {0x376B, 0x19},// -
247 {0x376C, 0x18},// -
248 {0x376D, 0x14},// -
249 {0x376E, 0x0F},// -
250 {0x3776, 0x00},// -
251 {0x3777, 0x00},// -
252 {0x3778, 0x46},// -
253 {0x3779, 0x00},// -
254 {0x377A, 0x08},// -
255 {0x377B, 0x01},// -
256 {0x377C, 0x45},// -
257 {0x377D, 0x01},// -
258 {0x377E, 0x23},// -
259 {0x377F, 0x02},// -
260 {0x3780, 0xD9},// -
261 {0x3781, 0x03},// -
262 {0x3782, 0xF5},// -
263 {0x3783, 0x06},// -
264 {0x3784, 0xA5},// -
265 {0x3788, 0x0F},// -
266 {0x378A, 0xD9},// -
267 {0x378B, 0x03},// -
268 {0x378C, 0xEB},// -
269 {0x378D, 0x05},// -
270 {0x378E, 0x87},// -
271 {0x378F, 0x06},// -
272 {0x3790, 0xF5},// -
273 {0x3792, 0x43},// -
274 {0x3794, 0x7A},// -
275 {0x3796, 0xA1},// -
276 {0x3E04, 0x0E},// -
277 {REG_NULL, 0x00},
278 };
279
280 /*
281 *IMX334LQR All-pixel scan CSI-2_4lane 37.125Mhz
282 *AD:10bit Output:10bit 891Mbps Master Mode 30fps
283 *Tool ver : Ver4.0
284 */
285 static const struct regval imx334_linear_10_3840x2160_regs[] = {
286 {0x302E, 0x18},
287 {0x302F, 0x0f},
288 {0x3030, 0xCA},// VMAX[19:0]
289 {0x3031, 0x08},//
290 {0x3034, 0x4c},
291 {0x3035, 0x04},
292 {0x3048, 0x00},// WDMODE[0]
293 {0x3049, 0x00},// WDSEL[1:0]
294 {0x304A, 0x00},// WD_SET1[2:0]
295 {0x304B, 0x01},// WD_SET2[3:0]
296 {0x304C, 0x14},// OPB_SIZE_V[5:0]
297 {0x3058, 0x05},// SHR0[19:0]
298 {0x3059, 0x00},//
299 {0x3068, 0x8B},// RHS1[19:0]
300 {0x3069, 0x00},//{
301 {0x3076, 0x84},
302 {0x3077, 0x08},
303 {0x315a, 0x06},
304 {0x319e, 0x02},
305 {0x31D7, 0x00},// XVSMSKCNT_INT[1:0]
306 {0x3200, 0x11},// FGAINEN[0]
307 {0x341C, 0x47},// ADBIT1[8:0]
308 {0x3a18, 0x7f},
309 {0x3a1a, 0x37},
310 {0x3a1c, 0x37},
311 {0x3a1e, 0xf7},
312 {0x3a1f, 0x00},
313 {0x3a20, 0x3f},
314 {0x3a22, 0x6f},
315 {0x3a24, 0x3f},
316 {0x3a26, 0x5f},
317 {0x3a28, 0x2f},
318 {REG_NULL, 0x00},
319 };
320
321 /*
322 *All-pixel scan CSI-2_4lane 37.125Mhz
323 *AD:10bit Output:10bit 1782Mbps Master Mode DOL HDR 2frame VC
324 *Tool ver : Ver3.0
325 */
326 static const struct regval imx334_hdr_10_3840x2160_regs[] = {
327 {0x302E, 0x18},
328 {0x302F, 0x0f},
329 {0x3030, 0xC4},// VMAX[19:0]
330 {0x3031, 0x09},//
331 {0x3034, 0xEF},// HMAX[15:0]
332 {0x3035, 0x01},//
333 {0x3048, 0x01},// WDMODE[0]
334 {0x3049, 0x01},// WDSEL[1:0]
335 {0x304A, 0x01},// WD_SET1[2:0]
336 {0x304B, 0x02},// WD_SET2[3:0]
337 {0x304C, 0x13},// OPB_SIZE_V[5:0]
338 {0x3058, 0xD0},// SHR0[19:0]
339 {0x3059, 0x07},//
340 {0x3068, 0x51},// RHS1[19:0]
341 {0x3069, 0x05},//{
342 {0x3076, 0x84},
343 {0x3077, 0x08},
344 {0x315A, 0x02},// INCKSEL2[1:0]
345 {0x319E, 0x00},
346 {0x31D7, 0x01},// XVSMSKCNT_INT[1:0]
347 {0x3200, 0x10},// FGAINEN[0]
348 {0x341C, 0xFF},// ADBIT1[8:0]
349 {0x3a18, 0xB7},
350 {0x3a1a, 0x67},
351 {0x3a1c, 0x6F},
352 {0x3a1e, 0xf7},
353 {0x3a1f, 0xDF},
354 {0x3a20, 0x6F},
355 {0x3a22, 0xCF},
356 {0x3a24, 0x6F},
357 {0x3a26, 0xB7},
358 {0x3a28, 0x5F},
359 {REG_NULL, 0x00},
360 };
361
362 static const struct regval imx334_12_3840x2160_global_regs[] = {
363 {0x3001, 0x00},
364 {0x3002, 0x00},
365 {0x31A1, 0x00},// XVS_DRV[1:0]
366 {0x3288, 0x21},// -
367 {0x328A, 0x02},// -
368 {0x3414, 0x05},// -
369 {0x3416, 0x18},// -
370 {0x35AC, 0x0E},// -
371 {0x3648, 0x01},// -
372 {0x364A, 0x04},// -
373 {0x364C, 0x04},// -
374 {0x3678, 0x01},// -
375 {0x367C, 0x31},// -
376 {0x367E, 0x31},// -
377 {0x3708, 0x02},// -
378 {0x3714, 0x01},// -
379 {0x3715, 0x02},// -
380 {0x3716, 0x02},// -
381 {0x3717, 0x02},// -
382 {0x371C, 0x3D},// -
383 {0x371D, 0x3F},// -
384 {0x372C, 0x00},// -
385 {0x372D, 0x00},// -
386 {0x372E, 0x46},// -
387 {0x372F, 0x00},// -
388 {0x3730, 0x89},// -
389 {0x3731, 0x00},// -
390 {0x3732, 0x08},// -
391 {0x3733, 0x01},// -
392 {0x3734, 0xFE},// -
393 {0x3735, 0x05},// -
394 {0x375D, 0x00},// -
395 {0x375E, 0x00},// -
396 {0x375F, 0x61},// -
397 {0x3760, 0x06},// -
398 {0x3768, 0x1B},// -
399 {0x3769, 0x1B},// -
400 {0x376A, 0x1A},// -
401 {0x376B, 0x19},// -
402 {0x376C, 0x18},// -
403 {0x376D, 0x14},// -
404 {0x376E, 0x0F},// -
405 {0x3776, 0x00},// -
406 {0x3777, 0x00},// -
407 {0x3778, 0x46},// -
408 {0x3779, 0x00},// -
409 {0x377A, 0x08},// -
410 {0x377B, 0x01},// -
411 {0x377C, 0x45},// -
412 {0x377D, 0x01},// -
413 {0x377E, 0x23},// -
414 {0x377F, 0x02},// -
415 {0x3780, 0xD9},// -
416 {0x3781, 0x03},// -
417 {0x3782, 0xF5},// -
418 {0x3783, 0x06},// -
419 {0x3784, 0xA5},// -
420 {0x3788, 0x0F},// -
421 {0x378A, 0xD9},// -
422 {0x378B, 0x03},// -
423 {0x378C, 0xEB},// -
424 {0x378D, 0x05},// -
425 {0x378E, 0x87},// -
426 {0x378F, 0x06},// -
427 {0x3790, 0xF5},// -
428 {0x3792, 0x43},// -
429 {0x3794, 0x7A},// -
430 {0x3796, 0xA1},// -
431 {0x3E04, 0x0E},// -
432 {REG_NULL, 0x00},
433 };
434 /*
435 *IMX334LQR All-pixel scan CSI-2_4lane 37.125Mhz
436 *AD:12bit Output:12bit 1188Mbps Master Mode 30fps
437 *Tool ver : Ver4.0
438 */
439 static const struct regval imx334_linear_12_3840x2160_regs[] = {
440 {0x302E, 0x18},
441 {0x302F, 0x0f},
442 {0x3030, 0xCA},// VMAX[19:0]
443 {0x3031, 0x08},//
444 {0x300C, 0x5B},// BCWAIT_TIME[7:0]
445 {0x300D, 0x40},// CPWAIT_TIME[7:0]
446 {0x3034, 0x4C},// HMAX[15:0]
447 {0x3035, 0x04},//
448 {0x3048, 0x00},// WDMODE[0]
449 {0x3049, 0x00},// WDSEL[1:0]
450 {0x304A, 0x00},// WD_SET1[2:0]
451 {0x304B, 0x01},// WD_SET2[3:0]
452 {0x304C, 0x14},// OPB_SIZE_V[5:0]
453 {0x3058, 0x17},// SHR0[19:0]
454 {0x3059, 0x00},//
455 {0x3068, 0x8B},// RHS1[19:0]
456 {0x3069, 0x00},//
457 {0x3076, 0x84},
458 {0x3077, 0x08},
459 {0x314C, 0x80},// INCKSEL 1[8:0]
460 {0x315A, 0x02},// INCKSEL2[1:0]
461 {0x316A, 0x7E},// INCKSEL4[1:0]
462 {0x319E, 0x01},// SYS_MODE
463 {0x31D7, 0x00},// XVSMSKCNT_INT[1:0]
464 {0x3200, 0x11},// FGAINEN[0]
465 {0x3A18, 0x8F},// TCLKPOST[15:0]
466 {0x3A1A, 0x4F},// TCLKPREPARE[15:0]
467 {0x3A1C, 0x47},// TCLKTRAIL[15:0]
468 {0x3A1E, 0x37},// TCLKZERO[15:0]
469 {0x3A20, 0x4F},// THSPREPARE[15:0]
470 {0x3A22, 0x87},// THSZERO[15:0]
471 {0x3A24, 0x4F},// THSTRAIL[15:0]
472 {0x3A26, 0x7F},// THSEXIT[15:0]
473 {0x3A28, 0x3F},// TLPX[15:0]
474 {REG_NULL, 0x00},
475 };
476
477 /*
478 *All-pixel scan CSI-2_4lane 74.25Mhz
479 *AD:12bit Output:12bit 1782Mbps Master Mode DOL HDR 2frame VC
480 *Tool ver : Ver3.0
481 */
482 static const struct regval imx334_hdr_12_74M_3840x2160_regs[] = {
483 {0x302E, 0x18},
484 {0x302F, 0x0f},
485 {0x3030, 0xC8},// VMAX[19:0]
486 {0x3031, 0x08},//
487 {0x300C, 0xB6},// BCWAIT_TIME[7:0]
488 {0x300D, 0x7F},// CPWAIT_TIME[7:0]
489 {0x3034, 0x26},// HMAX[15:0]
490 {0x3035, 0x02},//
491 {0x3048, 0x01},// WDMODE[0]
492 {0x3049, 0x01},// WDSEL[1:0]
493 {0x304A, 0x01},// WD_SET1[2:0]
494 {0x304B, 0x02},// WD_SET2[3:0]
495 {0x304C, 0x13},// OPB_SIZE_V[5:0]
496 {0x3058, 0xC2},// SHR0[19:0]
497 {0x3059, 0x01},//
498 {0x3068, 0x19},// RHS1[19:0]
499 {0x3069, 0x01},//
500 {0x3076, 0x84},
501 {0x3077, 0x08},
502 {0x314C, 0xC0},// INCKSEL 1[8:0]
503 {0x315A, 0x03},// INCKSEL2[1:0]
504 {0x316A, 0x7F},// INCKSEL4[1:0]
505 {0x319E, 0x00},// SYS_MODE
506 {0x31D7, 0x01},// XVSMSKCNT_INT[1:0]
507 {0x3200, 0x10},// FGAINEN[0]
508 {0x3A18, 0xB7},// TCLKPOST[15:0]
509 {0x3A1A, 0x67},// TCLKPREPARE[15:0]
510 {0x3A1C, 0x6F},// TCLKTRAIL[15:0]
511 {0x3A1E, 0xDF},// TCLKZERO[15:0]
512 {0x3A20, 0x6F},// THSPREPARE[15:0]
513 {0x3A22, 0xCF},// THSZERO[15:0]
514 {0x3A24, 0x6F},// THSTRAIL[15:0]
515 {0x3A26, 0xB7},// THSEXIT[15:0]
516 {0x3A28, 0x5F},// TLPX[15:0]
517 {REG_NULL, 0x00},
518 };
519
520 static const struct imx334_mode supported_modes[] = {
521 {
522 .width = 3864,
523 .height = 2180,
524 .max_fps = {
525 .numerator = 10000,
526 .denominator = 300000,
527 },
528 .exp_def = 0x0600,
529 .hts_def = 0x044C * 4,
530 .vts_def = 0x08CA,
531 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
532 .global_reg_list = imx334_10_3840x2160_global_regs,
533 .reg_list = imx334_linear_10_3840x2160_regs,
534 .hdr_mode = NO_HDR,
535 .vclk_freq = IMX334_XVCLK_FREQ_37,
536 .bpp = 10,
537 .mipi_freq_idx = 0,
538 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
539 }, {
540 .width = 3864,
541 .height = 2180,
542 .max_fps = {
543 .numerator = 10000,
544 .denominator = 300000,
545 },
546 .exp_def = 0x0080,
547 .hts_def = 0x01EF * 8,
548 .vts_def = 0x09C4 * 2,
549 .global_reg_list = imx334_10_3840x2160_global_regs,
550 .reg_list = imx334_hdr_10_3840x2160_regs,
551 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
552 .hdr_mode = HDR_X2,
553 .vclk_freq = IMX334_XVCLK_FREQ_37,
554 .bpp = 10,
555 .mipi_freq_idx = 2,
556 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
557 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
558 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
559 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
560 }, {
561 .width = 3864,
562 .height = 2180,
563 .max_fps = {
564 .numerator = 10000,
565 .denominator = 300000,
566 },
567 .exp_def = 0x0600,
568 .hts_def = 0x044C * 4,
569 .vts_def = 0x08CA,
570 .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
571 .global_reg_list = imx334_12_3840x2160_global_regs,
572 .reg_list = imx334_linear_12_3840x2160_regs,
573 .hdr_mode = NO_HDR,
574 .vclk_freq = IMX334_XVCLK_FREQ_37,
575 .bpp = 12,
576 .mipi_freq_idx = 1,
577 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
578 }, {
579 .width = 3864,
580 .height = 2180,
581 .max_fps = {
582 .numerator = 10000,
583 .denominator = 300000,
584 },
585 .exp_def = 0x0080,
586 .hts_def = 0x0226 * 8,
587 .vts_def = 0x08C8 * 2,
588 .global_reg_list = imx334_12_3840x2160_global_regs,
589 .reg_list = imx334_hdr_12_74M_3840x2160_regs,
590 .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
591 .hdr_mode = HDR_X2,
592 .vclk_freq = IMX334_XVCLK_FREQ_74,
593 .bpp = 12,
594 .mipi_freq_idx = 2,
595 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
596 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
597 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
598 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
599 },
600 };
601
602 static const s64 link_freq_menu_items[] = {
603 IMX334_LINK_FREQ_445,
604 IMX334_LINK_FREQ_594,
605 IMX334_LINK_FREQ_891,
606 };
607
608 static const char * const imx334_test_pattern_menu[] = {
609 "Disabled",
610 "Vertical Color Bar Type 1",
611 "Vertical Color Bar Type 2",
612 "Vertical Color Bar Type 3",
613 "Vertical Color Bar Type 4"
614 };
615
616 /* Write registers up to 4 at a time */
imx334_write_reg(struct i2c_client * client,u16 reg,int len,u32 val)617 static int imx334_write_reg(struct i2c_client *client, u16 reg,
618 int len, u32 val)
619 {
620 u32 buf_i, val_i;
621 u8 buf[6];
622 u8 *val_p;
623 __be32 val_be;
624
625 if (len > 4)
626 return -EINVAL;
627
628 buf[0] = reg >> 8;
629 buf[1] = reg & 0xff;
630
631 val_be = cpu_to_be32(val);
632 val_p = (u8 *)&val_be;
633 buf_i = 2;
634 val_i = 4 - len;
635
636 while (val_i < 4)
637 buf[buf_i++] = val_p[val_i++];
638
639 if (i2c_master_send(client, buf, len + 2) != len + 2)
640 return -EIO;
641
642 return 0;
643 }
644
imx334_write_array(struct i2c_client * client,const struct regval * regs)645 static int imx334_write_array(struct i2c_client *client,
646 const struct regval *regs)
647 {
648 u32 i;
649 int ret = 0;
650
651 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
652 if (unlikely(regs[i].addr == REG_DELAY))
653 usleep_range(regs[i].val, regs[i].val * 2);
654 else
655 ret = imx334_write_reg(client, regs[i].addr,
656 IMX334_REG_VALUE_08BIT,
657 regs[i].val);
658
659 return ret;
660 }
661
662 /* Read registers up to 4 at a time */
imx334_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)663 static int imx334_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
664 u32 *val)
665 {
666 struct i2c_msg msgs[2];
667 u8 *data_be_p;
668 __be32 data_be = 0;
669 __be16 reg_addr_be = cpu_to_be16(reg);
670 int ret, i;
671
672 if (len > 4 || !len)
673 return -EINVAL;
674
675 data_be_p = (u8 *)&data_be;
676 /* Write register address */
677 msgs[0].addr = client->addr;
678 msgs[0].flags = 0;
679 msgs[0].len = 2;
680 msgs[0].buf = (u8 *)®_addr_be;
681
682 /* Read data from register */
683 msgs[1].addr = client->addr;
684 msgs[1].flags = I2C_M_RD;
685 msgs[1].len = len;
686 msgs[1].buf = &data_be_p[4 - len];
687
688 for (i = 0; i < 3; i++) {
689 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
690 if (ret == ARRAY_SIZE(msgs))
691 break;
692 }
693 if (ret != ARRAY_SIZE(msgs) && i == 3)
694 return -EIO;
695
696 *val = be32_to_cpu(data_be);
697
698 return 0;
699 }
700
imx334_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)701 static int imx334_set_fmt(struct v4l2_subdev *sd,
702 struct v4l2_subdev_pad_config *cfg,
703 struct v4l2_subdev_format *fmt)
704 {
705 struct imx334 *imx334 = to_imx334(sd);
706 const struct imx334_mode *mode;
707 s64 h_blank, vblank_def;
708 s64 dst_pixel_rate = 0;
709 int ret = 0;
710
711 mutex_lock(&imx334->mutex);
712
713 mode = v4l2_find_nearest_size(supported_modes,
714 ARRAY_SIZE(supported_modes),
715 width, height,
716 fmt->format.width, fmt->format.height);
717 fmt->format.code = mode->bus_fmt;
718 fmt->format.width = mode->width;
719 fmt->format.height = mode->height;
720 fmt->format.field = V4L2_FIELD_NONE;
721 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
722 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
723 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
724 #else
725 mutex_unlock(&imx334->mutex);
726 return -ENOTTY;
727 #endif
728 } else {
729 imx334->cur_mode = mode;
730 imx334->cur_vts = imx334->cur_mode->vts_def;
731 h_blank = mode->hts_def - mode->width;
732 __v4l2_ctrl_modify_range(imx334->hblank, h_blank,
733 h_blank, 1, h_blank);
734 vblank_def = mode->vts_def - mode->height;
735 __v4l2_ctrl_modify_range(imx334->vblank, vblank_def,
736 IMX334_VTS_MAX - mode->height,
737 1, vblank_def);
738 if (imx334->cur_vclk_freq != mode->vclk_freq) {
739 clk_disable_unprepare(imx334->xvclk);
740 ret = clk_set_rate(imx334->xvclk, mode->vclk_freq);
741 ret |= clk_prepare_enable(imx334->xvclk);
742 if (ret < 0) {
743 dev_err(&imx334->client->dev, "Failed to enable xvclk\n");
744 mutex_unlock(&imx334->mutex);
745 return ret;
746 }
747 imx334->cur_vclk_freq = mode->vclk_freq;
748 }
749 if (imx334->cur_mipi_freq_idx != mode->mipi_freq_idx) {
750 dst_pixel_rate = ((u32)link_freq_menu_items[mode->mipi_freq_idx]) /
751 mode->bpp * 2 * IMX334_LANES;
752 __v4l2_ctrl_s_ctrl_int64(imx334->pixel_rate,
753 dst_pixel_rate);
754 __v4l2_ctrl_s_ctrl(imx334->link_freq,
755 mode->mipi_freq_idx);
756 imx334->cur_mipi_freq_idx = mode->mipi_freq_idx;
757 }
758 }
759 mutex_unlock(&imx334->mutex);
760 return 0;
761 }
762
imx334_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)763 static int imx334_get_fmt(struct v4l2_subdev *sd,
764 struct v4l2_subdev_pad_config *cfg,
765 struct v4l2_subdev_format *fmt)
766 {
767 struct imx334 *imx334 = to_imx334(sd);
768 const struct imx334_mode *mode = imx334->cur_mode;
769
770 mutex_lock(&imx334->mutex);
771 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
772 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
773 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
774 #else
775 mutex_unlock(&imx334->mutex);
776 return -ENOTTY;
777 #endif
778 } else {
779 fmt->format.width = mode->width;
780 fmt->format.height = mode->height;
781 fmt->format.code = mode->bus_fmt;
782 fmt->format.field = V4L2_FIELD_NONE;
783 /* format info: width/height/data type/virctual channel */
784 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
785 fmt->reserved[0] = mode->vc[fmt->pad];
786 else
787 fmt->reserved[0] = mode->vc[PAD0];
788 }
789 mutex_unlock(&imx334->mutex);
790
791 return 0;
792 }
793
imx334_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)794 static int imx334_enum_mbus_code(struct v4l2_subdev *sd,
795 struct v4l2_subdev_pad_config *cfg,
796 struct v4l2_subdev_mbus_code_enum *code)
797 {
798 struct imx334 *imx334 = to_imx334(sd);
799
800 if (code->index != 0)
801 return -EINVAL;
802 code->code = imx334->cur_mode->bus_fmt;
803
804 return 0;
805 }
806
imx334_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)807 static int imx334_enum_frame_sizes(struct v4l2_subdev *sd,
808 struct v4l2_subdev_pad_config *cfg,
809 struct v4l2_subdev_frame_size_enum *fse)
810 {
811 if (fse->index >= ARRAY_SIZE(supported_modes))
812 return -EINVAL;
813
814 if (fse->code != supported_modes[0].bus_fmt)
815 return -EINVAL;
816
817 fse->min_width = supported_modes[fse->index].width;
818 fse->max_width = supported_modes[fse->index].width;
819 fse->max_height = supported_modes[fse->index].height;
820 fse->min_height = supported_modes[fse->index].height;
821
822 return 0;
823 }
824
imx334_enable_test_pattern(struct imx334 * imx334,u32 pattern)825 static int imx334_enable_test_pattern(struct imx334 *imx334, u32 pattern)
826 {
827 u32 val;
828
829 if (pattern)
830 val = (pattern - 1) | IMX334_TEST_PATTERN_ENABLE;
831 else
832 val = IMX334_TEST_PATTERN_DISABLE;
833
834 return imx334_write_reg(imx334->client,
835 IMX334_REG_TEST_PATTERN,
836 IMX334_REG_VALUE_08BIT,
837 val);
838 }
839
imx334_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)840 static int imx334_g_frame_interval(struct v4l2_subdev *sd,
841 struct v4l2_subdev_frame_interval *fi)
842 {
843 struct imx334 *imx334 = to_imx334(sd);
844 const struct imx334_mode *mode = imx334->cur_mode;
845
846 fi->interval = mode->max_fps;
847
848 return 0;
849 }
850
imx334_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)851 static int imx334_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
852 struct v4l2_mbus_config *config)
853 {
854 struct imx334 *imx334 = to_imx334(sd);
855 const struct imx334_mode *mode = imx334->cur_mode;
856 u32 val = 0;
857
858 val = 1 << (IMX334_LANES - 1) |
859 V4L2_MBUS_CSI2_CHANNEL_0 |
860 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
861
862 config->flags = (mode->hdr_mode == NO_HDR) ? val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
863 config->type = V4L2_MBUS_CSI2_DPHY;
864 return 0;
865 }
866
imx334_get_module_inf(struct imx334 * imx334,struct rkmodule_inf * inf)867 static void imx334_get_module_inf(struct imx334 *imx334,
868 struct rkmodule_inf *inf)
869 {
870 memset(inf, 0, sizeof(*inf));
871 strlcpy(inf->base.sensor, IMX334_NAME, sizeof(inf->base.sensor));
872 strlcpy(inf->base.module, imx334->module_name,
873 sizeof(inf->base.module));
874 strlcpy(inf->base.lens, imx334->len_name, sizeof(inf->base.lens));
875 }
876
imx334_set_hdrae(struct imx334 * imx334,struct preisp_hdrae_exp_s * ae)877 static int imx334_set_hdrae(struct imx334 *imx334,
878 struct preisp_hdrae_exp_s *ae)
879 {
880 struct i2c_client *client = imx334->client;
881 u32 l_exp_time, m_exp_time, s_exp_time;
882 u32 l_a_gain, m_a_gain, s_a_gain;
883 u32 shr1 = 0;
884 u32 shr0 = 0;
885 u32 rhs1 = 0;
886 u32 rhs1_max = 0;
887 static int rhs1_old = 225;
888 int rhs1_change_limit;
889 int ret = 0;
890 u32 fsc = imx334->cur_vts;
891
892 if (!imx334->has_init_exp && !imx334->streaming) {
893 imx334->init_hdrae_exp = *ae;
894 imx334->has_init_exp = true;
895 dev_dbg(&imx334->client->dev, "imx334 don't stream, record exp for hdr!\n");
896 return ret;
897 }
898 l_exp_time = ae->long_exp_reg;
899 m_exp_time = ae->middle_exp_reg;
900 s_exp_time = ae->short_exp_reg;
901 l_a_gain = ae->long_gain_reg;
902 m_a_gain = ae->middle_gain_reg;
903 s_a_gain = ae->short_gain_reg;
904 dev_dbg(&client->dev,
905 "rev exp: L_exp:0x%x,0x%x, M_exp:0x%x,0x%x S_exp:0x%x,0x%x\n",
906 l_exp_time, l_a_gain,
907 m_exp_time, m_a_gain,
908 s_exp_time, s_a_gain);
909
910 if (imx334->cur_mode->hdr_mode == HDR_X2) {
911 //2 stagger
912 l_a_gain = m_a_gain;
913 l_exp_time = m_exp_time;
914 }
915 //gain effect n+1
916 ret |= imx334_write_reg(client,
917 IMX334_LF_GAIN_REG_L,
918 IMX334_REG_VALUE_08BIT,
919 l_a_gain & 0xff);
920 ret |= imx334_write_reg(client,
921 IMX334_SF1_GAIN_REG_L,
922 IMX334_REG_VALUE_08BIT,
923 s_a_gain & 0xff);
924
925 //long exposure and short exposure
926 shr0 = fsc - l_exp_time;
927 rhs1_max = (RHS1_MAX > (shr0 - 9)) ? (shr0 - 9) : RHS1_MAX;
928 rhs1_max = (rhs1_max >> 2) * 4 + 1;
929 rhs1 = ((SHR1_MIN + s_exp_time + 3) >> 2) * 4 + 1;
930 dev_dbg(&client->dev, "line(%d) rhs1 %d\n", __LINE__, rhs1);
931 if (rhs1 < 13)
932 rhs1 = 13;
933 else if (rhs1 > rhs1_max)
934 rhs1 = rhs1_max;
935 dev_dbg(&client->dev, "line(%d) rhs1 %d\n", __LINE__, rhs1);
936
937 //Dynamic adjustment rhs1 must meet the following conditions
938 rhs1_change_limit = rhs1_old + 2 * BRL - fsc + 2;
939 rhs1_change_limit = (rhs1_change_limit < 13) ? 13 : rhs1_change_limit;
940 rhs1_change_limit = ((rhs1_change_limit + 3) >> 2) * 4 + 1;
941 if (rhs1 < rhs1_change_limit)
942 rhs1 = rhs1_change_limit;
943
944 dev_dbg(&client->dev,
945 "line(%d) rhs1 %d,short time %d rhs1_old %d test %d\n",
946 __LINE__, rhs1, s_exp_time, rhs1_old,
947 (rhs1_old + 2 * BRL - fsc + 2));
948
949 rhs1_old = rhs1;
950 shr1 = rhs1 - s_exp_time;
951
952 if (shr1 < 9)
953 shr1 = 9;
954 else if (shr1 > (rhs1 - 2))
955 shr1 = rhs1 - 2;
956
957 if (shr0 < (rhs1 + 9))
958 shr0 = rhs1 + 9;
959 else if (shr0 > (fsc - 2))
960 shr0 = fsc - 2;
961
962 dev_dbg(&client->dev,
963 "fsc=%d,RHS1_MAX=%d,SHR1_MIN=%d,rhs1_max=%d\n",
964 fsc, RHS1_MAX, SHR1_MIN, rhs1_max);
965 dev_dbg(&client->dev,
966 "l_exp_time=%d,s_exp_time=%d,shr0=%d,shr1=%d,rhs1=%d,l_a_gain=%d,s_a_gain=%d\n",
967 l_exp_time, s_exp_time, shr0, shr1, rhs1, l_a_gain, s_a_gain);
968 //time effect n+2
969 ret |= imx334_write_reg(client,
970 IMX334_RHS1_REG_L,
971 IMX334_REG_VALUE_08BIT,
972 IMX334_FETCH_RHS1_L(rhs1));
973 ret |= imx334_write_reg(client,
974 IMX334_RHS1_REG_M,
975 IMX334_REG_VALUE_08BIT,
976 IMX334_FETCH_RHS1_M(rhs1));
977 ret |= imx334_write_reg(client,
978 IMX334_RHS1_REG_H,
979 IMX334_REG_VALUE_08BIT,
980 IMX334_FETCH_RHS1_H(rhs1));
981
982 ret |= imx334_write_reg(client,
983 IMX334_SF1_EXPO_REG_L,
984 IMX334_REG_VALUE_08BIT,
985 IMX334_FETCH_EXP_L(shr1));
986 ret |= imx334_write_reg(client,
987 IMX334_SF1_EXPO_REG_M,
988 IMX334_REG_VALUE_08BIT,
989 IMX334_FETCH_EXP_M(shr1));
990 ret |= imx334_write_reg(client,
991 IMX334_SF1_EXPO_REG_H,
992 IMX334_REG_VALUE_08BIT,
993 IMX334_FETCH_EXP_H(shr1));
994 ret |= imx334_write_reg(client,
995 IMX334_LF_EXPO_REG_L,
996 IMX334_REG_VALUE_08BIT,
997 IMX334_FETCH_EXP_L(shr0));
998 ret |= imx334_write_reg(client,
999 IMX334_LF_EXPO_REG_M,
1000 IMX334_REG_VALUE_08BIT,
1001 IMX334_FETCH_EXP_M(shr0));
1002 ret |= imx334_write_reg(client,
1003 IMX334_LF_EXPO_REG_H,
1004 IMX334_REG_VALUE_08BIT,
1005 IMX334_FETCH_EXP_H(shr0));
1006 return ret;
1007 }
1008
imx334_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1009 static long imx334_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1010 {
1011 struct imx334 *imx334 = to_imx334(sd);
1012 struct rkmodule_hdr_cfg *hdr;
1013 long ret = 0;
1014 u32 i, h, w;
1015 s64 dst_pixel_rate = 0;
1016 const struct imx334_mode *mode;
1017 u32 stream = 0;
1018
1019 switch (cmd) {
1020 case PREISP_CMD_SET_HDRAE_EXP:
1021 return imx334_set_hdrae(imx334, arg);
1022 case RKMODULE_GET_MODULE_INFO:
1023 imx334_get_module_inf(imx334, (struct rkmodule_inf *)arg);
1024 break;
1025 case RKMODULE_GET_HDR_CFG:
1026 hdr = (struct rkmodule_hdr_cfg *)arg;
1027 hdr->esp.mode = HDR_NORMAL_VC;
1028 hdr->hdr_mode = imx334->cur_mode->hdr_mode;
1029 break;
1030 case RKMODULE_SET_HDR_CFG:
1031 hdr = (struct rkmodule_hdr_cfg *)arg;
1032 w = imx334->cur_mode->width;
1033 h = imx334->cur_mode->height;
1034 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1035 if (w == supported_modes[i].width &&
1036 h == supported_modes[i].height &&
1037 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1038 imx334->cur_mode = &supported_modes[i];
1039 break;
1040 }
1041 }
1042 if (i == ARRAY_SIZE(supported_modes)) {
1043 dev_err(&imx334->client->dev,
1044 "not find hdr mode:%d %dx%d config\n",
1045 hdr->hdr_mode, w, h);
1046 ret = -EINVAL;
1047 } else {
1048 mode = imx334->cur_mode;
1049 imx334->cur_vts = mode->vts_def;
1050 w = mode->hts_def - mode->width;
1051 h = mode->vts_def - mode->height;
1052 __v4l2_ctrl_modify_range(imx334->hblank, w, w, 1, w);
1053 __v4l2_ctrl_modify_range(imx334->vblank, h,
1054 IMX334_VTS_MAX -
1055 mode->height,
1056 1, h);
1057 if (imx334->cur_vclk_freq != mode->vclk_freq) {
1058 clk_disable_unprepare(imx334->xvclk);
1059 ret = clk_set_rate(imx334->xvclk, mode->vclk_freq);
1060 ret |= clk_prepare_enable(imx334->xvclk);
1061 if (ret < 0) {
1062 dev_err(&imx334->client->dev, "Failed to enable xvclk\n");
1063 return ret;
1064 }
1065 imx334->cur_vclk_freq = mode->vclk_freq;
1066 }
1067 if (imx334->cur_mipi_freq_idx != mode->mipi_freq_idx) {
1068 dst_pixel_rate = ((u32)link_freq_menu_items[mode->mipi_freq_idx]) /
1069 mode->bpp * 2 * IMX334_LANES;
1070 __v4l2_ctrl_s_ctrl_int64(imx334->pixel_rate,
1071 dst_pixel_rate);
1072 __v4l2_ctrl_s_ctrl(imx334->link_freq,
1073 mode->mipi_freq_idx);
1074 imx334->cur_mipi_freq_idx = mode->mipi_freq_idx;
1075 }
1076 }
1077 break;
1078 case RKMODULE_SET_QUICK_STREAM:
1079
1080 stream = *((u32 *)arg);
1081
1082 if (stream)
1083 ret = imx334_write_reg(imx334->client, IMX334_REG_CTRL_MODE,
1084 IMX334_REG_VALUE_08BIT, 0);
1085 else
1086 ret = imx334_write_reg(imx334->client, IMX334_REG_CTRL_MODE,
1087 IMX334_REG_VALUE_08BIT, 1);
1088 break;
1089 default:
1090 ret = -ENOIOCTLCMD;
1091 break;
1092 }
1093
1094 return ret;
1095 }
1096
1097 #ifdef CONFIG_COMPAT
imx334_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1098 static long imx334_compat_ioctl32(struct v4l2_subdev *sd,
1099 unsigned int cmd, unsigned long arg)
1100 {
1101 void __user *up = compat_ptr(arg);
1102 struct rkmodule_inf *inf;
1103 struct rkmodule_awb_cfg *cfg;
1104 struct rkmodule_hdr_cfg *hdr;
1105 struct preisp_hdrae_exp_s *hdrae;
1106 long ret;
1107 u32 stream = 0;
1108
1109 switch (cmd) {
1110 case RKMODULE_GET_MODULE_INFO:
1111 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1112 if (!inf) {
1113 ret = -ENOMEM;
1114 return ret;
1115 }
1116
1117 ret = imx334_ioctl(sd, cmd, inf);
1118 if (!ret)
1119 ret = copy_to_user(up, inf, sizeof(*inf));
1120 kfree(inf);
1121 break;
1122 case RKMODULE_AWB_CFG:
1123 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1124 if (!cfg) {
1125 ret = -ENOMEM;
1126 return ret;
1127 }
1128
1129 ret = copy_from_user(cfg, up, sizeof(*cfg));
1130 if (!ret)
1131 ret = imx334_ioctl(sd, cmd, cfg);
1132 kfree(cfg);
1133 break;
1134 case RKMODULE_GET_HDR_CFG:
1135 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1136 if (!hdr) {
1137 ret = -ENOMEM;
1138 return ret;
1139 }
1140
1141 ret = imx334_ioctl(sd, cmd, hdr);
1142 if (!ret)
1143 ret = copy_to_user(up, hdr, sizeof(*hdr));
1144 kfree(hdr);
1145 break;
1146 case RKMODULE_SET_HDR_CFG:
1147 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1148 if (!hdr) {
1149 ret = -ENOMEM;
1150 return ret;
1151 }
1152
1153 ret = copy_from_user(hdr, up, sizeof(*hdr));
1154 if (!ret)
1155 ret = imx334_ioctl(sd, cmd, hdr);
1156 kfree(hdr);
1157 break;
1158 case PREISP_CMD_SET_HDRAE_EXP:
1159 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1160 if (!hdrae) {
1161 ret = -ENOMEM;
1162 return ret;
1163 }
1164
1165 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1166 if (!ret)
1167 ret = imx334_ioctl(sd, cmd, hdrae);
1168 kfree(hdrae);
1169 break;
1170 case RKMODULE_SET_QUICK_STREAM:
1171 ret = copy_from_user(&stream, up, sizeof(u32));
1172 if (!ret)
1173 ret = imx334_ioctl(sd, cmd, &stream);
1174 break;
1175 default:
1176 ret = -ENOIOCTLCMD;
1177 break;
1178 }
1179
1180 return ret;
1181 }
1182 #endif
1183
__imx334_start_stream(struct imx334 * imx334)1184 static int __imx334_start_stream(struct imx334 *imx334)
1185 {
1186 int ret;
1187
1188 ret = imx334_write_array(imx334->client, imx334->cur_mode->global_reg_list);
1189 if (ret)
1190 return ret;
1191 ret = imx334_write_array(imx334->client, imx334->cur_mode->reg_list);
1192 if (ret)
1193 return ret;
1194 /* In case these controls are set before streaming */
1195 if (imx334->has_init_exp && imx334->cur_mode->hdr_mode != NO_HDR) {
1196 ret = imx334_ioctl(&imx334->subdev, PREISP_CMD_SET_HDRAE_EXP,
1197 &imx334->init_hdrae_exp);
1198 if (ret) {
1199 dev_err(&imx334->client->dev,
1200 "init exp fail in hdr mode\n");
1201 return ret;
1202 }
1203 } else {
1204 mutex_unlock(&imx334->mutex);
1205 ret = v4l2_ctrl_handler_setup(&imx334->ctrl_handler);
1206 mutex_lock(&imx334->mutex);
1207 if (ret)
1208 return ret;
1209 }
1210 return imx334_write_reg(imx334->client, IMX334_REG_CTRL_MODE,
1211 IMX334_REG_VALUE_08BIT, 0);
1212 }
1213
__imx334_stop_stream(struct imx334 * imx334)1214 static int __imx334_stop_stream(struct imx334 *imx334)
1215 {
1216 return imx334_write_reg(imx334->client, IMX334_REG_CTRL_MODE,
1217 IMX334_REG_VALUE_08BIT, 1);
1218 }
1219
imx334_s_stream(struct v4l2_subdev * sd,int on)1220 static int imx334_s_stream(struct v4l2_subdev *sd, int on)
1221 {
1222 struct imx334 *imx334 = to_imx334(sd);
1223 struct i2c_client *client = imx334->client;
1224 int ret = 0;
1225
1226 mutex_lock(&imx334->mutex);
1227 on = !!on;
1228 if (on == imx334->streaming)
1229 goto unlock_and_return;
1230
1231 if (on) {
1232 ret = pm_runtime_get_sync(&client->dev);
1233 if (ret < 0) {
1234 pm_runtime_put_noidle(&client->dev);
1235 goto unlock_and_return;
1236 }
1237
1238 ret = __imx334_start_stream(imx334);
1239 if (ret) {
1240 v4l2_err(sd, "start stream failed while write regs\n");
1241 pm_runtime_put(&client->dev);
1242 goto unlock_and_return;
1243 }
1244 } else {
1245 __imx334_stop_stream(imx334);
1246 pm_runtime_put(&client->dev);
1247 }
1248
1249 imx334->streaming = on;
1250
1251 unlock_and_return:
1252 mutex_unlock(&imx334->mutex);
1253
1254 return ret;
1255 }
1256
imx334_s_power(struct v4l2_subdev * sd,int on)1257 static int imx334_s_power(struct v4l2_subdev *sd, int on)
1258 {
1259 struct imx334 *imx334 = to_imx334(sd);
1260 struct i2c_client *client = imx334->client;
1261 int ret = 0;
1262
1263 mutex_lock(&imx334->mutex);
1264
1265 /* If the power state is not modified - no work to do. */
1266 if (imx334->power_on == !!on)
1267 goto unlock_and_return;
1268
1269 if (on) {
1270 ret = pm_runtime_get_sync(&client->dev);
1271 if (ret < 0) {
1272 pm_runtime_put_noidle(&client->dev);
1273 goto unlock_and_return;
1274 }
1275
1276 imx334->power_on = true;
1277 } else {
1278 pm_runtime_put(&client->dev);
1279 imx334->power_on = false;
1280 }
1281
1282 unlock_and_return:
1283 mutex_unlock(&imx334->mutex);
1284
1285 return ret;
1286 }
1287
1288 /* Calculate the delay in us by clock rate and clock cycles */
imx334_cal_delay(u32 cycles,struct imx334 * imx334)1289 static inline u32 imx334_cal_delay(u32 cycles, struct imx334 *imx334)
1290 {
1291 if (imx334->cur_mode->vclk_freq == IMX334_XVCLK_FREQ_37)
1292 return DIV_ROUND_UP(cycles, IMX334_XVCLK_FREQ_37 / 1000 / 1000);
1293 else
1294 return DIV_ROUND_UP(cycles, IMX334_XVCLK_FREQ_74 / 1000 / 1000);
1295 }
1296
__imx334_power_on(struct imx334 * imx334)1297 static int __imx334_power_on(struct imx334 *imx334)
1298 {
1299 int ret;
1300 u32 delay_us;
1301 s64 vclk_freq;
1302 struct device *dev = &imx334->client->dev;
1303
1304 if (!IS_ERR_OR_NULL(imx334->pins_default)) {
1305 ret = pinctrl_select_state(imx334->pinctrl,
1306 imx334->pins_default);
1307 if (ret < 0)
1308 dev_err(dev, "could not set pins\n");
1309 }
1310
1311 if (imx334->cur_mode->vclk_freq == IMX334_XVCLK_FREQ_37)
1312 vclk_freq = IMX334_XVCLK_FREQ_37;
1313 else
1314 vclk_freq = IMX334_XVCLK_FREQ_74;
1315
1316 ret = clk_set_rate(imx334->xvclk, vclk_freq);
1317 if (ret < 0) {
1318 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
1319 return ret;
1320 }
1321 if (clk_get_rate(imx334->xvclk) != vclk_freq)
1322 dev_warn(dev, "xvclk mismatched, modes are based on 37.125MHz\n");
1323 ret = clk_prepare_enable(imx334->xvclk);
1324 if (ret < 0) {
1325 dev_err(dev, "Failed to enable xvclk\n");
1326 return ret;
1327 }
1328
1329 if (!IS_ERR(imx334->reset_gpio))
1330 gpiod_set_value_cansleep(imx334->reset_gpio, 0);
1331
1332 ret = regulator_bulk_enable(IMX334_NUM_SUPPLIES, imx334->supplies);
1333 if (ret < 0) {
1334 dev_err(dev, "Failed to enable regulators\n");
1335 goto disable_clk;
1336 }
1337
1338 if (!IS_ERR(imx334->reset_gpio))
1339 gpiod_set_value_cansleep(imx334->reset_gpio, 1);
1340
1341 usleep_range(500, 1000);
1342 if (!IS_ERR(imx334->pwdn_gpio))
1343 gpiod_set_value_cansleep(imx334->pwdn_gpio, 1);
1344
1345 /* 8192 cycles prior to first SCCB transaction */
1346 delay_us = imx334_cal_delay(8192, imx334);
1347 usleep_range(delay_us, delay_us * 2);
1348
1349 return 0;
1350
1351 disable_clk:
1352 clk_disable_unprepare(imx334->xvclk);
1353
1354 return ret;
1355 }
1356
__imx334_power_off(struct imx334 * imx334)1357 static void __imx334_power_off(struct imx334 *imx334)
1358 {
1359 if (!IS_ERR(imx334->pwdn_gpio))
1360 gpiod_set_value_cansleep(imx334->pwdn_gpio, 0);
1361 clk_disable_unprepare(imx334->xvclk);
1362 if (!IS_ERR(imx334->reset_gpio))
1363 gpiod_set_value_cansleep(imx334->reset_gpio, 0);
1364 regulator_bulk_disable(IMX334_NUM_SUPPLIES, imx334->supplies);
1365 }
1366
imx334_runtime_resume(struct device * dev)1367 static int imx334_runtime_resume(struct device *dev)
1368 {
1369 struct i2c_client *client = to_i2c_client(dev);
1370 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1371 struct imx334 *imx334 = to_imx334(sd);
1372
1373 return __imx334_power_on(imx334);
1374 }
1375
imx334_runtime_suspend(struct device * dev)1376 static int imx334_runtime_suspend(struct device *dev)
1377 {
1378 struct i2c_client *client = to_i2c_client(dev);
1379 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1380 struct imx334 *imx334 = to_imx334(sd);
1381
1382 __imx334_power_off(imx334);
1383
1384 return 0;
1385 }
1386
1387 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx334_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1388 static int imx334_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1389 {
1390 struct imx334 *imx334 = to_imx334(sd);
1391 struct v4l2_mbus_framefmt *try_fmt =
1392 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1393 const struct imx334_mode *def_mode = &supported_modes[0];
1394
1395 mutex_lock(&imx334->mutex);
1396 /* Initialize try_fmt */
1397 try_fmt->width = def_mode->width;
1398 try_fmt->height = def_mode->height;
1399 try_fmt->code = def_mode->bus_fmt;
1400 try_fmt->field = V4L2_FIELD_NONE;
1401
1402 mutex_unlock(&imx334->mutex);
1403 /* No crop or compose */
1404
1405 return 0;
1406 }
1407 #endif
1408
imx334_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1409 static int imx334_enum_frame_interval(struct v4l2_subdev *sd,
1410 struct v4l2_subdev_pad_config *cfg,
1411 struct v4l2_subdev_frame_interval_enum *fie)
1412 {
1413 if (fie->index >= ARRAY_SIZE(supported_modes))
1414 return -EINVAL;
1415
1416 fie->code = supported_modes[fie->index].bus_fmt;
1417
1418 fie->width = supported_modes[fie->index].width;
1419 fie->height = supported_modes[fie->index].height;
1420 fie->interval = supported_modes[fie->index].max_fps;
1421 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1422 return 0;
1423 }
1424
1425 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1426 #define DST_WIDTH 3840
1427 #define DST_HEIGHT 2160
1428
imx334_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1429 static int imx334_get_selection(struct v4l2_subdev *sd,
1430 struct v4l2_subdev_pad_config *cfg,
1431 struct v4l2_subdev_selection *sel)
1432 {
1433 struct imx334 *imx334 = to_imx334(sd);
1434
1435 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1436 sel->r.left = CROP_START(imx334->cur_mode->width, DST_WIDTH);
1437 sel->r.width = DST_WIDTH;
1438 sel->r.top = CROP_START(imx334->cur_mode->height, DST_HEIGHT);
1439 sel->r.height = DST_HEIGHT;
1440 return 0;
1441 }
1442 return -EINVAL;
1443 }
1444
1445 static const struct dev_pm_ops imx334_pm_ops = {
1446 SET_RUNTIME_PM_OPS(imx334_runtime_suspend,
1447 imx334_runtime_resume, NULL)
1448 };
1449
1450 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1451 static const struct v4l2_subdev_internal_ops imx334_internal_ops = {
1452 .open = imx334_open,
1453 };
1454 #endif
1455
1456 static const struct v4l2_subdev_core_ops imx334_core_ops = {
1457 .s_power = imx334_s_power,
1458 .ioctl = imx334_ioctl,
1459 #ifdef CONFIG_COMPAT
1460 .compat_ioctl32 = imx334_compat_ioctl32,
1461 #endif
1462 };
1463
1464 static const struct v4l2_subdev_video_ops imx334_video_ops = {
1465 .s_stream = imx334_s_stream,
1466 .g_frame_interval = imx334_g_frame_interval,
1467 };
1468
1469 static const struct v4l2_subdev_pad_ops imx334_pad_ops = {
1470 .enum_mbus_code = imx334_enum_mbus_code,
1471 .enum_frame_size = imx334_enum_frame_sizes,
1472 .enum_frame_interval = imx334_enum_frame_interval,
1473 .get_fmt = imx334_get_fmt,
1474 .set_fmt = imx334_set_fmt,
1475 .get_selection = imx334_get_selection,
1476 .get_mbus_config = imx334_g_mbus_config,
1477 };
1478
1479 static const struct v4l2_subdev_ops imx334_subdev_ops = {
1480 .core = &imx334_core_ops,
1481 .video = &imx334_video_ops,
1482 .pad = &imx334_pad_ops,
1483 };
1484
imx334_set_ctrl(struct v4l2_ctrl * ctrl)1485 static int imx334_set_ctrl(struct v4l2_ctrl *ctrl)
1486 {
1487 struct imx334 *imx334 = container_of(ctrl->handler,
1488 struct imx334, ctrl_handler);
1489 struct i2c_client *client = imx334->client;
1490 s64 max;
1491 int ret = 0;
1492 u32 shr0 = 0;
1493 u32 vts = 0;
1494 u32 flip = 0;
1495
1496 /* Propagate change of current control to all related controls */
1497 switch (ctrl->id) {
1498 case V4L2_CID_VBLANK:
1499 /* Update max exposure while meeting expected vblanking */
1500 max = imx334->cur_mode->height + ctrl->val - 4;
1501 __v4l2_ctrl_modify_range(imx334->exposure,
1502 imx334->exposure->minimum, max,
1503 imx334->exposure->step,
1504 imx334->exposure->default_value);
1505 break;
1506 }
1507
1508 if (!pm_runtime_get_if_in_use(&client->dev))
1509 return 0;
1510
1511 switch (ctrl->id) {
1512 case V4L2_CID_EXPOSURE:
1513 shr0 = imx334->cur_vts - ctrl->val;
1514 /* 4 least significant bits of expsoure are fractional part */
1515 ret = imx334_write_reg(imx334->client,
1516 IMX334_LF_EXPO_REG_H,
1517 IMX334_REG_VALUE_08BIT,
1518 IMX334_FETCH_EXP_H(shr0));
1519 ret |= imx334_write_reg(imx334->client,
1520 IMX334_LF_EXPO_REG_M,
1521 IMX334_REG_VALUE_08BIT,
1522 IMX334_FETCH_EXP_M(shr0));
1523 ret |= imx334_write_reg(imx334->client,
1524 IMX334_LF_EXPO_REG_L,
1525 IMX334_REG_VALUE_08BIT,
1526 IMX334_FETCH_EXP_L(shr0));
1527 break;
1528 case V4L2_CID_ANALOGUE_GAIN:
1529 ret = imx334_write_reg(imx334->client,
1530 IMX334_REG_GAIN,
1531 IMX334_REG_VALUE_08BIT, ctrl->val);
1532 break;
1533 case V4L2_CID_VBLANK:
1534 vts = ctrl->val + imx334->cur_mode->height;
1535 /*
1536 * vts of hdr mode is double to correct T-line calculation.
1537 * Restore before write to reg.
1538 */
1539 if (imx334->cur_mode->hdr_mode == HDR_X2) {
1540 vts = ((vts + 3) >> 2) * 4;
1541 imx334->cur_vts = vts;
1542 vts = vts >> 1;
1543 } else {
1544 imx334->cur_vts = vts;
1545 }
1546 ret = imx334_write_reg(imx334->client,
1547 IMX334_REG_VTS_H,
1548 IMX334_REG_VALUE_08BIT,
1549 IMX334_FETCH_VTS_H(vts));
1550 ret |= imx334_write_reg(imx334->client,
1551 IMX334_REG_VTS_M,
1552 IMX334_REG_VALUE_08BIT,
1553 IMX334_FETCH_VTS_M(vts));
1554 ret |= imx334_write_reg(imx334->client,
1555 IMX334_REG_VTS_L,
1556 IMX334_REG_VALUE_08BIT,
1557 IMX334_FETCH_VTS_L(vts));
1558 break;
1559 case V4L2_CID_TEST_PATTERN:
1560 ret = imx334_enable_test_pattern(imx334, ctrl->val);
1561 break;
1562 case V4L2_CID_HFLIP:
1563 ret = imx334_write_reg(imx334->client, IMX334_HREVERSE_REG,
1564 IMX334_REG_VALUE_08BIT, !!ctrl->val);
1565 break;
1566 case V4L2_CID_VFLIP:
1567 flip = ctrl->val;
1568 if (flip) {
1569 ret = imx334_write_reg(imx334->client, IMX334_VREVERSE_REG,
1570 IMX334_REG_VALUE_08BIT, !!flip);
1571 ret |= imx334_write_reg(imx334->client, 0x3080,
1572 IMX334_REG_VALUE_08BIT, 0xfe);
1573 ret |= imx334_write_reg(imx334->client, 0x309b,
1574 IMX334_REG_VALUE_08BIT, 0xfe);
1575 } else {
1576 ret = imx334_write_reg(imx334->client, IMX334_VREVERSE_REG,
1577 IMX334_REG_VALUE_08BIT, !!flip);
1578 ret |= imx334_write_reg(imx334->client, 0x3080,
1579 IMX334_REG_VALUE_08BIT, 0x02);
1580 ret |= imx334_write_reg(imx334->client, 0x309b,
1581 IMX334_REG_VALUE_08BIT, 0x02);
1582 }
1583 break;
1584 default:
1585 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1586 __func__, ctrl->id, ctrl->val);
1587 break;
1588 }
1589
1590 pm_runtime_put(&client->dev);
1591
1592 return ret;
1593 }
1594
1595 static const struct v4l2_ctrl_ops imx334_ctrl_ops = {
1596 .s_ctrl = imx334_set_ctrl,
1597 };
1598
imx334_initialize_controls(struct imx334 * imx334)1599 static int imx334_initialize_controls(struct imx334 *imx334)
1600 {
1601 const struct imx334_mode *mode;
1602 struct v4l2_ctrl_handler *handler;
1603 s64 exposure_max, vblank_def;
1604 u32 h_blank;
1605 int ret;
1606 s64 dst_pixel_rate = 0;
1607
1608 handler = &imx334->ctrl_handler;
1609 mode = imx334->cur_mode;
1610 ret = v4l2_ctrl_handler_init(handler, 9);
1611 if (ret)
1612 return ret;
1613 handler->lock = &imx334->mutex;
1614
1615 imx334->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1616 V4L2_CID_LINK_FREQ,
1617 2, 0, link_freq_menu_items);
1618
1619 dst_pixel_rate = ((u32)link_freq_menu_items[mode->mipi_freq_idx]) /
1620 mode->bpp * 2 * IMX334_LANES;
1621
1622 imx334->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1623 V4L2_CID_PIXEL_RATE,
1624 0, PIXEL_RATE_WITH_891M_10BIT,
1625 1, dst_pixel_rate);
1626 v4l2_ctrl_s_ctrl(imx334->link_freq,
1627 mode->mipi_freq_idx);
1628 imx334->cur_mipi_freq_idx = mode->mipi_freq_idx;
1629 imx334->cur_vclk_freq = mode->vclk_freq;
1630
1631 h_blank = mode->hts_def - mode->width;
1632 imx334->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1633 h_blank, h_blank, 1, h_blank);
1634 if (imx334->hblank)
1635 imx334->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1636
1637 vblank_def = mode->vts_def - mode->height;
1638 imx334->vblank = v4l2_ctrl_new_std(handler, &imx334_ctrl_ops,
1639 V4L2_CID_VBLANK, vblank_def,
1640 IMX334_VTS_MAX - mode->height,
1641 1, vblank_def);
1642 imx334->cur_vts = mode->vts_def;
1643 exposure_max = mode->vts_def - 4;
1644 imx334->exposure = v4l2_ctrl_new_std(handler, &imx334_ctrl_ops,
1645 V4L2_CID_EXPOSURE,
1646 IMX334_EXPOSURE_MIN,
1647 exposure_max,
1648 IMX334_EXPOSURE_STEP,
1649 mode->exp_def);
1650
1651 imx334->anal_gain = v4l2_ctrl_new_std(handler, &imx334_ctrl_ops,
1652 V4L2_CID_ANALOGUE_GAIN,
1653 IMX334_GAIN_MIN,
1654 IMX334_GAIN_MAX,
1655 IMX334_GAIN_STEP,
1656 IMX334_GAIN_DEFAULT);
1657
1658 imx334->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1659 &imx334_ctrl_ops,
1660 V4L2_CID_TEST_PATTERN,
1661 ARRAY_SIZE(imx334_test_pattern_menu) - 1,
1662 0, 0, imx334_test_pattern_menu);
1663
1664 v4l2_ctrl_new_std(handler, &imx334_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1665 v4l2_ctrl_new_std(handler, &imx334_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1666
1667 if (handler->error) {
1668 ret = handler->error;
1669 dev_err(&imx334->client->dev,
1670 "Failed to init controls( %d )\n", ret);
1671 goto err_free_handler;
1672 }
1673
1674 imx334->subdev.ctrl_handler = handler;
1675 imx334->has_init_exp = false;
1676 return 0;
1677
1678 err_free_handler:
1679 v4l2_ctrl_handler_free(handler);
1680
1681 return ret;
1682 }
1683
imx334_check_sensor_id(struct imx334 * imx334,struct i2c_client * client)1684 static int imx334_check_sensor_id(struct imx334 *imx334,
1685 struct i2c_client *client)
1686 {
1687 struct device *dev = &imx334->client->dev;
1688 u32 id = 0;
1689 int ret, i;
1690
1691 for (i = 0; i < 10; i++) {
1692 ret = imx334_read_reg(client, IMX334_REG_CHIP_ID,
1693 IMX334_REG_VALUE_08BIT, &id);
1694 if (id == CHIP_ID)
1695 break;
1696 }
1697
1698 if (id != CHIP_ID) {
1699 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1700 usleep_range(2000, 4000);
1701 return -ENODEV;
1702 }
1703
1704 dev_info(dev, "Detected imx334 id:%06x\n", CHIP_ID);
1705
1706 return 0;
1707 }
1708
imx334_configure_regulators(struct imx334 * imx334)1709 static int imx334_configure_regulators(struct imx334 *imx334)
1710 {
1711 unsigned int i;
1712
1713 for (i = 0; i < IMX334_NUM_SUPPLIES; i++)
1714 imx334->supplies[i].supply = imx334_supply_names[i];
1715
1716 return devm_regulator_bulk_get(&imx334->client->dev,
1717 IMX334_NUM_SUPPLIES,
1718 imx334->supplies);
1719 }
1720
imx334_probe(struct i2c_client * client,const struct i2c_device_id * id)1721 static int imx334_probe(struct i2c_client *client,
1722 const struct i2c_device_id *id)
1723 {
1724 struct device *dev = &client->dev;
1725 struct device_node *node = dev->of_node;
1726 struct imx334 *imx334;
1727 struct v4l2_subdev *sd;
1728 char facing[2];
1729 int ret;
1730 u32 i, hdr_mode = 0;
1731
1732 dev_info(dev, "driver version: %02x.%02x.%02x",
1733 DRIVER_VERSION >> 16,
1734 (DRIVER_VERSION & 0xff00) >> 8,
1735 DRIVER_VERSION & 0x00ff);
1736
1737 imx334 = devm_kzalloc(dev, sizeof(*imx334), GFP_KERNEL);
1738 if (!imx334)
1739 return -ENOMEM;
1740
1741 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1742 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1743 &imx334->module_index);
1744 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1745 &imx334->module_facing);
1746 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1747 &imx334->module_name);
1748 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1749 &imx334->len_name);
1750 if (ret) {
1751 dev_err(dev, "could not get module information!\n");
1752 return -EINVAL;
1753 }
1754
1755 imx334->client = client;
1756 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1757 if (hdr_mode == supported_modes[i].hdr_mode) {
1758 imx334->cur_mode = &supported_modes[i];
1759 break;
1760 }
1761 }
1762 if (i == ARRAY_SIZE(supported_modes))
1763 imx334->cur_mode = &supported_modes[0];
1764
1765 imx334->xvclk = devm_clk_get(dev, "xvclk");
1766 if (IS_ERR(imx334->xvclk)) {
1767 dev_err(dev, "Failed to get xvclk\n");
1768 return -EINVAL;
1769 }
1770
1771 imx334->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1772 if (IS_ERR(imx334->reset_gpio))
1773 dev_warn(dev, "Failed to get reset-gpios\n");
1774
1775 imx334->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1776 if (IS_ERR(imx334->pwdn_gpio))
1777 dev_warn(dev, "Failed to get pwdn-gpios\n");
1778
1779 imx334->pinctrl = devm_pinctrl_get(dev);
1780 if (!IS_ERR(imx334->pinctrl)) {
1781 imx334->pins_default =
1782 pinctrl_lookup_state(imx334->pinctrl,
1783 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1784 if (IS_ERR(imx334->pins_default))
1785 dev_info(dev, "could not get default pinstate\n");
1786
1787 imx334->pins_sleep =
1788 pinctrl_lookup_state(imx334->pinctrl,
1789 OF_CAMERA_PINCTRL_STATE_SLEEP);
1790 if (IS_ERR(imx334->pins_sleep))
1791 dev_info(dev, "could not get sleep pinstate\n");
1792 } else {
1793 dev_info(dev, "no pinctrl\n");
1794 }
1795
1796 ret = imx334_configure_regulators(imx334);
1797 if (ret) {
1798 dev_err(dev, "Failed to get power regulators\n");
1799 return ret;
1800 }
1801
1802 mutex_init(&imx334->mutex);
1803
1804 sd = &imx334->subdev;
1805 v4l2_i2c_subdev_init(sd, client, &imx334_subdev_ops);
1806
1807 ret = imx334_initialize_controls(imx334);
1808 if (ret)
1809 goto err_destroy_mutex;
1810
1811 ret = __imx334_power_on(imx334);
1812 if (ret)
1813 goto err_free_handler;
1814
1815 ret = imx334_check_sensor_id(imx334, client);
1816 if (ret)
1817 goto err_power_off;
1818
1819 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1820 sd->internal_ops = &imx334_internal_ops;
1821 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1822 #endif
1823 #if defined(CONFIG_MEDIA_CONTROLLER)
1824 imx334->pad.flags = MEDIA_PAD_FL_SOURCE;
1825 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1826 ret = media_entity_pads_init(&sd->entity, 1, &imx334->pad);
1827 if (ret < 0)
1828 goto err_power_off;
1829 #endif
1830
1831 memset(facing, 0, sizeof(facing));
1832 if (strcmp(imx334->module_facing, "back") == 0)
1833 facing[0] = 'b';
1834 else
1835 facing[0] = 'f';
1836
1837 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1838 imx334->module_index, facing,
1839 IMX334_NAME, dev_name(sd->dev));
1840 ret = v4l2_async_register_subdev_sensor_common(sd);
1841 if (ret) {
1842 dev_err(dev, "v4l2 async register subdev failed\n");
1843 goto err_clean_entity;
1844 }
1845
1846 pm_runtime_set_active(dev);
1847 pm_runtime_enable(dev);
1848 pm_runtime_idle(dev);
1849
1850 return 0;
1851
1852 err_clean_entity:
1853 #if defined(CONFIG_MEDIA_CONTROLLER)
1854 media_entity_cleanup(&sd->entity);
1855 #endif
1856 err_power_off:
1857 __imx334_power_off(imx334);
1858 err_free_handler:
1859 v4l2_ctrl_handler_free(&imx334->ctrl_handler);
1860 err_destroy_mutex:
1861 mutex_destroy(&imx334->mutex);
1862
1863 return ret;
1864 }
1865
imx334_remove(struct i2c_client * client)1866 static int imx334_remove(struct i2c_client *client)
1867 {
1868 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1869 struct imx334 *imx334 = to_imx334(sd);
1870
1871 v4l2_async_unregister_subdev(sd);
1872 #if defined(CONFIG_MEDIA_CONTROLLER)
1873 media_entity_cleanup(&sd->entity);
1874 #endif
1875 v4l2_ctrl_handler_free(&imx334->ctrl_handler);
1876 mutex_destroy(&imx334->mutex);
1877
1878 pm_runtime_disable(&client->dev);
1879 if (!pm_runtime_status_suspended(&client->dev))
1880 __imx334_power_off(imx334);
1881 pm_runtime_set_suspended(&client->dev);
1882
1883 return 0;
1884 }
1885
1886 #if IS_ENABLED(CONFIG_OF)
1887 static const struct of_device_id imx334_of_match[] = {
1888 { .compatible = "sony,imx334" },
1889 {},
1890 };
1891 MODULE_DEVICE_TABLE(of, imx334_of_match);
1892 #endif
1893
1894 static const struct i2c_device_id imx334_match_id[] = {
1895 { "sony,imx334", 0 },
1896 { },
1897 };
1898
1899 static struct i2c_driver imx334_i2c_driver = {
1900 .driver = {
1901 .name = IMX334_NAME,
1902 .pm = &imx334_pm_ops,
1903 .of_match_table = of_match_ptr(imx334_of_match),
1904 },
1905 .probe = &imx334_probe,
1906 .remove = &imx334_remove,
1907 .id_table = imx334_match_id,
1908 };
1909
sensor_mod_init(void)1910 static int __init sensor_mod_init(void)
1911 {
1912 return i2c_add_driver(&imx334_i2c_driver);
1913 }
1914
sensor_mod_exit(void)1915 static void __exit sensor_mod_exit(void)
1916 {
1917 i2c_del_driver(&imx334_i2c_driver);
1918 }
1919
1920 device_initcall_sync(sensor_mod_init);
1921 module_exit(sensor_mod_exit);
1922
1923 MODULE_DESCRIPTION("Sony imx334 sensor driver");
1924 MODULE_LICENSE("GPL v2");
1925