1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx327 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 * V0.0X01.0X03 add enum_frame_interval function.
7 * V0.0X01.0X04 support lvds interface.
8 * V0.0X01.0X05 add quick stream on/off
9 * V0.0X01.0X06 fixed linear mode exp calc
10 */
11
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/sysfs.h>
21 #include <linux/slab.h>
22 #include <linux/version.h>
23 #include <linux/rk-camera-module.h>
24 #include <linux/of_graph.h>
25 #include <media/media-entity.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-subdev.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-mediabus.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/rk-preisp.h>
33
34 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
35 #ifndef V4L2_CID_DIGITAL_GAIN
36 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
37 #endif
38
39 #define IMX327_LINK_FREQ_111M 111370000
40 #define IMX327_LINK_FREQ_222M 222750000
41 #define IMX327_2LANES 2
42 #define IMX327_4LANES 4
43 #define IMX327_BITS_PER_SAMPLE 10
44
45 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
46 #define IMX327_PIXEL_RATE_NORMAL (IMX327_LINK_FREQ_111M * 2 / 10 * IMX327_4LANES)
47 #define IMX327_PIXEL_RATE_HDR (IMX327_LINK_FREQ_222M * 2 / 10 * IMX327_4LANES)
48
49 #define IMX327_XVCLK_FREQ 37125000
50
51 #define CHIP_ID 0xb2
52 #define IMX327_REG_CHIP_ID 0x301e
53
54 #define IMX327_REG_CTRL_MODE 0x3000
55 #define IMX327_MODE_SW_STANDBY 0x1
56 #define IMX327_MODE_STREAMING 0x0
57
58 #define IMX327_REG_SHS1_H 0x3022
59 #define IMX327_REG_SHS1_M 0x3021
60 #define IMX327_REG_SHS1_L 0x3020
61
62 #define IMX327_REG_SHS2_H 0x3026
63 #define IMX327_REG_SHS2_M 0x3025
64 #define IMX327_REG_SHS2_L 0x3024
65
66 #define IMX327_REG_RHS1_H 0x3032
67 #define IMX327_REG_RHS1_M 0x3031
68 #define IMX327_REG_RHS1_L 0x3030
69
70 #define IMX327_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 16) & 0x0F)
71 #define IMX327_FETCH_MID_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF)
72 #define IMX327_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF)
73
74 #define IMX327_EXPOSURE_MIN 2
75 #define IMX327_EXPOSURE_STEP 1
76 #define IMX327_VTS_MAX 0x7fff
77
78 #define IMX327_GAIN_SWITCH_REG 0x3009
79 #define IMX327_REG_LF_GAIN 0x3014
80 #define IMX327_REG_SF_GAIN 0x30f2
81 #define IMX327_GAIN_MIN 0x00
82 #define IMX327_GAIN_MAX 0xee
83 #define IMX327_GAIN_STEP 1
84 #define IMX327_GAIN_DEFAULT 0x00
85
86 #define IMX327_GROUP_HOLD_REG 0x3001
87 #define IMX327_GROUP_HOLD_START 0x01
88 #define IMX327_GROUP_HOLD_END 0x00
89
90 #define USED_TEST_PATTERN
91 #ifdef USED_TEST_PATTERN
92 #define IMX327_REG_TEST_PATTERN 0x308c
93 #define IMX327_TEST_PATTERN_ENABLE BIT(0)
94 #endif
95
96 #define IMX327_REG_VTS_H 0x301a
97 #define IMX327_REG_VTS_M 0x3019
98 #define IMX327_REG_VTS_L 0x3018
99 #define IMX327_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 16) & 0x03)
100 #define IMX327_FETCH_MID_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF)
101 #define IMX327_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF)
102
103 #define REG_NULL 0xFFFF
104 #define REG_DELAY 0xFFFE
105
106 #define IMX327_REG_VALUE_08BIT 1
107 #define IMX327_REG_VALUE_16BIT 2
108 #define IMX327_REG_VALUE_24BIT 3
109
110 static bool g_isHCG;
111
112 #define IMX327_NAME "imx327"
113
114 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
115 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
116
117 #define IMX327_FLIP_REG 0x3007
118 #define MIRROR_BIT_MASK BIT(1)
119 #define FLIP_BIT_MASK BIT(0)
120
121 static const char * const imx327_supply_names[] = {
122 "avdd", /* Analog power */
123 "dovdd", /* Digital I/O power */
124 "dvdd", /* Digital core power */
125 };
126
127 #define IMX327_NUM_SUPPLIES ARRAY_SIZE(imx327_supply_names)
128
129 struct regval {
130 u16 addr;
131 u8 val;
132 };
133
134 struct imx327_mode {
135 u32 bus_fmt;
136 u32 width;
137 u32 height;
138 struct v4l2_fract max_fps;
139 u32 hts_def;
140 u32 vts_def;
141 u32 exp_def;
142 const struct regval *reg_list;
143 u32 hdr_mode;
144 struct rkmodule_lvds_cfg lvds_cfg;
145 };
146
147 struct imx327 {
148 struct i2c_client *client;
149 struct clk *xvclk;
150 struct gpio_desc *reset_gpio;
151 struct gpio_desc *pwdn_gpio;
152 struct regulator_bulk_data supplies[IMX327_NUM_SUPPLIES];
153
154 struct pinctrl *pinctrl;
155 struct pinctrl_state *pins_default;
156 struct pinctrl_state *pins_sleep;
157
158 struct v4l2_subdev subdev;
159 struct media_pad pad;
160 struct v4l2_ctrl_handler ctrl_handler;
161 struct v4l2_ctrl *exposure;
162 struct v4l2_ctrl *anal_gain;
163 struct v4l2_ctrl *digi_gain;
164 struct v4l2_ctrl *hblank;
165 struct v4l2_ctrl *vblank;
166 struct v4l2_ctrl *pixel_rate;
167 struct v4l2_ctrl *link_freq;
168 struct v4l2_ctrl *h_flip;
169 struct v4l2_ctrl *v_flip;
170 #ifdef USED_TEST_PATTERN
171 struct v4l2_ctrl *test_pattern;
172 #endif
173 struct mutex mutex;
174 bool streaming;
175 bool power_on;
176 const struct imx327_mode *support_modes;
177 u32 support_modes_num;
178 const struct imx327_mode *cur_mode;
179 u32 module_index;
180 const char *module_facing;
181 const char *module_name;
182 const char *len_name;
183 u32 cur_vts;
184 bool has_init_exp;
185 struct preisp_hdrae_exp_s init_hdrae_exp;
186 struct v4l2_fwnode_endpoint bus_cfg;
187 u8 flip;
188 };
189
190 #define to_imx327(sd) container_of(sd, struct imx327, subdev)
191
192 /*
193 * Xclk 37.125Mhz
194 */
195 static const struct regval imx327_global_regs[] = {
196 {REG_NULL, 0x00},
197 };
198
199 /*
200 * Xclk 37.125Mhz
201 * max_framerate 30fps
202 * lvds_datarate per lane 222.75Mbps 4 lane
203 */
204 static const struct regval imx327_linear_1920x1080_lvds_regs[] = {
205 {0x3003, 0x01},
206 {REG_DELAY, 0x10},
207 {0x3000, 0x01},
208 {0x3001, 0x00},
209 {0x3002, 0x01},
210 {0x3005, 0x00},
211 {0x3007, 0x00},
212 {0x3009, 0x02},
213 {0x300a, 0x3c},
214 {0x3010, 0x21},
215 {0x3011, 0x0a},
216 {0x3018, 0x46},
217 {0x3019, 0x05},
218 {0x301c, 0x30},
219 {0x301d, 0x11},
220 {0x3046, 0xe0},
221 {0x304b, 0x0a},
222 {0x305c, 0x18},
223 {0x305d, 0x00},
224 {0x305e, 0x20},
225 {0x305f, 0x01},
226 {0x309e, 0x4a},
227 {0x309f, 0x4a},
228 {0x311c, 0x0e},
229 {0x3128, 0x04},
230 {0x3129, 0x1d},
231 {0x313b, 0x41},
232 {0x315e, 0x1a},
233 {0x3164, 0x1a},
234 {0x317c, 0x12},
235 {0x31ec, 0x37},
236 {0x3480, 0x49},
237 {0x3002, 0x00},
238 {REG_NULL, 0x00},
239 };
240
241 /*
242 * Xclk 37.125Mhz
243 * max_framerate 30fps
244 * lvds_datarate per lane 445.5Mbps 4 lane
245 */
246 static const struct regval imx327_hdr2_1920x1080_lvds_regs[] = {
247 {0x3003, 0x01},
248 {REG_DELAY, 0x10},
249 {0x3000, 0x01},
250 {0x3001, 0x00},
251 {0x3002, 0x01},
252 {0x3005, 0x00},
253 {0x3007, 0x40},
254 {0x3009, 0x01},
255 {0x300a, 0x3c},
256 {0x300c, 0x11},
257 {0x3011, 0x02},
258 {0x3018, 0xb8},/* VMAX L */
259 {0x3019, 0x05},/* VMAX M */
260 {0x301c, 0xec},/* HMAX L */
261 {0x301d, 0x07},/* HMAX H */
262 {0x3020, 0x02},//hdr+ shs1 l short
263 {0x3021, 0x00},//hdr+ shs1 m
264 {0x3024, 0xc9},//hdr+ shs2 l
265 {0x3025, 0x07},//hdr+ shs2 m
266 {0x3030, 0xe1},//hdr+ IMX327_RHS1
267 {0x3031, 0x00},//hdr+IMX327_RHS1
268 {0x3045, 0x03},//hdr+
269 {0x3046, 0xe0},
270 {0x304b, 0x0a},
271 {0x305c, 0x18},
272 {0x305d, 0x03},
273 {0x305e, 0x20},
274 {0x305f, 0x01},
275 {0x309e, 0x4a},
276 {0x309f, 0x4a},
277 {0x30d2, 0x19},
278 {0x30d7, 0x03},
279 {0x3106, 0x11},
280 {0x3129, 0x1d},
281 {0x313b, 0x61},
282 {0x315e, 0x1a},
283 {0x3164, 0x1a},
284 {0x317c, 0x12},
285 {0x31ec, 0x37},
286 {0x3414, 0x00},
287 {0x3415, 0x00},
288 {0x3480, 0x49},
289 {0x31a0, 0xb4},
290 {0x31a1, 0x02},
291 {0x303c, 0x04},//Y offset
292 {0x303d, 0x00},
293 {0x303e, 0x41},
294 {0x303f, 0x04},//height
295 {0x303A, 0x08},//hdr+
296 {0x3010, 0x61},//hdr+ gain 1frame FPGC
297 {0x3014, 0x00},//hdr+ gain 1frame long
298 {0x30F0, 0x64},//hdr+ gain 2frame FPGC
299 {0x30f2, 0x00},//hdr+ gain 2frame short
300 {0x3002, 0x00},
301 {REG_NULL, 0x00},
302 };
303
304 /*
305 * Xclk 37.125Mhz
306 * max_framerate 30fps
307 * mipi_datarate per lane 222.75Mbps 4 lane
308 */
309 static const struct regval imx327_linear_1920x1080_mipi_regs[] = {
310 {0x3003, 0x01},
311 {REG_DELAY, 0x10},
312 {0x3000, 0x01},
313 {0x3001, 0x00},
314 {0x3002, 0x01},
315 {0x3005, 0x00},
316 {0x3007, 0x00},
317 {0x3009, 0x02},
318 {0x300A, 0x3c},
319 {0x3010, 0x21},
320 {0x3011, 0x0a},
321 {0x3018, 0x46},
322 {0x3019, 0x05},
323 {0x301C, 0x30},
324 {0x301D, 0x11},
325 {0x3046, 0x00},
326 {0x304B, 0x0A},
327 {0x305C, 0x18},
328 {0x305D, 0x03},
329 {0x305E, 0x20},
330 {0x305F, 0x01},
331 {0x309E, 0x4A},
332 {0x309F, 0x4A},
333 {0x311c, 0x0e},
334 {0x3128, 0x04},
335 {0x3129, 0x1d},
336 {0x313B, 0x41},
337 {0x315E, 0x1A},
338 {0x3164, 0x1A},
339 {0x317C, 0x12},
340 {0x31EC, 0x37},
341 {0x3405, 0x20},
342 {0x3407, 0x03},
343 {0x3414, 0x0A},
344 {0x3418, 0x49},
345 {0x3419, 0x04},
346 {0x3441, 0x0a},
347 {0x3442, 0x0a},
348 {0x3443, 0x03},
349 {0x3444, 0x20},
350 {0x3445, 0x25},
351 {0x3446, 0x47},
352 {0x3447, 0x00},
353 {0x3448, 0x1f},
354 {0x3449, 0x00},
355 {0x344A, 0x17},
356 {0x344B, 0x00},
357 {0x344C, 0x0F},
358 {0x344D, 0x00},
359 {0x344E, 0x17},
360 {0x344F, 0x00},
361 {0x3450, 0x47},
362 {0x3451, 0x00},
363 {0x3452, 0x0F},
364 {0x3453, 0x00},
365 {0x3454, 0x0f},
366 {0x3455, 0x00},
367 {0x3472, 0x9c},
368 {0x3473, 0x07},
369 {0x3480, 0x49},
370 {0x3002, 0x00},
371 {REG_NULL, 0x00},
372 };
373
374 /*
375 * Xclk 37.125Mhz
376 * max_framerate 30fps
377 * mipi_datarate per lane 445.5Mbps 4 lane
378 */
379 static const struct regval imx327_hdr2_1920x1080_mipi_regs[] = {
380 {0x3003, 0x01},
381 {REG_DELAY, 0x10},
382 {0x3000, 0x01},
383 {0x3001, 0x00},
384 {0x3002, 0x01},
385 {0x3005, 0x00},
386 {0x3007, 0x40},
387 {0x3009, 0x01},
388 {0x300a, 0x3c},
389 {0x300c, 0x11}, //hdr+
390 {0x3011, 0x02},
391 {0x3018, 0xb8},/* VMAX L */
392 {0x3019, 0x05},/* VMAX M */
393 {0x301a, 0x00},
394 {0x301c, 0xEc},/* HMAX L */
395 {0x301d, 0x07},/* HMAX H */
396 {0x3045, 0x05},//hdr+
397 {0x3046, 0x00},
398 {0x304b, 0x0a},
399 {0x305c, 0x18},
400 {0x305d, 0x03},
401 {0x305e, 0x20},
402 {0x305f, 0x01},
403 {0x309e, 0x4a},
404 {0x309f, 0x4a},
405 {0x30d2, 0x19},
406 {0x30d7, 0x03},
407 {0x3106, 0x11},//hdr+
408 {0x3129, 0x1d},
409 {0x313b, 0x61},
410 {0x315e, 0x1a},
411 {0x3164, 0x1a},
412 {0x317c, 0x12},
413 {0x31ec, 0x37},
414 {0x3405, 0x10},
415 {0x3407, 0x03},
416 {0x3414, 0x00},
417 {0x3415, 0x00},//hdr+
418 {0x3418, 0x72},
419 {0x3419, 0x09},
420 {0x3441, 0x0a},
421 {0x3442, 0x0a},
422 {0x3443, 0x03},
423 {0x3444, 0x20},
424 {0x3445, 0x25},
425 {0x3446, 0x57},
426 {0x3447, 0x00},
427 {0x3448, 0x37},//37?
428 {0x3449, 0x00},
429 {0x344a, 0x1f},
430 {0x344b, 0x00},
431 {0x344c, 0x1f},
432 {0x344d, 0x00},
433 {0x344e, 0x1f},
434 {0x344f, 0x00},
435 {0x3450, 0x77},
436 {0x3451, 0x00},
437 {0x3452, 0x1f},
438 {0x3453, 0x00},
439 {0x3454, 0x17},
440 {0x3455, 0x00},
441 {0x3472, 0xa0},
442 {0x3473, 0x07},
443 {0x347b, 0x23},
444 {0x3480, 0x49},
445 {0x31a0, 0xb4},//hdr+
446 {0x31a1, 0x02},//hdr+
447 {0x3020, 0x02},//hdr+ shs1 l short
448 {0x3021, 0x00},//hdr+ shs1 m
449 {0x3022, 0x00},//hdr+ shs1 h
450 {0x3030, 0xe1},//hdr+ IMX327_RHS1
451 {0x3031, 0x00},//hdr+IMX327_RHS1
452 {0x3032, 0x00},//hdr+
453 {0x31A0, 0xe8},//hdr+ HBLANK1
454 {0x31A1, 0x01},//hdr+
455 {0x303c, 0x04},
456 {0x303d, 0x00},
457 {0x303e, 0x41},
458 {0x303f, 0x04},
459 {0x303A, 0x08},//hdr+
460 {0x3024, 0xc9},//hdr+ shs2 l
461 {0x3025, 0x06},//hdr+ shs2 m
462 {0x3026, 0x00},//hdr+ shs2 h
463 {0x3010, 0x61},//hdr+ gain 1frame FPGC
464 {0x3014, 0x00},//hdr+ gain 1frame long
465 {0x30F0, 0x64},//hdr+ gain 2frame FPGC
466 {0x30f2, 0x00},//hdr+ gain 2frame short
467 {0x3002, 0x00},
468 {REG_NULL, 0x00},
469 };
470
471 /*
472 * The width and height must be configured to be
473 * the same as the current output resolution of the sensor.
474 * The input width of the isp needs to be 16 aligned.
475 * The input height of the isp needs to be 8 aligned.
476 * If the width or height does not meet the alignment rules,
477 * you can configure the cropping parameters with the following function to
478 * crop out the appropriate resolution.
479 * struct v4l2_subdev_pad_ops {
480 * .get_selection
481 * }
482 */
483 static const struct imx327_mode lvds_supported_modes[] = {
484 {
485 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
486 .width = 1948,
487 .height = 1110,
488 .max_fps = {
489 .numerator = 10000,
490 .denominator = 250000,
491 },
492 .exp_def = 0x03fe,
493 .hts_def = 0x1130,
494 .vts_def = 0x0546,
495 .reg_list = imx327_linear_1920x1080_lvds_regs,
496 .hdr_mode = NO_HDR,
497 .lvds_cfg = {
498 .mode = LS_FIRST,
499 .frm_sync_code[LVDS_CODE_GRP_LINEAR] = {
500 .odd_sync_code = {
501 .act = {
502 .sav = 0x200,
503 .eav = 0x274,
504 },
505 .blk = {
506 .sav = 0x2ac,
507 .eav = 0x2d8,
508 },
509 },
510 },
511 },
512 }, {
513 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
514 .width = 1948,
515 .height = 1098,
516 .max_fps = {
517 .numerator = 10000,
518 .denominator = 250000,
519 },
520 .exp_def = 0x0473,
521 .hts_def = 0x07ec,
522 .vts_def = 0x05b8 * 2,
523 .reg_list = imx327_hdr2_1920x1080_lvds_regs,
524 .hdr_mode = HDR_X2,
525 .lvds_cfg = {
526 .mode = SONY_DOL_HDR_1,
527 .frm_sync_code[LVDS_CODE_GRP_LONG] = {
528 .odd_sync_code = {
529 .act = {
530 .sav = 0x001,
531 .eav = 0x075,
532 },
533 .blk = {
534 .sav = 0x0ac,
535 .eav = 0x0d8,
536 },
537 },
538 .even_sync_code = {
539 .act = {
540 .sav = 0x101,
541 .eav = 0x175,
542 },
543 .blk = {
544 .sav = 0x1ac,
545 .eav = 0x1d8,
546 },
547 },
548 },
549 .frm_sync_code[LVDS_CODE_GRP_SHORT] = {
550 .odd_sync_code = {
551 .act = {
552 .sav = 0x002,
553 .eav = 0x076,
554 },
555 .blk = {
556 .sav = 0x0ac,
557 .eav = 0x0d8,
558 },
559 },
560 .even_sync_code = {
561 .act = {
562 .sav = 0x102,
563 .eav = 0x176,
564 },
565 .blk = {
566 .sav = 0x1ac,
567 .eav = 0x1d8,
568 },
569 },
570 },
571 },
572 },
573 };
574
575 static const struct imx327_mode mipi_supported_modes[] = {
576 {
577 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
578 .width = 1948,
579 .height = 1097,
580 .max_fps = {
581 .numerator = 10000,
582 .denominator = 250000,
583 },
584 .exp_def = 0x03fe,
585 .hts_def = 0x1130,
586 .vts_def = 0x0546,
587 .reg_list = imx327_linear_1920x1080_mipi_regs,
588 .hdr_mode = NO_HDR,
589 }, {
590 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
591 .width = 1952,
592 .height = 1089,
593 .max_fps = {
594 .numerator = 10000,
595 .denominator = 250000,
596 },
597 .exp_def = 0x0473,
598 .hts_def = 0x07ec,
599 .vts_def = 0x05b8 * 2,
600 .reg_list = imx327_hdr2_1920x1080_mipi_regs,
601 .hdr_mode = HDR_X2,
602 },
603 };
604
605 static const s64 link_freq_menu_items[] = {
606 IMX327_LINK_FREQ_111M,
607 IMX327_LINK_FREQ_222M
608 };
609
610 #ifdef USED_TEST_PATTERN
611 static const char * const imx327_test_pattern_menu[] = {
612 "Disabled",
613 "Bar Type 1",
614 "Bar Type 2",
615 "Bar Type 3",
616 "Bar Type 4",
617 "Bar Type 5",
618 "Bar Type 6",
619 "Bar Type 7",
620 "Bar Type 8",
621 "Bar Type 9",
622 "Bar Type 10",
623 "Bar Type 11",
624 "Bar Type 12",
625 "Bar Type 13",
626 "Bar Type 14",
627 "Bar Type 15"
628 };
629 #endif
630
631 /* Write registers up to 4 at a time */
imx327_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)632 static int imx327_write_reg(struct i2c_client *client, u16 reg,
633 u32 len, u32 val)
634 {
635 u32 buf_i, val_i;
636 u8 buf[6];
637 u8 *val_p;
638 __be32 val_be;
639
640 if (len > 4)
641 return -EINVAL;
642
643 buf[0] = reg >> 8;
644 buf[1] = reg & 0xff;
645
646 val_be = cpu_to_be32(val);
647 val_p = (u8 *)&val_be;
648 buf_i = 2;
649 val_i = 4 - len;
650
651 while (val_i < 4)
652 buf[buf_i++] = val_p[val_i++];
653
654 if (i2c_master_send(client, buf, len + 2) != len + 2)
655 return -EIO;
656
657 return 0;
658 }
659
imx327_write_array(struct i2c_client * client,const struct regval * regs)660 static int imx327_write_array(struct i2c_client *client,
661 const struct regval *regs)
662 {
663 u32 i;
664 int ret = 0;
665
666 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
667 if (unlikely(regs[i].addr == REG_DELAY))
668 usleep_range(regs[i].val * 1000, regs[i].val * 2000);
669 else
670 ret = imx327_write_reg(client, regs[i].addr,
671 IMX327_REG_VALUE_08BIT,
672 regs[i].val);
673
674 return ret;
675 }
676
677 /* Read registers up to 4 at a time */
imx327_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)678 static int imx327_read_reg(struct i2c_client *client, u16 reg,
679 unsigned int len, u32 *val)
680 {
681 struct i2c_msg msgs[2];
682 u8 *data_be_p;
683 __be32 data_be = 0;
684 __be16 reg_addr_be = cpu_to_be16(reg);
685 int ret;
686
687 if (len > 4 || !len)
688 return -EINVAL;
689
690 data_be_p = (u8 *)&data_be;
691 /* Write register address */
692 msgs[0].addr = client->addr;
693 msgs[0].flags = 0;
694 msgs[0].len = 2;
695 msgs[0].buf = (u8 *)®_addr_be;
696
697 /* Read data from register */
698 msgs[1].addr = client->addr;
699 msgs[1].flags = I2C_M_RD;
700 msgs[1].len = len;
701 msgs[1].buf = &data_be_p[4 - len];
702
703 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
704 if (ret != ARRAY_SIZE(msgs))
705 return -EIO;
706
707 *val = be32_to_cpu(data_be);
708 return 0;
709 }
710
imx327_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)711 static int imx327_set_fmt(struct v4l2_subdev *sd,
712 struct v4l2_subdev_pad_config *cfg,
713 struct v4l2_subdev_format *fmt)
714 {
715 struct imx327 *imx327 = to_imx327(sd);
716 const struct imx327_mode *mode;
717 s64 h_blank, vblank_def;
718 s32 dst_link_freq = 0;
719 s64 dst_pixel_rate = 0;
720
721 mutex_lock(&imx327->mutex);
722
723 mode = v4l2_find_nearest_size(imx327->support_modes,
724 imx327->support_modes_num,
725 width, height,
726 fmt->format.width, fmt->format.height);
727 fmt->format.code = mode->bus_fmt;
728 fmt->format.width = mode->width;
729 fmt->format.height = mode->height;
730 fmt->format.field = V4L2_FIELD_NONE;
731 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
732 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
733 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
734 #else
735 mutex_unlock(&imx327->mutex);
736 return -ENOTTY;
737 #endif
738 } else {
739 imx327->cur_mode = mode;
740 h_blank = mode->hts_def - mode->width;
741 __v4l2_ctrl_modify_range(imx327->hblank, h_blank,
742 h_blank, 1, h_blank);
743 vblank_def = mode->vts_def - mode->height;
744 __v4l2_ctrl_modify_range(imx327->vblank, vblank_def,
745 IMX327_VTS_MAX - mode->height,
746 1, vblank_def);
747 if (imx327->cur_mode->hdr_mode == NO_HDR) {
748 dst_link_freq = 0;
749 dst_pixel_rate = IMX327_LINK_FREQ_111M;
750 } else {
751 dst_link_freq = 1;
752 dst_pixel_rate = IMX327_LINK_FREQ_222M;
753 }
754 __v4l2_ctrl_s_ctrl_int64(imx327->pixel_rate,
755 dst_pixel_rate);
756 __v4l2_ctrl_s_ctrl(imx327->link_freq,
757 dst_link_freq);
758 imx327->cur_vts = mode->vts_def;
759 }
760
761 mutex_unlock(&imx327->mutex);
762
763 return 0;
764 }
765
imx327_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)766 static int imx327_get_fmt(struct v4l2_subdev *sd,
767 struct v4l2_subdev_pad_config *cfg,
768 struct v4l2_subdev_format *fmt)
769 {
770 struct imx327 *imx327 = to_imx327(sd);
771 const struct imx327_mode *mode = imx327->cur_mode;
772
773 mutex_lock(&imx327->mutex);
774 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
775 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
776 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
777 #else
778 mutex_unlock(&imx327->mutex);
779 return -ENOTTY;
780 #endif
781 } else {
782 fmt->format.width = mode->width;
783 fmt->format.height = mode->height;
784 fmt->format.code = mode->bus_fmt;
785 fmt->format.field = V4L2_FIELD_NONE;
786 }
787 mutex_unlock(&imx327->mutex);
788 return 0;
789 }
790
imx327_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)791 static int imx327_enum_mbus_code(struct v4l2_subdev *sd,
792 struct v4l2_subdev_pad_config *cfg,
793 struct v4l2_subdev_mbus_code_enum *code)
794 {
795 struct imx327 *imx327 = to_imx327(sd);
796 const struct imx327_mode *mode = imx327->cur_mode;
797
798 if (code->index != 0)
799 return -EINVAL;
800 code->code = mode->bus_fmt;
801
802 return 0;
803 }
804
imx327_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)805 static int imx327_enum_frame_sizes(struct v4l2_subdev *sd,
806 struct v4l2_subdev_pad_config *cfg,
807 struct v4l2_subdev_frame_size_enum *fse)
808 {
809 struct imx327 *imx327 = to_imx327(sd);
810
811 if (fse->index >= imx327->support_modes_num)
812 return -EINVAL;
813
814 if (fse->code != imx327->support_modes[fse->index].bus_fmt)
815 return -EINVAL;
816
817 fse->min_width = imx327->support_modes[fse->index].width;
818 fse->max_width = imx327->support_modes[fse->index].width;
819 fse->max_height = imx327->support_modes[fse->index].height;
820 fse->min_height = imx327->support_modes[fse->index].height;
821
822 return 0;
823 }
824
825 #ifdef USED_TEST_PATTERN
imx327_enable_test_pattern(struct imx327 * imx327,u32 pattern)826 static int imx327_enable_test_pattern(struct imx327 *imx327, u32 pattern)
827 {
828 u32 val = 0;
829
830 imx327_read_reg(imx327->client,
831 IMX327_REG_TEST_PATTERN,
832 IMX327_REG_VALUE_08BIT,
833 &val);
834 if (pattern) {
835 val = ((pattern - 1) << 4) | IMX327_TEST_PATTERN_ENABLE;
836 imx327_write_reg(imx327->client,
837 0x300a,
838 IMX327_REG_VALUE_08BIT,
839 0x00);
840 imx327_write_reg(imx327->client,
841 0x300e,
842 IMX327_REG_VALUE_08BIT,
843 0x00);
844 } else {
845 val &= ~IMX327_TEST_PATTERN_ENABLE;
846 imx327_write_reg(imx327->client,
847 0x300a,
848 IMX327_REG_VALUE_08BIT,
849 0x3c);
850 imx327_write_reg(imx327->client,
851 0x300e,
852 IMX327_REG_VALUE_08BIT,
853 0x01);
854 }
855 return imx327_write_reg(imx327->client,
856 IMX327_REG_TEST_PATTERN,
857 IMX327_REG_VALUE_08BIT,
858 val);
859 }
860 #endif
861
imx327_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)862 static int imx327_g_frame_interval(struct v4l2_subdev *sd,
863 struct v4l2_subdev_frame_interval *fi)
864 {
865 struct imx327 *imx327 = to_imx327(sd);
866 const struct imx327_mode *mode = imx327->cur_mode;
867
868 fi->interval = mode->max_fps;
869
870 return 0;
871 }
872
imx327_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)873 static int imx327_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
874 struct v4l2_mbus_config *config)
875 {
876 struct imx327 *imx327 = to_imx327(sd);
877 u32 val = 0;
878
879 val = 1 << (IMX327_4LANES - 1) |
880 V4L2_MBUS_CSI2_CHANNEL_0 |
881 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
882 config->type = imx327->bus_cfg.bus_type;
883 config->flags = val;
884
885 return 0;
886 }
887
imx327_set_hdrae(struct imx327 * imx327,struct preisp_hdrae_exp_s * ae)888 static int imx327_set_hdrae(struct imx327 *imx327,
889 struct preisp_hdrae_exp_s *ae)
890 {
891 u32 l_exp_time, m_exp_time, s_exp_time;
892 u32 l_gain, m_gain, s_gain;
893 u32 shs1, shs2, rhs1;
894 u32 gain_switch = 0;
895 int ret = 0;
896 u8 cg_mode = 0;
897 u32 fsc = imx327->cur_vts;//The HDR mode vts is double by default to workaround T-line
898
899 if (!imx327->has_init_exp && !imx327->streaming) {
900 imx327->init_hdrae_exp = *ae;
901 imx327->has_init_exp = true;
902 dev_dbg(&imx327->client->dev, "imx327 don't stream, record exp for hdr!\n");
903 return ret;
904 }
905
906 l_exp_time = ae->long_exp_reg;
907 m_exp_time = ae->middle_exp_reg;
908 s_exp_time = ae->short_exp_reg;
909 l_gain = ae->long_gain_reg;
910 m_gain = ae->middle_gain_reg;
911 s_gain = ae->short_gain_reg;
912
913 if (imx327->cur_mode->hdr_mode == HDR_X2) {
914 //2 stagger
915 l_gain = m_gain;
916 l_exp_time = m_exp_time;
917 cg_mode = ae->middle_cg_mode;
918 }
919 dev_dbg(&imx327->client->dev,
920 "rev exp req: L_time=%d, gain=%d, S_time=%d, gain=%d\n",
921 l_exp_time, l_gain,
922 s_exp_time, s_gain);
923 ret = imx327_read_reg(imx327->client, IMX327_GAIN_SWITCH_REG,
924 IMX327_REG_VALUE_08BIT, &gain_switch);
925 if (!g_isHCG && cg_mode == GAIN_MODE_HCG) {
926 gain_switch |= 0x0110;
927 g_isHCG = true;
928 } else if (g_isHCG && cg_mode == GAIN_MODE_LCG) {
929 gain_switch &= 0xef;
930 gain_switch |= 0x100;
931 g_isHCG = false;
932 }
933
934 //long exposure and short exposure
935 rhs1 = 0xe1;
936 shs1 = rhs1 - s_exp_time - 1;
937 shs2 = fsc - l_exp_time - 1;
938 if (shs1 < 2)
939 shs1 = 2;
940 if (shs2 < (rhs1 + 2))
941 shs2 = rhs1 + 2;
942 else if (shs2 > (fsc - 2))
943 shs2 = fsc - 2;
944
945 ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS1_L,
946 IMX327_REG_VALUE_08BIT,
947 IMX327_FETCH_LOW_BYTE_EXP(shs1));
948 ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS1_M,
949 IMX327_REG_VALUE_08BIT,
950 IMX327_FETCH_MID_BYTE_EXP(shs1));
951 ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS1_H,
952 IMX327_REG_VALUE_08BIT,
953 IMX327_FETCH_HIGH_BYTE_EXP(shs1));
954 ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS2_L,
955 IMX327_REG_VALUE_08BIT,
956 IMX327_FETCH_LOW_BYTE_EXP(shs2));
957 ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS2_M,
958 IMX327_REG_VALUE_08BIT,
959 IMX327_FETCH_MID_BYTE_EXP(shs2));
960 ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS2_H,
961 IMX327_REG_VALUE_08BIT,
962 IMX327_FETCH_HIGH_BYTE_EXP(shs2));
963
964 ret |= imx327_write_reg(imx327->client, IMX327_REG_LF_GAIN,
965 IMX327_REG_VALUE_08BIT,
966 l_gain);
967 ret |= imx327_write_reg(imx327->client, IMX327_REG_SF_GAIN,
968 IMX327_REG_VALUE_08BIT,
969 s_gain);
970 if (gain_switch & 0x100) {
971 ret |= imx327_write_reg(imx327->client,
972 IMX327_GROUP_HOLD_REG,
973 IMX327_REG_VALUE_08BIT,
974 IMX327_GROUP_HOLD_START);
975 ret |= imx327_write_reg(imx327->client, IMX327_GAIN_SWITCH_REG,
976 IMX327_REG_VALUE_08BIT, gain_switch);
977 ret |= imx327_write_reg(imx327->client,
978 IMX327_GROUP_HOLD_REG,
979 IMX327_REG_VALUE_08BIT,
980 IMX327_GROUP_HOLD_END);
981 }
982 dev_dbg(&imx327->client->dev,
983 "set l_gain:0x%x s_gain:0x%x shs2:0x%x shs1:0x%x\n",
984 l_gain, s_gain, shs2, shs1);
985 return ret;
986 }
987
imx327_get_module_inf(struct imx327 * imx327,struct rkmodule_inf * inf)988 static void imx327_get_module_inf(struct imx327 *imx327,
989 struct rkmodule_inf *inf)
990 {
991 memset(inf, 0, sizeof(*inf));
992 strlcpy(inf->base.sensor, IMX327_NAME, sizeof(inf->base.sensor));
993 strlcpy(inf->base.module, imx327->module_name,
994 sizeof(inf->base.module));
995 strlcpy(inf->base.lens, imx327->len_name, sizeof(inf->base.lens));
996 }
997
imx327_set_conversion_gain(struct imx327 * imx327,u32 * cg)998 static int imx327_set_conversion_gain(struct imx327 *imx327, u32 *cg)
999 {
1000 int ret = 0;
1001 struct i2c_client *client = imx327->client;
1002 int cur_cg = *cg;
1003 u32 gain_switch = 0;
1004
1005 ret = imx327_read_reg(client,
1006 IMX327_GAIN_SWITCH_REG,
1007 IMX327_REG_VALUE_08BIT,
1008 &gain_switch);
1009 if (g_isHCG && cur_cg == GAIN_MODE_LCG) {
1010 gain_switch &= 0xef;
1011 gain_switch |= 0x0100;
1012 g_isHCG = false;
1013 } else if (!g_isHCG && cur_cg == GAIN_MODE_HCG) {
1014 gain_switch |= 0x0110;
1015 g_isHCG = true;
1016 }
1017
1018 if (gain_switch & 0x100) {
1019 ret |= imx327_write_reg(client,
1020 IMX327_GROUP_HOLD_REG,
1021 IMX327_REG_VALUE_08BIT,
1022 IMX327_GROUP_HOLD_START);
1023 ret |= imx327_write_reg(client,
1024 IMX327_GAIN_SWITCH_REG,
1025 IMX327_REG_VALUE_08BIT,
1026 gain_switch & 0xff);
1027 ret |= imx327_write_reg(client,
1028 IMX327_GROUP_HOLD_REG,
1029 IMX327_REG_VALUE_08BIT,
1030 IMX327_GROUP_HOLD_END);
1031 }
1032
1033 return ret;
1034 }
1035
1036 #define USED_SYS_DEBUG
1037 #ifdef USED_SYS_DEBUG
1038 //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0037/cam_s_cg
set_conversion_gain_status(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1039 static ssize_t set_conversion_gain_status(struct device *dev,
1040 struct device_attribute *attr,
1041 const char *buf,
1042 size_t count)
1043 {
1044 struct i2c_client *client = to_i2c_client(dev);
1045 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1046 struct imx327 *imx327 = to_imx327(sd);
1047 int status = 0;
1048 int ret = 0;
1049
1050 ret = kstrtoint(buf, 0, &status);
1051 if (!ret && status >= 0 && status < 2)
1052 imx327_set_conversion_gain(imx327, &status);
1053 else
1054 dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
1055 return count;
1056 }
1057
1058 static struct device_attribute attributes[] = {
1059 __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
1060 };
1061
add_sysfs_interfaces(struct device * dev)1062 static int add_sysfs_interfaces(struct device *dev)
1063 {
1064 int i;
1065
1066 for (i = 0; i < ARRAY_SIZE(attributes); i++)
1067 if (device_create_file(dev, attributes + i))
1068 goto undo;
1069 return 0;
1070 undo:
1071 for (i--; i >= 0 ; i--)
1072 device_remove_file(dev, attributes + i);
1073 dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
1074 return -ENODEV;
1075 }
1076 #endif
1077
imx327_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1078 static long imx327_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1079 {
1080 struct imx327 *imx327 = to_imx327(sd);
1081 struct rkmodule_hdr_cfg *hdr;
1082 struct rkmodule_lvds_cfg *lvds_cfg;
1083 u32 i, h, w;
1084 long ret = 0;
1085 s64 dst_pixel_rate = 0;
1086 s32 dst_link_freq = 0;
1087 u32 stream = 0;
1088
1089 switch (cmd) {
1090 case RKMODULE_GET_MODULE_INFO:
1091 imx327_get_module_inf(imx327, (struct rkmodule_inf *)arg);
1092 break;
1093 case PREISP_CMD_SET_HDRAE_EXP:
1094 ret = imx327_set_hdrae(imx327, arg);
1095 break;
1096 case RKMODULE_GET_HDR_CFG:
1097 hdr = (struct rkmodule_hdr_cfg *)arg;
1098 if (imx327->cur_mode->hdr_mode == NO_HDR)
1099 hdr->esp.mode = HDR_NORMAL_VC;
1100 else
1101 hdr->esp.mode = HDR_ID_CODE;
1102 hdr->hdr_mode = imx327->cur_mode->hdr_mode;
1103 break;
1104 case RKMODULE_SET_HDR_CFG:
1105 hdr = (struct rkmodule_hdr_cfg *)arg;
1106 for (i = 0; i < imx327->support_modes_num; i++) {
1107 if (imx327->support_modes[i].hdr_mode == hdr->hdr_mode) {
1108 imx327->cur_mode = &imx327->support_modes[i];
1109 break;
1110 }
1111 }
1112 if (i == imx327->support_modes_num) {
1113 dev_err(&imx327->client->dev,
1114 "not find hdr mode:%d config\n",
1115 hdr->hdr_mode);
1116 ret = -EINVAL;
1117 } else {
1118 w = imx327->cur_mode->hts_def - imx327->cur_mode->width;
1119 h = imx327->cur_mode->vts_def - imx327->cur_mode->height;
1120 __v4l2_ctrl_modify_range(imx327->hblank, w, w, 1, w);
1121 __v4l2_ctrl_modify_range(imx327->vblank, h,
1122 IMX327_VTS_MAX - imx327->cur_mode->height,
1123 1, h);
1124 if (imx327->cur_mode->hdr_mode == NO_HDR) {
1125 dst_link_freq = 0;
1126 dst_pixel_rate = IMX327_PIXEL_RATE_NORMAL;
1127 } else {
1128 dst_link_freq = 1;
1129 dst_pixel_rate = IMX327_PIXEL_RATE_HDR;
1130 }
1131 __v4l2_ctrl_s_ctrl_int64(imx327->pixel_rate,
1132 dst_pixel_rate);
1133 __v4l2_ctrl_s_ctrl(imx327->link_freq,
1134 dst_link_freq);
1135 imx327->cur_vts = imx327->cur_mode->vts_def;
1136 }
1137 break;
1138 case RKMODULE_SET_CONVERSION_GAIN:
1139 ret = imx327_set_conversion_gain(imx327, (u32 *)arg);
1140 break;
1141 case RKMODULE_GET_LVDS_CFG:
1142 lvds_cfg = (struct rkmodule_lvds_cfg *)arg;
1143 if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2)
1144 memcpy(lvds_cfg, &imx327->cur_mode->lvds_cfg,
1145 sizeof(struct rkmodule_lvds_cfg));
1146 else
1147 ret = -ENOIOCTLCMD;
1148 break;
1149 case RKMODULE_SET_QUICK_STREAM:
1150
1151 stream = *((u32 *)arg);
1152
1153 if (stream)
1154 ret = imx327_write_reg(imx327->client,
1155 IMX327_REG_CTRL_MODE,
1156 IMX327_REG_VALUE_08BIT,
1157 0);
1158 else
1159 ret = imx327_write_reg(imx327->client,
1160 IMX327_REG_CTRL_MODE,
1161 IMX327_REG_VALUE_08BIT,
1162 1);
1163 break;
1164 default:
1165 ret = -ENOIOCTLCMD;
1166 break;
1167 }
1168 return ret;
1169 }
1170
1171 #ifdef CONFIG_COMPAT
imx327_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1172 static long imx327_compat_ioctl32(struct v4l2_subdev *sd,
1173 unsigned int cmd, unsigned long arg)
1174 {
1175 void __user *up = compat_ptr(arg);
1176 struct rkmodule_inf *inf;
1177 struct rkmodule_awb_cfg *cfg;
1178 struct rkmodule_hdr_cfg *hdr;
1179 struct preisp_hdrae_exp_s *hdrae;
1180 long ret;
1181 u32 cg = 0;
1182 u32 stream = 0;
1183
1184 switch (cmd) {
1185 case RKMODULE_GET_MODULE_INFO:
1186 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1187 if (!inf) {
1188 ret = -ENOMEM;
1189 return ret;
1190 }
1191
1192 ret = imx327_ioctl(sd, cmd, inf);
1193 if (!ret)
1194 ret = copy_to_user(up, inf, sizeof(*inf));
1195 kfree(inf);
1196 break;
1197 case RKMODULE_AWB_CFG:
1198 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1199 if (!cfg) {
1200 ret = -ENOMEM;
1201 return ret;
1202 }
1203 ret = copy_from_user(cfg, up, sizeof(*cfg));
1204 if (!ret)
1205 ret = imx327_ioctl(sd, cmd, cfg);
1206 kfree(cfg);
1207 break;
1208 case RKMODULE_GET_HDR_CFG:
1209 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1210 if (!hdr) {
1211 ret = -ENOMEM;
1212 return ret;
1213 }
1214
1215 ret = imx327_ioctl(sd, cmd, hdr);
1216 if (!ret)
1217 ret = copy_to_user(up, hdr, sizeof(*hdr));
1218 kfree(hdr);
1219 break;
1220 case RKMODULE_SET_HDR_CFG:
1221 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1222 if (!hdr) {
1223 ret = -ENOMEM;
1224 return ret;
1225 }
1226
1227 ret = copy_from_user(hdr, up, sizeof(*hdr));
1228 if (!ret)
1229 ret = imx327_ioctl(sd, cmd, hdr);
1230 kfree(hdr);
1231 break;
1232 case PREISP_CMD_SET_HDRAE_EXP:
1233 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1234 if (!hdrae) {
1235 ret = -ENOMEM;
1236 return ret;
1237 }
1238
1239 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1240 if (!ret)
1241 ret = imx327_ioctl(sd, cmd, hdrae);
1242 kfree(hdrae);
1243 break;
1244 case RKMODULE_SET_CONVERSION_GAIN:
1245 ret = copy_from_user(&cg, up, sizeof(cg));
1246 if (!ret)
1247 ret = imx327_ioctl(sd, cmd, &cg);
1248 break;
1249 case RKMODULE_SET_QUICK_STREAM:
1250 ret = copy_from_user(&stream, up, sizeof(u32));
1251 if (!ret)
1252 ret = imx327_ioctl(sd, cmd, &stream);
1253 break;
1254 default:
1255 ret = -ENOIOCTLCMD;
1256 break;
1257 }
1258
1259 return ret;
1260 }
1261 #endif
1262
imx327_init_conversion_gain(struct imx327 * imx327)1263 static int imx327_init_conversion_gain(struct imx327 *imx327)
1264 {
1265 int ret = 0;
1266 struct i2c_client *client = imx327->client;
1267 u32 val = 0;
1268
1269 ret = imx327_read_reg(client,
1270 IMX327_GAIN_SWITCH_REG,
1271 IMX327_REG_VALUE_08BIT,
1272 &val);
1273 val &= 0xef;
1274 ret = imx327_write_reg(client,
1275 IMX327_GAIN_SWITCH_REG,
1276 IMX327_REG_VALUE_08BIT,
1277 val);
1278 if (!ret)
1279 g_isHCG = false;
1280 return ret;
1281 }
1282
__imx327_start_stream(struct imx327 * imx327)1283 static int __imx327_start_stream(struct imx327 *imx327)
1284 {
1285 int ret;
1286
1287 ret = imx327_write_array(imx327->client, imx327->cur_mode->reg_list);
1288 if (ret)
1289 return ret;
1290 ret = imx327_init_conversion_gain(imx327);
1291 if (ret)
1292 return ret;
1293 /* In case these controls are set before streaming */
1294 ret = __v4l2_ctrl_handler_setup(&imx327->ctrl_handler);
1295 if (imx327->has_init_exp && imx327->cur_mode->hdr_mode != NO_HDR) {
1296 ret = imx327_ioctl(&imx327->subdev, PREISP_CMD_SET_HDRAE_EXP,
1297 &imx327->init_hdrae_exp);
1298 if (ret) {
1299 dev_err(&imx327->client->dev,
1300 "init exp fail in hdr mode\n");
1301 return ret;
1302 }
1303 }
1304
1305 ret = imx327_write_reg(imx327->client,
1306 IMX327_REG_CTRL_MODE,
1307 IMX327_REG_VALUE_08BIT,
1308 0);
1309 return ret;
1310 }
1311
__imx327_stop_stream(struct imx327 * imx327)1312 static int __imx327_stop_stream(struct imx327 *imx327)
1313 {
1314 return imx327_write_reg(imx327->client,
1315 IMX327_REG_CTRL_MODE,
1316 IMX327_REG_VALUE_08BIT,
1317 1);
1318 }
1319
imx327_s_stream(struct v4l2_subdev * sd,int on)1320 static int imx327_s_stream(struct v4l2_subdev *sd, int on)
1321 {
1322 struct imx327 *imx327 = to_imx327(sd);
1323 struct i2c_client *client = imx327->client;
1324 int ret = 0;
1325
1326 mutex_lock(&imx327->mutex);
1327 on = !!on;
1328 if (on == imx327->streaming)
1329 goto unlock_and_return;
1330
1331 if (on) {
1332 ret = pm_runtime_get_sync(&client->dev);
1333 if (ret < 0) {
1334 pm_runtime_put_noidle(&client->dev);
1335 goto unlock_and_return;
1336 }
1337
1338 ret = __imx327_start_stream(imx327);
1339 if (ret) {
1340 v4l2_err(sd, "start stream failed while write regs\n");
1341 pm_runtime_put(&client->dev);
1342 goto unlock_and_return;
1343 }
1344 } else {
1345 __imx327_stop_stream(imx327);
1346 pm_runtime_put(&client->dev);
1347 }
1348
1349 imx327->streaming = on;
1350
1351 unlock_and_return:
1352 mutex_unlock(&imx327->mutex);
1353
1354 return ret;
1355 }
1356
imx327_s_power(struct v4l2_subdev * sd,int on)1357 static int imx327_s_power(struct v4l2_subdev *sd, int on)
1358 {
1359 struct imx327 *imx327 = to_imx327(sd);
1360 struct i2c_client *client = imx327->client;
1361 int ret = 0;
1362
1363 mutex_lock(&imx327->mutex);
1364
1365 /* If the power state is not modified - no work to do. */
1366 if (imx327->power_on == !!on)
1367 goto unlock_and_return;
1368
1369 if (on) {
1370 ret = pm_runtime_get_sync(&client->dev);
1371 if (ret < 0) {
1372 pm_runtime_put_noidle(&client->dev);
1373 goto unlock_and_return;
1374 }
1375
1376 ret = imx327_write_array(imx327->client, imx327_global_regs);
1377 if (ret) {
1378 v4l2_err(sd, "could not set init registers\n");
1379 pm_runtime_put_noidle(&client->dev);
1380 goto unlock_and_return;
1381 }
1382
1383 imx327->power_on = true;
1384 } else {
1385 pm_runtime_put(&client->dev);
1386 imx327->power_on = false;
1387 }
1388
1389 unlock_and_return:
1390 mutex_unlock(&imx327->mutex);
1391
1392 return ret;
1393 }
1394
1395 /* Calculate the delay in us by clock rate and clock cycles */
imx327_cal_delay(u32 cycles)1396 static inline u32 imx327_cal_delay(u32 cycles)
1397 {
1398 return DIV_ROUND_UP(cycles, IMX327_XVCLK_FREQ / 1000 / 1000);
1399 }
1400
__imx327_power_on(struct imx327 * imx327)1401 static int __imx327_power_on(struct imx327 *imx327)
1402 {
1403 int ret;
1404 u32 delay_us;
1405 struct device *dev = &imx327->client->dev;
1406
1407 if (!IS_ERR_OR_NULL(imx327->pins_default)) {
1408 ret = pinctrl_select_state(imx327->pinctrl,
1409 imx327->pins_default);
1410 if (ret < 0)
1411 dev_err(dev, "could not set pins\n");
1412 }
1413
1414 ret = clk_set_rate(imx327->xvclk, IMX327_XVCLK_FREQ);
1415 if (ret < 0)
1416 dev_warn(dev, "Failed to set xvclk rate (37.125M Hz)\n");
1417
1418 if (clk_get_rate(imx327->xvclk) != IMX327_XVCLK_FREQ)
1419 dev_warn(dev, "xvclk mismatched,based on 24M Hz\n");
1420
1421 ret = clk_prepare_enable(imx327->xvclk);
1422 if (ret < 0) {
1423 dev_err(dev, "Failed to enable xvclk\n");
1424 return ret;
1425 }
1426
1427
1428 ret = regulator_bulk_enable(IMX327_NUM_SUPPLIES, imx327->supplies);
1429 if (ret < 0) {
1430 dev_err(dev, "Failed to enable regulators\n");
1431 goto disable_clk;
1432 }
1433
1434 if (!IS_ERR(imx327->reset_gpio))
1435 gpiod_set_value_cansleep(imx327->reset_gpio, 0);
1436 usleep_range(500, 1000);
1437 if (!IS_ERR(imx327->reset_gpio))
1438 gpiod_set_value_cansleep(imx327->reset_gpio, 1);
1439
1440 if (!IS_ERR(imx327->pwdn_gpio))
1441 gpiod_set_value_cansleep(imx327->pwdn_gpio, 1);
1442
1443 /* 8192 cycles prior to first SCCB transaction */
1444 delay_us = imx327_cal_delay(8192);
1445 usleep_range(delay_us, delay_us * 2);
1446 usleep_range(5000, 10000);
1447 return 0;
1448
1449 disable_clk:
1450 clk_disable_unprepare(imx327->xvclk);
1451
1452 return ret;
1453 }
1454
__imx327_power_off(struct imx327 * imx327)1455 static void __imx327_power_off(struct imx327 *imx327)
1456 {
1457 int ret;
1458 struct device *dev = &imx327->client->dev;
1459
1460 if (!IS_ERR(imx327->pwdn_gpio))
1461 gpiod_set_value_cansleep(imx327->pwdn_gpio, 0);
1462 clk_disable_unprepare(imx327->xvclk);
1463 if (!IS_ERR(imx327->reset_gpio))
1464 gpiod_set_value_cansleep(imx327->reset_gpio, 0);
1465 if (!IS_ERR_OR_NULL(imx327->pins_sleep)) {
1466 ret = pinctrl_select_state(imx327->pinctrl,
1467 imx327->pins_sleep);
1468 if (ret < 0)
1469 dev_dbg(dev, "could not set pins\n");
1470 }
1471 regulator_bulk_disable(IMX327_NUM_SUPPLIES, imx327->supplies);
1472 }
1473
imx327_runtime_resume(struct device * dev)1474 static int imx327_runtime_resume(struct device *dev)
1475 {
1476 struct i2c_client *client = to_i2c_client(dev);
1477 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1478 struct imx327 *imx327 = to_imx327(sd);
1479
1480 return __imx327_power_on(imx327);
1481 }
1482
imx327_runtime_suspend(struct device * dev)1483 static int imx327_runtime_suspend(struct device *dev)
1484 {
1485 struct i2c_client *client = to_i2c_client(dev);
1486 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1487 struct imx327 *imx327 = to_imx327(sd);
1488
1489 __imx327_power_off(imx327);
1490
1491 return 0;
1492 }
1493
1494 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx327_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1495 static int imx327_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1496 {
1497 struct imx327 *imx327 = to_imx327(sd);
1498 struct v4l2_mbus_framefmt *try_fmt =
1499 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1500 const struct imx327_mode *def_mode = &imx327->support_modes[0];
1501
1502 mutex_lock(&imx327->mutex);
1503 /* Initialize try_fmt */
1504 try_fmt->width = def_mode->width;
1505 try_fmt->height = def_mode->height;
1506 try_fmt->code = def_mode->bus_fmt;
1507 try_fmt->field = V4L2_FIELD_NONE;
1508
1509 mutex_unlock(&imx327->mutex);
1510 /* No crop or compose */
1511
1512 return 0;
1513 }
1514 #endif
1515
imx327_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1516 static int imx327_enum_frame_interval(struct v4l2_subdev *sd,
1517 struct v4l2_subdev_pad_config *cfg,
1518 struct v4l2_subdev_frame_interval_enum *fie)
1519 {
1520 struct imx327 *imx327 = to_imx327(sd);
1521
1522 if (fie->index >= imx327->support_modes_num)
1523 return -EINVAL;
1524
1525 fie->code = imx327->support_modes[fie->index].bus_fmt;
1526 fie->width = imx327->support_modes[fie->index].width;
1527 fie->height = imx327->support_modes[fie->index].height;
1528 fie->interval = imx327->support_modes[fie->index].max_fps;
1529 fie->reserved[0] = imx327->support_modes[fie->index].hdr_mode;
1530 return 0;
1531 }
1532
1533 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1534 #define DST_WIDTH 1920
1535 #define DST_HEIGHT 1080
1536
1537 /*
1538 * The resolution of the driver configuration needs to be exactly
1539 * the same as the current output resolution of the sensor,
1540 * the input width of the isp needs to be 16 aligned,
1541 * the input height of the isp needs to be 8 aligned.
1542 * Can be cropped to standard resolution by this function,
1543 * otherwise it will crop out strange resolution according
1544 * to the alignment rules.
1545 */
1546
imx327_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1547 static int imx327_get_selection(struct v4l2_subdev *sd,
1548 struct v4l2_subdev_pad_config *cfg,
1549 struct v4l2_subdev_selection *sel)
1550 {
1551 struct imx327 *imx327 = to_imx327(sd);
1552
1553 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1554 sel->r.left = CROP_START(imx327->cur_mode->width, DST_WIDTH);
1555 sel->r.width = DST_WIDTH;
1556 if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2) {
1557 if (imx327->cur_mode->hdr_mode == NO_HDR)
1558 sel->r.top = 21;
1559 else
1560 sel->r.top = 13;
1561 } else {
1562 sel->r.top = CROP_START(imx327->cur_mode->height, DST_HEIGHT);
1563 }
1564 sel->r.height = DST_HEIGHT;
1565 return 0;
1566 }
1567 return -EINVAL;
1568 }
1569
1570 static const struct dev_pm_ops imx327_pm_ops = {
1571 SET_RUNTIME_PM_OPS(imx327_runtime_suspend,
1572 imx327_runtime_resume, NULL)
1573 };
1574
1575 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1576 static const struct v4l2_subdev_internal_ops imx327_internal_ops = {
1577 .open = imx327_open,
1578 };
1579 #endif
1580
1581 static const struct v4l2_subdev_core_ops imx327_core_ops = {
1582 .s_power = imx327_s_power,
1583 .ioctl = imx327_ioctl,
1584 #ifdef CONFIG_COMPAT
1585 .compat_ioctl32 = imx327_compat_ioctl32,
1586 #endif
1587 };
1588
1589 static const struct v4l2_subdev_video_ops imx327_video_ops = {
1590 .s_stream = imx327_s_stream,
1591 .g_frame_interval = imx327_g_frame_interval,
1592 };
1593
1594 static const struct v4l2_subdev_pad_ops imx327_pad_ops = {
1595 .enum_mbus_code = imx327_enum_mbus_code,
1596 .enum_frame_size = imx327_enum_frame_sizes,
1597 .enum_frame_interval = imx327_enum_frame_interval,
1598 .get_fmt = imx327_get_fmt,
1599 .set_fmt = imx327_set_fmt,
1600 .get_selection = imx327_get_selection,
1601 .get_mbus_config = imx327_g_mbus_config,
1602 };
1603
1604 static const struct v4l2_subdev_ops imx327_subdev_ops = {
1605 .core = &imx327_core_ops,
1606 .video = &imx327_video_ops,
1607 .pad = &imx327_pad_ops,
1608 };
1609
imx327_set_ctrl(struct v4l2_ctrl * ctrl)1610 static int imx327_set_ctrl(struct v4l2_ctrl *ctrl)
1611 {
1612 struct imx327 *imx327 = container_of(ctrl->handler,
1613 struct imx327, ctrl_handler);
1614 struct i2c_client *client = imx327->client;
1615 s64 max;
1616 int ret = 0;
1617 u32 shs1 = 0;
1618 u32 vts = 0;
1619 u32 val = 0;
1620
1621 /* Propagate change of current control to all related controls */
1622 switch (ctrl->id) {
1623 case V4L2_CID_VBLANK:
1624 /* Update max exposure while meeting expected vblanking */
1625 max = imx327->cur_mode->height + ctrl->val - 2;
1626 __v4l2_ctrl_modify_range(imx327->exposure,
1627 imx327->exposure->minimum, max,
1628 imx327->exposure->step,
1629 imx327->exposure->default_value);
1630 break;
1631 }
1632
1633 if (!pm_runtime_get_if_in_use(&client->dev))
1634 return 0;
1635
1636 switch (ctrl->id) {
1637 case V4L2_CID_EXPOSURE:
1638 if (imx327->cur_mode->hdr_mode == NO_HDR) {
1639 shs1 = imx327->cur_vts - ctrl->val - 1;
1640 ret = imx327_write_reg(imx327->client,
1641 IMX327_REG_SHS1_H,
1642 IMX327_REG_VALUE_08BIT,
1643 IMX327_FETCH_HIGH_BYTE_EXP(shs1));
1644 ret |= imx327_write_reg(imx327->client,
1645 IMX327_REG_SHS1_M,
1646 IMX327_REG_VALUE_08BIT,
1647 IMX327_FETCH_MID_BYTE_EXP(shs1));
1648 ret |= imx327_write_reg(imx327->client,
1649 IMX327_REG_SHS1_L,
1650 IMX327_REG_VALUE_08BIT,
1651 IMX327_FETCH_LOW_BYTE_EXP(shs1));
1652 dev_dbg(&client->dev, "set exposure 0x%x, cur_vts 0x%x,shs1 0x%x\n",
1653 ctrl->val, imx327->cur_vts, shs1);
1654 }
1655 break;
1656 case V4L2_CID_ANALOGUE_GAIN:
1657 if (imx327->cur_mode->hdr_mode == NO_HDR) {
1658 ret = imx327_write_reg(imx327->client,
1659 IMX327_REG_LF_GAIN,
1660 IMX327_REG_VALUE_08BIT,
1661 ctrl->val);
1662 dev_dbg(&client->dev, "set analog gain 0x%x\n",
1663 ctrl->val);
1664 }
1665 break;
1666 case V4L2_CID_VBLANK:
1667 vts = ctrl->val + imx327->cur_mode->height;
1668 imx327->cur_vts = vts;
1669 if (imx327->cur_mode->hdr_mode == HDR_X2)
1670 vts /= 2;
1671 ret = imx327_write_reg(imx327->client,
1672 IMX327_REG_VTS_H,
1673 IMX327_REG_VALUE_08BIT,
1674 IMX327_FETCH_HIGH_BYTE_VTS(vts));
1675 ret |= imx327_write_reg(imx327->client,
1676 IMX327_REG_VTS_M,
1677 IMX327_REG_VALUE_08BIT,
1678 IMX327_FETCH_MID_BYTE_VTS(vts));
1679 ret |= imx327_write_reg(imx327->client,
1680 IMX327_REG_VTS_L,
1681 IMX327_REG_VALUE_08BIT,
1682 IMX327_FETCH_LOW_BYTE_VTS(vts));
1683 dev_dbg(&client->dev, "set vts 0x%x\n",
1684 vts);
1685 break;
1686 case V4L2_CID_TEST_PATTERN:
1687 #ifdef USED_TEST_PATTERN
1688 ret = imx327_enable_test_pattern(imx327, ctrl->val);
1689 #endif
1690 break;
1691 case V4L2_CID_HFLIP:
1692 ret = imx327_read_reg(client,
1693 IMX327_FLIP_REG,
1694 IMX327_REG_VALUE_08BIT,
1695 &val);
1696 if (ctrl->val)
1697 val |= MIRROR_BIT_MASK;
1698 else
1699 val &= ~MIRROR_BIT_MASK;
1700 ret |= imx327_write_reg(client,
1701 IMX327_FLIP_REG,
1702 IMX327_REG_VALUE_08BIT,
1703 val);
1704 if (ret == 0)
1705 imx327->flip = val;
1706 break;
1707 case V4L2_CID_VFLIP:
1708 ret = imx327_read_reg(client,
1709 IMX327_FLIP_REG,
1710 IMX327_REG_VALUE_08BIT,
1711 &val);
1712 if (ctrl->val)
1713 val |= FLIP_BIT_MASK;
1714 else
1715 val &= ~FLIP_BIT_MASK;
1716 ret |= imx327_write_reg(client,
1717 IMX327_FLIP_REG,
1718 IMX327_REG_VALUE_08BIT,
1719 val);
1720 if (ret == 0)
1721 imx327->flip = val;
1722 break;
1723 default:
1724 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1725 __func__, ctrl->id, ctrl->val);
1726 break;
1727 }
1728
1729 pm_runtime_put(&client->dev);
1730
1731 return ret;
1732 }
1733
1734 static const struct v4l2_ctrl_ops imx327_ctrl_ops = {
1735 .s_ctrl = imx327_set_ctrl,
1736 };
1737
imx327_initialize_controls(struct imx327 * imx327)1738 static int imx327_initialize_controls(struct imx327 *imx327)
1739 {
1740 const struct imx327_mode *mode;
1741 struct v4l2_ctrl_handler *handler;
1742 s64 exposure_max, vblank_def;
1743 u32 h_blank;
1744 int ret;
1745 s32 dst_link_freq = 0;
1746 s64 dst_pixel_rate = 0;
1747
1748 handler = &imx327->ctrl_handler;
1749 mode = imx327->cur_mode;
1750 ret = v4l2_ctrl_handler_init(handler, 9);
1751 if (ret)
1752 return ret;
1753 handler->lock = &imx327->mutex;
1754
1755 imx327->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1756 1, 0, link_freq_menu_items);
1757
1758 if (imx327->cur_mode->hdr_mode == NO_HDR) {
1759 dst_link_freq = 0;
1760 dst_pixel_rate = IMX327_PIXEL_RATE_NORMAL;
1761 } else {
1762 dst_link_freq = 1;
1763 dst_pixel_rate = IMX327_PIXEL_RATE_HDR;
1764 }
1765 __v4l2_ctrl_s_ctrl(imx327->link_freq,
1766 dst_link_freq);
1767 imx327->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1768 0, IMX327_PIXEL_RATE_HDR, 1, dst_pixel_rate);
1769
1770 h_blank = mode->hts_def - mode->width;
1771
1772 imx327->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1773 h_blank, h_blank, 1, h_blank);
1774 if (imx327->hblank)
1775 imx327->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1776
1777 vblank_def = mode->vts_def - mode->height;
1778 imx327->cur_vts = mode->vts_def;
1779 imx327->vblank = v4l2_ctrl_new_std(handler, &imx327_ctrl_ops,
1780 V4L2_CID_VBLANK, vblank_def,
1781 IMX327_VTS_MAX - mode->height,
1782 1, vblank_def);
1783
1784 exposure_max = mode->vts_def - 2;
1785
1786 imx327->exposure = v4l2_ctrl_new_std(handler, &imx327_ctrl_ops,
1787 V4L2_CID_EXPOSURE, IMX327_EXPOSURE_MIN,
1788 exposure_max, IMX327_EXPOSURE_STEP,
1789 mode->exp_def);
1790
1791 imx327->anal_gain = v4l2_ctrl_new_std(handler, &imx327_ctrl_ops,
1792 V4L2_CID_ANALOGUE_GAIN, IMX327_GAIN_MIN,
1793 IMX327_GAIN_MAX, IMX327_GAIN_STEP,
1794 IMX327_GAIN_DEFAULT);
1795
1796 #ifdef USED_TEST_PATTERN
1797 imx327->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1798 &imx327_ctrl_ops, V4L2_CID_TEST_PATTERN,
1799 ARRAY_SIZE(imx327_test_pattern_menu) - 1,
1800 0, 0, imx327_test_pattern_menu);
1801 #endif
1802 imx327->h_flip = v4l2_ctrl_new_std(handler, &imx327_ctrl_ops,
1803 V4L2_CID_HFLIP, 0, 1, 1, 0);
1804
1805 imx327->v_flip = v4l2_ctrl_new_std(handler, &imx327_ctrl_ops,
1806 V4L2_CID_VFLIP, 0, 1, 1, 0);
1807 imx327->flip = 0;
1808 if (handler->error) {
1809 ret = handler->error;
1810 dev_err(&imx327->client->dev,
1811 "Failed to init controls(%d)\n", ret);
1812 goto err_free_handler;
1813 }
1814
1815 imx327->subdev.ctrl_handler = handler;
1816 imx327->has_init_exp = false;
1817
1818 return 0;
1819
1820 err_free_handler:
1821 v4l2_ctrl_handler_free(handler);
1822
1823 return ret;
1824 }
1825
imx327_check_sensor_id(struct imx327 * imx327,struct i2c_client * client)1826 static int imx327_check_sensor_id(struct imx327 *imx327,
1827 struct i2c_client *client)
1828 {
1829 struct device *dev = &imx327->client->dev;
1830 u32 id = 0;
1831 int ret;
1832
1833 ret = imx327_read_reg(client, IMX327_REG_CHIP_ID,
1834 IMX327_REG_VALUE_08BIT, &id);
1835
1836 if (id != CHIP_ID) {
1837 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1838 return -EINVAL;
1839 }
1840 return ret;
1841 }
1842
imx327_configure_regulators(struct imx327 * imx327)1843 static int imx327_configure_regulators(struct imx327 *imx327)
1844 {
1845 unsigned int i;
1846
1847 for (i = 0; i < IMX327_NUM_SUPPLIES; i++)
1848 imx327->supplies[i].supply = imx327_supply_names[i];
1849
1850 return devm_regulator_bulk_get(&imx327->client->dev,
1851 IMX327_NUM_SUPPLIES,
1852 imx327->supplies);
1853 }
1854
imx327_probe(struct i2c_client * client,const struct i2c_device_id * id)1855 static int imx327_probe(struct i2c_client *client,
1856 const struct i2c_device_id *id)
1857 {
1858 struct device *dev = &client->dev;
1859 struct device_node *node = dev->of_node;
1860 struct imx327 *imx327;
1861 struct v4l2_subdev *sd;
1862 char facing[2];
1863 int ret;
1864 struct device_node *endpoint;
1865
1866 dev_info(dev, "driver version: %02x.%02x.%02x",
1867 DRIVER_VERSION >> 16,
1868 (DRIVER_VERSION & 0xff00) >> 8,
1869 DRIVER_VERSION & 0x00ff);
1870
1871 imx327 = devm_kzalloc(dev, sizeof(*imx327), GFP_KERNEL);
1872 if (!imx327)
1873 return -ENOMEM;
1874
1875 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1876 &imx327->module_index);
1877 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1878 &imx327->module_facing);
1879 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1880 &imx327->module_name);
1881 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1882 &imx327->len_name);
1883 if (ret) {
1884 dev_err(dev, "could not get module information!\n");
1885 return -EINVAL;
1886 }
1887 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1888 if (!endpoint) {
1889 dev_err(dev, "Failed to get endpoint\n");
1890 return -EINVAL;
1891 }
1892
1893 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
1894 &imx327->bus_cfg);
1895 if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2) {
1896 imx327->support_modes = lvds_supported_modes;
1897 imx327->support_modes_num = ARRAY_SIZE(lvds_supported_modes);
1898 } else {
1899 imx327->support_modes = mipi_supported_modes;
1900 imx327->support_modes_num = ARRAY_SIZE(mipi_supported_modes);
1901 }
1902 imx327->client = client;
1903 imx327->cur_mode = &imx327->support_modes[0];
1904
1905 imx327->xvclk = devm_clk_get(dev, "xvclk");
1906 if (IS_ERR(imx327->xvclk)) {
1907 dev_err(dev, "Failed to get xvclk\n");
1908 return -EINVAL;
1909 }
1910
1911 imx327->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1912 if (IS_ERR(imx327->reset_gpio))
1913 dev_warn(dev, "Failed to get reset-gpios\n");
1914
1915 imx327->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1916 if (IS_ERR(imx327->pwdn_gpio))
1917 dev_warn(dev, "Failed to get pwdn-gpios\n");
1918
1919 ret = imx327_configure_regulators(imx327);
1920 if (ret) {
1921 dev_err(dev, "Failed to get power regulators\n");
1922 return ret;
1923 }
1924
1925 imx327->pinctrl = devm_pinctrl_get(dev);
1926 if (!IS_ERR(imx327->pinctrl)) {
1927 imx327->pins_default =
1928 pinctrl_lookup_state(imx327->pinctrl,
1929 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1930 if (IS_ERR(imx327->pins_default))
1931 dev_err(dev, "could not get default pinstate\n");
1932
1933 imx327->pins_sleep =
1934 pinctrl_lookup_state(imx327->pinctrl,
1935 OF_CAMERA_PINCTRL_STATE_SLEEP);
1936 if (IS_ERR(imx327->pins_sleep))
1937 dev_err(dev, "could not get sleep pinstate\n");
1938 }
1939
1940 mutex_init(&imx327->mutex);
1941
1942 sd = &imx327->subdev;
1943 v4l2_i2c_subdev_init(sd, client, &imx327_subdev_ops);
1944 ret = imx327_initialize_controls(imx327);
1945 if (ret)
1946 goto err_destroy_mutex;
1947
1948 ret = __imx327_power_on(imx327);
1949 if (ret)
1950 goto err_free_handler;
1951
1952 ret = imx327_check_sensor_id(imx327, client);
1953 if (ret)
1954 goto err_power_off;
1955
1956 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1957 dev_err(dev, "set the video v4l2 subdev api\n");
1958 sd->internal_ops = &imx327_internal_ops;
1959 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1960 V4L2_SUBDEV_FL_HAS_EVENTS;
1961 #endif
1962 #if defined(CONFIG_MEDIA_CONTROLLER)
1963 dev_err(dev, "set the media controller\n");
1964 imx327->pad.flags = MEDIA_PAD_FL_SOURCE;
1965 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1966 ret = media_entity_pads_init(&sd->entity, 1, &imx327->pad);
1967 if (ret < 0)
1968 goto err_power_off;
1969 #endif
1970
1971 memset(facing, 0, sizeof(facing));
1972 if (strcmp(imx327->module_facing, "back") == 0)
1973 facing[0] = 'b';
1974 else
1975 facing[0] = 'f';
1976
1977 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1978 imx327->module_index, facing,
1979 IMX327_NAME, dev_name(sd->dev));
1980 ret = v4l2_async_register_subdev_sensor_common(sd);
1981 if (ret) {
1982 dev_err(dev, "v4l2 async register subdev failed\n");
1983 goto err_clean_entity;
1984 }
1985
1986 pm_runtime_set_active(dev);
1987 pm_runtime_enable(dev);
1988 pm_runtime_idle(dev);
1989 g_isHCG = false;
1990 #ifdef USED_SYS_DEBUG
1991 add_sysfs_interfaces(dev);
1992 #endif
1993 dev_err(dev, "v4l2 async register subdev success\n");
1994 return 0;
1995
1996 err_clean_entity:
1997 #if defined(CONFIG_MEDIA_CONTROLLER)
1998 media_entity_cleanup(&sd->entity);
1999 #endif
2000 err_power_off:
2001 __imx327_power_off(imx327);
2002 err_free_handler:
2003 v4l2_ctrl_handler_free(&imx327->ctrl_handler);
2004 err_destroy_mutex:
2005 mutex_destroy(&imx327->mutex);
2006
2007 return ret;
2008 }
2009
imx327_remove(struct i2c_client * client)2010 static int imx327_remove(struct i2c_client *client)
2011 {
2012 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2013 struct imx327 *imx327 = to_imx327(sd);
2014
2015 v4l2_async_unregister_subdev(sd);
2016 #if defined(CONFIG_MEDIA_CONTROLLER)
2017 media_entity_cleanup(&sd->entity);
2018 #endif
2019 v4l2_ctrl_handler_free(&imx327->ctrl_handler);
2020 mutex_destroy(&imx327->mutex);
2021
2022 pm_runtime_disable(&client->dev);
2023 if (!pm_runtime_status_suspended(&client->dev))
2024 __imx327_power_off(imx327);
2025 pm_runtime_set_suspended(&client->dev);
2026
2027 return 0;
2028 }
2029
2030 #if IS_ENABLED(CONFIG_OF)
2031 static const struct of_device_id imx327_of_match[] = {
2032 { .compatible = "sony,imx327" },
2033 {},
2034 };
2035 MODULE_DEVICE_TABLE(of, imx327_of_match);
2036 #endif
2037
2038 static const struct i2c_device_id imx327_match_id[] = {
2039 { "sony,imx327", 0 },
2040 { },
2041 };
2042
2043 static struct i2c_driver imx327_i2c_driver = {
2044 .driver = {
2045 .name = IMX327_NAME,
2046 .pm = &imx327_pm_ops,
2047 .of_match_table = of_match_ptr(imx327_of_match),
2048 },
2049 .probe = &imx327_probe,
2050 .remove = &imx327_remove,
2051 .id_table = imx327_match_id,
2052 };
2053
sensor_mod_init(void)2054 static int __init sensor_mod_init(void)
2055 {
2056 return i2c_add_driver(&imx327_i2c_driver);
2057 }
2058
sensor_mod_exit(void)2059 static void __exit sensor_mod_exit(void)
2060 {
2061 i2c_del_driver(&imx327_i2c_driver);
2062 }
2063
2064 device_initcall_sync(sensor_mod_init);
2065 module_exit(sensor_mod_exit);
2066
2067 MODULE_DESCRIPTION("Sony imx327 sensor driver");
2068 MODULE_LICENSE("GPL v2");
2069