1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx317 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 add enum_frame_interval function.
10 * V0.0X01.0X04 adjust exposue and gain control issues.
11 * V0.0X01.0X05 add quick stream on/off
12 * V0.0X01.0X06 add function g_mbus_config
13 */
14
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/delay.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/sysfs.h>
24 #include <linux/slab.h>
25 #include <linux/version.h>
26 #include <linux/rk-camera-module.h>
27 #include <media/media-entity.h>
28 #include <media/v4l2-async.h>
29 #include <media/v4l2-ctrls.h>
30 #include <media/v4l2-subdev.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/of.h>
33 #include <linux/of_graph.h>
34 #include <media/v4l2-fwnode.h>
35
36 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
37
38 #ifndef V4L2_CID_DIGITAL_GAIN
39 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
40 #endif
41
42 #define MIPI_FREQ 360000000U
43
44 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
45 #define IMX317_PIXEL_RATE (MIPI_FREQ * 2LL * 4LL / 10LL)
46
47 #define IMX317_XVCLK_FREQ 24000000
48
49 #define CHIP_ID 0x00
50 #define IMX317_REG_CHIP_ID 0x0000
51
52 #define IMX317_REG_CTRL_MODE 0x3000
53 #define IMX317_MODE_SW_STANDBY 0x12
54 #define IMX317_MODE_STREAMING 0x00
55
56 #define IMX317_REG_EXPOSURE_H 0x300D
57 #define IMX317_REG_EXPOSURE_L 0x300C
58 #define IMX317_EXPOSURE_MIN 12
59 #define IMX317_EXPOSURE_STEP 1
60 #define IMX317_VTS_MAX 0x7fff
61
62 #define IMX317_REG_GAIN_H 0x300B
63 #define IMX317_REG_GAIN_L 0x300A
64 #define IMX317_GAIN_H_MASK 0x07
65 #define IMX317_GAIN_H_SHIFT 8
66 #define IMX317_GAIN_L_MASK 0xFF
67
68 #define IMX317_GAIN_MIN 0x80
69 #define IMX317_GAIN_MAX (22U * IMX317_GAIN_MIN)
70 #define IMX317_GAIN_STEP 1
71 #define IMX317_GAIN_DEFAULT (20U * IMX317_GAIN_MIN)
72
73 #define IMX317_REG_VTS_H 0x30FA
74 #define IMX317_REG_VTS_M 0x30F9
75 #define IMX317_REG_VTS_L 0x30F8
76
77 #define REG_NULL 0xFFFF
78 #define REG_DELAY 0xFFFE
79
80 #define IMX317_REG_VALUE_08BIT 1
81 #define IMX317_REG_VALUE_16BIT 2
82 #define IMX317_REG_VALUE_24BIT 3
83
84 #define IMX317_LANES 2
85 #define IMX317_BITS_PER_SAMPLE 10
86
87 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
88 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
89
90 #define IMX317_NAME "imx317"
91 #define IMX317_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
92
93 static const struct regval *imx317_global_regs;
94
95 static const char * const imx317_supply_names[] = {
96 "avdd", /* Analog power */
97 "dovdd", /* Digital I/O power */
98 "dvdd", /* Digital core power */
99 };
100
101 #define IMX317_NUM_SUPPLIES ARRAY_SIZE(imx317_supply_names)
102
103 struct regval {
104 u16 addr;
105 u8 val;
106 };
107
108 struct imx317_mode {
109 u32 width;
110 u32 height;
111 struct v4l2_fract max_fps;
112 u32 hts_def;
113 u32 vts_def;
114 u32 exp_def;
115 const struct regval *reg_list;
116 };
117
118 struct imx317 {
119 struct i2c_client *client;
120 struct clk *xvclk;
121 struct gpio_desc *reset_gpio;
122 struct gpio_desc *pwdn_gpio;
123 struct gpio_desc *power_gpio;
124 struct regulator_bulk_data supplies[IMX317_NUM_SUPPLIES];
125
126 struct pinctrl *pinctrl;
127 struct pinctrl_state *pins_default;
128 struct pinctrl_state *pins_sleep;
129
130 struct v4l2_subdev subdev;
131 struct media_pad pad;
132 struct v4l2_ctrl_handler ctrl_handler;
133 struct v4l2_ctrl *link_freq;
134 struct v4l2_ctrl *exposure;
135 struct v4l2_ctrl *anal_gain;
136 struct v4l2_ctrl *digi_gain;
137 struct v4l2_ctrl *hblank;
138 struct v4l2_ctrl *vblank;
139 struct v4l2_ctrl *test_pattern;
140 struct mutex mutex;
141 bool streaming;
142 bool power_on;
143 const struct imx317_mode *cur_mode;
144 unsigned int lane_num;
145 unsigned int cfg_num;
146 unsigned int pixel_rate;
147 u32 module_index;
148 const char *module_facing;
149 const char *module_name;
150 const char *len_name;
151 };
152
153 #define to_imx317(sd) container_of(sd, struct imx317, subdev)
154
155 /*
156 * Xclk 24Mhz
157 */
158 static const struct regval imx317_global_regs_2lane[] = {
159 {0x3000, 0x1f},
160 {0x303E, 0x02},
161 {0x3120, 0xF0},
162 {0x3121, 0x00},
163 {0x3122, 0x02},
164 {0x3123, 0x01},
165 {0x3129, 0x9C},
166 {0x312A, 0x02},
167 {0x312D, 0x02},
168 {0x3AC4, 0x01},
169 {0x310B, 0x00},
170 {0x30EE, 0x01},
171 {0x3304, 0x32},
172 {0x3306, 0x32},
173 {0x3590, 0x32},
174 {0x3686, 0x32},
175 {0x3045, 0x32},
176 {0x301A, 0x00},
177 {0x304C, 0x00},
178 {0x304D, 0x03},
179 {0x331C, 0x1A},
180 {0x3502, 0x02},
181 {0x3529, 0x0E},
182 {0x352A, 0x0E},
183 {0x352B, 0x0E},
184 {0x3538, 0x0E},
185 {0x3539, 0x0E},
186 {0x3553, 0x00},
187 {0x357D, 0x05},
188 {0x357F, 0x05},
189 {0x3581, 0x04},
190 {0x3583, 0x76},
191 {0x3587, 0x01},
192 {0x35BB, 0x0E},
193 {0x35BC, 0x0E},
194 {0x35BD, 0x0E},
195 {0x35BE, 0x0E},
196 {0x35BF, 0x0E},
197 {0x366E, 0x00},
198 {0x366F, 0x00},
199 {0x3670, 0x00},
200 {0x3671, 0x00},
201 {0x3004, 0x01},
202 {0x3005, 0x01},
203 {0x3006, 0x00},
204 {0x3007, 0x02},
205 {0x300E, 0x00},
206 {0x300F, 0x00},
207 {0x3037, 0x00},
208 {0x3038, 0x00},
209 {0x3039, 0x00},
210 {0x303A, 0x00},
211 {0x303B, 0x00},
212 {0x30DD, 0x00},
213 {0x30DE, 0x00},
214 {0x30DF, 0x00},
215 {0x30E0, 0x00},
216 {0x30E1, 0x00},
217 {0x30E2, 0x01},
218 {0x30F6, 0xE0},
219 {0x30F7, 0x04},
220 {0x30F8, 0xDA},
221 {0x30F9, 0x16},
222 {0x30FA, 0x00},
223 {0x3130, 0x86},
224 {0x3131, 0x08},
225 {0x3132, 0x7E},
226 {0x3133, 0x08},
227 {0x3A54, 0x18},
228 {0x3A55, 0x0F},
229 {0x3342, 0x0A},
230 {0x3343, 0x00},
231 {0x3344, 0x16},
232 {0x3345, 0x00},
233 {0x3528, 0x0E},
234 {0x3554, 0x1F},
235 {0x3555, 0x01},
236 {0x3556, 0x01},
237 {0x3557, 0x01},
238 {0x3558, 0x01},
239 {0x3559, 0x00},
240 {0x355A, 0x00},
241 {0x35BA, 0x0E},
242 {0x366A, 0x1B},
243 {0x366B, 0x1A},
244 {0x366C, 0x19},
245 {0x366D, 0x17},
246 {0x33A6, 0x01},
247 {0x306B, 0x05},
248 {0x3A41, 0x08},
249 {0x3134, 0x77},
250 {0x3135, 0x00},
251 {0x3136, 0x67},
252 {0x3137, 0x00},
253 {0x3138, 0x37},
254 {0x3139, 0x00},
255 {0x313A, 0x37},
256 {0x313B, 0x00},
257 {0x313C, 0x37},
258 {0x313D, 0x00},
259 {0x313E, 0xDF},
260 {0x313F, 0x00},
261 {0x3140, 0x37},
262 {0x3141, 0x00},
263 {0x3142, 0x2F},
264 {0x3143, 0x00},
265 {0x3144, 0x0F},
266 {0x3145, 0x00},
267 {0x3A85, 0x03},
268 {0x3A86, 0x47},
269 {0x3A87, 0x00},
270 {0x3A43, 0x01},
271 {REG_DELAY, 0x10},
272 {0x303E, 0x02},
273 {REG_DELAY, 0x07},
274 {0x30F4, 0x00},
275 {0x3018, 0xA2},
276 {0x300a, 0x9c},
277 {0x300b, 0x02},
278 {0x300c, 0x0c},
279 {0x300d, 0x00},
280 {0x312e, 0x01}, //CSI_LANE_MODE
281 {0x3aa2, 0x01}, //PHYSICAL_LANE_NUM
282 {0x3001, 0x10},
283
284 {REG_NULL, 0x00},
285 };
286
287 /*
288 * Xclk 24Mhz
289 * max_framerate 30fps
290 * mipi_datarate per lane 720Mbps
291 * 2 lane
292 */
293 static const struct regval imx317_1932x1094_regs_2lane[] = {
294 {0x3000, 0x1f},
295 {0x3004, 0x02},
296 {0x3005, 0x21},
297 {0x3006, 0x00},
298 {0x3007, 0x11},
299 /* crop and scale*/
300 {0x3037, 0x01},
301 {0x3038, 0x00},
302 {0x3039, 0x00},
303 {0x303A, 0x00},
304 {0x303B, 0x0F},
305
306 {0x30E2, 0x02},
307 {0x30F6, 0x76},
308 {0x30F7, 0x02},
309 {0x30F8, 0x0a},
310 {0x30F9, 0x0f},
311 {0x30FA, 0x00},
312 {0x3130, 0x4e},
313 {0x3131, 0x04},
314 {0x3132, 0x46},
315 {0x3133, 0x04},
316 {0x3a54, 0x8c},
317 {0x3a55, 0x07},
318 {0x3344, 0x1a},
319 {0x3554, 0x00},
320 {REG_NULL, 0x00},
321 };
322
323 /*
324 * Xclk 24Mhz
325 * max_framerate 30fps
326 * mipi_datarate per lane 720Mbps
327 * 2 lane
328 */
329 static const struct regval imx317_3864x2174_regs_2lane[] = {
330 {0x3000, 0x1f},
331 {0x3004, 0x01},
332 {0x3005, 0x01},
333 {0x3006, 0x00},
334 {0x3007, 0x02},
335 /* crop and scale*/
336 {0x3037, 0x00},
337 {0x3038, 0x00},
338 {0x3039, 0x00},
339 {0x303A, 0x00},
340 {0x303B, 0x0F},
341
342 {0x30E2, 0x01},
343 {0x30F6, 0xE0},
344 {0x30F7, 0x04},
345 {0x30F8, 0xDA},
346 {0x30F9, 0x16},
347 {0x30FA, 0x00},
348 {0x3130, 0x86},
349 {0x3131, 0x08},
350 {0x3132, 0x7E},
351 {0x3133, 0x08},
352 {0x3A54, 0x18},
353 {0x3A55, 0x0F},
354 {0x3344, 0x16},
355 {0x3554, 0x1F},
356 {0x3A43, 0x01},
357 {REG_NULL, 0x00},
358 };
359
360 static const struct regval imx317_global_regs_4lane[] = {
361 {0x3000, 0x1f},
362 {0x303E, 0x02},
363 {0x3120, 0xF0},
364 {0x3121, 0x00},
365 {0x3122, 0x02},
366 {0x3123, 0x01},
367 {0x3129, 0x9C},
368 {0x312A, 0x02},
369 {0x312D, 0x02},
370 {0x3AC4, 0x01},
371 {0x310B, 0x00},
372 {0x30EE, 0x01},
373 {0x3304, 0x32},
374 {0x3306, 0x32},
375 {0x3590, 0x32},
376 {0x3686, 0x32},
377 {0x3045, 0x32},
378 {0x301A, 0x00},
379 {0x304C, 0x00},
380 {0x304D, 0x03},
381 {0x331C, 0x1A},
382 {0x3502, 0x02},
383 {0x3529, 0x0E},
384 {0x352A, 0x0E},
385 {0x352B, 0x0E},
386 {0x3538, 0x0E},
387 {0x3539, 0x0E},
388 {0x3553, 0x00},
389 {0x357D, 0x05},
390 {0x357F, 0x05},
391 {0x3581, 0x04},
392 {0x3583, 0x76},
393 {0x3587, 0x01},
394 {0x35BB, 0x0E},
395 {0x35BC, 0x0E},
396 {0x35BD, 0x0E},
397 {0x35BE, 0x0E},
398 {0x35BF, 0x0E},
399 {0x366E, 0x00},
400 {0x366F, 0x00},
401 {0x3670, 0x00},
402 {0x3671, 0x00},
403 {0x3004, 0x01},
404 {0x3005, 0x01},
405 {0x3006, 0x00},
406 {0x3007, 0x02},
407 {0x300E, 0x00},
408 {0x300F, 0x00},
409 {0x3037, 0x00},
410 {0x3038, 0x00},
411 {0x3039, 0x00},
412 {0x303A, 0x00},
413 {0x303B, 0x00},
414 {0x30DD, 0x00},
415 {0x30DE, 0x00},
416 {0x30DF, 0x00},
417 {0x30E0, 0x00},
418 {0x30E1, 0x00},
419 {0x30E2, 0x01},
420 {0x30F6, 0x10},
421 {0x30F7, 0x02},
422 {0x30F8, 0xc6},
423 {0x30F9, 0x11},
424 {0x30FA, 0x00},
425 {0x3130, 0x86},
426 {0x3131, 0x08},
427 {0x3132, 0x7E},
428 {0x3133, 0x08},
429 {0x3A54, 0x18},
430 {0x3A55, 0x0F},
431 {0x3342, 0x0A},
432 {0x3343, 0x00},
433 {0x3344, 0x16},
434 {0x3345, 0x00},
435 {0x3528, 0x0E},
436 {0x3554, 0x1F},
437 {0x3555, 0x01},
438 {0x3556, 0x01},
439 {0x3557, 0x01},
440 {0x3558, 0x01},
441 {0x3559, 0x00},
442 {0x355A, 0x00},
443 {0x35BA, 0x0E},
444 {0x366A, 0x1B},
445 {0x366B, 0x1A},
446 {0x366C, 0x19},
447 {0x366D, 0x17},
448 {0x33A6, 0x01},
449 {0x306B, 0x05},
450 {0x3A41, 0x08},
451 {0x3134, 0x77},
452 {0x3135, 0x00},
453 {0x3136, 0x67},
454 {0x3137, 0x00},
455 {0x3138, 0x37},
456 {0x3139, 0x00},
457 {0x313A, 0x37},
458 {0x313B, 0x00},
459 {0x313C, 0x37},
460 {0x313D, 0x00},
461 {0x313E, 0xDF},
462 {0x313F, 0x00},
463 {0x3140, 0x37},
464 {0x3141, 0x00},
465 {0x3142, 0x2F},
466 {0x3143, 0x00},
467 {0x3144, 0x0F},
468 {0x3145, 0x00},
469 {0x3A85, 0x03},
470 {0x3A86, 0x47},
471 {0x3A87, 0x00},
472 {0x3A43, 0x01},
473 {REG_DELAY, 0x10},
474 {0x303E, 0x02},
475 {REG_DELAY, 0x07},
476 {0x30F4, 0x00},
477 {0x3018, 0xA2},
478 {0x300a, 0x9c},
479 {0x300b, 0x02},
480 {0x300c, 0x0c},
481 {0x300d, 0x00},
482 {0x312e, 0x03}, //CSI_LANE_MODE
483 {0x3aa2, 0x03}, //PHYSICAL_LANE_NUM
484 {0x3001, 0x10},
485 {REG_NULL, 0x00},
486 };
487
488 /*
489 * Xclk 24Mhz
490 * max_framerate 30fps
491 * mipi_datarate per lane 720Mbps
492 * 4 lane
493 */
494 static const struct regval imx317_1932x1094_regs_4lane[] = {
495 {0x3000, 0x1f},
496 {0x3004, 0x02},
497 {0x3005, 0x21},
498 {0x3006, 0x00},
499 {0x3007, 0x11},
500 /* crop and scale*/
501 {0x3037, 0x01},
502 {0x3038, 0x00},
503 {0x3039, 0x00},
504 {0x303A, 0x00},
505 {0x303B, 0x0F},
506
507 {0x30E2, 0x02},
508 {0x30F6, 0x1e},
509 {0x30F7, 0x01},
510 {0x30F8, 0xD0},
511 {0x30F9, 0x20},
512 {0x30FA, 0x00},
513 {0x3130, 0x4e},
514 {0x3131, 0x04},
515 {0x3132, 0x46},
516 {0x3133, 0x04},
517 {0x3a54, 0x8c},
518 {0x3a55, 0x07},
519 {0x3344, 0x1a},
520 {0x3554, 0x00},
521 {0x3A43, 0x01},
522
523 {REG_NULL, 0x00},
524 };
525
526 /*
527 * Xclk 24Mhz
528 * max_framerate 30fps
529 * mipi_datarate per lane 720Mbps
530 * 4 lane
531 */
532 static const struct regval imx317_3864x2174_regs_4lane[] = {
533 {0x3000, 0x1f},
534 {0x3004, 0x01},
535 {0x3005, 0x01},
536 {0x3006, 0x00},
537 {0x3007, 0x02},
538 /* crop and scale*/
539 {0x3037, 0x00},
540 {0x3038, 0x00},
541 {0x3039, 0x00},
542 {0x303A, 0x00},
543 {0x303B, 0x0F},
544
545 {0x30E2, 0x01},
546 {0x30F6, 0x10},
547 {0x30F7, 0x02},
548 {0x30F8, 0xc6},
549 {0x30F9, 0x11},
550 {0x30FA, 0x00},
551 {0x3130, 0x86},
552 {0x3131, 0x08},
553 {0x3132, 0x7E},
554 {0x3133, 0x08},
555 {0x3A54, 0x18},
556 {0x3A55, 0x0F},
557 {0x3344, 0x16},
558 {0x3554, 0x1F},
559 {0x3A43, 0x01},
560 {REG_NULL, 0x00},
561 };
562
563 static const struct imx317_mode supported_modes_2lane[] = {
564 {
565 .width = 1920,
566 .height = 1080,
567 .max_fps = {
568 .numerator = 10000,
569 .denominator = 300000,
570 },
571 .exp_def = 0x000C,
572 .hts_def = 0x0276,
573 .vts_def = 0x0f0a,
574 .reg_list = imx317_1932x1094_regs_2lane,
575 },
576 {
577 .width = 3840,
578 .height = 2160,
579 .max_fps = {
580 .numerator = 10000,
581 .denominator = 100000,
582 },
583 .exp_def = 0x000c,
584 .hts_def = 0x04E0,
585 .vts_def = 0x16DA,
586 .reg_list = imx317_3864x2174_regs_2lane,
587 },
588 };
589
590 static const struct imx317_mode supported_modes_4lane[] = {
591 {
592 .width = 1920,
593 .height = 1080,
594 .max_fps = {
595 .numerator = 10000,
596 .denominator = 300000,
597 },
598 .exp_def = 0x000c,
599 .hts_def = 0x011E,
600 .vts_def = 0x20D0,
601 .reg_list = imx317_1932x1094_regs_4lane,
602 },
603 {
604 .width = 3840,
605 .height = 2160,
606 .max_fps = {
607 .numerator = 10000,
608 .denominator = 300000,
609 },
610 .exp_def = 0x000C,
611 .hts_def = 0x0210,
612 .vts_def = 0x11C6,
613 .reg_list = imx317_3864x2174_regs_4lane,
614 },
615 };
616
617 static const struct imx317_mode *supported_modes;
618
619 static const s64 link_freq_menu_items[] = {
620 MIPI_FREQ,
621 };
622
623 static const char * const imx317_test_pattern_menu[] = {
624 "Disabled",
625 "Vertical Color Bar Type 1",
626 "Vertical Color Bar Type 2",
627 "Vertical Color Bar Type 3",
628 "Vertical Color Bar Type 4"
629 };
630
631 /* Write registers up to 4 at a time */
imx317_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)632 static int imx317_write_reg(struct i2c_client *client, u16 reg,
633 u32 len, u32 val)
634 {
635 u32 buf_i, val_i;
636 u8 buf[6];
637 u8 *val_p;
638 __be32 val_be;
639
640 if (len > 4)
641 return -EINVAL;
642
643 buf[0] = reg >> 8;
644 buf[1] = reg & 0xff;
645
646 val_be = cpu_to_be32(val);
647 val_p = (u8 *)&val_be;
648 buf_i = 2;
649 val_i = 4 - len;
650
651 while (val_i < 4)
652 buf[buf_i++] = val_p[val_i++];
653
654 if (i2c_master_send(client, buf, len + 2) != len + 2)
655 return -EIO;
656
657 return 0;
658 }
659
imx317_write_array(struct i2c_client * client,const struct regval * regs)660 static int imx317_write_array(struct i2c_client *client,
661 const struct regval *regs)
662 {
663 u32 i;
664 int ret = 0;
665
666 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
667 if (regs[i].addr == REG_DELAY) {
668 usleep_range(regs[i].val, 2 * regs[i].val);
669 } else {
670 ret = imx317_write_reg(client, regs[i].addr,
671 IMX317_REG_VALUE_08BIT, regs[i].val);
672 }
673 }
674
675 return ret;
676 }
677
678 /* Read registers up to 4 at a time */
imx317_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)679 static int imx317_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
680 u32 *val)
681 {
682 struct i2c_msg msgs[2];
683 u8 *data_be_p;
684 __be32 data_be = 0;
685 __be16 reg_addr_be = cpu_to_be16(reg);
686 int ret;
687
688 if (len > 4 || !len)
689 return -EINVAL;
690
691 data_be_p = (u8 *)&data_be;
692
693 /* Write register address */
694 msgs[0].addr = client->addr;
695 msgs[0].flags = 0;
696 msgs[0].len = 2;
697 msgs[0].buf = (u8 *)®_addr_be;
698
699 /* Read data from register */
700 msgs[1].addr = client->addr;
701 msgs[1].flags = I2C_M_RD;
702 msgs[1].len = len;
703 msgs[1].buf = &data_be_p[4 - len];
704
705 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
706 if (ret != ARRAY_SIZE(msgs))
707 return -EIO;
708
709 *val = be32_to_cpu(data_be);
710
711 return 0;
712 }
713
imx317_get_reso_dist(const struct imx317_mode * mode,struct v4l2_mbus_framefmt * framefmt)714 static int imx317_get_reso_dist(const struct imx317_mode *mode,
715 struct v4l2_mbus_framefmt *framefmt)
716 {
717 return abs(mode->width - framefmt->width) +
718 abs(mode->height - framefmt->height);
719 }
720
721 static const struct imx317_mode *
imx317_find_best_fit(struct imx317 * imx317,struct v4l2_subdev_format * fmt)722 imx317_find_best_fit(struct imx317 *imx317,
723 struct v4l2_subdev_format *fmt)
724 {
725 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
726 int dist;
727 int cur_best_fit = 0;
728 int cur_best_fit_dist = -1;
729 unsigned int i;
730
731 for (i = 0; i < imx317->cfg_num; i++) {
732 dist = imx317_get_reso_dist(&supported_modes[i], framefmt);
733 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
734 cur_best_fit_dist = dist;
735 cur_best_fit = i;
736 }
737 }
738
739 return &supported_modes[cur_best_fit];
740 }
741
imx317_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)742 static int imx317_set_fmt(struct v4l2_subdev *sd,
743 struct v4l2_subdev_pad_config *cfg,
744 struct v4l2_subdev_format *fmt)
745 {
746 struct imx317 *imx317 = to_imx317(sd);
747 const struct imx317_mode *mode;
748 s64 h_blank, vblank_def;
749
750 mutex_lock(&imx317->mutex);
751
752 mode = imx317_find_best_fit(imx317, fmt);
753 fmt->format.code = IMX317_MEDIA_BUS_FMT;
754 fmt->format.width = mode->width;
755 fmt->format.height = mode->height;
756 fmt->format.field = V4L2_FIELD_NONE;
757 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
758 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
759 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
760 #else
761 mutex_unlock(&imx317->mutex);
762 return -ENOTTY;
763 #endif
764 } else {
765 imx317->cur_mode = mode;
766 h_blank = mode->hts_def;
767 __v4l2_ctrl_modify_range(imx317->hblank, h_blank,
768 h_blank, 1, h_blank);
769 vblank_def = mode->vts_def - mode->height;
770 __v4l2_ctrl_modify_range(imx317->vblank, vblank_def,
771 IMX317_VTS_MAX - mode->height,
772 1, vblank_def);
773 }
774
775 mutex_unlock(&imx317->mutex);
776
777 return 0;
778 }
779
imx317_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)780 static int imx317_get_fmt(struct v4l2_subdev *sd,
781 struct v4l2_subdev_pad_config *cfg,
782 struct v4l2_subdev_format *fmt)
783 {
784 struct imx317 *imx317 = to_imx317(sd);
785 const struct imx317_mode *mode = imx317->cur_mode;
786
787 mutex_lock(&imx317->mutex);
788 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
789 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
790 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
791 #else
792 mutex_unlock(&imx317->mutex);
793 return -ENOTTY;
794 #endif
795 } else {
796 fmt->format.width = mode->width;
797 fmt->format.height = mode->height;
798 fmt->format.code = IMX317_MEDIA_BUS_FMT;
799 fmt->format.field = V4L2_FIELD_NONE;
800 }
801 mutex_unlock(&imx317->mutex);
802
803 return 0;
804 }
805
imx317_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)806 static int imx317_enum_mbus_code(struct v4l2_subdev *sd,
807 struct v4l2_subdev_pad_config *cfg,
808 struct v4l2_subdev_mbus_code_enum *code)
809 {
810 if (code->index != 0)
811 return -EINVAL;
812 code->code = IMX317_MEDIA_BUS_FMT;
813
814 return 0;
815 }
816
imx317_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)817 static int imx317_enum_frame_sizes(struct v4l2_subdev *sd,
818 struct v4l2_subdev_pad_config *cfg,
819 struct v4l2_subdev_frame_size_enum *fse)
820 {
821 struct imx317 *imx317 = to_imx317(sd);
822
823 if (fse->index >= imx317->cfg_num)
824 return -EINVAL;
825
826 if (fse->code != IMX317_MEDIA_BUS_FMT)
827 return -EINVAL;
828
829 fse->min_width = supported_modes[fse->index].width;
830 fse->max_width = supported_modes[fse->index].width;
831 fse->max_height = supported_modes[fse->index].height;
832 fse->min_height = supported_modes[fse->index].height;
833
834 return 0;
835 }
836
imx317_enable_test_pattern(struct imx317 * imx317,u32 pattern)837 static int imx317_enable_test_pattern(struct imx317 *imx317, u32 pattern)
838 {
839 return 0;
840 }
841
imx317_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)842 static int imx317_g_frame_interval(struct v4l2_subdev *sd,
843 struct v4l2_subdev_frame_interval *fi)
844 {
845 struct imx317 *imx317 = to_imx317(sd);
846 const struct imx317_mode *mode = imx317->cur_mode;
847
848 fi->interval = mode->max_fps;
849
850 return 0;
851 }
852
imx317_get_module_inf(struct imx317 * imx317,struct rkmodule_inf * inf)853 static void imx317_get_module_inf(struct imx317 *imx317,
854 struct rkmodule_inf *inf)
855 {
856 memset(inf, 0, sizeof(*inf));
857 strlcpy(inf->base.sensor, IMX317_NAME, sizeof(inf->base.sensor));
858 strlcpy(inf->base.module, imx317->module_name,
859 sizeof(inf->base.module));
860 strlcpy(inf->base.lens, imx317->len_name, sizeof(inf->base.lens));
861 }
862
imx317_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)863 static long imx317_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
864 {
865 struct imx317 *imx317 = to_imx317(sd);
866 long ret = 0;
867 u32 stream = 0;
868
869 switch (cmd) {
870 case RKMODULE_GET_MODULE_INFO:
871 imx317_get_module_inf(imx317, (struct rkmodule_inf *)arg);
872 break;
873 case RKMODULE_SET_QUICK_STREAM:
874
875 stream = *((u32 *)arg);
876
877 if (stream)
878 imx317_write_reg(imx317->client, IMX317_REG_CTRL_MODE,
879 IMX317_REG_VALUE_08BIT, IMX317_MODE_STREAMING);
880 else
881 imx317_write_reg(imx317->client, IMX317_REG_CTRL_MODE,
882 IMX317_REG_VALUE_08BIT, IMX317_MODE_SW_STANDBY);
883 break;
884 default:
885 ret = -ENOIOCTLCMD;
886 break;
887 }
888
889 return ret;
890 }
891
892 #ifdef CONFIG_COMPAT
imx317_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)893 static long imx317_compat_ioctl32(struct v4l2_subdev *sd,
894 unsigned int cmd, unsigned long arg)
895 {
896 void __user *up = compat_ptr(arg);
897 struct rkmodule_inf *inf;
898 struct rkmodule_awb_cfg *cfg;
899 long ret;
900 u32 stream = 0;
901
902 switch (cmd) {
903 case RKMODULE_GET_MODULE_INFO:
904 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
905 if (!inf) {
906 ret = -ENOMEM;
907 return ret;
908 }
909
910 ret = imx317_ioctl(sd, cmd, inf);
911 if (!ret)
912 ret = copy_to_user(up, inf, sizeof(*inf));
913 kfree(inf);
914 break;
915 case RKMODULE_AWB_CFG:
916 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
917 if (!cfg) {
918 ret = -ENOMEM;
919 return ret;
920 }
921
922 ret = copy_from_user(cfg, up, sizeof(*cfg));
923 if (!ret)
924 ret = imx317_ioctl(sd, cmd, cfg);
925 kfree(cfg);
926 break;
927 case RKMODULE_SET_QUICK_STREAM:
928 ret = copy_from_user(&stream, up, sizeof(u32));
929 if (!ret)
930 ret = imx317_ioctl(sd, cmd, &stream);
931 break;
932 default:
933 ret = -ENOIOCTLCMD;
934 break;
935 }
936
937 return ret;
938 }
939 #endif
940
__imx317_start_stream(struct imx317 * imx317)941 static int __imx317_start_stream(struct imx317 *imx317)
942 {
943 int ret;
944
945 ret = imx317_write_array(imx317->client, imx317->cur_mode->reg_list);
946 if (ret)
947 return ret;
948
949 /* In case these controls are set before streaming */
950 mutex_unlock(&imx317->mutex);
951 ret = v4l2_ctrl_handler_setup(&imx317->ctrl_handler);
952 mutex_lock(&imx317->mutex);
953 if (ret)
954 return ret;
955
956 return imx317_write_reg(imx317->client, IMX317_REG_CTRL_MODE,
957 IMX317_REG_VALUE_08BIT, IMX317_MODE_STREAMING);
958 }
959
__imx317_stop_stream(struct imx317 * imx317)960 static int __imx317_stop_stream(struct imx317 *imx317)
961 {
962 return imx317_write_reg(imx317->client, IMX317_REG_CTRL_MODE,
963 IMX317_REG_VALUE_08BIT, IMX317_MODE_SW_STANDBY);
964 }
965
imx317_s_stream(struct v4l2_subdev * sd,int on)966 static int imx317_s_stream(struct v4l2_subdev *sd, int on)
967 {
968 struct imx317 *imx317 = to_imx317(sd);
969 struct i2c_client *client = imx317->client;
970 int ret = 0;
971
972 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
973 imx317->cur_mode->width,
974 imx317->cur_mode->height,
975 DIV_ROUND_CLOSEST(imx317->cur_mode->max_fps.denominator,
976 imx317->cur_mode->max_fps.numerator));
977
978 mutex_lock(&imx317->mutex);
979 on = !!on;
980 if (on == imx317->streaming)
981 goto unlock_and_return;
982
983 if (on) {
984 ret = pm_runtime_get_sync(&client->dev);
985 if (ret < 0) {
986 pm_runtime_put_noidle(&client->dev);
987 goto unlock_and_return;
988 }
989
990 ret = __imx317_start_stream(imx317);
991 if (ret) {
992 v4l2_err(sd, "start stream failed while write regs\n");
993 pm_runtime_put(&client->dev);
994 goto unlock_and_return;
995 }
996 } else {
997 __imx317_stop_stream(imx317);
998 pm_runtime_put(&client->dev);
999 }
1000
1001 imx317->streaming = on;
1002
1003 unlock_and_return:
1004 mutex_unlock(&imx317->mutex);
1005
1006 return ret;
1007 }
1008
imx317_s_power(struct v4l2_subdev * sd,int on)1009 static int imx317_s_power(struct v4l2_subdev *sd, int on)
1010 {
1011 struct imx317 *imx317 = to_imx317(sd);
1012 struct i2c_client *client = imx317->client;
1013 int ret = 0;
1014
1015 mutex_lock(&imx317->mutex);
1016
1017 /* If the power state is not modified - no work to do. */
1018 if (imx317->power_on == !!on)
1019 goto unlock_and_return;
1020
1021 if (on) {
1022 ret = pm_runtime_get_sync(&client->dev);
1023 if (ret < 0) {
1024 pm_runtime_put_noidle(&client->dev);
1025 goto unlock_and_return;
1026 }
1027
1028 ret = imx317_write_array(imx317->client, imx317_global_regs);
1029 if (ret) {
1030 v4l2_err(sd, "could not set init registers\n");
1031 pm_runtime_put_noidle(&client->dev);
1032 goto unlock_and_return;
1033 }
1034
1035 imx317->power_on = true;
1036 } else {
1037 pm_runtime_put(&client->dev);
1038 imx317->power_on = false;
1039 }
1040
1041 unlock_and_return:
1042 mutex_unlock(&imx317->mutex);
1043
1044 return ret;
1045 }
1046
1047 /* Calculate the delay in us by clock rate and clock cycles */
imx317_cal_delay(u32 cycles)1048 static inline u32 imx317_cal_delay(u32 cycles)
1049 {
1050 return DIV_ROUND_UP(cycles, IMX317_XVCLK_FREQ / 1000 / 1000);
1051 }
1052
__imx317_power_on(struct imx317 * imx317)1053 static int __imx317_power_on(struct imx317 *imx317)
1054 {
1055 int ret;
1056 u32 delay_us;
1057 struct device *dev = &imx317->client->dev;
1058
1059 if (!IS_ERR(imx317->power_gpio))
1060 gpiod_set_value_cansleep(imx317->power_gpio, 1);
1061 usleep_range(3000, 5000);
1062
1063 if (!IS_ERR_OR_NULL(imx317->pins_default)) {
1064 ret = pinctrl_select_state(imx317->pinctrl,
1065 imx317->pins_default);
1066 if (ret < 0)
1067 dev_err(dev, "could not set pins\n");
1068 }
1069 ret = clk_set_rate(imx317->xvclk, IMX317_XVCLK_FREQ);
1070 if (ret < 0)
1071 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1072 if (clk_get_rate(imx317->xvclk) != IMX317_XVCLK_FREQ)
1073 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1074 ret = clk_prepare_enable(imx317->xvclk);
1075 if (ret < 0) {
1076 dev_err(dev, "Failed to enable xvclk\n");
1077 return ret;
1078 }
1079 if (!IS_ERR(imx317->reset_gpio))
1080 gpiod_set_value_cansleep(imx317->reset_gpio, 0);
1081
1082 ret = regulator_bulk_enable(IMX317_NUM_SUPPLIES, imx317->supplies);
1083 if (ret < 0) {
1084 dev_err(dev, "Failed to enable regulators\n");
1085 goto disable_clk;
1086 }
1087
1088 if (!IS_ERR(imx317->reset_gpio))
1089 gpiod_set_value_cansleep(imx317->reset_gpio, 1);
1090
1091 usleep_range(500, 1000);
1092 if (!IS_ERR(imx317->pwdn_gpio))
1093 gpiod_set_value_cansleep(imx317->pwdn_gpio, 1);
1094
1095 /* 8192 cycles prior to first SCCB transaction */
1096 delay_us = imx317_cal_delay(8192);
1097 usleep_range(delay_us, delay_us * 2);
1098
1099 return 0;
1100
1101 disable_clk:
1102 clk_disable_unprepare(imx317->xvclk);
1103
1104 return ret;
1105 }
1106
__imx317_power_off(struct imx317 * imx317)1107 static void __imx317_power_off(struct imx317 *imx317)
1108 {
1109 int ret;
1110 struct device *dev = &imx317->client->dev;
1111
1112 if (!IS_ERR(imx317->pwdn_gpio))
1113 gpiod_set_value_cansleep(imx317->pwdn_gpio, 0);
1114 clk_disable_unprepare(imx317->xvclk);
1115 if (!IS_ERR(imx317->reset_gpio))
1116 gpiod_set_value_cansleep(imx317->reset_gpio, 0);
1117 if (!IS_ERR_OR_NULL(imx317->pins_sleep)) {
1118 ret = pinctrl_select_state(imx317->pinctrl,
1119 imx317->pins_sleep);
1120 if (ret < 0)
1121 dev_dbg(dev, "could not set pins\n");
1122 }
1123 if (!IS_ERR(imx317->power_gpio))
1124 gpiod_set_value_cansleep(imx317->power_gpio, 0);
1125 regulator_bulk_disable(IMX317_NUM_SUPPLIES, imx317->supplies);
1126 }
1127
imx317_runtime_resume(struct device * dev)1128 static int imx317_runtime_resume(struct device *dev)
1129 {
1130 struct i2c_client *client = to_i2c_client(dev);
1131 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1132 struct imx317 *imx317 = to_imx317(sd);
1133
1134 return __imx317_power_on(imx317);
1135 }
1136
imx317_runtime_suspend(struct device * dev)1137 static int imx317_runtime_suspend(struct device *dev)
1138 {
1139 struct i2c_client *client = to_i2c_client(dev);
1140 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1141 struct imx317 *imx317 = to_imx317(sd);
1142
1143 __imx317_power_off(imx317);
1144
1145 return 0;
1146 }
1147
1148 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx317_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1149 static int imx317_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1150 {
1151 struct imx317 *imx317 = to_imx317(sd);
1152 struct v4l2_mbus_framefmt *try_fmt =
1153 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1154 const struct imx317_mode *def_mode = &supported_modes[0];
1155
1156 mutex_lock(&imx317->mutex);
1157 /* Initialize try_fmt */
1158 try_fmt->width = def_mode->width;
1159 try_fmt->height = def_mode->height;
1160 try_fmt->code = IMX317_MEDIA_BUS_FMT;
1161 try_fmt->field = V4L2_FIELD_NONE;
1162
1163 mutex_unlock(&imx317->mutex);
1164 /* No crop or compose */
1165
1166 return 0;
1167 }
1168 #endif
1169
imx317_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1170 static int imx317_enum_frame_interval(struct v4l2_subdev *sd,
1171 struct v4l2_subdev_pad_config *cfg,
1172 struct v4l2_subdev_frame_interval_enum *fie)
1173 {
1174 struct imx317 *imx317 = to_imx317(sd);
1175
1176 if (fie->index >= imx317->cfg_num)
1177 return -EINVAL;
1178
1179 fie->code = IMX317_MEDIA_BUS_FMT;
1180 fie->width = supported_modes[fie->index].width;
1181 fie->height = supported_modes[fie->index].height;
1182 fie->interval = supported_modes[fie->index].max_fps;
1183 return 0;
1184 }
1185
imx317_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1186 static int imx317_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1187 struct v4l2_mbus_config *config)
1188 {
1189 u32 val = 0;
1190 struct imx317 *imx317 = to_imx317(sd);
1191
1192 val = 1 << (imx317->lane_num - 1) |
1193 V4L2_MBUS_CSI2_CHANNEL_0 |
1194 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1195 config->type = V4L2_MBUS_CSI2_DPHY;
1196 config->flags = val;
1197
1198 return 0;
1199 }
1200
1201 static const struct dev_pm_ops imx317_pm_ops = {
1202 SET_RUNTIME_PM_OPS(imx317_runtime_suspend,
1203 imx317_runtime_resume, NULL)
1204 };
1205
1206 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1207 static const struct v4l2_subdev_internal_ops imx317_internal_ops = {
1208 .open = imx317_open,
1209 };
1210 #endif
1211
1212 static const struct v4l2_subdev_core_ops imx317_core_ops = {
1213 .s_power = imx317_s_power,
1214 .ioctl = imx317_ioctl,
1215 #ifdef CONFIG_COMPAT
1216 .compat_ioctl32 = imx317_compat_ioctl32,
1217 #endif
1218 };
1219
1220 static const struct v4l2_subdev_video_ops imx317_video_ops = {
1221 .s_stream = imx317_s_stream,
1222 .g_frame_interval = imx317_g_frame_interval,
1223 };
1224
1225 static const struct v4l2_subdev_pad_ops imx317_pad_ops = {
1226 .enum_mbus_code = imx317_enum_mbus_code,
1227 .enum_frame_size = imx317_enum_frame_sizes,
1228 .enum_frame_interval = imx317_enum_frame_interval,
1229 .get_fmt = imx317_get_fmt,
1230 .set_fmt = imx317_set_fmt,
1231 .get_mbus_config = imx317_g_mbus_config,
1232 };
1233
1234 static const struct v4l2_subdev_ops imx317_subdev_ops = {
1235 .core = &imx317_core_ops,
1236 .video = &imx317_video_ops,
1237 .pad = &imx317_pad_ops,
1238 };
1239
imx317_set_ctrl(struct v4l2_ctrl * ctrl)1240 static int imx317_set_ctrl(struct v4l2_ctrl *ctrl)
1241 {
1242 struct imx317 *imx317 = container_of(ctrl->handler,
1243 struct imx317, ctrl_handler);
1244 struct i2c_client *client = imx317->client;
1245 s64 max;
1246 u32 val = 0;
1247 u32 vts_tmp = 0;
1248 int ret = 0;
1249
1250 /* Propagate change of current control to all related controls */
1251 switch (ctrl->id) {
1252 case V4L2_CID_VBLANK:
1253 /* Update max exposure while meeting expected vblanking */
1254 max = imx317->cur_mode->height + ctrl->val - 4;
1255 __v4l2_ctrl_modify_range(imx317->exposure,
1256 imx317->exposure->minimum, max,
1257 imx317->exposure->step,
1258 imx317->exposure->default_value);
1259 break;
1260 }
1261
1262 if (!pm_runtime_get_if_in_use(&client->dev))
1263 return 0;
1264
1265 switch (ctrl->id) {
1266 case V4L2_CID_EXPOSURE:
1267 /* 4 least significant bits of expsoure are fractional part */
1268 /* calculate actual integration time */
1269 ret = imx317_read_reg(imx317->client, IMX317_REG_VTS_H,
1270 IMX317_REG_VALUE_08BIT, &val);
1271 vts_tmp = (val & 0xff) << 16;
1272 ret |= imx317_read_reg(imx317->client, IMX317_REG_VTS_M,
1273 IMX317_REG_VALUE_08BIT, &val);
1274 vts_tmp = vts_tmp | ((val & 0xff) << 8);
1275 ret |= imx317_read_reg(imx317->client, IMX317_REG_VTS_L,
1276 IMX317_REG_VALUE_08BIT, &val);
1277 vts_tmp = vts_tmp | (val & 0xff);
1278 ctrl->val = vts_tmp + 1 - ctrl->val;
1279 ret = imx317_write_reg(imx317->client,
1280 IMX317_REG_EXPOSURE_H,
1281 IMX317_REG_VALUE_08BIT,
1282 (ctrl->val & 0xFF00) >> 8);
1283 ret |= imx317_write_reg(imx317->client,
1284 IMX317_REG_EXPOSURE_L,
1285 IMX317_REG_VALUE_08BIT,
1286 ctrl->val & 0xFF);
1287 break;
1288 case V4L2_CID_ANALOGUE_GAIN:
1289 if (ctrl->val > IMX317_GAIN_MAX)
1290 ctrl->val = IMX317_GAIN_MAX;
1291 if (ctrl->val < IMX317_GAIN_MIN)
1292 ctrl->val = IMX317_GAIN_MIN;
1293 val = 2048 - (2048 * IMX317_GAIN_MIN) / ctrl->val;
1294
1295 ret = imx317_write_reg(imx317->client, IMX317_REG_GAIN_H,
1296 IMX317_REG_VALUE_08BIT,
1297 (val >> IMX317_GAIN_H_SHIFT) & IMX317_GAIN_H_MASK);
1298 ret |= imx317_write_reg(imx317->client, IMX317_REG_GAIN_L,
1299 IMX317_REG_VALUE_08BIT,
1300 val & IMX317_GAIN_L_MASK);
1301 break;
1302 case V4L2_CID_VBLANK:
1303 val = ctrl->val + imx317->cur_mode->height;
1304 ret = imx317_write_reg(imx317->client, IMX317_REG_VTS_H,
1305 IMX317_REG_VALUE_08BIT,
1306 (val & 0x0F0000) >> 16);
1307 ret |= imx317_write_reg(imx317->client, IMX317_REG_VTS_M,
1308 IMX317_REG_VALUE_08BIT,
1309 (val & 0x00FF00) >> 8);
1310 ret |= imx317_write_reg(imx317->client, IMX317_REG_VTS_L,
1311 IMX317_REG_VALUE_08BIT,
1312 val & 0x0000FF);
1313 break;
1314 case V4L2_CID_TEST_PATTERN:
1315 ret = imx317_enable_test_pattern(imx317, ctrl->val);
1316 break;
1317 default:
1318 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1319 __func__, ctrl->id, ctrl->val);
1320 break;
1321 }
1322
1323 pm_runtime_put(&client->dev);
1324
1325 return ret;
1326 }
1327
1328 static const struct v4l2_ctrl_ops imx317_ctrl_ops = {
1329 .s_ctrl = imx317_set_ctrl,
1330 };
1331
imx317_initialize_controls(struct imx317 * imx317)1332 static int imx317_initialize_controls(struct imx317 *imx317)
1333 {
1334 const struct imx317_mode *mode;
1335 struct v4l2_ctrl_handler *handler;
1336 s64 exposure_max, vblank_def;
1337 u32 h_blank;
1338 int ret;
1339
1340 handler = &imx317->ctrl_handler;
1341 mode = imx317->cur_mode;
1342 ret = v4l2_ctrl_handler_init(handler, 8);
1343 if (ret)
1344 return ret;
1345 handler->lock = &imx317->mutex;
1346
1347 imx317->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1348 V4L2_CID_LINK_FREQ, 0, 0,
1349 link_freq_menu_items);
1350
1351 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1352 0, imx317->pixel_rate, 1, imx317->pixel_rate);
1353
1354 h_blank = mode->hts_def;
1355 imx317->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1356 h_blank, h_blank, 1, h_blank);
1357 if (imx317->hblank)
1358 imx317->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1359
1360 vblank_def = mode->vts_def - mode->height;
1361 imx317->vblank = v4l2_ctrl_new_std(handler, &imx317_ctrl_ops,
1362 V4L2_CID_VBLANK, vblank_def,
1363 IMX317_VTS_MAX - mode->height,
1364 1, vblank_def);
1365
1366 exposure_max = mode->vts_def - 4;
1367 imx317->exposure = v4l2_ctrl_new_std(handler, &imx317_ctrl_ops,
1368 V4L2_CID_EXPOSURE, IMX317_EXPOSURE_MIN,
1369 exposure_max, IMX317_EXPOSURE_STEP,
1370 mode->exp_def);
1371
1372 imx317->anal_gain = v4l2_ctrl_new_std(handler, &imx317_ctrl_ops,
1373 V4L2_CID_ANALOGUE_GAIN, IMX317_GAIN_MIN,
1374 IMX317_GAIN_MAX, IMX317_GAIN_STEP,
1375 IMX317_GAIN_DEFAULT);
1376
1377 imx317->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1378 &imx317_ctrl_ops, V4L2_CID_TEST_PATTERN,
1379 ARRAY_SIZE(imx317_test_pattern_menu) - 1,
1380 0, 0, imx317_test_pattern_menu);
1381
1382 if (handler->error) {
1383 ret = handler->error;
1384 dev_err(&imx317->client->dev,
1385 "Failed to init controls(%d)\n", ret);
1386 goto err_free_handler;
1387 }
1388
1389 imx317->subdev.ctrl_handler = handler;
1390
1391 return 0;
1392
1393 err_free_handler:
1394 v4l2_ctrl_handler_free(handler);
1395
1396 return ret;
1397 }
1398
imx317_check_sensor_id(struct imx317 * imx317,struct i2c_client * client)1399 static int imx317_check_sensor_id(struct imx317 *imx317,
1400 struct i2c_client *client)
1401 {
1402 struct device *dev = &imx317->client->dev;
1403 u32 id = 0;
1404 int ret;
1405
1406 ret = imx317_read_reg(client, IMX317_REG_CHIP_ID,
1407 IMX317_REG_VALUE_08BIT, &id);
1408 if (id != CHIP_ID) {
1409 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1410 return -ENODEV;
1411 }
1412
1413 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1414
1415 return 0;
1416 }
1417
imx317_configure_regulators(struct imx317 * imx317)1418 static int imx317_configure_regulators(struct imx317 *imx317)
1419 {
1420 unsigned int i;
1421
1422 for (i = 0; i < IMX317_NUM_SUPPLIES; i++)
1423 imx317->supplies[i].supply = imx317_supply_names[i];
1424
1425 return devm_regulator_bulk_get(&imx317->client->dev,
1426 IMX317_NUM_SUPPLIES,
1427 imx317->supplies);
1428 }
1429
imx317_parse_of(struct imx317 * imx317)1430 static int imx317_parse_of(struct imx317 *imx317)
1431 {
1432 struct device *dev = &imx317->client->dev;
1433 struct device_node *endpoint;
1434 struct fwnode_handle *fwnode;
1435 int rval;
1436
1437 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1438 if (!endpoint) {
1439 dev_err(dev, "Failed to get endpoint\n");
1440 return -EINVAL;
1441 }
1442 fwnode = of_fwnode_handle(endpoint);
1443 rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
1444 of_node_put(endpoint);
1445 if (rval <= 0) {
1446 dev_warn(dev, " Get mipi lane num failed!\n");
1447 return -1;
1448 }
1449
1450 imx317->lane_num = rval;
1451 if (4 == imx317->lane_num) {
1452 imx317->cur_mode = &supported_modes_4lane[0];
1453 supported_modes = supported_modes_4lane;
1454 imx317->cfg_num = ARRAY_SIZE(supported_modes_4lane);
1455 imx317_global_regs = imx317_global_regs_4lane;
1456 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1457 imx317->pixel_rate = MIPI_FREQ * 2U * imx317->lane_num / 10U;
1458 dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
1459 imx317->lane_num, imx317->pixel_rate);
1460 } else {
1461 imx317->cur_mode = &supported_modes_2lane[0];
1462 supported_modes = supported_modes_2lane;
1463 imx317->cfg_num = ARRAY_SIZE(supported_modes_2lane);
1464 imx317_global_regs = imx317_global_regs_2lane;
1465 /*pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1466 imx317->pixel_rate = MIPI_FREQ * 2U * (imx317->lane_num) / 10U;
1467 dev_info(dev, "lane_num(%d) pixel_rate(%u), not supported yet!\n",
1468 imx317->lane_num, imx317->pixel_rate);
1469 }
1470 return 0;
1471 }
1472
imx317_probe(struct i2c_client * client,const struct i2c_device_id * id)1473 static int imx317_probe(struct i2c_client *client,
1474 const struct i2c_device_id *id)
1475 {
1476 struct device *dev = &client->dev;
1477 struct device_node *node = dev->of_node;
1478 struct imx317 *imx317;
1479 struct v4l2_subdev *sd;
1480 char facing[2];
1481 int ret;
1482
1483 dev_info(dev, "driver version: %02x.%02x.%02x",
1484 DRIVER_VERSION >> 16,
1485 (DRIVER_VERSION & 0xff00) >> 8,
1486 DRIVER_VERSION & 0x00ff);
1487
1488 imx317 = devm_kzalloc(dev, sizeof(*imx317), GFP_KERNEL);
1489 if (!imx317)
1490 return -ENOMEM;
1491
1492 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1493 &imx317->module_index);
1494 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1495 &imx317->module_facing);
1496 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1497 &imx317->module_name);
1498 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1499 &imx317->len_name);
1500 if (ret) {
1501 dev_err(dev, "could not get module information!\n");
1502 return -EINVAL;
1503 }
1504
1505 imx317->client = client;
1506 imx317->cur_mode = &supported_modes[0];
1507
1508 imx317->xvclk = devm_clk_get(dev, "xvclk");
1509 if (IS_ERR(imx317->xvclk)) {
1510 dev_err(dev, "Failed to get xvclk\n");
1511 return -EINVAL;
1512 }
1513
1514 imx317->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1515 if (IS_ERR(imx317->power_gpio))
1516 dev_warn(dev, "Failed to get power-gpios\n");
1517 imx317->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1518 if (IS_ERR(imx317->reset_gpio))
1519 dev_warn(dev, "Failed to get reset-gpios\n");
1520
1521 imx317->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1522 if (IS_ERR(imx317->pwdn_gpio))
1523 dev_warn(dev, "Failed to get pwdn-gpios\n");
1524
1525 ret = imx317_parse_of(imx317);
1526 if (ret != 0)
1527 return -EINVAL;
1528
1529 imx317->pinctrl = devm_pinctrl_get(dev);
1530 if (!IS_ERR(imx317->pinctrl)) {
1531 imx317->pins_default =
1532 pinctrl_lookup_state(imx317->pinctrl,
1533 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1534 if (IS_ERR(imx317->pins_default))
1535 dev_err(dev, "could not get default pinstate\n");
1536
1537 imx317->pins_sleep =
1538 pinctrl_lookup_state(imx317->pinctrl,
1539 OF_CAMERA_PINCTRL_STATE_SLEEP);
1540 if (IS_ERR(imx317->pins_sleep))
1541 dev_err(dev, "could not get sleep pinstate\n");
1542 } else {
1543 dev_err(dev, "no pinctrl\n");
1544 }
1545
1546 ret = imx317_configure_regulators(imx317);
1547 if (ret) {
1548 dev_err(dev, "Failed to get power regulators\n");
1549 return ret;
1550 }
1551
1552 mutex_init(&imx317->mutex);
1553
1554 sd = &imx317->subdev;
1555 v4l2_i2c_subdev_init(sd, client, &imx317_subdev_ops);
1556 ret = imx317_initialize_controls(imx317);
1557 if (ret)
1558 goto err_destroy_mutex;
1559
1560 ret = __imx317_power_on(imx317);
1561 if (ret)
1562 goto err_free_handler;
1563
1564 ret = imx317_check_sensor_id(imx317, client);
1565 if (ret)
1566 goto err_power_off;
1567
1568 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1569 sd->internal_ops = &imx317_internal_ops;
1570 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1571 V4L2_SUBDEV_FL_HAS_EVENTS;
1572 #endif
1573 #if defined(CONFIG_MEDIA_CONTROLLER)
1574 imx317->pad.flags = MEDIA_PAD_FL_SOURCE;
1575 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1576 ret = media_entity_pads_init(&sd->entity, 1, &imx317->pad);
1577 if (ret < 0)
1578 goto err_power_off;
1579 #endif
1580
1581 memset(facing, 0, sizeof(facing));
1582 if (strcmp(imx317->module_facing, "back") == 0)
1583 facing[0] = 'b';
1584 else
1585 facing[0] = 'f';
1586
1587 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1588 imx317->module_index, facing,
1589 IMX317_NAME, dev_name(sd->dev));
1590 ret = v4l2_async_register_subdev_sensor_common(sd);
1591 if (ret) {
1592 dev_err(dev, "v4l2 async register subdev failed\n");
1593 goto err_clean_entity;
1594 }
1595
1596 pm_runtime_set_active(dev);
1597 pm_runtime_enable(dev);
1598 pm_runtime_idle(dev);
1599
1600 return 0;
1601
1602 err_clean_entity:
1603 #if defined(CONFIG_MEDIA_CONTROLLER)
1604 media_entity_cleanup(&sd->entity);
1605 #endif
1606 err_power_off:
1607 __imx317_power_off(imx317);
1608 err_free_handler:
1609 v4l2_ctrl_handler_free(&imx317->ctrl_handler);
1610 err_destroy_mutex:
1611 mutex_destroy(&imx317->mutex);
1612
1613 return ret;
1614 }
1615
imx317_remove(struct i2c_client * client)1616 static int imx317_remove(struct i2c_client *client)
1617 {
1618 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1619 struct imx317 *imx317 = to_imx317(sd);
1620
1621 v4l2_async_unregister_subdev(sd);
1622 #if defined(CONFIG_MEDIA_CONTROLLER)
1623 media_entity_cleanup(&sd->entity);
1624 #endif
1625 v4l2_ctrl_handler_free(&imx317->ctrl_handler);
1626 mutex_destroy(&imx317->mutex);
1627
1628 pm_runtime_disable(&client->dev);
1629 if (!pm_runtime_status_suspended(&client->dev))
1630 __imx317_power_off(imx317);
1631 pm_runtime_set_suspended(&client->dev);
1632
1633 return 0;
1634 }
1635
1636 #if IS_ENABLED(CONFIG_OF)
1637 static const struct of_device_id imx317_of_match[] = {
1638 { .compatible = "sony,imx317" },
1639 {},
1640 };
1641 MODULE_DEVICE_TABLE(of, imx317_of_match);
1642 #endif
1643
1644 static const struct i2c_device_id imx317_match_id[] = {
1645 { "sony,imx317", 0 },
1646 { },
1647 };
1648
1649 static struct i2c_driver imx317_i2c_driver = {
1650 .driver = {
1651 .name = IMX317_NAME,
1652 .pm = &imx317_pm_ops,
1653 .of_match_table = of_match_ptr(imx317_of_match),
1654 },
1655 .probe = &imx317_probe,
1656 .remove = &imx317_remove,
1657 .id_table = imx317_match_id,
1658 };
1659
sensor_mod_init(void)1660 static int __init sensor_mod_init(void)
1661 {
1662 return i2c_add_driver(&imx317_i2c_driver);
1663 }
1664
sensor_mod_exit(void)1665 static void __exit sensor_mod_exit(void)
1666 {
1667 i2c_del_driver(&imx317_i2c_driver);
1668 }
1669
1670 device_initcall_sync(sensor_mod_init);
1671 module_exit(sensor_mod_exit);
1672
1673 MODULE_DESCRIPTION("OmniVision imx317 sensor driver");
1674 MODULE_LICENSE("GPL v2");
1675