1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx307 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 * v1.0x01.0x01 support lvds interface,include linear and hdr transmission via vipcap
7 * support mipi linear mode
8 * v1.0x01.0x02
9 * 1.fixed lvds output data offset, because lvds regards ob line as valid data output
10 * 2.support test pattern
11 * v1.0x01.0x03 update frame rate from 25fps to 30fps
12 * v1.0x01.0x04 update max exposure and formula
13 * shs1 = vts - (line + 1)
14 * V0.0X01.0X05 add quick stream on/off
15 * V0.0X01.0X06 support lvds 2lane
16 */
17
18 #include <linux/clk.h>
19 #include <linux/device.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/i2c.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/sysfs.h>
27 #include <linux/slab.h>
28 #include <linux/version.h>
29 #include <linux/rk-camera-module.h>
30 #include <linux/of_graph.h>
31 #include <media/media-entity.h>
32 #include <media/v4l2-async.h>
33 #include <media/v4l2-ctrls.h>
34 #include <media/v4l2-subdev.h>
35 #include <media/v4l2-fwnode.h>
36 #include <media/v4l2-mediabus.h>
37 #include <linux/pinctrl/consumer.h>
38 #include <linux/rk-preisp.h>
39
40 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
41 #ifndef V4L2_CID_DIGITAL_GAIN
42 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
43 #endif
44
45 #define IMX307_LINK_FREQ_111M 111370000
46 #define IMX307_LINK_FREQ_222M 222750000
47 #define IMX307_2LANES 2
48 #define IMX307_4LANES 4
49 #define IMX307_BITS_PER_SAMPLE 10
50
51 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
52 #define IMX307_PIXEL_RATE_NORMAL (IMX307_LINK_FREQ_111M * 2 / 10 * IMX307_4LANES)
53 #define IMX307_PIXEL_RATE_HDR (IMX307_LINK_FREQ_222M * 2 / 10 * IMX307_4LANES)
54
55 #define IMX307_XVCLK_FREQ 37125000
56
57 #define CHIP_ID 0xb2
58 #define IMX307_REG_CHIP_ID 0x301e
59
60 #define IMX307_REG_CTRL_MODE 0x3000
61 #define IMX307_MODE_SW_STANDBY 0x1
62 #define IMX307_MODE_STREAMING 0x0
63
64 #define IMX307_REG_SHS1_H 0x3022
65 #define IMX307_REG_SHS1_M 0x3021
66 #define IMX307_REG_SHS1_L 0x3020
67
68 #define IMX307_REG_SHS2_H 0x3026
69 #define IMX307_REG_SHS2_M 0x3025
70 #define IMX307_REG_SHS2_L 0x3024
71
72 #define IMX307_REG_RHS1_H 0x3032
73 #define IMX307_REG_RHS1_M 0x3031
74 #define IMX307_REG_RHS1_L 0x3030
75
76 #define IMX307_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 16) & 0x0F)
77 #define IMX307_FETCH_MID_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF)
78 #define IMX307_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF)
79
80 #define IMX307_EXPOSURE_MIN 2
81 #define IMX307_EXPOSURE_STEP 1
82 #define IMX307_VTS_MAX 0x7fff
83
84 #define IMX307_GAIN_SWITCH_REG 0x3009
85 #define IMX307_REG_LF_GAIN 0x3014
86 #define IMX307_REG_SF_GAIN 0x30f2
87 #define IMX307_GAIN_MIN 0x00
88 #define IMX307_GAIN_MAX 0xee
89 #define IMX307_GAIN_STEP 1
90 #define IMX307_GAIN_DEFAULT 0x00
91
92 #define IMX307_GROUP_HOLD_REG 0x3001
93 #define IMX307_GROUP_HOLD_START 0x01
94 #define IMX307_GROUP_HOLD_END 0x00
95
96 #define USED_TEST_PATTERN
97 #ifdef USED_TEST_PATTERN
98 #define IMX307_REG_TEST_PATTERN 0x308c
99 #define IMX307_TEST_PATTERN_ENABLE BIT(0)
100 #endif
101
102 #define IMX307_REG_VTS_H 0x301a
103 #define IMX307_REG_VTS_M 0x3019
104 #define IMX307_REG_VTS_L 0x3018
105 #define IMX307_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 16) & 0x03)
106 #define IMX307_FETCH_MID_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF)
107 #define IMX307_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF)
108
109 #define REG_NULL 0xFFFF
110 #define REG_DELAY 0xFFFE
111
112 #define IMX307_REG_VALUE_08BIT 1
113 #define IMX307_REG_VALUE_16BIT 2
114 #define IMX307_REG_VALUE_24BIT 3
115
116 static bool g_isHCG;
117
118 #define IMX307_NAME "imx307"
119
120 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
121 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
122
123 #define IMX307_FLIP_REG 0x3007
124 #define MIRROR_BIT_MASK BIT(1)
125 #define FLIP_BIT_MASK BIT(0)
126
127 #define RHS1 0X0B
128
129 static const char * const imx307_supply_names[] = {
130 "avdd", /* Analog power */
131 "dovdd", /* Digital I/O power */
132 "dvdd", /* Digital core power */
133 };
134
135 #define IMX307_NUM_SUPPLIES ARRAY_SIZE(imx307_supply_names)
136
137 struct regval {
138 u16 addr;
139 u8 val;
140 };
141
142 struct imx307_mode {
143 u32 bus_fmt;
144 u32 width;
145 u32 height;
146 struct v4l2_fract max_fps;
147 u32 hts_def;
148 u32 vts_def;
149 u32 exp_def;
150 const struct regval *reg_list;
151 u32 hdr_mode;
152 struct rkmodule_lvds_cfg lvds_cfg;
153 u32 freq_idx;
154 u32 lanes;
155 u32 bpp;
156 };
157
158 struct imx307 {
159 struct i2c_client *client;
160 struct clk *xvclk;
161 struct gpio_desc *reset_gpio;
162 struct gpio_desc *pwdn_gpio;
163 struct regulator_bulk_data supplies[IMX307_NUM_SUPPLIES];
164
165 struct pinctrl *pinctrl;
166 struct pinctrl_state *pins_default;
167 struct pinctrl_state *pins_sleep;
168
169 struct v4l2_subdev subdev;
170 struct media_pad pad;
171 struct v4l2_ctrl_handler ctrl_handler;
172 struct v4l2_ctrl *exposure;
173 struct v4l2_ctrl *anal_gain;
174 struct v4l2_ctrl *digi_gain;
175 struct v4l2_ctrl *hblank;
176 struct v4l2_ctrl *vblank;
177 struct v4l2_ctrl *pixel_rate;
178 struct v4l2_ctrl *link_freq;
179 struct v4l2_ctrl *h_flip;
180 struct v4l2_ctrl *v_flip;
181 #ifdef USED_TEST_PATTERN
182 struct v4l2_ctrl *test_pattern;
183 #endif
184 struct mutex mutex;
185 bool streaming;
186 bool power_on;
187 const struct imx307_mode *support_modes;
188 u32 support_modes_num;
189 const struct imx307_mode *cur_mode;
190 u32 module_index;
191 const char *module_facing;
192 const char *module_name;
193 const char *len_name;
194 u32 cur_vts;
195 bool has_init_exp;
196 struct preisp_hdrae_exp_s init_hdrae_exp;
197 struct v4l2_fwnode_endpoint bus_cfg;
198 u8 flip;
199 };
200
201 #define to_imx307(sd) container_of(sd, struct imx307, subdev)
202
203 /*
204 * Xclk 37.125Mhz
205 */
206 static const struct regval imx307_global_regs[] = {
207 {REG_NULL, 0x00},
208 };
209
210 /*
211 * Xclk 37.125Mhz
212 * max_framerate 30fps
213 * lvds_datarate per lane 111Mbps 2 lane
214 */
215 static const struct regval imx307_linear_1920x1080_30fps_lvds_2lane_regs[] = {
216 {0x3003, 0x01},
217 {REG_DELAY, 0x10},
218 {0x3000, 0x01},
219 {0x3001, 0x00},
220 {0x3002, 0x01},
221 {0x3005, 0x00},
222 {0x3007, 0x00},
223 {0x3009, 0x02},
224 {0x300a, 0x3c},
225 {0x3010, 0x21},
226 {0x3011, 0x0a},
227 {0x3018, 0x65},
228 {0x3019, 0x04},
229 {0x301c, 0x30},
230 {0x301d, 0x11},
231 {0x3046, 0xD0},
232 {0x304b, 0x0a},
233 {0x305c, 0x18},
234 {0x305d, 0x00},
235 {0x305e, 0x20},
236 {0x305f, 0x01},
237 {0x309e, 0x4a},
238 {0x309f, 0x4a},
239 {0x311c, 0x0e},
240 {0x3128, 0x04},
241 {0x3129, 0x1d},
242 {0x313b, 0x41},
243 {0x315e, 0x1a},
244 {0x3164, 0x1a},
245 {0x317c, 0x12},
246 {0x31ec, 0x37},
247 {0x3480, 0x49},
248 {0x3002, 0x00},
249 {REG_NULL, 0x00},
250 };
251
252 /*
253 * Xclk 37.125Mhz
254 * max_framerate 15fps
255 * lvds_datarate per lane 222Mbps 2 lane
256 */
257 static const struct regval imx307_hdr2_1920x1080_lvds_2lane_regs[] = {
258 {0x3003, 0x01},
259 {REG_DELAY, 0x10},
260 {0x3000, 0x01},
261 {0x3001, 0x00},
262 {0x3002, 0x01},
263 {0x3005, 0x00},
264 {0x3007, 0x00},
265 {0x3009, 0x02},
266 {0x300a, 0x3c},
267 {0x300c, 0x11},
268 {0x3010, 0x21},
269 {0x3011, 0x0a},
270 {0x3014, 0x0f},
271 {0x3018, 0x65},/* VMAX L */
272 {0x3019, 0x04},/* VMAX M */
273 {0x301c, 0x30},/* HMAX L */
274 {0x301d, 0x11},/* HMAX H */
275 {0x3020, 0x02},//hdr+ shs1 l short
276 {0x3021, 0x00},//hdr+ shs1 m
277 {0x3024, 0x49},//hdr+ shs2 l
278 {0x3025, 0x04},//hdr+ shs2 m
279 {0x3030, RHS1},//hdr+ IMX327_RHS1
280 {0x3031, 0x00},//hdr+IMX327_RHS1
281 {0x3045, 0x03},//hdr+
282 {0x3046, 0xd0},
283 {0x305c, 0x18},
284 {0x305d, 0x00},
285 {0x305e, 0x20},
286 {0x305f, 0x01},
287 {0x309e, 0x4a},
288 {0x309f, 0x4a},
289 {0x30d2, 0x19},
290 {0x30d7, 0x03},
291 {0x3106, 0x10},
292 {0x311c, 0x0e},
293 {0x3128, 0x04},
294 {0x3129, 0x1d},
295 {0x313b, 0x41},
296 {0x315e, 0x1a},
297 {0x3164, 0x1a},
298 {0x317c, 0x12},
299 {0x31ec, 0x37},
300 {0x3480, 0x49},
301 {0x31a0, 0xb4},
302 {0x31a1, 0x02},
303 {0x303c, 0x04},//Y offset
304 {0x303d, 0x00},
305 {0x303e, 0x41},
306 {0x303f, 0x04},//height
307 {0x303A, 0x08},//hdr+
308 {0x3010, 0x61},//hdr+ gain 1frame FPGC
309 {0x3014, 0x00},//hdr+ gain 1frame long
310 {0x30F0, 0x64},//hdr+ gain 2frame FPGC
311 {0x30f2, 0x00},//hdr+ gain 2frame short
312 {0x3002, 0x00},
313 {0x304B, 0x0a},
314 {REG_NULL, 0x00},
315 };
316
317 /*
318 * Xclk 37.125Mhz
319 * max_framerate 30fps
320 * lvds_datarate per lane 222.75Mbps 4 lane
321 */
322 static const struct regval imx307_linear_1920x1080_30fps_lvds_regs[] = {
323 {0x3003, 0x01},
324 {REG_DELAY, 0x10},
325 {0x3000, 0x01},
326 {0x3001, 0x00},
327 {0x3002, 0x01},
328 {0x3005, 0x00},
329 {0x3007, 0x00},
330 {0x3009, 0x02},
331 {0x300a, 0x3c},
332 {0x3010, 0x21},
333 {0x3011, 0x0a},
334 {0x3018, 0x65},
335 {0x3019, 0x04},
336 {0x301c, 0x30},
337 {0x301d, 0x11},
338 {0x3046, 0xe0},
339 {0x304b, 0x0a},
340 {0x305c, 0x18},
341 {0x305d, 0x00},
342 {0x305e, 0x20},
343 {0x305f, 0x01},
344 {0x309e, 0x4a},
345 {0x309f, 0x4a},
346 {0x311c, 0x0e},
347 {0x3128, 0x04},
348 {0x3129, 0x1d},
349 {0x313b, 0x41},
350 {0x315e, 0x1a},
351 {0x3164, 0x1a},
352 {0x317c, 0x12},
353 {0x31ec, 0x37},
354 {0x3480, 0x49},
355 {0x3002, 0x00},
356 {REG_NULL, 0x00},
357 };
358
359 /*
360 * Xclk 37.125Mhz
361 * max_framerate 60fps
362 * lvds_datarate per lane 445.5Mbps 4 lane
363 */
364 static const struct regval imx307_linear_1920x1080_60fps_lvds_regs[] = {
365 {0x3003, 0x01},
366 {REG_DELAY, 0x10},
367 {0x3000, 0x01},
368 {0x3001, 0x00},
369 {0x3002, 0x01},
370 {0x3005, 0x00},
371 {0x3007, 0x00},
372 {0x3009, 0x01},
373 {0x300a, 0x3c},
374 {0x3010, 0x21},
375 {0x3011, 0x0a},
376 {0x3018, 0x65},
377 {0x3019, 0x04},
378 {0x301c, 0x98},
379 {0x301d, 0x08},
380 {0x3046, 0xe0},
381 {0x304b, 0x0a},
382 {0x305c, 0x18},
383 {0x305d, 0x00},
384 {0x305e, 0x20},
385 {0x305f, 0x01},
386 {0x309e, 0x4a},
387 {0x309f, 0x4a},
388 {0x311c, 0x0e},
389 {0x3128, 0x04},
390 {0x3129, 0x1d},
391 {0x313b, 0x41},
392 {0x315e, 0x1a},
393 {0x3164, 0x1a},
394 {0x317c, 0x12},
395 {0x31ec, 0x37},
396 {0x3480, 0x49},
397 {0x3002, 0x00},
398 {REG_NULL, 0x00},
399 };
400
401 /*
402 * Xclk 37.125Mhz
403 * max_framerate 30fps
404 * lvds_datarate per lane 445.5Mbps 4 lane
405 */
406 static const struct regval imx307_hdr2_1920x1080_lvds_regs[] = {
407 {0x3003, 0x01},
408 {REG_DELAY, 0x10},
409 {0x3000, 0x01},
410 {0x3001, 0x00},
411 {0x3002, 0x01},
412 {0x3005, 0x00},
413 {0x3007, 0x40},
414 {0x3009, 0x01},
415 {0x300a, 0x3c},
416 {0x300c, 0x11},
417 {0x3011, 0x02},
418 {0x3018, 0xc4},/* VMAX L */
419 {0x3019, 0x04},/* VMAX M */
420 {0x301c, 0xec},/* HMAX L */
421 {0x301d, 0x07},/* HMAX H */
422 {0x3020, 0x02},//hdr+ shs1 l short
423 {0x3021, 0x00},//hdr+ shs1 m
424 {0x3024, 0xc9},//hdr+ shs2 l
425 {0x3025, 0x07},//hdr+ shs2 m
426 {0x3030, 0xe1},//hdr+ IMX327_RHS1
427 {0x3031, 0x00},//hdr+IMX327_RHS1
428 {0x3045, 0x03},//hdr+
429 {0x3046, 0xe0},
430 {0x304b, 0x0a},
431 {0x305c, 0x18},
432 {0x305d, 0x03},
433 {0x305e, 0x20},
434 {0x305f, 0x01},
435 {0x309e, 0x4a},
436 {0x309f, 0x4a},
437 {0x30d2, 0x19},
438 {0x30d7, 0x03},
439 {0x3106, 0x11},
440 {0x3129, 0x1d},
441 {0x313b, 0x61},
442 {0x315e, 0x1a},
443 {0x3164, 0x1a},
444 {0x317c, 0x12},
445 {0x31ec, 0x37},
446 {0x3414, 0x00},
447 {0x3415, 0x00},
448 {0x3480, 0x49},
449 {0x31a0, 0xb4},
450 {0x31a1, 0x02},
451 {0x303c, 0x04},//Y offset
452 {0x303d, 0x00},
453 {0x303e, 0x41},
454 {0x303f, 0x04},//height
455 {0x303A, 0x08},//hdr+
456 {0x3010, 0x61},//hdr+ gain 1frame FPGC
457 {0x3014, 0x00},//hdr+ gain 1frame long
458 {0x30F0, 0x64},//hdr+ gain 2frame FPGC
459 {0x30f2, 0x00},//hdr+ gain 2frame short
460 {0x3002, 0x00},
461 {REG_NULL, 0x00},
462 };
463
464 /*
465 * Xclk 37.125Mhz
466 * max_framerate 30fps
467 * mipi_datarate per lane 222.75Mbps 4 lane
468 */
469 static const struct regval imx307_linear_1920x1080_mipi_regs[] = {
470 {0x3003, 0x01},
471 {REG_DELAY, 0x10},
472 {0x3000, 0x01},
473 {0x3001, 0x00},
474 {0x3002, 0x01},
475 {0x3005, 0x00},
476 {0x3007, 0x00},
477 {0x3009, 0x02},
478 {0x300A, 0x3c},
479 {0x3010, 0x21},
480 {0x3011, 0x0a},
481 {0x3018, 0x65},
482 {0x3019, 0x04},
483 {0x301C, 0x30},
484 {0x301D, 0x11},
485 {0x3046, 0x00},
486 {0x304B, 0x0A},
487 {0x305C, 0x18},
488 {0x305D, 0x03},
489 {0x305E, 0x20},
490 {0x305F, 0x01},
491 {0x309E, 0x4A},
492 {0x309F, 0x4A},
493 {0x311c, 0x0e},
494 {0x3128, 0x04},
495 {0x3129, 0x1d},
496 {0x313B, 0x41},
497 {0x315E, 0x1A},
498 {0x3164, 0x1A},
499 {0x317C, 0x12},
500 {0x31EC, 0x37},
501 {0x3405, 0x20},
502 {0x3407, 0x03},
503 {0x3414, 0x0A},
504 {0x3418, 0x49},
505 {0x3419, 0x04},
506 {0x3441, 0x0a},
507 {0x3442, 0x0a},
508 {0x3443, 0x03},
509 {0x3444, 0x20},
510 {0x3445, 0x25},
511 {0x3446, 0x47},
512 {0x3447, 0x00},
513 {0x3448, 0x1f},
514 {0x3449, 0x00},
515 {0x344A, 0x17},
516 {0x344B, 0x00},
517 {0x344C, 0x0F},
518 {0x344D, 0x00},
519 {0x344E, 0x17},
520 {0x344F, 0x00},
521 {0x3450, 0x47},
522 {0x3451, 0x00},
523 {0x3452, 0x0F},
524 {0x3453, 0x00},
525 {0x3454, 0x0f},
526 {0x3455, 0x00},
527 {0x3472, 0x9c},
528 {0x3473, 0x07},
529 {0x3480, 0x49},
530 {0x3002, 0x00},
531 {REG_NULL, 0x00},
532 };
533
534 /*
535 * Xclk 37.125Mhz
536 * max_framerate 30fps
537 * mipi_datarate per lane 445.5Mbps 4 lane
538 */
539 static const struct regval imx307_hdr2_1920x1080_mipi_regs[] = {
540 {0x3003, 0x01},
541 {REG_DELAY, 0x10},
542 {0x3000, 0x01},
543 {0x3001, 0x00},
544 {0x3002, 0x01},
545 {0x3005, 0x00},
546 {0x3007, 0x40},
547 {0x3009, 0x01},
548 {0x300a, 0x3c},
549 {0x300c, 0x11}, //hdr+
550 {0x3011, 0x02},
551 {0x3018, 0xc4},/* VMAX L */
552 {0x3019, 0x04},/* VMAX M */
553 {0x301a, 0x00},
554 {0x301c, 0xEc},/* HMAX L */
555 {0x301d, 0x07},/* HMAX H */
556 {0x3045, 0x05},//hdr+
557 {0x3046, 0x00},
558 {0x304b, 0x0a},
559 {0x305c, 0x18},
560 {0x305d, 0x03},
561 {0x305e, 0x20},
562 {0x305f, 0x01},
563 {0x309e, 0x4a},
564 {0x309f, 0x4a},
565 {0x30d2, 0x19},
566 {0x30d7, 0x03},
567 {0x3106, 0x11},//hdr+
568 {0x3129, 0x1d},
569 {0x313b, 0x61},
570 {0x315e, 0x1a},
571 {0x3164, 0x1a},
572 {0x317c, 0x12},
573 {0x31ec, 0x37},
574 {0x3405, 0x10},
575 {0x3407, 0x03},
576 {0x3414, 0x00},
577 {0x3415, 0x00},//hdr+
578 {0x3418, 0x72},
579 {0x3419, 0x09},
580 {0x3441, 0x0a},
581 {0x3442, 0x0a},
582 {0x3443, 0x03},
583 {0x3444, 0x20},
584 {0x3445, 0x25},
585 {0x3446, 0x57},
586 {0x3447, 0x00},
587 {0x3448, 0x37},//37?
588 {0x3449, 0x00},
589 {0x344a, 0x1f},
590 {0x344b, 0x00},
591 {0x344c, 0x1f},
592 {0x344d, 0x00},
593 {0x344e, 0x1f},
594 {0x344f, 0x00},
595 {0x3450, 0x77},
596 {0x3451, 0x00},
597 {0x3452, 0x1f},
598 {0x3453, 0x00},
599 {0x3454, 0x17},
600 {0x3455, 0x00},
601 {0x3472, 0xa0},
602 {0x3473, 0x07},
603 {0x347b, 0x23},
604 {0x3480, 0x49},
605 {0x31a0, 0xb4},//hdr+
606 {0x31a1, 0x02},//hdr+
607 {0x3020, 0x02},//hdr+ shs1 l short
608 {0x3021, 0x00},//hdr+ shs1 m
609 {0x3022, 0x00},//hdr+ shs1 h
610 {0x3030, 0xe1},//hdr+ IMX307_RHS1
611 {0x3031, 0x00},//hdr+IMX307_RHS1
612 {0x3032, 0x00},//hdr+
613 {0x31A0, 0xe8},//hdr+ HBLANK1
614 {0x31A1, 0x01},//hdr+
615 {0x303c, 0x04},
616 {0x303d, 0x00},
617 {0x303e, 0x41},
618 {0x303f, 0x04},
619 {0x303A, 0x08},//hdr+
620 {0x3024, 0xc9},//hdr+ shs2 l
621 {0x3025, 0x06},//hdr+ shs2 m
622 {0x3026, 0x00},//hdr+ shs2 h
623 {0x3010, 0x61},//hdr+ gain 1frame FPGC
624 {0x3014, 0x00},//hdr+ gain 1frame long
625 {0x30F0, 0x64},//hdr+ gain 2frame FPGC
626 {0x30f2, 0x00},//hdr+ gain 2frame short
627 {0x3002, 0x00},
628 {REG_NULL, 0x00},
629 };
630
631 /*
632 * The width and height must be configured to be
633 * the same as the current output resolution of the sensor.
634 * The input width of the isp needs to be 16 aligned.
635 * The input height of the isp needs to be 8 aligned.
636 * If the width or height does not meet the alignment rules,
637 * you can configure the cropping parameters with the following function to
638 * crop out the appropriate resolution.
639 * struct v4l2_subdev_pad_ops {
640 * .get_selection
641 * }
642 */
643
644 static const struct imx307_mode lvds_2lane_supported_modes[] = {
645 {
646 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
647 .width = 1948,
648 .height = 1110,
649 .max_fps = {
650 .numerator = 10000,
651 .denominator = 300000,
652 },
653 .exp_def = 0x03fe,
654 .hts_def = 0x1130,
655 .vts_def = 0x0465,
656 .reg_list = imx307_linear_1920x1080_30fps_lvds_2lane_regs,
657 .hdr_mode = NO_HDR,
658 .lanes = 2,
659 .freq_idx = 0,
660 .bpp = 10,
661 .lvds_cfg = {
662 .mode = LS_FIRST,
663 .frm_sync_code[LVDS_CODE_GRP_LINEAR] = {
664 .odd_sync_code = {
665 .act = {
666 .sav = 0x200,
667 .eav = 0x274,
668 },
669 .blk = {
670 .sav = 0x2ac,
671 .eav = 0x2d8,
672 },
673 },
674 },
675 },
676 },
677 {
678 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
679 .width = 1948,
680 .height = 1098,
681 .max_fps = {
682 .numerator = 10000,
683 .denominator = 150000,
684 },
685 .exp_def = 0x0473,
686 .hts_def = 0x07ec,
687 .vts_def = 0x04c4 * 2,
688 .reg_list = imx307_hdr2_1920x1080_lvds_2lane_regs,
689 .hdr_mode = HDR_X2,
690 .lanes = 2,
691 .freq_idx = 1,
692 .bpp = 10,
693 .lvds_cfg = {
694 .mode = SONY_DOL_HDR_1,
695 .frm_sync_code[LVDS_CODE_GRP_LONG] = {
696 .odd_sync_code = {
697 .act = {
698 .sav = 0x001,
699 .eav = 0x075,
700 },
701 .blk = {
702 .sav = 0x0ac,
703 .eav = 0x0d8,
704 },
705 },
706 .even_sync_code = {
707 .act = {
708 .sav = 0x101,
709 .eav = 0x175,
710 },
711 .blk = {
712 .sav = 0x1ac,
713 .eav = 0x1d8,
714 },
715 },
716 },
717 .frm_sync_code[LVDS_CODE_GRP_SHORT] = {
718 .odd_sync_code = {
719 .act = {
720 .sav = 0x002,
721 .eav = 0x076,
722 },
723 .blk = {
724 .sav = 0x0ac,
725 .eav = 0x0d8,
726 },
727 },
728 .even_sync_code = {
729 .act = {
730 .sav = 0x102,
731 .eav = 0x176,
732 },
733 .blk = {
734 .sav = 0x1ac,
735 .eav = 0x1d8,
736 },
737 },
738 },
739 },
740 },
741 };
742
743 static const struct imx307_mode lvds_supported_modes[] = {
744 {
745 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
746 .width = 1948,
747 .height = 1110,
748 .max_fps = {
749 .numerator = 10000,
750 .denominator = 600000,
751 },
752 .exp_def = 0x03fe,
753 .hts_def = 0x0889,
754 .vts_def = 0x0465,
755 .reg_list = imx307_linear_1920x1080_60fps_lvds_regs,
756 .hdr_mode = NO_HDR,
757 .lanes = 4,
758 .freq_idx = 0,
759 .bpp = 10,
760 .lvds_cfg = {
761 .mode = LS_FIRST,
762 .frm_sync_code[LVDS_CODE_GRP_LINEAR] = {
763 .odd_sync_code = {
764 .act = {
765 .sav = 0x200,
766 .eav = 0x274,
767 },
768 .blk = {
769 .sav = 0x2ac,
770 .eav = 0x2d8,
771 },
772 },
773 },
774 },
775 }, {
776 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
777 .width = 1948,
778 .height = 1110,
779 .max_fps = {
780 .numerator = 10000,
781 .denominator = 300000,
782 },
783 .exp_def = 0x03fe,
784 .hts_def = 0x1130,
785 .vts_def = 0x0465,
786 .reg_list = imx307_linear_1920x1080_30fps_lvds_regs,
787 .hdr_mode = NO_HDR,
788 .lanes = 4,
789 .freq_idx = 0,
790 .bpp = 10,
791 .lvds_cfg = {
792 .mode = LS_FIRST,
793 .frm_sync_code[LVDS_CODE_GRP_LINEAR] = {
794 .odd_sync_code = {
795 .act = {
796 .sav = 0x200,
797 .eav = 0x274,
798 },
799 .blk = {
800 .sav = 0x2ac,
801 .eav = 0x2d8,
802 },
803 },
804 },
805 },
806 },
807 {
808 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
809 .width = 1948,
810 .height = 1098,
811 .max_fps = {
812 .numerator = 10000,
813 .denominator = 300000,
814 },
815 .exp_def = 0x0473,
816 .hts_def = 0x07ec,
817 .vts_def = 0x04c4 * 2,
818 .reg_list = imx307_hdr2_1920x1080_lvds_regs,
819 .hdr_mode = HDR_X2,
820 .lanes = 4,
821 .freq_idx = 1,
822 .bpp = 10,
823 .lvds_cfg = {
824 .mode = SONY_DOL_HDR_1,
825 .frm_sync_code[LVDS_CODE_GRP_LONG] = {
826 .odd_sync_code = {
827 .act = {
828 .sav = 0x001,
829 .eav = 0x075,
830 },
831 .blk = {
832 .sav = 0x0ac,
833 .eav = 0x0d8,
834 },
835 },
836 .even_sync_code = {
837 .act = {
838 .sav = 0x101,
839 .eav = 0x175,
840 },
841 .blk = {
842 .sav = 0x1ac,
843 .eav = 0x1d8,
844 },
845 },
846 },
847 .frm_sync_code[LVDS_CODE_GRP_SHORT] = {
848 .odd_sync_code = {
849 .act = {
850 .sav = 0x002,
851 .eav = 0x076,
852 },
853 .blk = {
854 .sav = 0x0ac,
855 .eav = 0x0d8,
856 },
857 },
858 .even_sync_code = {
859 .act = {
860 .sav = 0x102,
861 .eav = 0x176,
862 },
863 .blk = {
864 .sav = 0x1ac,
865 .eav = 0x1d8,
866 },
867 },
868 },
869 },
870 },
871 };
872
873 static const struct imx307_mode mipi_supported_modes[] = {
874 {
875 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
876 .width = 1948,
877 .height = 1097,
878 .max_fps = {
879 .numerator = 10000,
880 .denominator = 300000,
881 },
882 .exp_def = 0x03fe,
883 .hts_def = 0x1130,
884 .vts_def = 0x0465,
885 .reg_list = imx307_linear_1920x1080_mipi_regs,
886 .hdr_mode = NO_HDR,
887 .lanes = 4,
888 .freq_idx = 0,
889 .bpp = 10,
890 }, {
891 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
892 .width = 1952,
893 .height = 1089,
894 .max_fps = {
895 .numerator = 10000,
896 .denominator = 300000,
897 },
898 .exp_def = 0x0473,
899 .hts_def = 0x07ec,
900 .vts_def = 0x04c4 * 2,
901 .reg_list = imx307_hdr2_1920x1080_mipi_regs,
902 .hdr_mode = HDR_X2,
903 .lanes = 4,
904 .freq_idx = 1,
905 .bpp = 10,
906 },
907 };
908
909 static const s64 link_freq_menu_items[] = {
910 IMX307_LINK_FREQ_111M,
911 IMX307_LINK_FREQ_222M
912 };
913
914 #ifdef USED_TEST_PATTERN
915 static const char * const imx307_test_pattern_menu[] = {
916 "Disabled",
917 "Bar Type 1",
918 "Bar Type 2",
919 "Bar Type 3",
920 "Bar Type 4",
921 "Bar Type 5",
922 "Bar Type 6",
923 "Bar Type 7",
924 "Bar Type 8",
925 "Bar Type 9",
926 "Bar Type 10",
927 "Bar Type 11",
928 "Bar Type 12",
929 "Bar Type 13",
930 "Bar Type 14",
931 "Bar Type 15"
932 };
933 #endif
934
935 /* Write registers up to 4 at a time */
imx307_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)936 static int imx307_write_reg(struct i2c_client *client, u16 reg,
937 u32 len, u32 val)
938 {
939 u32 buf_i, val_i;
940 u8 buf[6];
941 u8 *val_p;
942 __be32 val_be;
943
944 if (len > 4)
945 return -EINVAL;
946
947 buf[0] = reg >> 8;
948 buf[1] = reg & 0xff;
949
950 val_be = cpu_to_be32(val);
951 val_p = (u8 *)&val_be;
952 buf_i = 2;
953 val_i = 4 - len;
954
955 while (val_i < 4)
956 buf[buf_i++] = val_p[val_i++];
957
958 if (i2c_master_send(client, buf, len + 2) != len + 2)
959 return -EIO;
960
961 return 0;
962 }
963
imx307_write_array(struct i2c_client * client,const struct regval * regs)964 static int imx307_write_array(struct i2c_client *client,
965 const struct regval *regs)
966 {
967 u32 i;
968 int ret = 0;
969
970 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
971 if (unlikely(regs[i].addr == REG_DELAY))
972 usleep_range(regs[i].val * 1000, regs[i].val * 2000);
973 else
974 ret = imx307_write_reg(client, regs[i].addr,
975 IMX307_REG_VALUE_08BIT,
976 regs[i].val);
977
978 return ret;
979 }
980
981 /* Read registers up to 4 at a time */
imx307_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)982 static int imx307_read_reg(struct i2c_client *client, u16 reg,
983 unsigned int len, u32 *val)
984 {
985 struct i2c_msg msgs[2];
986 u8 *data_be_p;
987 __be32 data_be = 0;
988 __be16 reg_addr_be = cpu_to_be16(reg);
989 int ret;
990
991 if (len > 4 || !len)
992 return -EINVAL;
993
994 data_be_p = (u8 *)&data_be;
995 /* Write register address */
996 msgs[0].addr = client->addr;
997 msgs[0].flags = 0;
998 msgs[0].len = 2;
999 msgs[0].buf = (u8 *)®_addr_be;
1000
1001 /* Read data from register */
1002 msgs[1].addr = client->addr;
1003 msgs[1].flags = I2C_M_RD;
1004 msgs[1].len = len;
1005 msgs[1].buf = &data_be_p[4 - len];
1006
1007 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1008 if (ret != ARRAY_SIZE(msgs))
1009 return -EIO;
1010
1011 *val = be32_to_cpu(data_be);
1012 return 0;
1013 }
1014
imx307_get_reso_dist(const struct imx307_mode * mode,struct v4l2_mbus_framefmt * framefmt)1015 static int imx307_get_reso_dist(const struct imx307_mode *mode,
1016 struct v4l2_mbus_framefmt *framefmt)
1017 {
1018 return abs(mode->width - framefmt->width) +
1019 abs(mode->height - framefmt->height);
1020 }
1021
1022 static const struct imx307_mode *
imx307_find_best_fit(struct imx307 * imx307,struct v4l2_subdev_format * fmt)1023 imx307_find_best_fit(struct imx307 *imx307, struct v4l2_subdev_format *fmt)
1024 {
1025 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1026 int dist;
1027 int cur_best_fit = 0;
1028 int cur_best_fit_dist = -1;
1029 unsigned int i;
1030
1031 for (i = 0; i < imx307->support_modes_num; i++) {
1032 dist = imx307_get_reso_dist(&imx307->support_modes[i], framefmt);
1033 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1034 cur_best_fit_dist = dist;
1035 cur_best_fit = i;
1036 }
1037 }
1038 return &imx307->support_modes[cur_best_fit];
1039 }
1040
imx307_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1041 static int imx307_set_fmt(struct v4l2_subdev *sd,
1042 struct v4l2_subdev_pad_config *cfg,
1043 struct v4l2_subdev_format *fmt)
1044 {
1045 struct imx307 *imx307 = to_imx307(sd);
1046 const struct imx307_mode *mode;
1047 s64 h_blank, vblank_def;
1048 s32 dst_link_freq = 0;
1049 s64 dst_pixel_rate = 0;
1050
1051 mutex_lock(&imx307->mutex);
1052
1053 mode = imx307_find_best_fit(imx307, fmt);
1054 fmt->format.code = mode->bus_fmt;
1055 fmt->format.width = mode->width;
1056 fmt->format.height = mode->height;
1057 fmt->format.field = V4L2_FIELD_NONE;
1058 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1059 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1060 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1061 #else
1062 mutex_unlock(&imx307->mutex);
1063 return -ENOTTY;
1064 #endif
1065 } else {
1066 imx307->cur_mode = mode;
1067 h_blank = mode->hts_def - mode->width;
1068 __v4l2_ctrl_modify_range(imx307->hblank, h_blank,
1069 h_blank, 1, h_blank);
1070 vblank_def = mode->vts_def - mode->height;
1071 __v4l2_ctrl_modify_range(imx307->vblank, vblank_def,
1072 IMX307_VTS_MAX - mode->height,
1073 1, vblank_def);
1074 dst_link_freq = mode->freq_idx;
1075 dst_pixel_rate = (u32)link_freq_menu_items[mode->freq_idx] / mode->bpp * 2 * mode->lanes;
1076 __v4l2_ctrl_s_ctrl_int64(imx307->pixel_rate,
1077 dst_pixel_rate);
1078 __v4l2_ctrl_s_ctrl(imx307->link_freq,
1079 dst_link_freq);
1080 imx307->cur_vts = mode->vts_def;
1081 }
1082
1083 mutex_unlock(&imx307->mutex);
1084
1085 return 0;
1086 }
1087
imx307_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1088 static int imx307_get_fmt(struct v4l2_subdev *sd,
1089 struct v4l2_subdev_pad_config *cfg,
1090 struct v4l2_subdev_format *fmt)
1091 {
1092 struct imx307 *imx307 = to_imx307(sd);
1093 const struct imx307_mode *mode = imx307->cur_mode;
1094
1095 mutex_lock(&imx307->mutex);
1096 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1097 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1098 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1099 #else
1100 mutex_unlock(&imx307->mutex);
1101 return -ENOTTY;
1102 #endif
1103 } else {
1104 fmt->format.width = mode->width;
1105 fmt->format.height = mode->height;
1106 fmt->format.code = mode->bus_fmt;
1107 fmt->format.field = V4L2_FIELD_NONE;
1108 }
1109 mutex_unlock(&imx307->mutex);
1110 return 0;
1111 }
1112
imx307_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1113 static int imx307_enum_mbus_code(struct v4l2_subdev *sd,
1114 struct v4l2_subdev_pad_config *cfg,
1115 struct v4l2_subdev_mbus_code_enum *code)
1116 {
1117 struct imx307 *imx307 = to_imx307(sd);
1118 const struct imx307_mode *mode = imx307->cur_mode;
1119
1120 if (code->index != 0)
1121 return -EINVAL;
1122 code->code = mode->bus_fmt;
1123
1124 return 0;
1125 }
1126
imx307_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1127 static int imx307_enum_frame_sizes(struct v4l2_subdev *sd,
1128 struct v4l2_subdev_pad_config *cfg,
1129 struct v4l2_subdev_frame_size_enum *fse)
1130 {
1131 struct imx307 *imx307 = to_imx307(sd);
1132
1133 if (fse->index >= imx307->support_modes_num)
1134 return -EINVAL;
1135
1136 if (fse->code != imx307->support_modes[fse->index].bus_fmt)
1137 return -EINVAL;
1138
1139 fse->min_width = imx307->support_modes[fse->index].width;
1140 fse->max_width = imx307->support_modes[fse->index].width;
1141 fse->max_height = imx307->support_modes[fse->index].height;
1142 fse->min_height = imx307->support_modes[fse->index].height;
1143
1144 return 0;
1145 }
1146
1147 #ifdef USED_TEST_PATTERN
imx307_enable_test_pattern(struct imx307 * imx307,u32 pattern)1148 static int imx307_enable_test_pattern(struct imx307 *imx307, u32 pattern)
1149 {
1150 u32 val = 0;
1151
1152 imx307_read_reg(imx307->client,
1153 IMX307_REG_TEST_PATTERN,
1154 IMX307_REG_VALUE_08BIT,
1155 &val);
1156 if (pattern) {
1157 val = ((pattern - 1) << 4) | IMX307_TEST_PATTERN_ENABLE;
1158 imx307_write_reg(imx307->client,
1159 0x300a,
1160 IMX307_REG_VALUE_08BIT,
1161 0x00);
1162 imx307_write_reg(imx307->client,
1163 0x300e,
1164 IMX307_REG_VALUE_08BIT,
1165 0x00);
1166 } else {
1167 val &= ~IMX307_TEST_PATTERN_ENABLE;
1168 imx307_write_reg(imx307->client,
1169 0x300a,
1170 IMX307_REG_VALUE_08BIT,
1171 0x3c);
1172 imx307_write_reg(imx307->client,
1173 0x300e,
1174 IMX307_REG_VALUE_08BIT,
1175 0x01);
1176 }
1177 return imx307_write_reg(imx307->client,
1178 IMX307_REG_TEST_PATTERN,
1179 IMX307_REG_VALUE_08BIT,
1180 val);
1181 }
1182 #endif
1183
imx307_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1184 static int imx307_g_frame_interval(struct v4l2_subdev *sd,
1185 struct v4l2_subdev_frame_interval *fi)
1186 {
1187 struct imx307 *imx307 = to_imx307(sd);
1188 const struct imx307_mode *mode = imx307->cur_mode;
1189
1190 fi->interval = mode->max_fps;
1191
1192 return 0;
1193 }
1194
imx307_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1195 static int imx307_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1196 struct v4l2_mbus_config *config)
1197 {
1198 struct imx307 *imx307 = to_imx307(sd);
1199 u32 val = 0;
1200
1201 val = 1 << (imx307->cur_mode->lanes - 1) |
1202 V4L2_MBUS_CSI2_CHANNEL_0 |
1203 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1204 config->type = imx307->bus_cfg.bus_type;
1205 config->flags = val;
1206
1207 return 0;
1208 }
1209
imx307_set_hdrae(struct imx307 * imx307,struct preisp_hdrae_exp_s * ae)1210 static int imx307_set_hdrae(struct imx307 *imx307,
1211 struct preisp_hdrae_exp_s *ae)
1212 {
1213 u32 l_exp_time, m_exp_time, s_exp_time;
1214 u32 l_gain, m_gain, s_gain;
1215 u32 shs1, shs2, rhs1;
1216 u32 gain_switch = 0;
1217 int ret = 0;
1218 u8 cg_mode = 0;
1219 u32 fsc = imx307->cur_vts;//The HDR mode vts is double by default to workaround T-line
1220
1221 if (!imx307->has_init_exp && !imx307->streaming) {
1222 imx307->init_hdrae_exp = *ae;
1223 imx307->has_init_exp = true;
1224 dev_dbg(&imx307->client->dev, "imx307 don't stream, record exp for hdr!\n");
1225 return ret;
1226 }
1227
1228 l_exp_time = ae->long_exp_reg;
1229 m_exp_time = ae->middle_exp_reg;
1230 s_exp_time = ae->short_exp_reg;
1231 l_gain = ae->long_gain_reg;
1232 m_gain = ae->middle_gain_reg;
1233 s_gain = ae->short_gain_reg;
1234
1235 if (imx307->cur_mode->hdr_mode == HDR_X2) {
1236 //2 stagger
1237 l_gain = m_gain;
1238 l_exp_time = m_exp_time;
1239 cg_mode = ae->middle_cg_mode;
1240 }
1241 dev_dbg(&imx307->client->dev,
1242 "rev exp req: L_time=%d, gain=%d, S_time=%d, gain=%d\n",
1243 l_exp_time, l_gain,
1244 s_exp_time, s_gain);
1245 ret = imx307_read_reg(imx307->client, IMX307_GAIN_SWITCH_REG,
1246 IMX307_REG_VALUE_08BIT, &gain_switch);
1247 if (!g_isHCG && cg_mode == GAIN_MODE_HCG) {
1248 gain_switch |= 0x0110;
1249 g_isHCG = true;
1250 } else if (g_isHCG && cg_mode == GAIN_MODE_LCG) {
1251 gain_switch &= 0xef;
1252 gain_switch |= 0x100;
1253 g_isHCG = false;
1254 }
1255
1256 //long exposure and short exposure
1257 if (imx307->cur_mode->lanes == 2 && imx307->bus_cfg.bus_type == V4L2_MBUS_CCP2)
1258 rhs1 = RHS1;
1259 else
1260 rhs1 = 0xe1;
1261 shs1 = rhs1 - s_exp_time - 1;
1262 shs2 = fsc - l_exp_time - 1;
1263 if (shs1 < 2)
1264 shs1 = 2;
1265 if (shs2 < (rhs1 + 2))
1266 shs2 = rhs1 + 2;
1267 else if (shs2 > (fsc - 2))
1268 shs2 = fsc - 2;
1269
1270 ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS1_L,
1271 IMX307_REG_VALUE_08BIT,
1272 IMX307_FETCH_LOW_BYTE_EXP(shs1));
1273 ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS1_M,
1274 IMX307_REG_VALUE_08BIT,
1275 IMX307_FETCH_MID_BYTE_EXP(shs1));
1276 ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS1_H,
1277 IMX307_REG_VALUE_08BIT,
1278 IMX307_FETCH_HIGH_BYTE_EXP(shs1));
1279 ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS2_L,
1280 IMX307_REG_VALUE_08BIT,
1281 IMX307_FETCH_LOW_BYTE_EXP(shs2));
1282 ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS2_M,
1283 IMX307_REG_VALUE_08BIT,
1284 IMX307_FETCH_MID_BYTE_EXP(shs2));
1285 ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS2_H,
1286 IMX307_REG_VALUE_08BIT,
1287 IMX307_FETCH_HIGH_BYTE_EXP(shs2));
1288
1289 ret |= imx307_write_reg(imx307->client, IMX307_REG_LF_GAIN,
1290 IMX307_REG_VALUE_08BIT,
1291 l_gain);
1292 ret |= imx307_write_reg(imx307->client, IMX307_REG_SF_GAIN,
1293 IMX307_REG_VALUE_08BIT,
1294 s_gain);
1295 if (gain_switch & 0x100) {
1296 ret |= imx307_write_reg(imx307->client,
1297 IMX307_GROUP_HOLD_REG,
1298 IMX307_REG_VALUE_08BIT,
1299 IMX307_GROUP_HOLD_START);
1300 ret |= imx307_write_reg(imx307->client, IMX307_GAIN_SWITCH_REG,
1301 IMX307_REG_VALUE_08BIT, gain_switch);
1302 ret |= imx307_write_reg(imx307->client,
1303 IMX307_GROUP_HOLD_REG,
1304 IMX307_REG_VALUE_08BIT,
1305 IMX307_GROUP_HOLD_END);
1306 }
1307 dev_dbg(&imx307->client->dev,
1308 "set l_gain:0x%x s_gain:0x%x shs2:0x%x shs1:0x%x\n",
1309 l_gain, s_gain, shs2, shs1);
1310 return ret;
1311 }
1312
imx307_get_module_inf(struct imx307 * imx307,struct rkmodule_inf * inf)1313 static void imx307_get_module_inf(struct imx307 *imx307,
1314 struct rkmodule_inf *inf)
1315 {
1316 memset(inf, 0, sizeof(*inf));
1317 strlcpy(inf->base.sensor, IMX307_NAME, sizeof(inf->base.sensor));
1318 strlcpy(inf->base.module, imx307->module_name,
1319 sizeof(inf->base.module));
1320 strlcpy(inf->base.lens, imx307->len_name, sizeof(inf->base.lens));
1321 }
1322
imx307_set_conversion_gain(struct imx307 * imx307,u32 * cg)1323 static int imx307_set_conversion_gain(struct imx307 *imx307, u32 *cg)
1324 {
1325 int ret = 0;
1326 struct i2c_client *client = imx307->client;
1327 int cur_cg = *cg;
1328 u32 gain_switch = 0;
1329
1330 ret = imx307_read_reg(client,
1331 IMX307_GAIN_SWITCH_REG,
1332 IMX307_REG_VALUE_08BIT,
1333 &gain_switch);
1334 if (g_isHCG && cur_cg == GAIN_MODE_LCG) {
1335 gain_switch &= 0xef;
1336 gain_switch |= 0x0100;
1337 g_isHCG = false;
1338 } else if (!g_isHCG && cur_cg == GAIN_MODE_HCG) {
1339 gain_switch |= 0x0110;
1340 g_isHCG = true;
1341 }
1342
1343 if (gain_switch & 0x100) {
1344 ret |= imx307_write_reg(client,
1345 IMX307_GROUP_HOLD_REG,
1346 IMX307_REG_VALUE_08BIT,
1347 IMX307_GROUP_HOLD_START);
1348 ret |= imx307_write_reg(client,
1349 IMX307_GAIN_SWITCH_REG,
1350 IMX307_REG_VALUE_08BIT,
1351 gain_switch & 0xff);
1352 ret |= imx307_write_reg(client,
1353 IMX307_GROUP_HOLD_REG,
1354 IMX307_REG_VALUE_08BIT,
1355 IMX307_GROUP_HOLD_END);
1356 }
1357
1358 return ret;
1359 }
1360
1361 #define USED_SYS_DEBUG
1362 #ifdef USED_SYS_DEBUG
1363 //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0037/cam_s_cg
set_conversion_gain_status(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1364 static ssize_t set_conversion_gain_status(struct device *dev,
1365 struct device_attribute *attr,
1366 const char *buf,
1367 size_t count)
1368 {
1369 struct i2c_client *client = to_i2c_client(dev);
1370 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1371 struct imx307 *imx307 = to_imx307(sd);
1372 int status = 0;
1373 int ret = 0;
1374
1375 ret = kstrtoint(buf, 0, &status);
1376 if (!ret && status >= 0 && status < 2)
1377 imx307_set_conversion_gain(imx307, &status);
1378 else
1379 dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
1380 return count;
1381 }
1382
1383 static struct device_attribute attributes[] = {
1384 __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
1385 };
1386
add_sysfs_interfaces(struct device * dev)1387 static int add_sysfs_interfaces(struct device *dev)
1388 {
1389 int i;
1390
1391 for (i = 0; i < ARRAY_SIZE(attributes); i++)
1392 if (device_create_file(dev, attributes + i))
1393 goto undo;
1394 return 0;
1395 undo:
1396 for (i--; i >= 0 ; i--)
1397 device_remove_file(dev, attributes + i);
1398 dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
1399 return -ENODEV;
1400 }
1401 #endif
1402
imx307_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1403 static long imx307_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1404 {
1405 struct imx307 *imx307 = to_imx307(sd);
1406 struct rkmodule_hdr_cfg *hdr;
1407 struct rkmodule_lvds_cfg *lvds_cfg;
1408 const struct imx307_mode *mode;
1409 u32 i, h, w;
1410 long ret = 0;
1411 s64 dst_pixel_rate = 0;
1412 s32 dst_link_freq = 0;
1413 u32 stream = 0;
1414
1415 switch (cmd) {
1416 case RKMODULE_GET_MODULE_INFO:
1417 imx307_get_module_inf(imx307, (struct rkmodule_inf *)arg);
1418 break;
1419 case PREISP_CMD_SET_HDRAE_EXP:
1420 ret = imx307_set_hdrae(imx307, arg);
1421 break;
1422 case RKMODULE_GET_HDR_CFG:
1423 hdr = (struct rkmodule_hdr_cfg *)arg;
1424 if (imx307->cur_mode->hdr_mode == NO_HDR)
1425 hdr->esp.mode = HDR_NORMAL_VC;
1426 else
1427 hdr->esp.mode = HDR_ID_CODE;
1428 hdr->hdr_mode = imx307->cur_mode->hdr_mode;
1429 break;
1430 case RKMODULE_SET_HDR_CFG:
1431 hdr = (struct rkmodule_hdr_cfg *)arg;
1432 for (i = 0; i < imx307->support_modes_num; i++) {
1433 if (imx307->support_modes[i].hdr_mode == hdr->hdr_mode) {
1434 imx307->cur_mode = &imx307->support_modes[i];
1435 break;
1436 }
1437 }
1438 if (i == imx307->support_modes_num) {
1439 dev_err(&imx307->client->dev,
1440 "not find hdr mode:%d config\n",
1441 hdr->hdr_mode);
1442 ret = -EINVAL;
1443 } else {
1444 mode = imx307->cur_mode;
1445 w = mode->hts_def - mode->width;
1446 h = mode->vts_def - mode->height;
1447 __v4l2_ctrl_modify_range(imx307->hblank, w, w, 1, w);
1448 __v4l2_ctrl_modify_range(imx307->vblank, h,
1449 IMX307_VTS_MAX - mode->height,
1450 1, h);
1451 dst_link_freq = mode->freq_idx;
1452 dst_pixel_rate = (u32)link_freq_menu_items[mode->freq_idx] / mode->bpp * 2 * mode->lanes;
1453 __v4l2_ctrl_s_ctrl_int64(imx307->pixel_rate,
1454 dst_pixel_rate);
1455 __v4l2_ctrl_s_ctrl(imx307->link_freq,
1456 dst_link_freq);
1457 imx307->cur_vts = mode->vts_def;
1458 }
1459 break;
1460 case RKMODULE_SET_CONVERSION_GAIN:
1461 ret = imx307_set_conversion_gain(imx307, (u32 *)arg);
1462 break;
1463 case RKMODULE_GET_LVDS_CFG:
1464 lvds_cfg = (struct rkmodule_lvds_cfg *)arg;
1465 if (imx307->bus_cfg.bus_type == V4L2_MBUS_CCP2)
1466 memcpy(lvds_cfg, &imx307->cur_mode->lvds_cfg,
1467 sizeof(struct rkmodule_lvds_cfg));
1468 else
1469 ret = -ENOIOCTLCMD;
1470 break;
1471 case RKMODULE_SET_QUICK_STREAM:
1472
1473 stream = *((u32 *)arg);
1474
1475 if (stream)
1476 ret = imx307_write_reg(imx307->client,
1477 IMX307_REG_CTRL_MODE,
1478 IMX307_REG_VALUE_08BIT,
1479 0);
1480 else
1481 ret = imx307_write_reg(imx307->client,
1482 IMX307_REG_CTRL_MODE,
1483 IMX307_REG_VALUE_08BIT,
1484 1);
1485 break;
1486 default:
1487 ret = -ENOIOCTLCMD;
1488 break;
1489 }
1490 return ret;
1491 }
1492
1493 #ifdef CONFIG_COMPAT
imx307_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1494 static long imx307_compat_ioctl32(struct v4l2_subdev *sd,
1495 unsigned int cmd, unsigned long arg)
1496 {
1497 void __user *up = compat_ptr(arg);
1498 struct rkmodule_inf *inf;
1499 struct rkmodule_awb_cfg *cfg;
1500 struct rkmodule_hdr_cfg *hdr;
1501 struct preisp_hdrae_exp_s *hdrae;
1502 long ret;
1503 u32 cg = 0;
1504 u32 stream = 0;
1505
1506 switch (cmd) {
1507 case RKMODULE_GET_MODULE_INFO:
1508 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1509 if (!inf) {
1510 ret = -ENOMEM;
1511 return ret;
1512 }
1513
1514 ret = imx307_ioctl(sd, cmd, inf);
1515 if (!ret)
1516 ret = copy_to_user(up, inf, sizeof(*inf));
1517 kfree(inf);
1518 break;
1519 case RKMODULE_AWB_CFG:
1520 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1521 if (!cfg) {
1522 ret = -ENOMEM;
1523 return ret;
1524 }
1525 ret = copy_from_user(cfg, up, sizeof(*cfg));
1526 if (!ret)
1527 ret = imx307_ioctl(sd, cmd, cfg);
1528 kfree(cfg);
1529 break;
1530 case RKMODULE_GET_HDR_CFG:
1531 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1532 if (!hdr) {
1533 ret = -ENOMEM;
1534 return ret;
1535 }
1536
1537 ret = imx307_ioctl(sd, cmd, hdr);
1538 if (!ret)
1539 ret = copy_to_user(up, hdr, sizeof(*hdr));
1540 kfree(hdr);
1541 break;
1542 case RKMODULE_SET_HDR_CFG:
1543 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1544 if (!hdr) {
1545 ret = -ENOMEM;
1546 return ret;
1547 }
1548
1549 ret = copy_from_user(hdr, up, sizeof(*hdr));
1550 if (!ret)
1551 ret = imx307_ioctl(sd, cmd, hdr);
1552 kfree(hdr);
1553 break;
1554 case PREISP_CMD_SET_HDRAE_EXP:
1555 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1556 if (!hdrae) {
1557 ret = -ENOMEM;
1558 return ret;
1559 }
1560
1561 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1562 if (!ret)
1563 ret = imx307_ioctl(sd, cmd, hdrae);
1564 kfree(hdrae);
1565 break;
1566 case RKMODULE_SET_CONVERSION_GAIN:
1567 ret = copy_from_user(&cg, up, sizeof(cg));
1568 if (!ret)
1569 ret = imx307_ioctl(sd, cmd, &cg);
1570 break;
1571 case RKMODULE_SET_QUICK_STREAM:
1572 ret = copy_from_user(&stream, up, sizeof(u32));
1573 if (!ret)
1574 ret = imx307_ioctl(sd, cmd, &stream);
1575 break;
1576 default:
1577 ret = -ENOIOCTLCMD;
1578 break;
1579 }
1580
1581 return ret;
1582 }
1583 #endif
1584
imx307_init_conversion_gain(struct imx307 * imx307)1585 static int imx307_init_conversion_gain(struct imx307 *imx307)
1586 {
1587 int ret = 0;
1588 struct i2c_client *client = imx307->client;
1589 u32 val = 0;
1590
1591 ret = imx307_read_reg(client,
1592 IMX307_GAIN_SWITCH_REG,
1593 IMX307_REG_VALUE_08BIT,
1594 &val);
1595 val &= 0xef;
1596 ret |= imx307_write_reg(client,
1597 IMX307_GAIN_SWITCH_REG,
1598 IMX307_REG_VALUE_08BIT,
1599 val);
1600 if (!ret)
1601 g_isHCG = false;
1602 return ret;
1603 }
1604
__imx307_start_stream(struct imx307 * imx307)1605 static int __imx307_start_stream(struct imx307 *imx307)
1606 {
1607 int ret;
1608
1609 ret = imx307_write_array(imx307->client, imx307->cur_mode->reg_list);
1610 if (ret)
1611 return ret;
1612 ret = imx307_init_conversion_gain(imx307);
1613 if (ret)
1614 return ret;
1615 /* In case these controls are set before streaming */
1616 ret = __v4l2_ctrl_handler_setup(&imx307->ctrl_handler);
1617 if (ret)
1618 return ret;
1619 if (imx307->has_init_exp && imx307->cur_mode->hdr_mode != NO_HDR) {
1620 ret = imx307_ioctl(&imx307->subdev, PREISP_CMD_SET_HDRAE_EXP,
1621 &imx307->init_hdrae_exp);
1622 if (ret) {
1623 dev_err(&imx307->client->dev,
1624 "init exp fail in hdr mode\n");
1625 return ret;
1626 }
1627 }
1628
1629 ret = imx307_write_reg(imx307->client,
1630 IMX307_REG_CTRL_MODE,
1631 IMX307_REG_VALUE_08BIT,
1632 0);
1633 return ret;
1634 }
1635
__imx307_stop_stream(struct imx307 * imx307)1636 static int __imx307_stop_stream(struct imx307 *imx307)
1637 {
1638 return imx307_write_reg(imx307->client,
1639 IMX307_REG_CTRL_MODE,
1640 IMX307_REG_VALUE_08BIT,
1641 1);
1642 }
1643
imx307_s_stream(struct v4l2_subdev * sd,int on)1644 static int imx307_s_stream(struct v4l2_subdev *sd, int on)
1645 {
1646 struct imx307 *imx307 = to_imx307(sd);
1647 struct i2c_client *client = imx307->client;
1648 int ret = 0;
1649
1650 mutex_lock(&imx307->mutex);
1651 on = !!on;
1652 if (on == imx307->streaming)
1653 goto unlock_and_return;
1654
1655 if (on) {
1656 ret = pm_runtime_get_sync(&client->dev);
1657 if (ret < 0) {
1658 pm_runtime_put_noidle(&client->dev);
1659 goto unlock_and_return;
1660 }
1661
1662 ret = __imx307_start_stream(imx307);
1663 if (ret) {
1664 v4l2_err(sd, "start stream failed while write regs\n");
1665 pm_runtime_put(&client->dev);
1666 goto unlock_and_return;
1667 }
1668 } else {
1669 __imx307_stop_stream(imx307);
1670 pm_runtime_put(&client->dev);
1671 }
1672
1673 imx307->streaming = on;
1674
1675 unlock_and_return:
1676 mutex_unlock(&imx307->mutex);
1677
1678 return ret;
1679 }
1680
imx307_s_power(struct v4l2_subdev * sd,int on)1681 static int imx307_s_power(struct v4l2_subdev *sd, int on)
1682 {
1683 struct imx307 *imx307 = to_imx307(sd);
1684 struct i2c_client *client = imx307->client;
1685 int ret = 0;
1686
1687 mutex_lock(&imx307->mutex);
1688
1689 /* If the power state is not modified - no work to do. */
1690 if (imx307->power_on == !!on)
1691 goto unlock_and_return;
1692
1693 if (on) {
1694 ret = pm_runtime_get_sync(&client->dev);
1695 if (ret < 0) {
1696 pm_runtime_put_noidle(&client->dev);
1697 goto unlock_and_return;
1698 }
1699
1700 ret = imx307_write_array(imx307->client, imx307_global_regs);
1701 if (ret) {
1702 v4l2_err(sd, "could not set init registers\n");
1703 pm_runtime_put_noidle(&client->dev);
1704 goto unlock_and_return;
1705 }
1706
1707 imx307->power_on = true;
1708 } else {
1709 pm_runtime_put(&client->dev);
1710 imx307->power_on = false;
1711 }
1712
1713 unlock_and_return:
1714 mutex_unlock(&imx307->mutex);
1715
1716 return ret;
1717 }
1718
1719 /* Calculate the delay in us by clock rate and clock cycles */
imx307_cal_delay(u32 cycles)1720 static inline u32 imx307_cal_delay(u32 cycles)
1721 {
1722 return DIV_ROUND_UP(cycles, IMX307_XVCLK_FREQ / 1000 / 1000);
1723 }
1724
__imx307_power_on(struct imx307 * imx307)1725 static int __imx307_power_on(struct imx307 *imx307)
1726 {
1727 int ret;
1728 u32 delay_us;
1729 struct device *dev = &imx307->client->dev;
1730
1731 if (!IS_ERR_OR_NULL(imx307->pins_default)) {
1732 ret = pinctrl_select_state(imx307->pinctrl,
1733 imx307->pins_default);
1734 if (ret < 0)
1735 dev_err(dev, "could not set pins\n");
1736 }
1737
1738 ret = clk_set_rate(imx307->xvclk, IMX307_XVCLK_FREQ);
1739 if (ret < 0)
1740 dev_warn(dev, "Failed to set xvclk rate (37.125M Hz)\n");
1741
1742 if (clk_get_rate(imx307->xvclk) != IMX307_XVCLK_FREQ)
1743 dev_warn(dev, "xvclk mismatched,based on 24M Hz\n");
1744
1745 ret = clk_prepare_enable(imx307->xvclk);
1746 if (ret < 0) {
1747 dev_err(dev, "Failed to enable xvclk\n");
1748 return ret;
1749 }
1750
1751
1752 ret = regulator_bulk_enable(IMX307_NUM_SUPPLIES, imx307->supplies);
1753 if (ret < 0) {
1754 dev_err(dev, "Failed to enable regulators\n");
1755 goto disable_clk;
1756 }
1757
1758 if (!IS_ERR(imx307->reset_gpio))
1759 gpiod_set_value_cansleep(imx307->reset_gpio, 0);
1760 usleep_range(500, 1000);
1761 if (!IS_ERR(imx307->reset_gpio))
1762 gpiod_set_value_cansleep(imx307->reset_gpio, 1);
1763
1764 if (!IS_ERR(imx307->pwdn_gpio))
1765 gpiod_set_value_cansleep(imx307->pwdn_gpio, 1);
1766
1767 /* 8192 cycles prior to first SCCB transaction */
1768 delay_us = imx307_cal_delay(8192);
1769 usleep_range(delay_us, delay_us * 2);
1770 usleep_range(5000, 10000);
1771 return 0;
1772
1773 disable_clk:
1774 clk_disable_unprepare(imx307->xvclk);
1775
1776 return ret;
1777 }
1778
__imx307_power_off(struct imx307 * imx307)1779 static void __imx307_power_off(struct imx307 *imx307)
1780 {
1781 int ret;
1782 struct device *dev = &imx307->client->dev;
1783
1784 if (!IS_ERR(imx307->pwdn_gpio))
1785 gpiod_set_value_cansleep(imx307->pwdn_gpio, 0);
1786 clk_disable_unprepare(imx307->xvclk);
1787 if (!IS_ERR(imx307->reset_gpio))
1788 gpiod_set_value_cansleep(imx307->reset_gpio, 0);
1789 if (!IS_ERR_OR_NULL(imx307->pins_sleep)) {
1790 ret = pinctrl_select_state(imx307->pinctrl,
1791 imx307->pins_sleep);
1792 if (ret < 0)
1793 dev_dbg(dev, "could not set pins\n");
1794 }
1795 regulator_bulk_disable(IMX307_NUM_SUPPLIES, imx307->supplies);
1796 }
1797
imx307_runtime_resume(struct device * dev)1798 static int imx307_runtime_resume(struct device *dev)
1799 {
1800 struct i2c_client *client = to_i2c_client(dev);
1801 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1802 struct imx307 *imx307 = to_imx307(sd);
1803
1804 return __imx307_power_on(imx307);
1805 }
1806
imx307_runtime_suspend(struct device * dev)1807 static int imx307_runtime_suspend(struct device *dev)
1808 {
1809 struct i2c_client *client = to_i2c_client(dev);
1810 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1811 struct imx307 *imx307 = to_imx307(sd);
1812
1813 __imx307_power_off(imx307);
1814
1815 return 0;
1816 }
1817
1818 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx307_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1819 static int imx307_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1820 {
1821 struct imx307 *imx307 = to_imx307(sd);
1822 struct v4l2_mbus_framefmt *try_fmt =
1823 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1824 const struct imx307_mode *def_mode = &imx307->support_modes[0];
1825
1826 mutex_lock(&imx307->mutex);
1827 /* Initialize try_fmt */
1828 try_fmt->width = def_mode->width;
1829 try_fmt->height = def_mode->height;
1830 try_fmt->code = def_mode->bus_fmt;
1831 try_fmt->field = V4L2_FIELD_NONE;
1832
1833 mutex_unlock(&imx307->mutex);
1834 /* No crop or compose */
1835
1836 return 0;
1837 }
1838 #endif
1839
imx307_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1840 static int imx307_enum_frame_interval(struct v4l2_subdev *sd,
1841 struct v4l2_subdev_pad_config *cfg,
1842 struct v4l2_subdev_frame_interval_enum *fie)
1843 {
1844 struct imx307 *imx307 = to_imx307(sd);
1845
1846 if (fie->index >= imx307->support_modes_num)
1847 return -EINVAL;
1848
1849 fie->code = imx307->support_modes[fie->index].bus_fmt;
1850 fie->width = imx307->support_modes[fie->index].width;
1851 fie->height = imx307->support_modes[fie->index].height;
1852 fie->interval = imx307->support_modes[fie->index].max_fps;
1853 fie->reserved[0] = imx307->support_modes[fie->index].hdr_mode;
1854 return 0;
1855 }
1856
1857 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1858 #define DST_WIDTH 1920
1859 #define DST_HEIGHT 1080
1860
1861 /*
1862 * The resolution of the driver configuration needs to be exactly
1863 * the same as the current output resolution of the sensor,
1864 * the input width of the isp needs to be 16 aligned,
1865 * the input height of the isp needs to be 8 aligned.
1866 * Can be cropped to standard resolution by this function,
1867 * otherwise it will crop out strange resolution according
1868 * to the alignment rules.
1869 */
1870
imx307_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1871 static int imx307_get_selection(struct v4l2_subdev *sd,
1872 struct v4l2_subdev_pad_config *cfg,
1873 struct v4l2_subdev_selection *sel)
1874 {
1875 struct imx307 *imx307 = to_imx307(sd);
1876
1877 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1878 sel->r.left = CROP_START(imx307->cur_mode->width, DST_WIDTH);
1879 sel->r.width = DST_WIDTH;
1880 if (imx307->bus_cfg.bus_type == V4L2_MBUS_CCP2) {
1881 if (imx307->cur_mode->hdr_mode == NO_HDR)
1882 sel->r.top = 21;
1883 else
1884 sel->r.top = 13;
1885 } else {
1886 sel->r.top = CROP_START(imx307->cur_mode->height, DST_HEIGHT);
1887 }
1888 sel->r.height = DST_HEIGHT;
1889 return 0;
1890 }
1891 return -EINVAL;
1892 }
1893
1894 static const struct dev_pm_ops imx307_pm_ops = {
1895 SET_RUNTIME_PM_OPS(imx307_runtime_suspend,
1896 imx307_runtime_resume, NULL)
1897 };
1898
1899 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1900 static const struct v4l2_subdev_internal_ops imx307_internal_ops = {
1901 .open = imx307_open,
1902 };
1903 #endif
1904
1905 static const struct v4l2_subdev_core_ops imx307_core_ops = {
1906 .s_power = imx307_s_power,
1907 .ioctl = imx307_ioctl,
1908 #ifdef CONFIG_COMPAT
1909 .compat_ioctl32 = imx307_compat_ioctl32,
1910 #endif
1911 };
1912
1913 static const struct v4l2_subdev_video_ops imx307_video_ops = {
1914 .s_stream = imx307_s_stream,
1915 .g_frame_interval = imx307_g_frame_interval,
1916 };
1917
1918 static const struct v4l2_subdev_pad_ops imx307_pad_ops = {
1919 .enum_mbus_code = imx307_enum_mbus_code,
1920 .enum_frame_size = imx307_enum_frame_sizes,
1921 .enum_frame_interval = imx307_enum_frame_interval,
1922 .get_fmt = imx307_get_fmt,
1923 .set_fmt = imx307_set_fmt,
1924 .get_selection = imx307_get_selection,
1925 .get_mbus_config = imx307_g_mbus_config,
1926 };
1927
1928 static const struct v4l2_subdev_ops imx307_subdev_ops = {
1929 .core = &imx307_core_ops,
1930 .video = &imx307_video_ops,
1931 .pad = &imx307_pad_ops,
1932 };
1933
imx307_set_ctrl(struct v4l2_ctrl * ctrl)1934 static int imx307_set_ctrl(struct v4l2_ctrl *ctrl)
1935 {
1936 struct imx307 *imx307 = container_of(ctrl->handler,
1937 struct imx307, ctrl_handler);
1938 struct i2c_client *client = imx307->client;
1939 s64 max;
1940 int ret = 0;
1941 u32 shs1 = 0;
1942 u32 vts = 0;
1943 u32 val = 0;
1944
1945 /* Propagate change of current control to all related controls */
1946 switch (ctrl->id) {
1947 case V4L2_CID_VBLANK:
1948 /* Update max exposure while meeting expected vblanking */
1949 max = imx307->cur_mode->height + ctrl->val - 2;
1950 __v4l2_ctrl_modify_range(imx307->exposure,
1951 imx307->exposure->minimum, max,
1952 imx307->exposure->step,
1953 imx307->exposure->default_value);
1954 break;
1955 }
1956
1957 if (!pm_runtime_get_if_in_use(&client->dev))
1958 return 0;
1959
1960 switch (ctrl->id) {
1961 case V4L2_CID_EXPOSURE:
1962 if (imx307->cur_mode->hdr_mode == NO_HDR) {
1963 shs1 = imx307->cur_vts - (ctrl->val + 1);
1964 ret = imx307_write_reg(imx307->client,
1965 IMX307_REG_SHS1_H,
1966 IMX307_REG_VALUE_08BIT,
1967 IMX307_FETCH_HIGH_BYTE_EXP(shs1));
1968 ret |= imx307_write_reg(imx307->client,
1969 IMX307_REG_SHS1_M,
1970 IMX307_REG_VALUE_08BIT,
1971 IMX307_FETCH_MID_BYTE_EXP(shs1));
1972 ret |= imx307_write_reg(imx307->client,
1973 IMX307_REG_SHS1_L,
1974 IMX307_REG_VALUE_08BIT,
1975 IMX307_FETCH_LOW_BYTE_EXP(shs1));
1976 dev_dbg(&client->dev, "set exposure 0x%x, cur_vts 0x%x,shs1 0x%x\n",
1977 ctrl->val, imx307->cur_vts, shs1);
1978 }
1979 break;
1980 case V4L2_CID_ANALOGUE_GAIN:
1981 if (imx307->cur_mode->hdr_mode == NO_HDR) {
1982 ret = imx307_write_reg(imx307->client,
1983 IMX307_REG_LF_GAIN,
1984 IMX307_REG_VALUE_08BIT,
1985 ctrl->val);
1986 dev_dbg(&client->dev, "set analog gain 0x%x\n",
1987 ctrl->val);
1988 }
1989 break;
1990 case V4L2_CID_VBLANK:
1991 vts = ctrl->val + imx307->cur_mode->height;
1992 imx307->cur_vts = vts;
1993 if (imx307->cur_mode->hdr_mode == HDR_X2)
1994 vts /= 2;
1995 ret = imx307_write_reg(imx307->client,
1996 IMX307_REG_VTS_H,
1997 IMX307_REG_VALUE_08BIT,
1998 IMX307_FETCH_HIGH_BYTE_VTS(vts));
1999 ret |= imx307_write_reg(imx307->client,
2000 IMX307_REG_VTS_M,
2001 IMX307_REG_VALUE_08BIT,
2002 IMX307_FETCH_MID_BYTE_VTS(vts));
2003 ret |= imx307_write_reg(imx307->client,
2004 IMX307_REG_VTS_L,
2005 IMX307_REG_VALUE_08BIT,
2006 IMX307_FETCH_LOW_BYTE_VTS(vts));
2007 dev_dbg(&client->dev, "set vts 0x%x\n",
2008 vts);
2009 break;
2010 case V4L2_CID_TEST_PATTERN:
2011 #ifdef USED_TEST_PATTERN
2012 ret = imx307_enable_test_pattern(imx307, ctrl->val);
2013 #endif
2014 break;
2015 case V4L2_CID_HFLIP:
2016 ret = imx307_read_reg(client,
2017 IMX307_FLIP_REG,
2018 IMX307_REG_VALUE_08BIT,
2019 &val);
2020 if (ctrl->val)
2021 val |= MIRROR_BIT_MASK;
2022 else
2023 val &= ~MIRROR_BIT_MASK;
2024 ret |= imx307_write_reg(client,
2025 IMX307_FLIP_REG,
2026 IMX307_REG_VALUE_08BIT,
2027 val);
2028 if (ret == 0)
2029 imx307->flip = val;
2030 break;
2031 case V4L2_CID_VFLIP:
2032 ret = imx307_read_reg(client,
2033 IMX307_FLIP_REG,
2034 IMX307_REG_VALUE_08BIT,
2035 &val);
2036 if (ctrl->val)
2037 val |= FLIP_BIT_MASK;
2038 else
2039 val &= ~FLIP_BIT_MASK;
2040 ret |= imx307_write_reg(client,
2041 IMX307_FLIP_REG,
2042 IMX307_REG_VALUE_08BIT,
2043 val);
2044 if (ret == 0)
2045 imx307->flip = val;
2046 break;
2047 default:
2048 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
2049 __func__, ctrl->id, ctrl->val);
2050 break;
2051 }
2052
2053 pm_runtime_put(&client->dev);
2054
2055 return ret;
2056 }
2057
2058 static const struct v4l2_ctrl_ops imx307_ctrl_ops = {
2059 .s_ctrl = imx307_set_ctrl,
2060 };
2061
imx307_initialize_controls(struct imx307 * imx307)2062 static int imx307_initialize_controls(struct imx307 *imx307)
2063 {
2064 const struct imx307_mode *mode;
2065 struct v4l2_ctrl_handler *handler;
2066 s64 exposure_max, vblank_def;
2067 u32 h_blank;
2068 int ret;
2069 s32 dst_link_freq = 0;
2070 s64 dst_pixel_rate = 0;
2071
2072 handler = &imx307->ctrl_handler;
2073 mode = imx307->cur_mode;
2074 ret = v4l2_ctrl_handler_init(handler, 9);
2075 if (ret)
2076 return ret;
2077 handler->lock = &imx307->mutex;
2078
2079 imx307->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
2080 1, 0, link_freq_menu_items);
2081
2082 dst_link_freq = mode->freq_idx;
2083 dst_pixel_rate = (u32)link_freq_menu_items[mode->freq_idx] / mode->bpp * 2 * mode->lanes;
2084 __v4l2_ctrl_s_ctrl(imx307->link_freq,
2085 dst_link_freq);
2086 imx307->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
2087 0, IMX307_PIXEL_RATE_HDR, 1, dst_pixel_rate);
2088
2089 h_blank = mode->hts_def - mode->width;
2090
2091 imx307->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
2092 h_blank, h_blank, 1, h_blank);
2093 if (imx307->hblank)
2094 imx307->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2095
2096 vblank_def = mode->vts_def - mode->height;
2097 imx307->cur_vts = mode->vts_def;
2098 imx307->vblank = v4l2_ctrl_new_std(handler, &imx307_ctrl_ops,
2099 V4L2_CID_VBLANK, vblank_def,
2100 IMX307_VTS_MAX - mode->height,
2101 1, vblank_def);
2102
2103 exposure_max = mode->vts_def - 4;
2104
2105 imx307->exposure = v4l2_ctrl_new_std(handler, &imx307_ctrl_ops,
2106 V4L2_CID_EXPOSURE, IMX307_EXPOSURE_MIN,
2107 exposure_max, IMX307_EXPOSURE_STEP,
2108 mode->exp_def);
2109
2110 imx307->anal_gain = v4l2_ctrl_new_std(handler, &imx307_ctrl_ops,
2111 V4L2_CID_ANALOGUE_GAIN, IMX307_GAIN_MIN,
2112 IMX307_GAIN_MAX, IMX307_GAIN_STEP,
2113 IMX307_GAIN_DEFAULT);
2114
2115 #ifdef USED_TEST_PATTERN
2116 imx307->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
2117 &imx307_ctrl_ops, V4L2_CID_TEST_PATTERN,
2118 ARRAY_SIZE(imx307_test_pattern_menu) - 1,
2119 0, 0, imx307_test_pattern_menu);
2120 #endif
2121 imx307->h_flip = v4l2_ctrl_new_std(handler, &imx307_ctrl_ops,
2122 V4L2_CID_HFLIP, 0, 1, 1, 0);
2123
2124 imx307->v_flip = v4l2_ctrl_new_std(handler, &imx307_ctrl_ops,
2125 V4L2_CID_VFLIP, 0, 1, 1, 0);
2126 imx307->flip = 0;
2127 if (handler->error) {
2128 ret = handler->error;
2129 dev_err(&imx307->client->dev,
2130 "Failed to init controls(%d)\n", ret);
2131 goto err_free_handler;
2132 }
2133
2134 imx307->subdev.ctrl_handler = handler;
2135 imx307->has_init_exp = false;
2136
2137 return 0;
2138
2139 err_free_handler:
2140 v4l2_ctrl_handler_free(handler);
2141
2142 return ret;
2143 }
2144
imx307_check_sensor_id(struct imx307 * imx307,struct i2c_client * client)2145 static int imx307_check_sensor_id(struct imx307 *imx307,
2146 struct i2c_client *client)
2147 {
2148 struct device *dev = &imx307->client->dev;
2149 u32 id = 0;
2150 int ret;
2151
2152 ret = imx307_read_reg(client, IMX307_REG_CHIP_ID,
2153 IMX307_REG_VALUE_08BIT, &id);
2154
2155 if (id != CHIP_ID) {
2156 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
2157 return -EINVAL;
2158 }
2159 return ret;
2160 }
2161
imx307_configure_regulators(struct imx307 * imx307)2162 static int imx307_configure_regulators(struct imx307 *imx307)
2163 {
2164 unsigned int i;
2165
2166 for (i = 0; i < IMX307_NUM_SUPPLIES; i++)
2167 imx307->supplies[i].supply = imx307_supply_names[i];
2168
2169 return devm_regulator_bulk_get(&imx307->client->dev,
2170 IMX307_NUM_SUPPLIES,
2171 imx307->supplies);
2172 }
2173
imx307_probe(struct i2c_client * client,const struct i2c_device_id * id)2174 static int imx307_probe(struct i2c_client *client,
2175 const struct i2c_device_id *id)
2176 {
2177 struct device *dev = &client->dev;
2178 struct device_node *node = dev->of_node;
2179 struct imx307 *imx307;
2180 struct v4l2_subdev *sd;
2181 char facing[2];
2182 int ret;
2183 struct device_node *endpoint;
2184
2185 dev_info(dev, "driver version: %02x.%02x.%02x",
2186 DRIVER_VERSION >> 16,
2187 (DRIVER_VERSION & 0xff00) >> 8,
2188 DRIVER_VERSION & 0x00ff);
2189
2190 imx307 = devm_kzalloc(dev, sizeof(*imx307), GFP_KERNEL);
2191 if (!imx307)
2192 return -ENOMEM;
2193
2194 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2195 &imx307->module_index);
2196 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2197 &imx307->module_facing);
2198 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2199 &imx307->module_name);
2200 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2201 &imx307->len_name);
2202 if (ret) {
2203 dev_err(dev, "could not get module information!\n");
2204 return -EINVAL;
2205 }
2206 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
2207 if (!endpoint) {
2208 dev_err(dev, "Failed to get endpoint\n");
2209 return -EINVAL;
2210 }
2211
2212 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
2213 &imx307->bus_cfg);
2214 if (ret)
2215 dev_warn(dev, "could not get bus config!\n");
2216 if (imx307->bus_cfg.bus_type == V4L2_MBUS_CCP2) {
2217 if (imx307->bus_cfg.bus.mipi_csi1.data_lane == 2) {
2218 imx307->support_modes = lvds_2lane_supported_modes;
2219 imx307->support_modes_num = ARRAY_SIZE(lvds_2lane_supported_modes);
2220 } else if (imx307->bus_cfg.bus.mipi_csi1.data_lane == 4) {
2221 imx307->support_modes = lvds_supported_modes;
2222 imx307->support_modes_num = ARRAY_SIZE(lvds_supported_modes);
2223 } else {
2224 dev_err(dev, "lvds lanes err!\n");
2225 }
2226 } else {
2227 imx307->support_modes = mipi_supported_modes;
2228 imx307->support_modes_num = ARRAY_SIZE(mipi_supported_modes);
2229 }
2230 imx307->client = client;
2231 imx307->cur_mode = &imx307->support_modes[0];
2232
2233 imx307->xvclk = devm_clk_get(dev, "xvclk");
2234 if (IS_ERR(imx307->xvclk)) {
2235 dev_err(dev, "Failed to get xvclk\n");
2236 return -EINVAL;
2237 }
2238
2239 imx307->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2240 if (IS_ERR(imx307->reset_gpio))
2241 dev_warn(dev, "Failed to get reset-gpios\n");
2242
2243 imx307->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
2244 if (IS_ERR(imx307->pwdn_gpio))
2245 dev_warn(dev, "Failed to get pwdn-gpios\n");
2246
2247 ret = imx307_configure_regulators(imx307);
2248 if (ret) {
2249 dev_err(dev, "Failed to get power regulators\n");
2250 return ret;
2251 }
2252
2253 imx307->pinctrl = devm_pinctrl_get(dev);
2254 if (!IS_ERR(imx307->pinctrl)) {
2255 imx307->pins_default =
2256 pinctrl_lookup_state(imx307->pinctrl,
2257 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2258 if (IS_ERR(imx307->pins_default))
2259 dev_err(dev, "could not get default pinstate\n");
2260
2261 imx307->pins_sleep =
2262 pinctrl_lookup_state(imx307->pinctrl,
2263 OF_CAMERA_PINCTRL_STATE_SLEEP);
2264 if (IS_ERR(imx307->pins_sleep))
2265 dev_err(dev, "could not get sleep pinstate\n");
2266 }
2267
2268 mutex_init(&imx307->mutex);
2269
2270 sd = &imx307->subdev;
2271 v4l2_i2c_subdev_init(sd, client, &imx307_subdev_ops);
2272 ret = imx307_initialize_controls(imx307);
2273 if (ret)
2274 goto err_destroy_mutex;
2275
2276 ret = __imx307_power_on(imx307);
2277 if (ret)
2278 goto err_free_handler;
2279
2280 ret = imx307_check_sensor_id(imx307, client);
2281 if (ret)
2282 goto err_power_off;
2283
2284 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2285 dev_err(dev, "set the video v4l2 subdev api\n");
2286 sd->internal_ops = &imx307_internal_ops;
2287 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2288 V4L2_SUBDEV_FL_HAS_EVENTS;
2289 #endif
2290 #if defined(CONFIG_MEDIA_CONTROLLER)
2291 dev_err(dev, "set the media controller\n");
2292 imx307->pad.flags = MEDIA_PAD_FL_SOURCE;
2293 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2294 ret = media_entity_pads_init(&sd->entity, 1, &imx307->pad);
2295 if (ret < 0)
2296 goto err_power_off;
2297 #endif
2298
2299 memset(facing, 0, sizeof(facing));
2300 if (strcmp(imx307->module_facing, "back") == 0)
2301 facing[0] = 'b';
2302 else
2303 facing[0] = 'f';
2304
2305 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2306 imx307->module_index, facing,
2307 IMX307_NAME, dev_name(sd->dev));
2308 ret = v4l2_async_register_subdev_sensor_common(sd);
2309 if (ret) {
2310 dev_err(dev, "v4l2 async register subdev failed\n");
2311 goto err_clean_entity;
2312 }
2313
2314 pm_runtime_set_active(dev);
2315 pm_runtime_enable(dev);
2316 pm_runtime_idle(dev);
2317 g_isHCG = false;
2318 #ifdef USED_SYS_DEBUG
2319 add_sysfs_interfaces(dev);
2320 #endif
2321 dev_err(dev, "v4l2 async register subdev success\n");
2322 return 0;
2323
2324 err_clean_entity:
2325 #if defined(CONFIG_MEDIA_CONTROLLER)
2326 media_entity_cleanup(&sd->entity);
2327 #endif
2328 err_power_off:
2329 __imx307_power_off(imx307);
2330 err_free_handler:
2331 v4l2_ctrl_handler_free(&imx307->ctrl_handler);
2332 err_destroy_mutex:
2333 mutex_destroy(&imx307->mutex);
2334
2335 return ret;
2336 }
2337
imx307_remove(struct i2c_client * client)2338 static int imx307_remove(struct i2c_client *client)
2339 {
2340 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2341 struct imx307 *imx307 = to_imx307(sd);
2342
2343 v4l2_async_unregister_subdev(sd);
2344 #if defined(CONFIG_MEDIA_CONTROLLER)
2345 media_entity_cleanup(&sd->entity);
2346 #endif
2347 v4l2_ctrl_handler_free(&imx307->ctrl_handler);
2348 mutex_destroy(&imx307->mutex);
2349
2350 pm_runtime_disable(&client->dev);
2351 if (!pm_runtime_status_suspended(&client->dev))
2352 __imx307_power_off(imx307);
2353 pm_runtime_set_suspended(&client->dev);
2354
2355 return 0;
2356 }
2357
2358 #if IS_ENABLED(CONFIG_OF)
2359 static const struct of_device_id imx307_of_match[] = {
2360 { .compatible = "sony,imx307" },
2361 {},
2362 };
2363 MODULE_DEVICE_TABLE(of, imx307_of_match);
2364 #endif
2365
2366 static const struct i2c_device_id imx307_match_id[] = {
2367 { "sony,imx307", 0 },
2368 { },
2369 };
2370
2371 static struct i2c_driver imx307_i2c_driver = {
2372 .driver = {
2373 .name = IMX307_NAME,
2374 .pm = &imx307_pm_ops,
2375 .of_match_table = of_match_ptr(imx307_of_match),
2376 },
2377 .probe = &imx307_probe,
2378 .remove = &imx307_remove,
2379 .id_table = imx307_match_id,
2380 };
2381
sensor_mod_init(void)2382 static int __init sensor_mod_init(void)
2383 {
2384 return i2c_add_driver(&imx307_i2c_driver);
2385 }
2386
sensor_mod_exit(void)2387 static void __exit sensor_mod_exit(void)
2388 {
2389 i2c_del_driver(&imx307_i2c_driver);
2390 }
2391
2392 device_initcall_sync(sensor_mod_init);
2393 module_exit(sensor_mod_exit);
2394
2395 MODULE_DESCRIPTION("Sony imx307 sensor driver");
2396 MODULE_LICENSE("GPL v2");
2397