1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * imx214 camera driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * V0.0X01.0X00 first version.
8*4882a593Smuzhiyun * V0.0X01.0X01 fix compile errors.
9*4882a593Smuzhiyun * V0.0X01.0X02 add 4lane mode support.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/device.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/pm_runtime.h>
20*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
21*4882a593Smuzhiyun #include <linux/sysfs.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun #include <linux/version.h>
24*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
25*4882a593Smuzhiyun #include <media/media-entity.h>
26*4882a593Smuzhiyun #include <media/v4l2-async.h>
27*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
28*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
29*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
30*4882a593Smuzhiyun #include <media/v4l2-mediabus.h>
31*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
32*4882a593Smuzhiyun #include <linux/rk-preisp.h>
33*4882a593Smuzhiyun #include <linux/of_graph.h>
34*4882a593Smuzhiyun #include "imx214_eeprom_head.h"
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
39*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
40*4882a593Smuzhiyun #endif
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define IMX214_LINK_FREQ_600MHZ 600000000U
43*4882a593Smuzhiyun /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
44*4882a593Smuzhiyun #define IMX214_PIXEL_RATE (IMX214_LINK_FREQ_600MHZ * 2LL * 4LL / 10LL)
45*4882a593Smuzhiyun #define IMX214_XVCLK_FREQ 24000000
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define CHIP_ID 0x0214
48*4882a593Smuzhiyun #define IMX214_REG_CHIP_ID 0x0016
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define IMX214_REG_CTRL_MODE 0x0100
51*4882a593Smuzhiyun #define IMX214_MODE_SW_STANDBY 0x0
52*4882a593Smuzhiyun #define IMX214_MODE_STREAMING BIT(0)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define IMX214_REG_EXPOSURE 0x0202
55*4882a593Smuzhiyun #define IMX214_EXPOSURE_MIN 4
56*4882a593Smuzhiyun #define IMX214_EXPOSURE_STEP 1
57*4882a593Smuzhiyun #define IMX214_VTS_MAX 0xffff
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define IMX214_REG_GAIN_H 0x0204
60*4882a593Smuzhiyun #define IMX214_REG_GAIN_L 0x0205
61*4882a593Smuzhiyun #define IMX214_GAIN_MIN 0x200
62*4882a593Smuzhiyun #define IMX214_GAIN_MAX 0x1fff
63*4882a593Smuzhiyun #define IMX214_GAIN_STEP 0x200
64*4882a593Smuzhiyun #define IMX214_GAIN_DEFAULT 0x800
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define IMX214_REG_TEST_PATTERN 0x5e00
67*4882a593Smuzhiyun #define IMX214_TEST_PATTERN_ENABLE 0x80
68*4882a593Smuzhiyun #define IMX214_TEST_PATTERN_DISABLE 0x0
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define IMX214_REG_VTS 0x0340
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define REG_NULL 0xFFFF
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define IMX214_REG_VALUE_08BIT 1
75*4882a593Smuzhiyun #define IMX214_REG_VALUE_16BIT 2
76*4882a593Smuzhiyun #define IMX214_REG_VALUE_24BIT 3
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define IMX214_BITS_PER_SAMPLE 10
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
81*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define IMX214_NAME "imx214"
84*4882a593Smuzhiyun #define IMX214_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* OTP MACRO */
87*4882a593Smuzhiyun #define MODULE_BKX 0X01
88*4882a593Smuzhiyun #define MODULE_TYPE MODULE_BKX
89*4882a593Smuzhiyun #if MODULE_TYPE == MODULE_BKX
90*4882a593Smuzhiyun #define RG_Ratio_Typical_Default (0x026e)
91*4882a593Smuzhiyun #define BG_Ratio_Typical_Default (0x0280)
92*4882a593Smuzhiyun #else
93*4882a593Smuzhiyun #define RG_Ratio_Typical_Default (0x16f)
94*4882a593Smuzhiyun #define BG_Ratio_Typical_Default (0x16f)
95*4882a593Smuzhiyun #endif
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static const char * const imx214_supply_names[] = {
98*4882a593Smuzhiyun "avdd", /* Analog power */
99*4882a593Smuzhiyun "dovdd", /* Digital I/O power */
100*4882a593Smuzhiyun "dvdd", /* Digital core power */
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define IMX214_NUM_SUPPLIES ARRAY_SIZE(imx214_supply_names)
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun struct regval {
106*4882a593Smuzhiyun u16 addr;
107*4882a593Smuzhiyun u8 val;
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun struct imx214_mode {
111*4882a593Smuzhiyun u32 width;
112*4882a593Smuzhiyun u32 height;
113*4882a593Smuzhiyun struct v4l2_fract max_fps;
114*4882a593Smuzhiyun u32 hts_def;
115*4882a593Smuzhiyun u32 vts_def;
116*4882a593Smuzhiyun u32 exp_def;
117*4882a593Smuzhiyun u32 link_freq_idx;
118*4882a593Smuzhiyun u32 bpp;
119*4882a593Smuzhiyun const struct regval *reg_list;
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun struct imx214 {
123*4882a593Smuzhiyun struct i2c_client *client;
124*4882a593Smuzhiyun struct clk *xvclk;
125*4882a593Smuzhiyun struct gpio_desc *power_gpio;
126*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
127*4882a593Smuzhiyun struct gpio_desc *pwdn_gpio;
128*4882a593Smuzhiyun struct regulator_bulk_data supplies[IMX214_NUM_SUPPLIES];
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun struct pinctrl *pinctrl;
131*4882a593Smuzhiyun struct pinctrl_state *pins_default;
132*4882a593Smuzhiyun struct pinctrl_state *pins_sleep;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun struct v4l2_subdev subdev;
135*4882a593Smuzhiyun struct media_pad pad;
136*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
137*4882a593Smuzhiyun struct v4l2_ctrl *exposure;
138*4882a593Smuzhiyun struct v4l2_ctrl *anal_gain;
139*4882a593Smuzhiyun struct v4l2_ctrl *digi_gain;
140*4882a593Smuzhiyun struct v4l2_ctrl *hblank;
141*4882a593Smuzhiyun struct v4l2_ctrl *vblank;
142*4882a593Smuzhiyun struct v4l2_ctrl *pixel_rate;
143*4882a593Smuzhiyun struct v4l2_ctrl *link_freq;
144*4882a593Smuzhiyun struct v4l2_ctrl *test_pattern;
145*4882a593Smuzhiyun struct mutex mutex;
146*4882a593Smuzhiyun struct v4l2_fwnode_endpoint bus_cfg;
147*4882a593Smuzhiyun bool streaming;
148*4882a593Smuzhiyun bool power_on;
149*4882a593Smuzhiyun const struct imx214_mode *support_modes;
150*4882a593Smuzhiyun const struct imx214_mode *cur_mode;
151*4882a593Smuzhiyun u32 module_index;
152*4882a593Smuzhiyun u32 cfg_num;
153*4882a593Smuzhiyun const char *module_facing;
154*4882a593Smuzhiyun const char *module_name;
155*4882a593Smuzhiyun const char *len_name;
156*4882a593Smuzhiyun struct imx214_otp_info *otp;
157*4882a593Smuzhiyun struct rkmodule_inf module_inf;
158*4882a593Smuzhiyun struct rkmodule_awb_cfg awb_cfg;
159*4882a593Smuzhiyun struct rkmodule_lsc_cfg lsc_cfg;
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun #define to_imx214(sd) container_of(sd, struct imx214, subdev)
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun struct imx214_id_name {
165*4882a593Smuzhiyun u32 id;
166*4882a593Smuzhiyun char name[RKMODULE_NAME_LEN];
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun static const struct imx214_id_name imx214_module_info[] = {
170*4882a593Smuzhiyun {0x36, "GuangDongLiteArray"},
171*4882a593Smuzhiyun {0x0d, "CameraKing"},
172*4882a593Smuzhiyun {0x00, "Unknown"}
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun static const struct imx214_id_name imx214_lens_info[] = {
176*4882a593Smuzhiyun {0x47, "Sunny 3923C"},
177*4882a593Smuzhiyun {0x07, "Largen 9611A6"},
178*4882a593Smuzhiyun {0x00, "Unknown"}
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun /*
181*4882a593Smuzhiyun * Xclk 24Mhz
182*4882a593Smuzhiyun */
183*4882a593Smuzhiyun static const struct regval imx214_global_regs[] = {
184*4882a593Smuzhiyun {0x0136, 0x18},
185*4882a593Smuzhiyun {0x0137, 0x00},
186*4882a593Smuzhiyun {0x0101, 0x00},
187*4882a593Smuzhiyun {0x0105, 0x01},
188*4882a593Smuzhiyun {0x0106, 0x01},
189*4882a593Smuzhiyun {0x4550, 0x02},
190*4882a593Smuzhiyun {0x4601, 0x04},
191*4882a593Smuzhiyun {0x4642, 0x01},
192*4882a593Smuzhiyun {0x6227, 0x11},
193*4882a593Smuzhiyun {0x6276, 0x00},
194*4882a593Smuzhiyun {0x900E, 0x06},
195*4882a593Smuzhiyun {0xA802, 0x90},
196*4882a593Smuzhiyun {0xA803, 0x11},
197*4882a593Smuzhiyun {0xA804, 0x62},
198*4882a593Smuzhiyun {0xA805, 0x77},
199*4882a593Smuzhiyun {0xA806, 0xAE},
200*4882a593Smuzhiyun {0xA807, 0x34},
201*4882a593Smuzhiyun {0xA808, 0xAE},
202*4882a593Smuzhiyun {0xA809, 0x35},
203*4882a593Smuzhiyun {0xA80A, 0x62},
204*4882a593Smuzhiyun {0xA80B, 0x83},
205*4882a593Smuzhiyun {0xAE33, 0x00},
206*4882a593Smuzhiyun {0x4174, 0x00},
207*4882a593Smuzhiyun {0x4175, 0x11},
208*4882a593Smuzhiyun {0x4612, 0x29},
209*4882a593Smuzhiyun {0x461B, 0x2C},
210*4882a593Smuzhiyun {0x461F, 0x06},
211*4882a593Smuzhiyun {0x4635, 0x07},
212*4882a593Smuzhiyun {0x4637, 0x30},
213*4882a593Smuzhiyun {0x463F, 0x18},
214*4882a593Smuzhiyun {0x4641, 0x0D},
215*4882a593Smuzhiyun {0x465B, 0x2C},
216*4882a593Smuzhiyun {0x465F, 0x2B},
217*4882a593Smuzhiyun {0x4663, 0x2B},
218*4882a593Smuzhiyun {0x4667, 0x24},
219*4882a593Smuzhiyun {0x466F, 0x24},
220*4882a593Smuzhiyun {0x470E, 0x09},
221*4882a593Smuzhiyun {0x4909, 0xAB},
222*4882a593Smuzhiyun {0x490B, 0x95},
223*4882a593Smuzhiyun {0x4915, 0x5D},
224*4882a593Smuzhiyun {0x4A5F, 0xFF},
225*4882a593Smuzhiyun {0x4A61, 0xFF},
226*4882a593Smuzhiyun {0x4A73, 0x62},
227*4882a593Smuzhiyun {0x4A85, 0x00},
228*4882a593Smuzhiyun {0x4A87, 0xFF},
229*4882a593Smuzhiyun {0x583C, 0x04},
230*4882a593Smuzhiyun {0x620E, 0x04},
231*4882a593Smuzhiyun {0x6EB2, 0x01},
232*4882a593Smuzhiyun {0x6EB3, 0x00},
233*4882a593Smuzhiyun {0x9300, 0x02},
234*4882a593Smuzhiyun {REG_NULL, 0x00},
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun static const struct regval imx214_2104x1560_30fps_regs_2lane[] = {
238*4882a593Smuzhiyun {0x0114, 0x01},
239*4882a593Smuzhiyun {0x0220, 0x00},
240*4882a593Smuzhiyun {0x0221, 0x11},
241*4882a593Smuzhiyun {0x0222, 0x01},
242*4882a593Smuzhiyun {0x0340, 0x06},
243*4882a593Smuzhiyun {0x0341, 0x40},
244*4882a593Smuzhiyun {0x0342, 0x13},
245*4882a593Smuzhiyun {0x0343, 0x90},
246*4882a593Smuzhiyun {0x0344, 0x00},
247*4882a593Smuzhiyun {0x0345, 0x00},
248*4882a593Smuzhiyun {0x0346, 0x00},
249*4882a593Smuzhiyun {0x0347, 0x00},
250*4882a593Smuzhiyun {0x0348, 0x10},
251*4882a593Smuzhiyun {0x0349, 0x6F},
252*4882a593Smuzhiyun {0x034A, 0x0C},
253*4882a593Smuzhiyun {0x034B, 0x2F},
254*4882a593Smuzhiyun {0x0381, 0x01},
255*4882a593Smuzhiyun {0x0383, 0x01},
256*4882a593Smuzhiyun {0x0385, 0x01},
257*4882a593Smuzhiyun {0x0387, 0x01},
258*4882a593Smuzhiyun {0x0900, 0x01},
259*4882a593Smuzhiyun {0x0901, 0x22},
260*4882a593Smuzhiyun {0x0902, 0x02},
261*4882a593Smuzhiyun {0x3000, 0x35},
262*4882a593Smuzhiyun {0x3054, 0x01},
263*4882a593Smuzhiyun {0x305C, 0x11},
264*4882a593Smuzhiyun {0x0112, 0x0A},
265*4882a593Smuzhiyun {0x0113, 0x0A},
266*4882a593Smuzhiyun {0x034C, 0x08},
267*4882a593Smuzhiyun {0x034D, 0x38},
268*4882a593Smuzhiyun {0x034E, 0x06},
269*4882a593Smuzhiyun {0x034F, 0x18},
270*4882a593Smuzhiyun {0x0401, 0x00},
271*4882a593Smuzhiyun {0x0404, 0x00},
272*4882a593Smuzhiyun {0x0405, 0x10},
273*4882a593Smuzhiyun {0x0408, 0x00},
274*4882a593Smuzhiyun {0x0409, 0x00},
275*4882a593Smuzhiyun {0x040A, 0x00},
276*4882a593Smuzhiyun {0x040B, 0x00},
277*4882a593Smuzhiyun {0x040C, 0x08},
278*4882a593Smuzhiyun {0x040D, 0x38},
279*4882a593Smuzhiyun {0x040E, 0x06},
280*4882a593Smuzhiyun {0x040F, 0x18},
281*4882a593Smuzhiyun {0x0301, 0x05},
282*4882a593Smuzhiyun {0x0303, 0x04},
283*4882a593Smuzhiyun {0x0305, 0x03},
284*4882a593Smuzhiyun {0x0306, 0x00},
285*4882a593Smuzhiyun {0x0307, 0x96},
286*4882a593Smuzhiyun {0x0309, 0x0A},
287*4882a593Smuzhiyun {0x030B, 0x01},
288*4882a593Smuzhiyun {0x0310, 0x00},
289*4882a593Smuzhiyun {0x0820, 0x09},
290*4882a593Smuzhiyun {0x0821, 0x60},
291*4882a593Smuzhiyun {0x0822, 0x00},
292*4882a593Smuzhiyun {0x0823, 0x00},
293*4882a593Smuzhiyun {0x3A03, 0x06},
294*4882a593Smuzhiyun {0x3A04, 0x68},
295*4882a593Smuzhiyun {0x3A05, 0x01},
296*4882a593Smuzhiyun {0x0B06, 0x01},
297*4882a593Smuzhiyun {0x30A2, 0x00},
298*4882a593Smuzhiyun {0x30B4, 0x00},
299*4882a593Smuzhiyun {0x3A02, 0xFF},
300*4882a593Smuzhiyun {0x3011, 0x00},
301*4882a593Smuzhiyun {0x3013, 0x01},
302*4882a593Smuzhiyun {0x4170, 0x00},
303*4882a593Smuzhiyun {0x4171, 0x10},
304*4882a593Smuzhiyun {0x4176, 0x00},
305*4882a593Smuzhiyun {0x4177, 0x3C},
306*4882a593Smuzhiyun {0xAE20, 0x04},
307*4882a593Smuzhiyun {0xAE21, 0x5C},
308*4882a593Smuzhiyun {0x0100, 0x00},
309*4882a593Smuzhiyun {REG_NULL, 0x00},
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun static const struct regval imx214_4208x3120_15fps_regs_2lane[] = {
313*4882a593Smuzhiyun {0x0114, 0x01},
314*4882a593Smuzhiyun {0x0220, 0x00},
315*4882a593Smuzhiyun {0x0221, 0x11},
316*4882a593Smuzhiyun {0x0222, 0x01},
317*4882a593Smuzhiyun {0x0340, 0x0C},
318*4882a593Smuzhiyun {0x0341, 0x58},
319*4882a593Smuzhiyun {0x0342, 0x13},
320*4882a593Smuzhiyun {0x0343, 0x90},
321*4882a593Smuzhiyun {0x0344, 0x00},
322*4882a593Smuzhiyun {0x0345, 0x00},
323*4882a593Smuzhiyun {0x0346, 0x00},
324*4882a593Smuzhiyun {0x0347, 0x00},
325*4882a593Smuzhiyun {0x0348, 0x10},
326*4882a593Smuzhiyun {0x0349, 0x6F},
327*4882a593Smuzhiyun {0x034A, 0x0C},
328*4882a593Smuzhiyun {0x034B, 0x2F},
329*4882a593Smuzhiyun {0x0381, 0x01},
330*4882a593Smuzhiyun {0x0383, 0x01},
331*4882a593Smuzhiyun {0x0385, 0x01},
332*4882a593Smuzhiyun {0x0387, 0x01},
333*4882a593Smuzhiyun {0x0900, 0x00},
334*4882a593Smuzhiyun {0x0901, 0x00},
335*4882a593Smuzhiyun {0x0902, 0x00},
336*4882a593Smuzhiyun {0x3000, 0x35},
337*4882a593Smuzhiyun {0x3054, 0x01},
338*4882a593Smuzhiyun {0x305C, 0x11},
339*4882a593Smuzhiyun {0x0112, 0x0A},
340*4882a593Smuzhiyun {0x0113, 0x0A},
341*4882a593Smuzhiyun {0x034C, 0x10},
342*4882a593Smuzhiyun {0x034D, 0x70},
343*4882a593Smuzhiyun {0x034E, 0x0C},
344*4882a593Smuzhiyun {0x034F, 0x30},
345*4882a593Smuzhiyun {0x0401, 0x00},
346*4882a593Smuzhiyun {0x0404, 0x00},
347*4882a593Smuzhiyun {0x0405, 0x10},
348*4882a593Smuzhiyun {0x0408, 0x00},
349*4882a593Smuzhiyun {0x0409, 0x00},
350*4882a593Smuzhiyun {0x040A, 0x00},
351*4882a593Smuzhiyun {0x040B, 0x00},
352*4882a593Smuzhiyun {0x040C, 0x10},
353*4882a593Smuzhiyun {0x040D, 0x70},
354*4882a593Smuzhiyun {0x040E, 0x0C},
355*4882a593Smuzhiyun {0x040F, 0x30},
356*4882a593Smuzhiyun {0x0301, 0x05},
357*4882a593Smuzhiyun {0x0303, 0x04},
358*4882a593Smuzhiyun {0x0305, 0x03},
359*4882a593Smuzhiyun {0x0306, 0x00},
360*4882a593Smuzhiyun {0x0307, 0x96},
361*4882a593Smuzhiyun {0x0309, 0x0A},
362*4882a593Smuzhiyun {0x030B, 0x01},
363*4882a593Smuzhiyun {0x0310, 0x00},
364*4882a593Smuzhiyun {0x0820, 0x09},
365*4882a593Smuzhiyun {0x0821, 0x60},
366*4882a593Smuzhiyun {0x0822, 0x00},
367*4882a593Smuzhiyun {0x0823, 0x00},
368*4882a593Smuzhiyun {0x3A03, 0x08},
369*4882a593Smuzhiyun {0x3A04, 0x70},
370*4882a593Smuzhiyun {0x3A05, 0x02},
371*4882a593Smuzhiyun {0x0B06, 0x01},
372*4882a593Smuzhiyun {0x30A2, 0x00},
373*4882a593Smuzhiyun {0x30B4, 0x00},
374*4882a593Smuzhiyun {0x3A02, 0xFF},
375*4882a593Smuzhiyun {0x3011, 0x00},
376*4882a593Smuzhiyun {0x3013, 0x01},
377*4882a593Smuzhiyun {0x4170, 0x00},
378*4882a593Smuzhiyun {0x4171, 0x10},
379*4882a593Smuzhiyun {0x4176, 0x00},
380*4882a593Smuzhiyun {0x4177, 0x3C},
381*4882a593Smuzhiyun {0xAE20, 0x04},
382*4882a593Smuzhiyun {0xAE21, 0x5C},
383*4882a593Smuzhiyun {0x0100, 0x00},
384*4882a593Smuzhiyun {REG_NULL, 0x00},
385*4882a593Smuzhiyun };
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun static const struct regval imx214_2104x1560_30fps_regs_4lane[] = {
388*4882a593Smuzhiyun {0x0114, 0x03},
389*4882a593Smuzhiyun {0x0220, 0x00},
390*4882a593Smuzhiyun {0x0221, 0x11},
391*4882a593Smuzhiyun {0x0222, 0x01},
392*4882a593Smuzhiyun {0x0340, 0x08},
393*4882a593Smuzhiyun {0x0341, 0x3E},
394*4882a593Smuzhiyun {0x0342, 0x13},
395*4882a593Smuzhiyun {0x0343, 0x90},
396*4882a593Smuzhiyun {0x0344, 0x00},
397*4882a593Smuzhiyun {0x0345, 0x00},
398*4882a593Smuzhiyun {0x0346, 0x00},
399*4882a593Smuzhiyun {0x0347, 0x00},
400*4882a593Smuzhiyun {0x0348, 0x10},
401*4882a593Smuzhiyun {0x0349, 0x6F},
402*4882a593Smuzhiyun {0x034A, 0x0C},
403*4882a593Smuzhiyun {0x034B, 0x2F},
404*4882a593Smuzhiyun {0x0381, 0x01},
405*4882a593Smuzhiyun {0x0383, 0x01},
406*4882a593Smuzhiyun {0x0385, 0x01},
407*4882a593Smuzhiyun {0x0387, 0x01},
408*4882a593Smuzhiyun {0x0900, 0x01},
409*4882a593Smuzhiyun {0x0901, 0x22},
410*4882a593Smuzhiyun {0x0902, 0x02},
411*4882a593Smuzhiyun {0x3000, 0x35},
412*4882a593Smuzhiyun {0x3054, 0x01},
413*4882a593Smuzhiyun {0x305C, 0x11},
414*4882a593Smuzhiyun {0x0112, 0x0A},
415*4882a593Smuzhiyun {0x0113, 0x0A},
416*4882a593Smuzhiyun {0x034C, 0x08},
417*4882a593Smuzhiyun {0x034D, 0x38},
418*4882a593Smuzhiyun {0x034E, 0x06},
419*4882a593Smuzhiyun {0x034F, 0x18},
420*4882a593Smuzhiyun {0x0401, 0x00},
421*4882a593Smuzhiyun {0x0404, 0x00},
422*4882a593Smuzhiyun {0x0405, 0x10},
423*4882a593Smuzhiyun {0x0408, 0x00},
424*4882a593Smuzhiyun {0x0409, 0x00},
425*4882a593Smuzhiyun {0x040A, 0x00},
426*4882a593Smuzhiyun {0x040B, 0x00},
427*4882a593Smuzhiyun {0x040C, 0x08},
428*4882a593Smuzhiyun {0x040D, 0x38},
429*4882a593Smuzhiyun {0x040E, 0x06},
430*4882a593Smuzhiyun {0x040F, 0x18},
431*4882a593Smuzhiyun {0x0301, 0x05},
432*4882a593Smuzhiyun {0x0303, 0x02},
433*4882a593Smuzhiyun {0x0305, 0x03},
434*4882a593Smuzhiyun {0x0306, 0x00},
435*4882a593Smuzhiyun {0x0307, 0x64},
436*4882a593Smuzhiyun {0x0309, 0x0A},
437*4882a593Smuzhiyun {0x030B, 0x01},
438*4882a593Smuzhiyun {0x0310, 0x00},
439*4882a593Smuzhiyun {0x0820, 0x0C},
440*4882a593Smuzhiyun {0x0821, 0x80},
441*4882a593Smuzhiyun {0x0822, 0x00},
442*4882a593Smuzhiyun {0x0823, 0x00},
443*4882a593Smuzhiyun {0x3A03, 0x06},
444*4882a593Smuzhiyun {0x3A04, 0x68},
445*4882a593Smuzhiyun {0x3A05, 0x01},
446*4882a593Smuzhiyun {0x0B06, 0x01},
447*4882a593Smuzhiyun {0x30A2, 0x00},
448*4882a593Smuzhiyun {0x30B4, 0x00},
449*4882a593Smuzhiyun {0x3A02, 0xFF},
450*4882a593Smuzhiyun {0x3011, 0x00},
451*4882a593Smuzhiyun {0x3013, 0x00},
452*4882a593Smuzhiyun {0x0202, 0x08},
453*4882a593Smuzhiyun {0x0203, 0x34},
454*4882a593Smuzhiyun {0x0224, 0x01},
455*4882a593Smuzhiyun {0x0225, 0xF4},
456*4882a593Smuzhiyun {0x0204, 0x00},
457*4882a593Smuzhiyun {0x0205, 0x00},
458*4882a593Smuzhiyun {0x020E, 0x01},
459*4882a593Smuzhiyun {0x020F, 0x00},
460*4882a593Smuzhiyun {0x0210, 0x01},
461*4882a593Smuzhiyun {0x0211, 0x00},
462*4882a593Smuzhiyun {0x0212, 0x01},
463*4882a593Smuzhiyun {0x0213, 0x00},
464*4882a593Smuzhiyun {0x0214, 0x01},
465*4882a593Smuzhiyun {0x0215, 0x00},
466*4882a593Smuzhiyun {0x0216, 0x00},
467*4882a593Smuzhiyun {0x0217, 0x00},
468*4882a593Smuzhiyun {0x4170, 0x00},
469*4882a593Smuzhiyun {0x4171, 0x10},
470*4882a593Smuzhiyun {0x4176, 0x00},
471*4882a593Smuzhiyun {0x4177, 0x3C},
472*4882a593Smuzhiyun {0xAE20, 0x04},
473*4882a593Smuzhiyun {0xAE21, 0x5C},
474*4882a593Smuzhiyun {0x0138, 0x01},
475*4882a593Smuzhiyun {0x0100, 0x00},
476*4882a593Smuzhiyun {REG_NULL, 0x00},
477*4882a593Smuzhiyun };
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun static const struct regval imx214_4208x3120_30fps_regs_4lane[] = {
480*4882a593Smuzhiyun {0x0114, 0x03},
481*4882a593Smuzhiyun {0x0220, 0x00},
482*4882a593Smuzhiyun {0x0221, 0x11},
483*4882a593Smuzhiyun {0x0222, 0x01},
484*4882a593Smuzhiyun {0x0340, 0x0C},
485*4882a593Smuzhiyun {0x0341, 0x58},
486*4882a593Smuzhiyun {0x0342, 0x13},
487*4882a593Smuzhiyun {0x0343, 0x90},
488*4882a593Smuzhiyun {0x0344, 0x00},
489*4882a593Smuzhiyun {0x0345, 0x00},
490*4882a593Smuzhiyun {0x0346, 0x00},
491*4882a593Smuzhiyun {0x0347, 0x00},
492*4882a593Smuzhiyun {0x0348, 0x10},
493*4882a593Smuzhiyun {0x0349, 0x6F},
494*4882a593Smuzhiyun {0x034A, 0x0C},
495*4882a593Smuzhiyun {0x034B, 0x2F},
496*4882a593Smuzhiyun {0x0381, 0x01},
497*4882a593Smuzhiyun {0x0383, 0x01},
498*4882a593Smuzhiyun {0x0385, 0x01},
499*4882a593Smuzhiyun {0x0387, 0x01},
500*4882a593Smuzhiyun {0x0900, 0x00},
501*4882a593Smuzhiyun {0x0901, 0x00},
502*4882a593Smuzhiyun {0x0902, 0x00},
503*4882a593Smuzhiyun {0x3000, 0x35},
504*4882a593Smuzhiyun {0x3054, 0x01},
505*4882a593Smuzhiyun {0x305C, 0x11},
506*4882a593Smuzhiyun {0x0112, 0x0A},
507*4882a593Smuzhiyun {0x0113, 0x0A},
508*4882a593Smuzhiyun {0x034C, 0x10},
509*4882a593Smuzhiyun {0x034D, 0x70},
510*4882a593Smuzhiyun {0x034E, 0x0C},
511*4882a593Smuzhiyun {0x034F, 0x30},
512*4882a593Smuzhiyun {0x0401, 0x00},
513*4882a593Smuzhiyun {0x0404, 0x00},
514*4882a593Smuzhiyun {0x0405, 0x10},
515*4882a593Smuzhiyun {0x0408, 0x00},
516*4882a593Smuzhiyun {0x0409, 0x00},
517*4882a593Smuzhiyun {0x040A, 0x00},
518*4882a593Smuzhiyun {0x040B, 0x00},
519*4882a593Smuzhiyun {0x040C, 0x10},
520*4882a593Smuzhiyun {0x040D, 0x70},
521*4882a593Smuzhiyun {0x040E, 0x0C},
522*4882a593Smuzhiyun {0x040F, 0x30},
523*4882a593Smuzhiyun {0x0301, 0x05},
524*4882a593Smuzhiyun {0x0303, 0x02},
525*4882a593Smuzhiyun {0x0305, 0x03},
526*4882a593Smuzhiyun {0x0306, 0x00},
527*4882a593Smuzhiyun {0x0307, 0x96},
528*4882a593Smuzhiyun {0x0309, 0x0A},
529*4882a593Smuzhiyun {0x030B, 0x01},
530*4882a593Smuzhiyun {0x0310, 0x00},
531*4882a593Smuzhiyun {0x0820, 0x12},
532*4882a593Smuzhiyun {0x0821, 0xC0},
533*4882a593Smuzhiyun {0x0822, 0x00},
534*4882a593Smuzhiyun {0x0823, 0x00},
535*4882a593Smuzhiyun {0x3A03, 0x09},
536*4882a593Smuzhiyun {0x3A04, 0x20},
537*4882a593Smuzhiyun {0x3A05, 0x01},
538*4882a593Smuzhiyun {0x0B06, 0x01},
539*4882a593Smuzhiyun {0x30A2, 0x00},
540*4882a593Smuzhiyun {0x30B4, 0x00},
541*4882a593Smuzhiyun {0x3A02, 0xFF},
542*4882a593Smuzhiyun {0x3011, 0x00},
543*4882a593Smuzhiyun {0x3013, 0x01},
544*4882a593Smuzhiyun {0x0202, 0x0C},
545*4882a593Smuzhiyun {0x0203, 0x4E},
546*4882a593Smuzhiyun {0x0224, 0x01},
547*4882a593Smuzhiyun {0x0225, 0xF4},
548*4882a593Smuzhiyun {0x0204, 0x00},
549*4882a593Smuzhiyun {0x0205, 0x00},
550*4882a593Smuzhiyun {0x020E, 0x01},
551*4882a593Smuzhiyun {0x020F, 0x00},
552*4882a593Smuzhiyun {0x0210, 0x01},
553*4882a593Smuzhiyun {0x0211, 0x00},
554*4882a593Smuzhiyun {0x0212, 0x01},
555*4882a593Smuzhiyun {0x0213, 0x00},
556*4882a593Smuzhiyun {0x0214, 0x01},
557*4882a593Smuzhiyun {0x0215, 0x00},
558*4882a593Smuzhiyun {0x0216, 0x00},
559*4882a593Smuzhiyun {0x0217, 0x00},
560*4882a593Smuzhiyun {0x4170, 0x00},
561*4882a593Smuzhiyun {0x4171, 0x10},
562*4882a593Smuzhiyun {0x4176, 0x00},
563*4882a593Smuzhiyun {0x4177, 0x3C},
564*4882a593Smuzhiyun {0xAE20, 0x04},
565*4882a593Smuzhiyun {0xAE21, 0x5C},
566*4882a593Smuzhiyun {0x0100, 0x00},
567*4882a593Smuzhiyun {REG_NULL, 0x00},
568*4882a593Smuzhiyun };
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun static const struct imx214_mode supported_modes_2lane[] = {
571*4882a593Smuzhiyun {
572*4882a593Smuzhiyun .width = 4208,
573*4882a593Smuzhiyun .height = 3120,
574*4882a593Smuzhiyun .max_fps = {
575*4882a593Smuzhiyun .numerator = 10000,
576*4882a593Smuzhiyun .denominator = 150000,
577*4882a593Smuzhiyun },
578*4882a593Smuzhiyun .exp_def = 0x0c70,
579*4882a593Smuzhiyun .hts_def = 0x1390,
580*4882a593Smuzhiyun .vts_def = 0x0c7a,
581*4882a593Smuzhiyun .bpp = 10,
582*4882a593Smuzhiyun .reg_list = imx214_4208x3120_15fps_regs_2lane,
583*4882a593Smuzhiyun .link_freq_idx = 0,
584*4882a593Smuzhiyun },
585*4882a593Smuzhiyun {
586*4882a593Smuzhiyun .width = 2104,
587*4882a593Smuzhiyun .height = 1560,
588*4882a593Smuzhiyun .max_fps = {
589*4882a593Smuzhiyun .numerator = 10000,
590*4882a593Smuzhiyun .denominator = 300000,
591*4882a593Smuzhiyun },
592*4882a593Smuzhiyun .exp_def = 0x0630,
593*4882a593Smuzhiyun .hts_def = 0x1390,
594*4882a593Smuzhiyun .vts_def = 0x0640,
595*4882a593Smuzhiyun .bpp = 10,
596*4882a593Smuzhiyun .reg_list = imx214_2104x1560_30fps_regs_2lane,
597*4882a593Smuzhiyun .link_freq_idx = 0,
598*4882a593Smuzhiyun },
599*4882a593Smuzhiyun };
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun static const struct imx214_mode supported_modes_4lane[] = {
602*4882a593Smuzhiyun {
603*4882a593Smuzhiyun .width = 4208,
604*4882a593Smuzhiyun .height = 3120,
605*4882a593Smuzhiyun .max_fps = {
606*4882a593Smuzhiyun .numerator = 10000,
607*4882a593Smuzhiyun .denominator = 300000,
608*4882a593Smuzhiyun },
609*4882a593Smuzhiyun .exp_def = 0x0c50,
610*4882a593Smuzhiyun .hts_def = 0x1390,
611*4882a593Smuzhiyun .vts_def = 0x0c58,
612*4882a593Smuzhiyun .bpp = 10,
613*4882a593Smuzhiyun .reg_list = imx214_4208x3120_30fps_regs_4lane,
614*4882a593Smuzhiyun .link_freq_idx = 0,
615*4882a593Smuzhiyun },
616*4882a593Smuzhiyun {
617*4882a593Smuzhiyun .width = 2104,
618*4882a593Smuzhiyun .height = 1560,
619*4882a593Smuzhiyun .max_fps = {
620*4882a593Smuzhiyun .numerator = 10000,
621*4882a593Smuzhiyun .denominator = 300000,
622*4882a593Smuzhiyun },
623*4882a593Smuzhiyun .exp_def = 0x083a,
624*4882a593Smuzhiyun .hts_def = 0x1390,
625*4882a593Smuzhiyun .vts_def = 0x083E,
626*4882a593Smuzhiyun .bpp = 10,
627*4882a593Smuzhiyun .reg_list = imx214_2104x1560_30fps_regs_4lane,
628*4882a593Smuzhiyun .link_freq_idx = 0,
629*4882a593Smuzhiyun },
630*4882a593Smuzhiyun };
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun static const s64 link_freq_items[] = {
633*4882a593Smuzhiyun IMX214_LINK_FREQ_600MHZ,
634*4882a593Smuzhiyun };
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun static const char * const imx214_test_pattern_menu[] = {
637*4882a593Smuzhiyun "Disabled",
638*4882a593Smuzhiyun "Vertical Color Bar Type 1",
639*4882a593Smuzhiyun "Vertical Color Bar Type 2",
640*4882a593Smuzhiyun "Vertical Color Bar Type 3",
641*4882a593Smuzhiyun "Vertical Color Bar Type 4"
642*4882a593Smuzhiyun };
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun /* Write registers up to 4 at a time */
imx214_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)645*4882a593Smuzhiyun static int imx214_write_reg(struct i2c_client *client, u16 reg,
646*4882a593Smuzhiyun u32 len, u32 val)
647*4882a593Smuzhiyun {
648*4882a593Smuzhiyun u32 buf_i, val_i;
649*4882a593Smuzhiyun u8 buf[6];
650*4882a593Smuzhiyun u8 *val_p;
651*4882a593Smuzhiyun __be32 val_be;
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun if (len > 4)
656*4882a593Smuzhiyun return -EINVAL;
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun buf[0] = reg >> 8;
659*4882a593Smuzhiyun buf[1] = reg & 0xff;
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun val_be = cpu_to_be32(val);
662*4882a593Smuzhiyun val_p = (u8 *)&val_be;
663*4882a593Smuzhiyun buf_i = 2;
664*4882a593Smuzhiyun val_i = 4 - len;
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun while (val_i < 4)
667*4882a593Smuzhiyun buf[buf_i++] = val_p[val_i++];
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun if (i2c_master_send(client, buf, len + 2) != len + 2)
670*4882a593Smuzhiyun return -EIO;
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun return 0;
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun
imx214_write_array(struct i2c_client * client,const struct regval * regs)675*4882a593Smuzhiyun static int imx214_write_array(struct i2c_client *client,
676*4882a593Smuzhiyun const struct regval *regs)
677*4882a593Smuzhiyun {
678*4882a593Smuzhiyun u32 i;
679*4882a593Smuzhiyun int ret = 0;
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
682*4882a593Smuzhiyun ret = imx214_write_reg(client, regs[i].addr,
683*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT,
684*4882a593Smuzhiyun regs[i].val);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun return ret;
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun /* Read registers up to 4 at a time */
imx214_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)690*4882a593Smuzhiyun static int imx214_read_reg(struct i2c_client *client, u16 reg,
691*4882a593Smuzhiyun unsigned int len, u32 *val)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun struct i2c_msg msgs[2];
694*4882a593Smuzhiyun u8 *data_be_p;
695*4882a593Smuzhiyun __be32 data_be = 0;
696*4882a593Smuzhiyun __be16 reg_addr_be = cpu_to_be16(reg);
697*4882a593Smuzhiyun int ret;
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun if (len > 4 || !len)
700*4882a593Smuzhiyun return -EINVAL;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun data_be_p = (u8 *)&data_be;
703*4882a593Smuzhiyun /* Write register address */
704*4882a593Smuzhiyun msgs[0].addr = client->addr;
705*4882a593Smuzhiyun msgs[0].flags = 0;
706*4882a593Smuzhiyun msgs[0].len = 2;
707*4882a593Smuzhiyun msgs[0].buf = (u8 *)®_addr_be;
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun /* Read data from register */
710*4882a593Smuzhiyun msgs[1].addr = client->addr;
711*4882a593Smuzhiyun msgs[1].flags = I2C_M_RD;
712*4882a593Smuzhiyun msgs[1].len = len;
713*4882a593Smuzhiyun msgs[1].buf = &data_be_p[4 - len];
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
716*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs))
717*4882a593Smuzhiyun return -EIO;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun *val = be32_to_cpu(data_be);
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun return 0;
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun
imx214_get_reso_dist(const struct imx214_mode * mode,struct v4l2_mbus_framefmt * framefmt)724*4882a593Smuzhiyun static int imx214_get_reso_dist(const struct imx214_mode *mode,
725*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt)
726*4882a593Smuzhiyun {
727*4882a593Smuzhiyun return abs(mode->width - framefmt->width) +
728*4882a593Smuzhiyun abs(mode->height - framefmt->height);
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun static const struct imx214_mode *
imx214_find_best_fit(struct imx214 * imx214,struct v4l2_subdev_format * fmt)732*4882a593Smuzhiyun imx214_find_best_fit(struct imx214 *imx214, struct v4l2_subdev_format *fmt)
733*4882a593Smuzhiyun {
734*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt = &fmt->format;
735*4882a593Smuzhiyun int dist;
736*4882a593Smuzhiyun int cur_best_fit = 0;
737*4882a593Smuzhiyun int cur_best_fit_dist = -1;
738*4882a593Smuzhiyun unsigned int i;
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun for (i = 0; i < imx214->cfg_num; i++) {
741*4882a593Smuzhiyun dist = imx214_get_reso_dist(&imx214->support_modes[i], framefmt);
742*4882a593Smuzhiyun if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
743*4882a593Smuzhiyun cur_best_fit_dist = dist;
744*4882a593Smuzhiyun cur_best_fit = i;
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun return &imx214->support_modes[cur_best_fit];
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun
imx214_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)751*4882a593Smuzhiyun static int imx214_set_fmt(struct v4l2_subdev *sd,
752*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
753*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
754*4882a593Smuzhiyun {
755*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
756*4882a593Smuzhiyun const struct imx214_mode *mode;
757*4882a593Smuzhiyun s64 h_blank, vblank_def;
758*4882a593Smuzhiyun u64 pixel_rate = 0;
759*4882a593Smuzhiyun u32 lane_num = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun mutex_lock(&imx214->mutex);
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun mode = imx214_find_best_fit(imx214, fmt);
764*4882a593Smuzhiyun fmt->format.code = IMX214_MEDIA_BUS_FMT;
765*4882a593Smuzhiyun fmt->format.width = mode->width;
766*4882a593Smuzhiyun fmt->format.height = mode->height;
767*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
768*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
769*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
770*4882a593Smuzhiyun *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
771*4882a593Smuzhiyun #else
772*4882a593Smuzhiyun mutex_unlock(&imx214->mutex);
773*4882a593Smuzhiyun return -ENOTTY;
774*4882a593Smuzhiyun #endif
775*4882a593Smuzhiyun } else {
776*4882a593Smuzhiyun imx214->cur_mode = mode;
777*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
778*4882a593Smuzhiyun __v4l2_ctrl_modify_range(imx214->hblank, h_blank,
779*4882a593Smuzhiyun h_blank, 1, h_blank);
780*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
781*4882a593Smuzhiyun __v4l2_ctrl_modify_range(imx214->vblank, vblank_def,
782*4882a593Smuzhiyun IMX214_VTS_MAX - mode->height,
783*4882a593Smuzhiyun 1, vblank_def);
784*4882a593Smuzhiyun pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl_int64(imx214->pixel_rate,
787*4882a593Smuzhiyun pixel_rate);
788*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(imx214->link_freq,
789*4882a593Smuzhiyun mode->link_freq_idx);
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun mutex_unlock(&imx214->mutex);
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun return 0;
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun
imx214_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)797*4882a593Smuzhiyun static int imx214_get_fmt(struct v4l2_subdev *sd,
798*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
799*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
800*4882a593Smuzhiyun {
801*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
802*4882a593Smuzhiyun const struct imx214_mode *mode = imx214->cur_mode;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun mutex_lock(&imx214->mutex);
805*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
806*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
807*4882a593Smuzhiyun fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
808*4882a593Smuzhiyun #else
809*4882a593Smuzhiyun mutex_unlock(&imx214->mutex);
810*4882a593Smuzhiyun return -ENOTTY;
811*4882a593Smuzhiyun #endif
812*4882a593Smuzhiyun } else {
813*4882a593Smuzhiyun fmt->format.width = mode->width;
814*4882a593Smuzhiyun fmt->format.height = mode->height;
815*4882a593Smuzhiyun fmt->format.code = IMX214_MEDIA_BUS_FMT;
816*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
817*4882a593Smuzhiyun }
818*4882a593Smuzhiyun mutex_unlock(&imx214->mutex);
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun return 0;
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun
imx214_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)823*4882a593Smuzhiyun static int imx214_enum_mbus_code(struct v4l2_subdev *sd,
824*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
825*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun if (code->index != 0)
828*4882a593Smuzhiyun return -EINVAL;
829*4882a593Smuzhiyun code->code = IMX214_MEDIA_BUS_FMT;
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun return 0;
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun
imx214_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)834*4882a593Smuzhiyun static int imx214_enum_frame_sizes(struct v4l2_subdev *sd,
835*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
836*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun if (fse->index >= imx214->cfg_num)
841*4882a593Smuzhiyun return -EINVAL;
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun if (fse->code != IMX214_MEDIA_BUS_FMT)
844*4882a593Smuzhiyun return -EINVAL;
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun fse->min_width = imx214->support_modes[fse->index].width;
847*4882a593Smuzhiyun fse->max_width = imx214->support_modes[fse->index].width;
848*4882a593Smuzhiyun fse->max_height = imx214->support_modes[fse->index].height;
849*4882a593Smuzhiyun fse->min_height = imx214->support_modes[fse->index].height;
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun return 0;
852*4882a593Smuzhiyun }
853*4882a593Smuzhiyun
imx214_enable_test_pattern(struct imx214 * imx214,u32 pattern)854*4882a593Smuzhiyun static int imx214_enable_test_pattern(struct imx214 *imx214, u32 pattern)
855*4882a593Smuzhiyun {
856*4882a593Smuzhiyun u32 val;
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun if (pattern)
859*4882a593Smuzhiyun val = (pattern - 1) | IMX214_TEST_PATTERN_ENABLE;
860*4882a593Smuzhiyun else
861*4882a593Smuzhiyun val = IMX214_TEST_PATTERN_DISABLE;
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun return imx214_write_reg(imx214->client,
864*4882a593Smuzhiyun IMX214_REG_TEST_PATTERN,
865*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT,
866*4882a593Smuzhiyun val);
867*4882a593Smuzhiyun }
868*4882a593Smuzhiyun
imx214_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)869*4882a593Smuzhiyun static int imx214_g_frame_interval(struct v4l2_subdev *sd,
870*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *fi)
871*4882a593Smuzhiyun {
872*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
873*4882a593Smuzhiyun const struct imx214_mode *mode = imx214->cur_mode;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun fi->interval = mode->max_fps;
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun return 0;
878*4882a593Smuzhiyun }
879*4882a593Smuzhiyun
imx214_get_otp(struct imx214_otp_info * otp,struct rkmodule_inf * inf)880*4882a593Smuzhiyun static void imx214_get_otp(struct imx214_otp_info *otp,
881*4882a593Smuzhiyun struct rkmodule_inf *inf)
882*4882a593Smuzhiyun {
883*4882a593Smuzhiyun u32 i;
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun /* fac */
886*4882a593Smuzhiyun if (otp->flag & 0x80) {
887*4882a593Smuzhiyun inf->fac.flag = 1;
888*4882a593Smuzhiyun inf->fac.year = otp->year;
889*4882a593Smuzhiyun inf->fac.month = otp->month;
890*4882a593Smuzhiyun inf->fac.day = otp->day;
891*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(imx214_module_info) - 1; i++) {
892*4882a593Smuzhiyun if (imx214_module_info[i].id == otp->module_id)
893*4882a593Smuzhiyun break;
894*4882a593Smuzhiyun }
895*4882a593Smuzhiyun strscpy(inf->fac.module, imx214_module_info[i].name,
896*4882a593Smuzhiyun sizeof(inf->fac.module));
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(imx214_lens_info) - 1; i++) {
899*4882a593Smuzhiyun if (imx214_lens_info[i].id == otp->lens_id)
900*4882a593Smuzhiyun break;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun strscpy(inf->fac.lens, imx214_lens_info[i].name,
903*4882a593Smuzhiyun sizeof(inf->fac.lens));
904*4882a593Smuzhiyun }
905*4882a593Smuzhiyun /* awb */
906*4882a593Smuzhiyun if (otp->flag & 0x40) {
907*4882a593Smuzhiyun inf->awb.flag = 1;
908*4882a593Smuzhiyun inf->awb.r_value = otp->rg_ratio;
909*4882a593Smuzhiyun inf->awb.b_value = otp->bg_ratio;
910*4882a593Smuzhiyun inf->awb.gr_value = 0x400;
911*4882a593Smuzhiyun inf->awb.gb_value = 0x400;
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun inf->awb.golden_r_value = 0;
914*4882a593Smuzhiyun inf->awb.golden_b_value = 0;
915*4882a593Smuzhiyun inf->awb.golden_gr_value = 0;
916*4882a593Smuzhiyun inf->awb.golden_gb_value = 0;
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun /* af */
919*4882a593Smuzhiyun if (otp->flag & 0x20) {
920*4882a593Smuzhiyun inf->af.flag = 1;
921*4882a593Smuzhiyun inf->af.af_otp[0].vcm_start = otp->vcm_start;
922*4882a593Smuzhiyun inf->af.af_otp[0].vcm_end = otp->vcm_end;
923*4882a593Smuzhiyun inf->af.af_otp[0].vcm_dir = otp->vcm_dir;
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun /* lsc */
926*4882a593Smuzhiyun if (otp->flag & 0x10) {
927*4882a593Smuzhiyun inf->lsc.flag = 1;
928*4882a593Smuzhiyun inf->lsc.decimal_bits = 0;
929*4882a593Smuzhiyun inf->lsc.lsc_w = 9;
930*4882a593Smuzhiyun inf->lsc.lsc_h = 14;
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun for (i = 0; i < 126; i++) {
933*4882a593Smuzhiyun inf->lsc.lsc_r[i] = otp->lenc[i];
934*4882a593Smuzhiyun inf->lsc.lsc_gr[i] = otp->lenc[i + 126];
935*4882a593Smuzhiyun inf->lsc.lsc_gb[i] = otp->lenc[i + 252];
936*4882a593Smuzhiyun inf->lsc.lsc_b[i] = otp->lenc[i + 378];
937*4882a593Smuzhiyun }
938*4882a593Smuzhiyun }
939*4882a593Smuzhiyun }
940*4882a593Smuzhiyun
imx214_get_module_inf(struct imx214 * imx214,struct rkmodule_inf * inf)941*4882a593Smuzhiyun static void imx214_get_module_inf(struct imx214 *imx214,
942*4882a593Smuzhiyun struct rkmodule_inf *inf)
943*4882a593Smuzhiyun {
944*4882a593Smuzhiyun struct imx214_otp_info *otp = imx214->otp;
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
947*4882a593Smuzhiyun strscpy(inf->base.sensor, IMX214_NAME, sizeof(inf->base.sensor));
948*4882a593Smuzhiyun strscpy(inf->base.module, imx214->module_name,
949*4882a593Smuzhiyun sizeof(inf->base.module));
950*4882a593Smuzhiyun strscpy(inf->base.lens, imx214->len_name, sizeof(inf->base.lens));
951*4882a593Smuzhiyun if (otp)
952*4882a593Smuzhiyun imx214_get_otp(otp, inf);
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun
imx214_set_awb_cfg(struct imx214 * imx214,struct rkmodule_awb_cfg * cfg)955*4882a593Smuzhiyun static void imx214_set_awb_cfg(struct imx214 *imx214,
956*4882a593Smuzhiyun struct rkmodule_awb_cfg *cfg)
957*4882a593Smuzhiyun {
958*4882a593Smuzhiyun mutex_lock(&imx214->mutex);
959*4882a593Smuzhiyun memcpy(&imx214->awb_cfg, cfg, sizeof(*cfg));
960*4882a593Smuzhiyun mutex_unlock(&imx214->mutex);
961*4882a593Smuzhiyun }
962*4882a593Smuzhiyun
imx214_set_lsc_cfg(struct imx214 * imx214,struct rkmodule_lsc_cfg * cfg)963*4882a593Smuzhiyun static void imx214_set_lsc_cfg(struct imx214 *imx214,
964*4882a593Smuzhiyun struct rkmodule_lsc_cfg *cfg)
965*4882a593Smuzhiyun {
966*4882a593Smuzhiyun mutex_lock(&imx214->mutex);
967*4882a593Smuzhiyun memcpy(&imx214->lsc_cfg, cfg, sizeof(*cfg));
968*4882a593Smuzhiyun mutex_unlock(&imx214->mutex);
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun
imx214_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)971*4882a593Smuzhiyun static long imx214_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
974*4882a593Smuzhiyun long ret = 0;
975*4882a593Smuzhiyun u32 stream = 0;
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun switch (cmd) {
978*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
979*4882a593Smuzhiyun imx214_get_module_inf(imx214, (struct rkmodule_inf *)arg);
980*4882a593Smuzhiyun break;
981*4882a593Smuzhiyun case RKMODULE_AWB_CFG:
982*4882a593Smuzhiyun imx214_set_awb_cfg(imx214, (struct rkmodule_awb_cfg *)arg);
983*4882a593Smuzhiyun break;
984*4882a593Smuzhiyun case RKMODULE_LSC_CFG:
985*4882a593Smuzhiyun imx214_set_lsc_cfg(imx214, (struct rkmodule_lsc_cfg *)arg);
986*4882a593Smuzhiyun break;
987*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun stream = *((u32 *)arg);
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun if (stream)
992*4882a593Smuzhiyun ret = imx214_write_reg(imx214->client,
993*4882a593Smuzhiyun IMX214_REG_CTRL_MODE,
994*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT,
995*4882a593Smuzhiyun IMX214_MODE_STREAMING);
996*4882a593Smuzhiyun else
997*4882a593Smuzhiyun ret = imx214_write_reg(imx214->client,
998*4882a593Smuzhiyun IMX214_REG_CTRL_MODE,
999*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT,
1000*4882a593Smuzhiyun IMX214_MODE_SW_STANDBY);
1001*4882a593Smuzhiyun break;
1002*4882a593Smuzhiyun default:
1003*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
1004*4882a593Smuzhiyun break;
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun return ret;
1008*4882a593Smuzhiyun }
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
imx214_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1011*4882a593Smuzhiyun static long imx214_compat_ioctl32(struct v4l2_subdev *sd,
1012*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
1013*4882a593Smuzhiyun {
1014*4882a593Smuzhiyun void __user *up = compat_ptr(arg);
1015*4882a593Smuzhiyun struct rkmodule_inf *inf;
1016*4882a593Smuzhiyun struct rkmodule_awb_cfg *cfg;
1017*4882a593Smuzhiyun struct rkmodule_lsc_cfg *lsc_cfg;
1018*4882a593Smuzhiyun long ret = 0;
1019*4882a593Smuzhiyun u32 stream = 0;
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun switch (cmd) {
1022*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
1023*4882a593Smuzhiyun inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1024*4882a593Smuzhiyun if (!inf) {
1025*4882a593Smuzhiyun ret = -ENOMEM;
1026*4882a593Smuzhiyun return ret;
1027*4882a593Smuzhiyun }
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun ret = imx214_ioctl(sd, cmd, inf);
1030*4882a593Smuzhiyun if (!ret) {
1031*4882a593Smuzhiyun ret = copy_to_user(up, inf, sizeof(*inf));
1032*4882a593Smuzhiyun if (ret)
1033*4882a593Smuzhiyun ret = -EFAULT;
1034*4882a593Smuzhiyun }
1035*4882a593Smuzhiyun kfree(inf);
1036*4882a593Smuzhiyun break;
1037*4882a593Smuzhiyun case RKMODULE_AWB_CFG:
1038*4882a593Smuzhiyun cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1039*4882a593Smuzhiyun if (!cfg) {
1040*4882a593Smuzhiyun ret = -ENOMEM;
1041*4882a593Smuzhiyun return ret;
1042*4882a593Smuzhiyun }
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun ret = copy_from_user(cfg, up, sizeof(*cfg));
1045*4882a593Smuzhiyun if (!ret)
1046*4882a593Smuzhiyun ret = imx214_ioctl(sd, cmd, cfg);
1047*4882a593Smuzhiyun else
1048*4882a593Smuzhiyun ret = -EFAULT;
1049*4882a593Smuzhiyun kfree(cfg);
1050*4882a593Smuzhiyun break;
1051*4882a593Smuzhiyun case RKMODULE_LSC_CFG:
1052*4882a593Smuzhiyun lsc_cfg = kzalloc(sizeof(*lsc_cfg), GFP_KERNEL);
1053*4882a593Smuzhiyun if (!lsc_cfg) {
1054*4882a593Smuzhiyun ret = -ENOMEM;
1055*4882a593Smuzhiyun return ret;
1056*4882a593Smuzhiyun }
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun ret = copy_from_user(lsc_cfg, up, sizeof(*lsc_cfg));
1059*4882a593Smuzhiyun if (!ret)
1060*4882a593Smuzhiyun ret = imx214_ioctl(sd, cmd, lsc_cfg);
1061*4882a593Smuzhiyun else
1062*4882a593Smuzhiyun ret = -EFAULT;
1063*4882a593Smuzhiyun kfree(lsc_cfg);
1064*4882a593Smuzhiyun break;
1065*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
1066*4882a593Smuzhiyun ret = copy_from_user(&stream, up, sizeof(u32));
1067*4882a593Smuzhiyun if (!ret)
1068*4882a593Smuzhiyun ret = imx214_ioctl(sd, cmd, &stream);
1069*4882a593Smuzhiyun else
1070*4882a593Smuzhiyun ret = -EFAULT;
1071*4882a593Smuzhiyun break;
1072*4882a593Smuzhiyun default:
1073*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
1074*4882a593Smuzhiyun break;
1075*4882a593Smuzhiyun }
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun return ret;
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun #endif
1080*4882a593Smuzhiyun
imx214_apply_otp(struct imx214 * imx214)1081*4882a593Smuzhiyun static int imx214_apply_otp(struct imx214 *imx214)
1082*4882a593Smuzhiyun {
1083*4882a593Smuzhiyun int R_gain, G_gain, B_gain, base_gain;
1084*4882a593Smuzhiyun struct i2c_client *client = imx214->client;
1085*4882a593Smuzhiyun struct imx214_otp_info *otp_ptr = imx214->otp;
1086*4882a593Smuzhiyun struct rkmodule_awb_cfg *awb_cfg = &imx214->awb_cfg;
1087*4882a593Smuzhiyun struct rkmodule_lsc_cfg *lsc_cfg = &imx214->lsc_cfg;
1088*4882a593Smuzhiyun u32 golden_bg_ratio = 0;
1089*4882a593Smuzhiyun u32 golden_rg_ratio = 0;
1090*4882a593Smuzhiyun u32 golden_g_value = 0;
1091*4882a593Smuzhiyun u32 bg_ratio;
1092*4882a593Smuzhiyun u32 rg_ratio;
1093*4882a593Smuzhiyun //u32 g_value;
1094*4882a593Smuzhiyun u32 i;
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun if (!otp_ptr)
1097*4882a593Smuzhiyun return 0;
1098*4882a593Smuzhiyun if (awb_cfg->enable) {
1099*4882a593Smuzhiyun golden_g_value = (awb_cfg->golden_gb_value +
1100*4882a593Smuzhiyun awb_cfg->golden_gr_value) / 2;
1101*4882a593Smuzhiyun if (golden_g_value != 0) {
1102*4882a593Smuzhiyun golden_rg_ratio = awb_cfg->golden_r_value * 0x400
1103*4882a593Smuzhiyun / golden_g_value;
1104*4882a593Smuzhiyun golden_bg_ratio = awb_cfg->golden_b_value * 0x400
1105*4882a593Smuzhiyun / golden_g_value;
1106*4882a593Smuzhiyun } else {
1107*4882a593Smuzhiyun golden_rg_ratio = RG_Ratio_Typical_Default;
1108*4882a593Smuzhiyun golden_bg_ratio = BG_Ratio_Typical_Default;
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun }
1111*4882a593Smuzhiyun /* apply OTP WB Calibration */
1112*4882a593Smuzhiyun if ((otp_ptr->flag & 0x40) && golden_bg_ratio && golden_rg_ratio) {
1113*4882a593Smuzhiyun rg_ratio = otp_ptr->rg_ratio;
1114*4882a593Smuzhiyun bg_ratio = otp_ptr->bg_ratio;
1115*4882a593Smuzhiyun dev_dbg(&client->dev, "rg:0x%x,bg:0x%x,gol rg:0x%x,bg:0x%x\n",
1116*4882a593Smuzhiyun rg_ratio, bg_ratio, golden_rg_ratio, golden_bg_ratio);
1117*4882a593Smuzhiyun /* calculate G gain */
1118*4882a593Smuzhiyun R_gain = golden_rg_ratio * 1000 / rg_ratio;
1119*4882a593Smuzhiyun B_gain = golden_bg_ratio * 1000 / bg_ratio;
1120*4882a593Smuzhiyun G_gain = 1000;
1121*4882a593Smuzhiyun if (R_gain < 1000 || B_gain < 1000) {
1122*4882a593Smuzhiyun if (R_gain < B_gain)
1123*4882a593Smuzhiyun base_gain = R_gain;
1124*4882a593Smuzhiyun else
1125*4882a593Smuzhiyun base_gain = B_gain;
1126*4882a593Smuzhiyun } else {
1127*4882a593Smuzhiyun base_gain = G_gain;
1128*4882a593Smuzhiyun }
1129*4882a593Smuzhiyun R_gain = 0x100 * R_gain / (base_gain);
1130*4882a593Smuzhiyun B_gain = 0x100 * B_gain / (base_gain);
1131*4882a593Smuzhiyun G_gain = 0x100 * G_gain / (base_gain);
1132*4882a593Smuzhiyun /* update sensor WB gain */
1133*4882a593Smuzhiyun if (R_gain > 0x100) {
1134*4882a593Smuzhiyun imx214_write_reg(client, 0x0210,
1135*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, R_gain >> 8);
1136*4882a593Smuzhiyun imx214_write_reg(client, 0x0211,
1137*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, R_gain & 0x00ff);
1138*4882a593Smuzhiyun }
1139*4882a593Smuzhiyun if (G_gain > 0x100) {
1140*4882a593Smuzhiyun imx214_write_reg(client, 0x020e,
1141*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, G_gain >> 8);
1142*4882a593Smuzhiyun imx214_write_reg(client, 0x020f,
1143*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, G_gain & 0x00ff);
1144*4882a593Smuzhiyun imx214_write_reg(client, 0x0214,
1145*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, G_gain >> 8);
1146*4882a593Smuzhiyun imx214_write_reg(client, 0x0215,
1147*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, G_gain & 0x00ff);
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun if (B_gain > 0x100) {
1150*4882a593Smuzhiyun imx214_write_reg(client, 0x0212,
1151*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, B_gain >> 8);
1152*4882a593Smuzhiyun imx214_write_reg(client, 0x0213,
1153*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, B_gain & 0x00ff);
1154*4882a593Smuzhiyun }
1155*4882a593Smuzhiyun dev_dbg(&client->dev, "apply awb gain: 0x%x, 0x%x, 0x%x\n",
1156*4882a593Smuzhiyun R_gain, G_gain, B_gain);
1157*4882a593Smuzhiyun }
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun /* apply OTP Lenc Calibration */
1160*4882a593Smuzhiyun if ((otp_ptr->flag & 0x10) && lsc_cfg->enable) {
1161*4882a593Smuzhiyun for (i = 0; i < 504; i++) {
1162*4882a593Smuzhiyun imx214_write_reg(client, 0xA300 + i,
1163*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, otp_ptr->lenc[i]);
1164*4882a593Smuzhiyun dev_dbg(&client->dev, "apply lenc[%d]: 0x%x\n",
1165*4882a593Smuzhiyun i, otp_ptr->lenc[i]);
1166*4882a593Smuzhiyun }
1167*4882a593Smuzhiyun usleep_range(1000, 2000);
1168*4882a593Smuzhiyun //choose lsc table 1
1169*4882a593Smuzhiyun imx214_write_reg(client, 0x3021,
1170*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, 0x01);
1171*4882a593Smuzhiyun //enable lsc
1172*4882a593Smuzhiyun imx214_write_reg(client, 0x0B00,
1173*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, 0x01);
1174*4882a593Smuzhiyun }
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun /* apply OTP SPC Calibration */
1177*4882a593Smuzhiyun if (otp_ptr->flag & 0x08) {
1178*4882a593Smuzhiyun for (i = 0; i < 63; i++) {
1179*4882a593Smuzhiyun imx214_write_reg(client, 0xD04C + i,
1180*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, otp_ptr->spc[i]);
1181*4882a593Smuzhiyun dev_dbg(&client->dev, "apply spc[%d]: 0x%x\n",
1182*4882a593Smuzhiyun i, otp_ptr->spc[i]);
1183*4882a593Smuzhiyun imx214_write_reg(client, 0xD08C + i,
1184*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, otp_ptr->spc[i + 63]);
1185*4882a593Smuzhiyun dev_dbg(&client->dev, "apply spc[%d]: 0x%x\n",
1186*4882a593Smuzhiyun i + 63, otp_ptr->spc[i + 63]);
1187*4882a593Smuzhiyun }
1188*4882a593Smuzhiyun //enable spc
1189*4882a593Smuzhiyun imx214_write_reg(client, 0x7BC8,
1190*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT, 0x01);
1191*4882a593Smuzhiyun }
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun return 0;
1194*4882a593Smuzhiyun }
1195*4882a593Smuzhiyun
__imx214_start_stream(struct imx214 * imx214)1196*4882a593Smuzhiyun static int __imx214_start_stream(struct imx214 *imx214)
1197*4882a593Smuzhiyun {
1198*4882a593Smuzhiyun int ret;
1199*4882a593Smuzhiyun
1200*4882a593Smuzhiyun ret = imx214_write_array(imx214->client, imx214->cur_mode->reg_list);
1201*4882a593Smuzhiyun if (ret)
1202*4882a593Smuzhiyun return ret;
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun /* In case these controls are set before streaming */
1205*4882a593Smuzhiyun mutex_unlock(&imx214->mutex);
1206*4882a593Smuzhiyun ret = v4l2_ctrl_handler_setup(&imx214->ctrl_handler);
1207*4882a593Smuzhiyun mutex_lock(&imx214->mutex);
1208*4882a593Smuzhiyun if (ret)
1209*4882a593Smuzhiyun return ret;
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun ret = imx214_apply_otp(imx214);
1212*4882a593Smuzhiyun if (ret)
1213*4882a593Smuzhiyun return ret;
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun return imx214_write_reg(imx214->client,
1216*4882a593Smuzhiyun IMX214_REG_CTRL_MODE,
1217*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT,
1218*4882a593Smuzhiyun IMX214_MODE_STREAMING);
1219*4882a593Smuzhiyun }
1220*4882a593Smuzhiyun
__imx214_stop_stream(struct imx214 * imx214)1221*4882a593Smuzhiyun static int __imx214_stop_stream(struct imx214 *imx214)
1222*4882a593Smuzhiyun {
1223*4882a593Smuzhiyun return imx214_write_reg(imx214->client,
1224*4882a593Smuzhiyun IMX214_REG_CTRL_MODE,
1225*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT,
1226*4882a593Smuzhiyun IMX214_MODE_SW_STANDBY);
1227*4882a593Smuzhiyun }
1228*4882a593Smuzhiyun
imx214_s_stream(struct v4l2_subdev * sd,int on)1229*4882a593Smuzhiyun static int imx214_s_stream(struct v4l2_subdev *sd, int on)
1230*4882a593Smuzhiyun {
1231*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
1232*4882a593Smuzhiyun struct i2c_client *client = imx214->client;
1233*4882a593Smuzhiyun int ret = 0;
1234*4882a593Smuzhiyun
1235*4882a593Smuzhiyun dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1236*4882a593Smuzhiyun imx214->cur_mode->width,
1237*4882a593Smuzhiyun imx214->cur_mode->height,
1238*4882a593Smuzhiyun DIV_ROUND_CLOSEST(imx214->cur_mode->max_fps.denominator,
1239*4882a593Smuzhiyun imx214->cur_mode->max_fps.numerator));
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun mutex_lock(&imx214->mutex);
1243*4882a593Smuzhiyun on = !!on;
1244*4882a593Smuzhiyun if (on == imx214->streaming)
1245*4882a593Smuzhiyun goto unlock_and_return;
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun if (on) {
1248*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
1249*4882a593Smuzhiyun if (ret < 0) {
1250*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1251*4882a593Smuzhiyun goto unlock_and_return;
1252*4882a593Smuzhiyun }
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun ret = __imx214_start_stream(imx214);
1255*4882a593Smuzhiyun if (ret) {
1256*4882a593Smuzhiyun v4l2_err(sd, "start stream failed while write regs\n");
1257*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1258*4882a593Smuzhiyun goto unlock_and_return;
1259*4882a593Smuzhiyun }
1260*4882a593Smuzhiyun } else {
1261*4882a593Smuzhiyun __imx214_stop_stream(imx214);
1262*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1263*4882a593Smuzhiyun }
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun imx214->streaming = on;
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun unlock_and_return:
1268*4882a593Smuzhiyun mutex_unlock(&imx214->mutex);
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun return ret;
1271*4882a593Smuzhiyun }
1272*4882a593Smuzhiyun
imx214_s_power(struct v4l2_subdev * sd,int on)1273*4882a593Smuzhiyun static int imx214_s_power(struct v4l2_subdev *sd, int on)
1274*4882a593Smuzhiyun {
1275*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
1276*4882a593Smuzhiyun struct i2c_client *client = imx214->client;
1277*4882a593Smuzhiyun int ret = 0;
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun mutex_lock(&imx214->mutex);
1280*4882a593Smuzhiyun
1281*4882a593Smuzhiyun /* If the power state is not modified - no work to do. */
1282*4882a593Smuzhiyun if (imx214->power_on == !!on)
1283*4882a593Smuzhiyun goto unlock_and_return;
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun if (on) {
1286*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
1287*4882a593Smuzhiyun if (ret < 0) {
1288*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1289*4882a593Smuzhiyun goto unlock_and_return;
1290*4882a593Smuzhiyun }
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun ret = imx214_write_array(imx214->client, imx214_global_regs);
1293*4882a593Smuzhiyun if (ret) {
1294*4882a593Smuzhiyun v4l2_err(sd, "could not set init registers\n");
1295*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1296*4882a593Smuzhiyun goto unlock_and_return;
1297*4882a593Smuzhiyun }
1298*4882a593Smuzhiyun
1299*4882a593Smuzhiyun imx214->power_on = true;
1300*4882a593Smuzhiyun } else {
1301*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1302*4882a593Smuzhiyun imx214->power_on = false;
1303*4882a593Smuzhiyun }
1304*4882a593Smuzhiyun
1305*4882a593Smuzhiyun unlock_and_return:
1306*4882a593Smuzhiyun mutex_unlock(&imx214->mutex);
1307*4882a593Smuzhiyun
1308*4882a593Smuzhiyun return ret;
1309*4882a593Smuzhiyun }
1310*4882a593Smuzhiyun
1311*4882a593Smuzhiyun /* Calculate the delay in us by clock rate and clock cycles */
imx214_cal_delay(u32 cycles)1312*4882a593Smuzhiyun static inline u32 imx214_cal_delay(u32 cycles)
1313*4882a593Smuzhiyun {
1314*4882a593Smuzhiyun return DIV_ROUND_UP(cycles, IMX214_XVCLK_FREQ / 1000 / 1000);
1315*4882a593Smuzhiyun }
1316*4882a593Smuzhiyun
__imx214_power_on(struct imx214 * imx214)1317*4882a593Smuzhiyun static int __imx214_power_on(struct imx214 *imx214)
1318*4882a593Smuzhiyun {
1319*4882a593Smuzhiyun int ret;
1320*4882a593Smuzhiyun u32 delay_us;
1321*4882a593Smuzhiyun struct device *dev = &imx214->client->dev;
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun if (!IS_ERR(imx214->power_gpio))
1324*4882a593Smuzhiyun gpiod_set_value_cansleep(imx214->power_gpio, 1);
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun usleep_range(1000, 2000);
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(imx214->pins_default)) {
1329*4882a593Smuzhiyun ret = pinctrl_select_state(imx214->pinctrl,
1330*4882a593Smuzhiyun imx214->pins_default);
1331*4882a593Smuzhiyun if (ret < 0)
1332*4882a593Smuzhiyun dev_err(dev, "could not set pins\n");
1333*4882a593Smuzhiyun }
1334*4882a593Smuzhiyun ret = clk_set_rate(imx214->xvclk, IMX214_XVCLK_FREQ);
1335*4882a593Smuzhiyun if (ret < 0)
1336*4882a593Smuzhiyun dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1337*4882a593Smuzhiyun if (clk_get_rate(imx214->xvclk) != IMX214_XVCLK_FREQ)
1338*4882a593Smuzhiyun dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1339*4882a593Smuzhiyun ret = clk_prepare_enable(imx214->xvclk);
1340*4882a593Smuzhiyun if (ret < 0) {
1341*4882a593Smuzhiyun dev_err(dev, "Failed to enable xvclk\n");
1342*4882a593Smuzhiyun return ret;
1343*4882a593Smuzhiyun }
1344*4882a593Smuzhiyun if (!IS_ERR(imx214->reset_gpio))
1345*4882a593Smuzhiyun gpiod_set_value_cansleep(imx214->reset_gpio, 0);
1346*4882a593Smuzhiyun
1347*4882a593Smuzhiyun ret = regulator_bulk_enable(IMX214_NUM_SUPPLIES, imx214->supplies);
1348*4882a593Smuzhiyun if (ret < 0) {
1349*4882a593Smuzhiyun dev_err(dev, "Failed to enable regulators\n");
1350*4882a593Smuzhiyun goto disable_clk;
1351*4882a593Smuzhiyun }
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun if (!IS_ERR(imx214->reset_gpio))
1354*4882a593Smuzhiyun gpiod_set_value_cansleep(imx214->reset_gpio, 1);
1355*4882a593Smuzhiyun
1356*4882a593Smuzhiyun usleep_range(500, 1000);
1357*4882a593Smuzhiyun if (!IS_ERR(imx214->pwdn_gpio))
1358*4882a593Smuzhiyun gpiod_set_value_cansleep(imx214->pwdn_gpio, 1);
1359*4882a593Smuzhiyun
1360*4882a593Smuzhiyun /* 8192 cycles prior to first SCCB transaction */
1361*4882a593Smuzhiyun delay_us = imx214_cal_delay(8192);
1362*4882a593Smuzhiyun usleep_range(delay_us, delay_us * 2);
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun return 0;
1365*4882a593Smuzhiyun
1366*4882a593Smuzhiyun disable_clk:
1367*4882a593Smuzhiyun clk_disable_unprepare(imx214->xvclk);
1368*4882a593Smuzhiyun
1369*4882a593Smuzhiyun return ret;
1370*4882a593Smuzhiyun }
1371*4882a593Smuzhiyun
__imx214_power_off(struct imx214 * imx214)1372*4882a593Smuzhiyun static void __imx214_power_off(struct imx214 *imx214)
1373*4882a593Smuzhiyun {
1374*4882a593Smuzhiyun int ret;
1375*4882a593Smuzhiyun struct device *dev = &imx214->client->dev;
1376*4882a593Smuzhiyun
1377*4882a593Smuzhiyun if (!IS_ERR(imx214->pwdn_gpio))
1378*4882a593Smuzhiyun gpiod_set_value_cansleep(imx214->pwdn_gpio, 0);
1379*4882a593Smuzhiyun clk_disable_unprepare(imx214->xvclk);
1380*4882a593Smuzhiyun if (!IS_ERR(imx214->reset_gpio))
1381*4882a593Smuzhiyun gpiod_set_value_cansleep(imx214->reset_gpio, 0);
1382*4882a593Smuzhiyun
1383*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(imx214->pins_sleep)) {
1384*4882a593Smuzhiyun ret = pinctrl_select_state(imx214->pinctrl,
1385*4882a593Smuzhiyun imx214->pins_sleep);
1386*4882a593Smuzhiyun if (ret < 0)
1387*4882a593Smuzhiyun dev_dbg(dev, "could not set pins\n");
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun if (!IS_ERR(imx214->power_gpio))
1390*4882a593Smuzhiyun gpiod_set_value_cansleep(imx214->power_gpio, 0);
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun regulator_bulk_disable(IMX214_NUM_SUPPLIES, imx214->supplies);
1393*4882a593Smuzhiyun }
1394*4882a593Smuzhiyun
imx214_runtime_resume(struct device * dev)1395*4882a593Smuzhiyun static int imx214_runtime_resume(struct device *dev)
1396*4882a593Smuzhiyun {
1397*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
1398*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1399*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun return __imx214_power_on(imx214);
1402*4882a593Smuzhiyun }
1403*4882a593Smuzhiyun
imx214_runtime_suspend(struct device * dev)1404*4882a593Smuzhiyun static int imx214_runtime_suspend(struct device *dev)
1405*4882a593Smuzhiyun {
1406*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
1407*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1408*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun __imx214_power_off(imx214);
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun return 0;
1413*4882a593Smuzhiyun }
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx214_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1416*4882a593Smuzhiyun static int imx214_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1417*4882a593Smuzhiyun {
1418*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
1419*4882a593Smuzhiyun struct v4l2_mbus_framefmt *try_fmt =
1420*4882a593Smuzhiyun v4l2_subdev_get_try_format(sd, fh->pad, 0);
1421*4882a593Smuzhiyun const struct imx214_mode *def_mode = &imx214->support_modes[0];
1422*4882a593Smuzhiyun
1423*4882a593Smuzhiyun mutex_lock(&imx214->mutex);
1424*4882a593Smuzhiyun /* Initialize try_fmt */
1425*4882a593Smuzhiyun try_fmt->width = def_mode->width;
1426*4882a593Smuzhiyun try_fmt->height = def_mode->height;
1427*4882a593Smuzhiyun try_fmt->code = IMX214_MEDIA_BUS_FMT;
1428*4882a593Smuzhiyun try_fmt->field = V4L2_FIELD_NONE;
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun mutex_unlock(&imx214->mutex);
1431*4882a593Smuzhiyun /* No crop or compose */
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun return 0;
1434*4882a593Smuzhiyun }
1435*4882a593Smuzhiyun #endif
1436*4882a593Smuzhiyun
imx214_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1437*4882a593Smuzhiyun static int imx214_enum_frame_interval(struct v4l2_subdev *sd,
1438*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
1439*4882a593Smuzhiyun struct v4l2_subdev_frame_interval_enum *fie)
1440*4882a593Smuzhiyun {
1441*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
1442*4882a593Smuzhiyun
1443*4882a593Smuzhiyun if (fie->index >= imx214->cfg_num)
1444*4882a593Smuzhiyun return -EINVAL;
1445*4882a593Smuzhiyun
1446*4882a593Smuzhiyun fie->code = IMX214_MEDIA_BUS_FMT;
1447*4882a593Smuzhiyun fie->width = imx214->support_modes[fie->index].width;
1448*4882a593Smuzhiyun fie->height = imx214->support_modes[fie->index].height;
1449*4882a593Smuzhiyun fie->interval = imx214->support_modes[fie->index].max_fps;
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun return 0;
1452*4882a593Smuzhiyun }
1453*4882a593Smuzhiyun
imx214_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)1454*4882a593Smuzhiyun static int imx214_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1455*4882a593Smuzhiyun struct v4l2_mbus_config *config)
1456*4882a593Smuzhiyun {
1457*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
1458*4882a593Smuzhiyun u32 lane_num = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
1459*4882a593Smuzhiyun u32 val = 0;
1460*4882a593Smuzhiyun
1461*4882a593Smuzhiyun val = 1 << (lane_num - 1) |
1462*4882a593Smuzhiyun V4L2_MBUS_CSI2_CHANNEL_0 |
1463*4882a593Smuzhiyun V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1464*4882a593Smuzhiyun
1465*4882a593Smuzhiyun config->type = V4L2_MBUS_CSI2_DPHY;
1466*4882a593Smuzhiyun config->flags = val;
1467*4882a593Smuzhiyun
1468*4882a593Smuzhiyun return 0;
1469*4882a593Smuzhiyun }
1470*4882a593Smuzhiyun
1471*4882a593Smuzhiyun #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1472*4882a593Smuzhiyun #define DST_WIDTH_2096 2096
1473*4882a593Smuzhiyun #define DST_HEIGHT_1560 1560
1474*4882a593Smuzhiyun
imx214_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1475*4882a593Smuzhiyun static int imx214_get_selection(struct v4l2_subdev *sd,
1476*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
1477*4882a593Smuzhiyun struct v4l2_subdev_selection *sel)
1478*4882a593Smuzhiyun {
1479*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
1480*4882a593Smuzhiyun
1481*4882a593Smuzhiyun if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1482*4882a593Smuzhiyun if (imx214->cur_mode->width == 2104) {
1483*4882a593Smuzhiyun sel->r.left = CROP_START(imx214->cur_mode->width, DST_WIDTH_2096);
1484*4882a593Smuzhiyun sel->r.width = DST_WIDTH_2096;
1485*4882a593Smuzhiyun sel->r.top = CROP_START(imx214->cur_mode->height, DST_HEIGHT_1560);
1486*4882a593Smuzhiyun sel->r.height = DST_HEIGHT_1560;
1487*4882a593Smuzhiyun } else {
1488*4882a593Smuzhiyun sel->r.left = CROP_START(imx214->cur_mode->width,
1489*4882a593Smuzhiyun imx214->cur_mode->width);
1490*4882a593Smuzhiyun sel->r.width = imx214->cur_mode->width;
1491*4882a593Smuzhiyun sel->r.top = CROP_START(imx214->cur_mode->height,
1492*4882a593Smuzhiyun imx214->cur_mode->height);
1493*4882a593Smuzhiyun sel->r.height = imx214->cur_mode->height;
1494*4882a593Smuzhiyun }
1495*4882a593Smuzhiyun return 0;
1496*4882a593Smuzhiyun }
1497*4882a593Smuzhiyun
1498*4882a593Smuzhiyun return -EINVAL;
1499*4882a593Smuzhiyun }
1500*4882a593Smuzhiyun
1501*4882a593Smuzhiyun static const struct dev_pm_ops imx214_pm_ops = {
1502*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(imx214_runtime_suspend,
1503*4882a593Smuzhiyun imx214_runtime_resume, NULL)
1504*4882a593Smuzhiyun };
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1507*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops imx214_internal_ops = {
1508*4882a593Smuzhiyun .open = imx214_open,
1509*4882a593Smuzhiyun };
1510*4882a593Smuzhiyun #endif
1511*4882a593Smuzhiyun
1512*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops imx214_core_ops = {
1513*4882a593Smuzhiyun .s_power = imx214_s_power,
1514*4882a593Smuzhiyun .ioctl = imx214_ioctl,
1515*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1516*4882a593Smuzhiyun .compat_ioctl32 = imx214_compat_ioctl32,
1517*4882a593Smuzhiyun #endif
1518*4882a593Smuzhiyun };
1519*4882a593Smuzhiyun
1520*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops imx214_video_ops = {
1521*4882a593Smuzhiyun .s_stream = imx214_s_stream,
1522*4882a593Smuzhiyun .g_frame_interval = imx214_g_frame_interval,
1523*4882a593Smuzhiyun };
1524*4882a593Smuzhiyun
1525*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops imx214_pad_ops = {
1526*4882a593Smuzhiyun .enum_mbus_code = imx214_enum_mbus_code,
1527*4882a593Smuzhiyun .enum_frame_size = imx214_enum_frame_sizes,
1528*4882a593Smuzhiyun .enum_frame_interval = imx214_enum_frame_interval,
1529*4882a593Smuzhiyun .get_fmt = imx214_get_fmt,
1530*4882a593Smuzhiyun .set_fmt = imx214_set_fmt,
1531*4882a593Smuzhiyun .get_selection = imx214_get_selection,
1532*4882a593Smuzhiyun .get_mbus_config = imx214_g_mbus_config,
1533*4882a593Smuzhiyun };
1534*4882a593Smuzhiyun
1535*4882a593Smuzhiyun static const struct v4l2_subdev_ops imx214_subdev_ops = {
1536*4882a593Smuzhiyun .core = &imx214_core_ops,
1537*4882a593Smuzhiyun .video = &imx214_video_ops,
1538*4882a593Smuzhiyun .pad = &imx214_pad_ops,
1539*4882a593Smuzhiyun };
1540*4882a593Smuzhiyun
imx214_set_gain_reg(struct imx214 * imx214,u32 a_gain)1541*4882a593Smuzhiyun static int imx214_set_gain_reg(struct imx214 *imx214, u32 a_gain)
1542*4882a593Smuzhiyun {
1543*4882a593Smuzhiyun int ret = 0;
1544*4882a593Smuzhiyun u32 gain_reg = 0;
1545*4882a593Smuzhiyun
1546*4882a593Smuzhiyun gain_reg = (512 - (512 * 512 / a_gain));
1547*4882a593Smuzhiyun if (gain_reg > 480)
1548*4882a593Smuzhiyun gain_reg = 480;
1549*4882a593Smuzhiyun
1550*4882a593Smuzhiyun ret = imx214_write_reg(imx214->client,
1551*4882a593Smuzhiyun IMX214_REG_GAIN_H,
1552*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT,
1553*4882a593Smuzhiyun ((gain_reg & 0x100) >> 8));
1554*4882a593Smuzhiyun ret |= imx214_write_reg(imx214->client,
1555*4882a593Smuzhiyun IMX214_REG_GAIN_L,
1556*4882a593Smuzhiyun IMX214_REG_VALUE_08BIT,
1557*4882a593Smuzhiyun (gain_reg & 0xff));
1558*4882a593Smuzhiyun return ret;
1559*4882a593Smuzhiyun }
1560*4882a593Smuzhiyun
imx214_set_ctrl(struct v4l2_ctrl * ctrl)1561*4882a593Smuzhiyun static int imx214_set_ctrl(struct v4l2_ctrl *ctrl)
1562*4882a593Smuzhiyun {
1563*4882a593Smuzhiyun struct imx214 *imx214 = container_of(ctrl->handler,
1564*4882a593Smuzhiyun struct imx214, ctrl_handler);
1565*4882a593Smuzhiyun struct i2c_client *client = imx214->client;
1566*4882a593Smuzhiyun s64 max;
1567*4882a593Smuzhiyun int ret = 0;
1568*4882a593Smuzhiyun
1569*4882a593Smuzhiyun /* Propagate change of current control to all related controls */
1570*4882a593Smuzhiyun switch (ctrl->id) {
1571*4882a593Smuzhiyun case V4L2_CID_VBLANK:
1572*4882a593Smuzhiyun /* Update max exposure while meeting expected vblanking */
1573*4882a593Smuzhiyun max = imx214->cur_mode->height + ctrl->val - 4;
1574*4882a593Smuzhiyun __v4l2_ctrl_modify_range(imx214->exposure,
1575*4882a593Smuzhiyun imx214->exposure->minimum, max,
1576*4882a593Smuzhiyun imx214->exposure->step,
1577*4882a593Smuzhiyun imx214->exposure->default_value);
1578*4882a593Smuzhiyun break;
1579*4882a593Smuzhiyun }
1580*4882a593Smuzhiyun
1581*4882a593Smuzhiyun if (!pm_runtime_get_if_in_use(&client->dev))
1582*4882a593Smuzhiyun return 0;
1583*4882a593Smuzhiyun
1584*4882a593Smuzhiyun switch (ctrl->id) {
1585*4882a593Smuzhiyun case V4L2_CID_EXPOSURE:
1586*4882a593Smuzhiyun /* 4 least significant bits of expsoure are fractional part */
1587*4882a593Smuzhiyun ret = imx214_write_reg(imx214->client,
1588*4882a593Smuzhiyun IMX214_REG_EXPOSURE,
1589*4882a593Smuzhiyun IMX214_REG_VALUE_16BIT,
1590*4882a593Smuzhiyun ctrl->val);
1591*4882a593Smuzhiyun break;
1592*4882a593Smuzhiyun case V4L2_CID_ANALOGUE_GAIN:
1593*4882a593Smuzhiyun ret = imx214_set_gain_reg(imx214, ctrl->val);
1594*4882a593Smuzhiyun break;
1595*4882a593Smuzhiyun case V4L2_CID_VBLANK:
1596*4882a593Smuzhiyun ret = imx214_write_reg(imx214->client,
1597*4882a593Smuzhiyun IMX214_REG_VTS,
1598*4882a593Smuzhiyun IMX214_REG_VALUE_16BIT,
1599*4882a593Smuzhiyun ctrl->val + imx214->cur_mode->height);
1600*4882a593Smuzhiyun break;
1601*4882a593Smuzhiyun case V4L2_CID_TEST_PATTERN:
1602*4882a593Smuzhiyun ret = imx214_enable_test_pattern(imx214, ctrl->val);
1603*4882a593Smuzhiyun break;
1604*4882a593Smuzhiyun default:
1605*4882a593Smuzhiyun dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1606*4882a593Smuzhiyun __func__, ctrl->id, ctrl->val);
1607*4882a593Smuzhiyun break;
1608*4882a593Smuzhiyun }
1609*4882a593Smuzhiyun
1610*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun return ret;
1613*4882a593Smuzhiyun }
1614*4882a593Smuzhiyun
1615*4882a593Smuzhiyun static const struct v4l2_ctrl_ops imx214_ctrl_ops = {
1616*4882a593Smuzhiyun .s_ctrl = imx214_set_ctrl,
1617*4882a593Smuzhiyun };
1618*4882a593Smuzhiyun
imx214_initialize_controls(struct imx214 * imx214)1619*4882a593Smuzhiyun static int imx214_initialize_controls(struct imx214 *imx214)
1620*4882a593Smuzhiyun {
1621*4882a593Smuzhiyun const struct imx214_mode *mode;
1622*4882a593Smuzhiyun struct v4l2_ctrl_handler *handler;
1623*4882a593Smuzhiyun s64 exposure_max, vblank_def;
1624*4882a593Smuzhiyun u32 h_blank;
1625*4882a593Smuzhiyun int ret;
1626*4882a593Smuzhiyun u64 dst_pixel_rate = 0;
1627*4882a593Smuzhiyun u32 lane_num = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
1628*4882a593Smuzhiyun
1629*4882a593Smuzhiyun handler = &imx214->ctrl_handler;
1630*4882a593Smuzhiyun mode = imx214->cur_mode;
1631*4882a593Smuzhiyun ret = v4l2_ctrl_handler_init(handler, 8);
1632*4882a593Smuzhiyun if (ret)
1633*4882a593Smuzhiyun return ret;
1634*4882a593Smuzhiyun handler->lock = &imx214->mutex;
1635*4882a593Smuzhiyun
1636*4882a593Smuzhiyun imx214->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1637*4882a593Smuzhiyun V4L2_CID_LINK_FREQ,
1638*4882a593Smuzhiyun 1, 0, link_freq_items);
1639*4882a593Smuzhiyun
1640*4882a593Smuzhiyun dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1641*4882a593Smuzhiyun
1642*4882a593Smuzhiyun imx214->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1643*4882a593Smuzhiyun V4L2_CID_PIXEL_RATE,
1644*4882a593Smuzhiyun 0, IMX214_PIXEL_RATE,
1645*4882a593Smuzhiyun 1, dst_pixel_rate);
1646*4882a593Smuzhiyun
1647*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(imx214->link_freq,
1648*4882a593Smuzhiyun mode->link_freq_idx);
1649*4882a593Smuzhiyun
1650*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
1651*4882a593Smuzhiyun imx214->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1652*4882a593Smuzhiyun h_blank, h_blank, 1, h_blank);
1653*4882a593Smuzhiyun if (imx214->hblank)
1654*4882a593Smuzhiyun imx214->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1655*4882a593Smuzhiyun
1656*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
1657*4882a593Smuzhiyun imx214->vblank = v4l2_ctrl_new_std(handler, &imx214_ctrl_ops,
1658*4882a593Smuzhiyun V4L2_CID_VBLANK, vblank_def,
1659*4882a593Smuzhiyun IMX214_VTS_MAX - mode->height,
1660*4882a593Smuzhiyun 1, vblank_def);
1661*4882a593Smuzhiyun
1662*4882a593Smuzhiyun exposure_max = mode->vts_def - 4;
1663*4882a593Smuzhiyun imx214->exposure = v4l2_ctrl_new_std(handler, &imx214_ctrl_ops,
1664*4882a593Smuzhiyun V4L2_CID_EXPOSURE, IMX214_EXPOSURE_MIN,
1665*4882a593Smuzhiyun exposure_max, IMX214_EXPOSURE_STEP,
1666*4882a593Smuzhiyun mode->exp_def);
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun imx214->anal_gain = v4l2_ctrl_new_std(handler, &imx214_ctrl_ops,
1669*4882a593Smuzhiyun V4L2_CID_ANALOGUE_GAIN, IMX214_GAIN_MIN,
1670*4882a593Smuzhiyun IMX214_GAIN_MAX, IMX214_GAIN_STEP,
1671*4882a593Smuzhiyun IMX214_GAIN_DEFAULT);
1672*4882a593Smuzhiyun
1673*4882a593Smuzhiyun imx214->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1674*4882a593Smuzhiyun &imx214_ctrl_ops, V4L2_CID_TEST_PATTERN,
1675*4882a593Smuzhiyun ARRAY_SIZE(imx214_test_pattern_menu) - 1,
1676*4882a593Smuzhiyun 0, 0, imx214_test_pattern_menu);
1677*4882a593Smuzhiyun
1678*4882a593Smuzhiyun if (handler->error) {
1679*4882a593Smuzhiyun ret = handler->error;
1680*4882a593Smuzhiyun dev_err(&imx214->client->dev,
1681*4882a593Smuzhiyun "Failed to init controls(%d)\n", ret);
1682*4882a593Smuzhiyun goto err_free_handler;
1683*4882a593Smuzhiyun }
1684*4882a593Smuzhiyun
1685*4882a593Smuzhiyun imx214->subdev.ctrl_handler = handler;
1686*4882a593Smuzhiyun
1687*4882a593Smuzhiyun return 0;
1688*4882a593Smuzhiyun
1689*4882a593Smuzhiyun err_free_handler:
1690*4882a593Smuzhiyun v4l2_ctrl_handler_free(handler);
1691*4882a593Smuzhiyun
1692*4882a593Smuzhiyun return ret;
1693*4882a593Smuzhiyun }
1694*4882a593Smuzhiyun
imx214_check_sensor_id(struct imx214 * imx214,struct i2c_client * client)1695*4882a593Smuzhiyun static int imx214_check_sensor_id(struct imx214 *imx214,
1696*4882a593Smuzhiyun struct i2c_client *client)
1697*4882a593Smuzhiyun {
1698*4882a593Smuzhiyun struct device *dev = &imx214->client->dev;
1699*4882a593Smuzhiyun u32 id = 0;
1700*4882a593Smuzhiyun int ret;
1701*4882a593Smuzhiyun
1702*4882a593Smuzhiyun ret = imx214_read_reg(client, IMX214_REG_CHIP_ID,
1703*4882a593Smuzhiyun IMX214_REG_VALUE_16BIT, &id);
1704*4882a593Smuzhiyun if (id != CHIP_ID) {
1705*4882a593Smuzhiyun dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
1706*4882a593Smuzhiyun return -ENODEV;
1707*4882a593Smuzhiyun }
1708*4882a593Smuzhiyun
1709*4882a593Smuzhiyun dev_info(dev, "Detected OV%04x sensor\n", id);
1710*4882a593Smuzhiyun
1711*4882a593Smuzhiyun return 0;
1712*4882a593Smuzhiyun }
1713*4882a593Smuzhiyun
imx214_configure_regulators(struct imx214 * imx214)1714*4882a593Smuzhiyun static int imx214_configure_regulators(struct imx214 *imx214)
1715*4882a593Smuzhiyun {
1716*4882a593Smuzhiyun unsigned int i;
1717*4882a593Smuzhiyun
1718*4882a593Smuzhiyun for (i = 0; i < IMX214_NUM_SUPPLIES; i++)
1719*4882a593Smuzhiyun imx214->supplies[i].supply = imx214_supply_names[i];
1720*4882a593Smuzhiyun
1721*4882a593Smuzhiyun return devm_regulator_bulk_get(&imx214->client->dev,
1722*4882a593Smuzhiyun IMX214_NUM_SUPPLIES,
1723*4882a593Smuzhiyun imx214->supplies);
1724*4882a593Smuzhiyun }
1725*4882a593Smuzhiyun
imx214_probe(struct i2c_client * client,const struct i2c_device_id * id)1726*4882a593Smuzhiyun static int imx214_probe(struct i2c_client *client,
1727*4882a593Smuzhiyun const struct i2c_device_id *id)
1728*4882a593Smuzhiyun {
1729*4882a593Smuzhiyun struct device *dev = &client->dev;
1730*4882a593Smuzhiyun struct device_node *node = dev->of_node;
1731*4882a593Smuzhiyun struct imx214 *imx214;
1732*4882a593Smuzhiyun struct v4l2_subdev *sd;
1733*4882a593Smuzhiyun struct device_node *endpoint;
1734*4882a593Smuzhiyun char facing[2];
1735*4882a593Smuzhiyun struct device_node *eeprom_ctrl_node;
1736*4882a593Smuzhiyun struct i2c_client *eeprom_ctrl_client;
1737*4882a593Smuzhiyun struct v4l2_subdev *eeprom_ctrl;
1738*4882a593Smuzhiyun struct imx214_otp_info *otp_ptr;
1739*4882a593Smuzhiyun int ret;
1740*4882a593Smuzhiyun
1741*4882a593Smuzhiyun dev_info(dev, "driver version: %02x.%02x.%02x",
1742*4882a593Smuzhiyun DRIVER_VERSION >> 16,
1743*4882a593Smuzhiyun (DRIVER_VERSION & 0xff00) >> 8,
1744*4882a593Smuzhiyun DRIVER_VERSION & 0x00ff);
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun imx214 = devm_kzalloc(dev, sizeof(*imx214), GFP_KERNEL);
1747*4882a593Smuzhiyun if (!imx214)
1748*4882a593Smuzhiyun return -ENOMEM;
1749*4882a593Smuzhiyun
1750*4882a593Smuzhiyun ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1751*4882a593Smuzhiyun &imx214->module_index);
1752*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1753*4882a593Smuzhiyun &imx214->module_facing);
1754*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1755*4882a593Smuzhiyun &imx214->module_name);
1756*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1757*4882a593Smuzhiyun &imx214->len_name);
1758*4882a593Smuzhiyun if (ret) {
1759*4882a593Smuzhiyun dev_err(dev, "could not get module information!\n");
1760*4882a593Smuzhiyun return -EINVAL;
1761*4882a593Smuzhiyun }
1762*4882a593Smuzhiyun
1763*4882a593Smuzhiyun imx214->client = client;
1764*4882a593Smuzhiyun endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1765*4882a593Smuzhiyun if (!endpoint) {
1766*4882a593Smuzhiyun dev_err(dev, "Failed to get endpoint\n");
1767*4882a593Smuzhiyun return -EINVAL;
1768*4882a593Smuzhiyun }
1769*4882a593Smuzhiyun ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
1770*4882a593Smuzhiyun &imx214->bus_cfg);
1771*4882a593Smuzhiyun if (ret) {
1772*4882a593Smuzhiyun dev_err(dev, "Failed to get bus cfg\n");
1773*4882a593Smuzhiyun return ret;
1774*4882a593Smuzhiyun }
1775*4882a593Smuzhiyun if (imx214->bus_cfg.bus.mipi_csi2.num_data_lanes == 4) {
1776*4882a593Smuzhiyun imx214->support_modes = supported_modes_4lane;
1777*4882a593Smuzhiyun imx214->cfg_num = ARRAY_SIZE(supported_modes_4lane);
1778*4882a593Smuzhiyun } else {
1779*4882a593Smuzhiyun imx214->support_modes = supported_modes_2lane;
1780*4882a593Smuzhiyun imx214->cfg_num = ARRAY_SIZE(supported_modes_2lane);
1781*4882a593Smuzhiyun }
1782*4882a593Smuzhiyun imx214->cur_mode = &imx214->support_modes[0];
1783*4882a593Smuzhiyun
1784*4882a593Smuzhiyun imx214->xvclk = devm_clk_get(dev, "xvclk");
1785*4882a593Smuzhiyun if (IS_ERR(imx214->xvclk)) {
1786*4882a593Smuzhiyun dev_err(dev, "Failed to get xvclk\n");
1787*4882a593Smuzhiyun return -EINVAL;
1788*4882a593Smuzhiyun }
1789*4882a593Smuzhiyun
1790*4882a593Smuzhiyun imx214->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1791*4882a593Smuzhiyun if (IS_ERR(imx214->power_gpio))
1792*4882a593Smuzhiyun dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
1793*4882a593Smuzhiyun
1794*4882a593Smuzhiyun imx214->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1795*4882a593Smuzhiyun if (IS_ERR(imx214->reset_gpio))
1796*4882a593Smuzhiyun dev_warn(dev, "Failed to get reset-gpios\n");
1797*4882a593Smuzhiyun
1798*4882a593Smuzhiyun imx214->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1799*4882a593Smuzhiyun if (IS_ERR(imx214->pwdn_gpio))
1800*4882a593Smuzhiyun dev_warn(dev, "Failed to get pwdn-gpios\n");
1801*4882a593Smuzhiyun
1802*4882a593Smuzhiyun ret = imx214_configure_regulators(imx214);
1803*4882a593Smuzhiyun if (ret) {
1804*4882a593Smuzhiyun dev_err(dev, "Failed to get power regulators\n");
1805*4882a593Smuzhiyun return ret;
1806*4882a593Smuzhiyun }
1807*4882a593Smuzhiyun
1808*4882a593Smuzhiyun imx214->pinctrl = devm_pinctrl_get(dev);
1809*4882a593Smuzhiyun if (!IS_ERR(imx214->pinctrl)) {
1810*4882a593Smuzhiyun imx214->pins_default =
1811*4882a593Smuzhiyun pinctrl_lookup_state(imx214->pinctrl,
1812*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_DEFAULT);
1813*4882a593Smuzhiyun if (IS_ERR(imx214->pins_default))
1814*4882a593Smuzhiyun dev_err(dev, "could not get default pinstate\n");
1815*4882a593Smuzhiyun
1816*4882a593Smuzhiyun imx214->pins_sleep =
1817*4882a593Smuzhiyun pinctrl_lookup_state(imx214->pinctrl,
1818*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_SLEEP);
1819*4882a593Smuzhiyun if (IS_ERR(imx214->pins_sleep))
1820*4882a593Smuzhiyun dev_err(dev, "could not get sleep pinstate\n");
1821*4882a593Smuzhiyun }
1822*4882a593Smuzhiyun
1823*4882a593Smuzhiyun mutex_init(&imx214->mutex);
1824*4882a593Smuzhiyun
1825*4882a593Smuzhiyun sd = &imx214->subdev;
1826*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &imx214_subdev_ops);
1827*4882a593Smuzhiyun ret = imx214_initialize_controls(imx214);
1828*4882a593Smuzhiyun if (ret)
1829*4882a593Smuzhiyun goto err_destroy_mutex;
1830*4882a593Smuzhiyun
1831*4882a593Smuzhiyun ret = __imx214_power_on(imx214);
1832*4882a593Smuzhiyun if (ret)
1833*4882a593Smuzhiyun goto err_free_handler;
1834*4882a593Smuzhiyun
1835*4882a593Smuzhiyun ret = imx214_check_sensor_id(imx214, client);
1836*4882a593Smuzhiyun if (ret)
1837*4882a593Smuzhiyun goto err_power_off;
1838*4882a593Smuzhiyun
1839*4882a593Smuzhiyun eeprom_ctrl_node = of_parse_phandle(node, "eeprom-ctrl", 0);
1840*4882a593Smuzhiyun if (eeprom_ctrl_node) {
1841*4882a593Smuzhiyun eeprom_ctrl_client =
1842*4882a593Smuzhiyun of_find_i2c_device_by_node(eeprom_ctrl_node);
1843*4882a593Smuzhiyun of_node_put(eeprom_ctrl_node);
1844*4882a593Smuzhiyun if (IS_ERR_OR_NULL(eeprom_ctrl_client)) {
1845*4882a593Smuzhiyun dev_err(dev, "can not get node\n");
1846*4882a593Smuzhiyun goto continue_probe;
1847*4882a593Smuzhiyun }
1848*4882a593Smuzhiyun eeprom_ctrl = i2c_get_clientdata(eeprom_ctrl_client);
1849*4882a593Smuzhiyun if (IS_ERR_OR_NULL(eeprom_ctrl)) {
1850*4882a593Smuzhiyun dev_err(dev, "can not get eeprom i2c client\n");
1851*4882a593Smuzhiyun } else {
1852*4882a593Smuzhiyun otp_ptr = devm_kzalloc(dev, sizeof(*otp_ptr),
1853*4882a593Smuzhiyun GFP_KERNEL);
1854*4882a593Smuzhiyun if (!otp_ptr)
1855*4882a593Smuzhiyun return -ENOMEM;
1856*4882a593Smuzhiyun ret = v4l2_subdev_call(eeprom_ctrl,
1857*4882a593Smuzhiyun core, ioctl, 0, otp_ptr);
1858*4882a593Smuzhiyun if (!ret) {
1859*4882a593Smuzhiyun imx214->otp = otp_ptr;
1860*4882a593Smuzhiyun } else {
1861*4882a593Smuzhiyun imx214->otp = NULL;
1862*4882a593Smuzhiyun devm_kfree(dev, otp_ptr);
1863*4882a593Smuzhiyun }
1864*4882a593Smuzhiyun }
1865*4882a593Smuzhiyun }
1866*4882a593Smuzhiyun
1867*4882a593Smuzhiyun continue_probe:
1868*4882a593Smuzhiyun
1869*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1870*4882a593Smuzhiyun sd->internal_ops = &imx214_internal_ops;
1871*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1872*4882a593Smuzhiyun #endif
1873*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1874*4882a593Smuzhiyun imx214->pad.flags = MEDIA_PAD_FL_SOURCE;
1875*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1876*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, 1, &imx214->pad);
1877*4882a593Smuzhiyun if (ret < 0)
1878*4882a593Smuzhiyun goto err_power_off;
1879*4882a593Smuzhiyun #endif
1880*4882a593Smuzhiyun
1881*4882a593Smuzhiyun memset(facing, 0, sizeof(facing));
1882*4882a593Smuzhiyun if (strcmp(imx214->module_facing, "back") == 0)
1883*4882a593Smuzhiyun facing[0] = 'b';
1884*4882a593Smuzhiyun else
1885*4882a593Smuzhiyun facing[0] = 'f';
1886*4882a593Smuzhiyun
1887*4882a593Smuzhiyun snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1888*4882a593Smuzhiyun imx214->module_index, facing,
1889*4882a593Smuzhiyun IMX214_NAME, dev_name(sd->dev));
1890*4882a593Smuzhiyun ret = v4l2_async_register_subdev_sensor_common(sd);
1891*4882a593Smuzhiyun if (ret) {
1892*4882a593Smuzhiyun dev_err(dev, "v4l2 async register subdev failed\n");
1893*4882a593Smuzhiyun goto err_clean_entity;
1894*4882a593Smuzhiyun }
1895*4882a593Smuzhiyun
1896*4882a593Smuzhiyun pm_runtime_set_active(dev);
1897*4882a593Smuzhiyun pm_runtime_enable(dev);
1898*4882a593Smuzhiyun pm_runtime_idle(dev);
1899*4882a593Smuzhiyun
1900*4882a593Smuzhiyun return 0;
1901*4882a593Smuzhiyun
1902*4882a593Smuzhiyun err_clean_entity:
1903*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1904*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1905*4882a593Smuzhiyun #endif
1906*4882a593Smuzhiyun err_power_off:
1907*4882a593Smuzhiyun __imx214_power_off(imx214);
1908*4882a593Smuzhiyun err_free_handler:
1909*4882a593Smuzhiyun v4l2_ctrl_handler_free(&imx214->ctrl_handler);
1910*4882a593Smuzhiyun err_destroy_mutex:
1911*4882a593Smuzhiyun mutex_destroy(&imx214->mutex);
1912*4882a593Smuzhiyun
1913*4882a593Smuzhiyun return ret;
1914*4882a593Smuzhiyun }
1915*4882a593Smuzhiyun
imx214_remove(struct i2c_client * client)1916*4882a593Smuzhiyun static int imx214_remove(struct i2c_client *client)
1917*4882a593Smuzhiyun {
1918*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1919*4882a593Smuzhiyun struct imx214 *imx214 = to_imx214(sd);
1920*4882a593Smuzhiyun
1921*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
1922*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1923*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1924*4882a593Smuzhiyun #endif
1925*4882a593Smuzhiyun v4l2_ctrl_handler_free(&imx214->ctrl_handler);
1926*4882a593Smuzhiyun mutex_destroy(&imx214->mutex);
1927*4882a593Smuzhiyun
1928*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1929*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&client->dev))
1930*4882a593Smuzhiyun __imx214_power_off(imx214);
1931*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
1932*4882a593Smuzhiyun
1933*4882a593Smuzhiyun return 0;
1934*4882a593Smuzhiyun }
1935*4882a593Smuzhiyun
1936*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1937*4882a593Smuzhiyun static const struct of_device_id imx214_of_match[] = {
1938*4882a593Smuzhiyun { .compatible = "sony,imx214" },
1939*4882a593Smuzhiyun {},
1940*4882a593Smuzhiyun };
1941*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, imx214_of_match);
1942*4882a593Smuzhiyun #endif
1943*4882a593Smuzhiyun
1944*4882a593Smuzhiyun static const struct i2c_device_id imx214_match_id[] = {
1945*4882a593Smuzhiyun { "sony,imx214", 0 },
1946*4882a593Smuzhiyun {},
1947*4882a593Smuzhiyun };
1948*4882a593Smuzhiyun
1949*4882a593Smuzhiyun static struct i2c_driver imx214_i2c_driver = {
1950*4882a593Smuzhiyun .driver = {
1951*4882a593Smuzhiyun .name = IMX214_NAME,
1952*4882a593Smuzhiyun .pm = &imx214_pm_ops,
1953*4882a593Smuzhiyun .of_match_table = of_match_ptr(imx214_of_match),
1954*4882a593Smuzhiyun },
1955*4882a593Smuzhiyun .probe = &imx214_probe,
1956*4882a593Smuzhiyun .remove = &imx214_remove,
1957*4882a593Smuzhiyun .id_table = imx214_match_id,
1958*4882a593Smuzhiyun };
1959*4882a593Smuzhiyun
sensor_mod_init(void)1960*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1961*4882a593Smuzhiyun {
1962*4882a593Smuzhiyun return i2c_add_driver(&imx214_i2c_driver);
1963*4882a593Smuzhiyun }
1964*4882a593Smuzhiyun
sensor_mod_exit(void)1965*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1966*4882a593Smuzhiyun {
1967*4882a593Smuzhiyun i2c_del_driver(&imx214_i2c_driver);
1968*4882a593Smuzhiyun }
1969*4882a593Smuzhiyun
1970*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1971*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1972*4882a593Smuzhiyun
1973*4882a593Smuzhiyun MODULE_DESCRIPTION("Sony imx214 sensor driver");
1974*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1975