1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc8034 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 add enum_frame_interval function.
10 * V0.0X01.0X04 add quick stream on/off
11 * V0.0X01.0X05 add function g_mbus_config
12 * V0.0X01.0X06
13 * 1. add 2lane support.
14 * 2. add some debug info.
15 * 3. adjust gc8034_g_mbus_config function.
16 * V0.0X01.0X07 support get channel info
17 * V0.0X01.0X08
18 * 1. default support 2lane full 30fps.
19 * 2. default support rk otp spec.
20 * V0.0X01.0X09 adjust supply sequence to suit spec
21 */
22 //#define DEBUG
23 #include <linux/clk.h>
24 #include <linux/device.h>
25 #include <linux/delay.h>
26 #include <linux/gpio/consumer.h>
27 #include <linux/i2c.h>
28 #include <linux/module.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/of.h>
31 #include <linux/of_graph.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/sysfs.h>
34 #include <linux/version.h>
35 #include <linux/rk-camera-module.h>
36 #include <media/media-entity.h>
37 #include <media/v4l2-async.h>
38 #include <media/v4l2-ctrls.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-event.h>
41 #include <media/v4l2-fwnode.h>
42 #include <media/v4l2-image-sizes.h>
43 #include <media/v4l2-mediabus.h>
44 #include <media/v4l2-subdev.h>
45 #include <linux/pinctrl/consumer.h>
46 #include <linux/slab.h>
47 #include <linux/of_graph.h>
48 #include "otp_eeprom.h"
49
50 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x09)
51
52 #ifndef V4L2_CID_DIGITAL_GAIN
53 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
54 #endif
55
56 #define GC8034_LANES 4
57 #define GC8034_BITS_PER_SAMPLE 10
58 #define GC8034_MIPI_FREQ_336MHZ 336000000U
59 #define GC8034_MIPI_FREQ_634MHZ 634000000U
60
61 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
62 #define GC8034_PIXEL_RATE 288000000
63 #define GC8034_XVCLK_FREQ 24000000
64
65 #define CHIP_ID 0x8044
66 #define GC8034_REG_CHIP_ID_H 0xf0
67 #define GC8034_REG_CHIP_ID_L 0xf1
68
69 #define GC8034_REG_SET_PAGE 0xfe
70 #define GC8034_SET_PAGE_ZERO 0x00
71
72 #define GC8034_REG_CTRL_MODE 0x3f
73 #define GC8034_MODE_SW_STANDBY 0x00
74 #define GC8034_MODE_STREAMING 0xd0
75
76 #define GC8034_REG_EXPOSURE_H 0x03
77 #define GC8034_REG_EXPOSURE_L 0x04
78 #define GC8034_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0x7F) /* 4 Bits */
79 #define GC8034_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 8 Bits */
80 #define GC8034_EXPOSURE_MIN 4
81 #define GC8034_EXPOSURE_STEP 1
82 #define GC8034_VTS_MAX 0x1fff
83
84 #define GC8034_REG_AGAIN 0xb6
85 #define GC8034_REG_DGAIN_INT 0xb1
86 #define GC8034_REG_DGAIN_FRAC 0xb2
87 #define GC8034_GAIN_MIN 64
88 #define GC8034_GAIN_MAX 1092
89 #define GC8034_GAIN_STEP 1
90 #define GC8034_GAIN_DEFAULT 64
91
92 #define GC8034_REG_VTS_H 0x07
93 #define GC8034_REG_VTS_L 0x08
94
95 #define REG_NULL 0xFF
96
97 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
98 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
99
100 #define GC8034_NAME "gc8034"
101 #define GC8034_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
102
103 /* use RK_OTP or old mode */
104 #define RK_OTP
105 /* choose 2lane support full 30fps or 15fps */
106 #define GC8034_2LANE_30FPS
107
108 static const char * const gc8034_supply_names[] = {
109 "dovdd", /* Digital I/O power */
110 "dvdd", /* Digital core power */
111 "avdd", /* Analog power */
112 };
113
114 #define GC8034_NUM_SUPPLIES ARRAY_SIZE(gc8034_supply_names)
115
116 #ifndef RK_OTP
117 struct gc8034_dd {
118 u16 x;
119 u16 y;
120 u16 t;
121 };
122
123 struct gc8034_otp_info {
124 int flag; //bit[7]: info bit[6]:wb bit[5]:vcm bit[4]:lenc
125 //bit[3] dd bit[2] chip version
126 u32 module_id;
127 u32 lens_id;
128 u32 year;
129 u32 month;
130 u32 day;
131 u32 rg_ratio;
132 u32 bg_ratio;
133 u32 golden_rg;
134 u32 golden_bg;
135 u8 lsc[396];
136 u32 vcm_start;
137 u32 vcm_end;
138 u32 vcm_dir;
139 u32 dd_cnt;
140 struct gc8034_dd dd_param[160];
141 u16 reg_page[5];
142 u16 reg_addr[5];
143 u16 reg_value[5];
144 u16 reg_num;
145 };
146
147 struct gc8034_id_name {
148 u32 id;
149 char name[RKMODULE_NAME_LEN];
150 };
151
152 static const struct gc8034_id_name gc8034_module_info[] = {
153 {0x0d, "CameraKing"},
154 {0x00, "Unknown"}
155 };
156
157 static const struct gc8034_id_name gc8034_lens_info[] = {
158 {0xd0, "CK8401"},
159 {0x00, "Unknown"}
160 };
161 #endif
162
163 struct regval {
164 u8 addr;
165 u8 val;
166 };
167
168 struct gc8034_mode {
169 u32 width;
170 u32 height;
171 struct v4l2_fract max_fps;
172 u32 hts_def;
173 u32 vts_def;
174 u32 exp_def;
175 u32 mipi_freq_idx;
176 const struct regval *global_reg_list;
177 const struct regval *reg_list;
178 u32 vc[PAD_MAX];
179 };
180
181 struct gc8034 {
182 struct i2c_client *client;
183 struct clk *xvclk;
184 struct gpio_desc *power_gpio;
185 struct gpio_desc *reset_gpio;
186 struct gpio_desc *pwdn_gpio;
187 struct regulator_bulk_data supplies[GC8034_NUM_SUPPLIES];
188 struct pinctrl *pinctrl;
189 struct pinctrl_state *pins_default;
190 struct pinctrl_state *pins_sleep;
191 struct v4l2_subdev subdev;
192 struct media_pad pad;
193 struct v4l2_ctrl_handler ctrl_handler;
194 struct v4l2_ctrl *exposure;
195 struct v4l2_ctrl *anal_gain;
196 struct v4l2_ctrl *digi_gain;
197 struct v4l2_ctrl *hblank;
198 struct v4l2_ctrl *vblank;
199 struct v4l2_ctrl *link_freq;
200 struct mutex mutex;
201 bool streaming;
202 unsigned int lane_num;
203 unsigned int cfg_num;
204 unsigned int pixel_rate;
205 bool power_on;
206 const struct gc8034_mode *cur_mode;
207 u32 module_index;
208 const char *module_facing;
209 const char *module_name;
210 const char *len_name;
211 u32 Dgain_ratio;
212 #ifdef RK_OTP
213 struct otp_info *otp;
214 #else
215 struct gc8034_otp_info *otp;
216 #endif
217 struct rkmodule_inf module_inf;
218 struct rkmodule_awb_cfg awb_cfg;
219 };
220
221 #define to_gc8034(sd) container_of(sd, struct gc8034, subdev)
222
223 #undef GC8034_MIRROR_NORMAL
224 #undef GC8034_MIRROR_H
225 #undef GC8034_MIRROR_V
226 #undef GC8034_MIRROR_HV
227 /* If you use the otp function, keep the otp_drv ->
228 * gc8034_common_otp_drv.h consistent.
229 */
230 #define GC8034_MIRROR_NORMAL
231
232 #if defined(GC8034_MIRROR_NORMAL)
233 #define GC8034_MIRROR 0xc0
234 #define BINNING_STARTY 0x04
235 #define BINNING_STARTX 0x05
236 #define FULL_STARTY 0x08
237 #define FULL_STARTX 0x09
238 #elif defined(GC8034_MIRROR_H)
239 #define GC8034_MIRROR 0xc1
240 #define BINNING_STARTY 0x04
241 #define BINNING_STARTX 0x04
242 #define FULL_STARTY 0x08
243 #define FULL_STARTX 0x08
244 #elif defined(GC8034_MIRROR_V)
245 #define GC8034_MIRROR 0xc2
246 #define BINNING_STARTY 0x05
247 #define BINNING_STARTX 0x05
248 #define FULL_STARTY 0x09
249 #define FULL_STARTX 0x09
250 #elif defined(GC8034_MIRROR_HV)
251 #define GC8034_MIRROR 0xc3
252 #define BINNING_STARTY 0x05
253 #define BINNING_STARTX 0x04
254 #define FULL_STARTY 0x09
255 #define FULL_STARTX 0x08
256 #else
257 #define GC8034_MIRROR 0xc0
258 #define BINNING_STARTY 0x04
259 #define BINNING_STARTX 0x05
260 #define FULL_STARTY 0x08
261 #define FULL_STARTX 0x09
262 #endif
263
264 /*
265 * Xclk 24Mhz
266 */
267 static const struct regval gc8034_global_regs_2lane[] = {
268 #ifdef GC8034_2LANE_30FPS
269 /* SYS */
270 {0xf2, 0x00},
271 {0xf4, 0x90},
272 {0xf5, 0x3d},
273 {0xf6, 0x44},
274 {0xf8, 0x63},
275 {0xfa, 0x42},
276 {0xf9, 0x00},
277 {0xf7, 0x95},
278 {0xfc, 0x00},
279 {0xfc, 0x00},
280 {0xfc, 0xea},
281 {0xfe, 0x03},
282 {0x03, 0x9a},
283 {0xfc, 0xee},
284 {0xfe, 0x00},
285 {0x88, 0x03},
286
287 /*Cisctl&Analog*/
288 {0xfe, 0x00},
289 {0x03, 0x08},
290 {0x04, 0xc6},
291 {0x05, 0x02},
292 {0x06, 0x16},
293 {0x07, 0x00},
294 {0x08, 0x10},
295 {0x0a, 0x3a}, //row start
296 {0x0b, 0x00},
297 {0x0c, 0x04}, //col start
298 {0x0d, 0x09},
299 {0x0e, 0xa0}, //win_height 2464
300 {0x0f, 0x0c},
301 {0x10, 0xd4}, //win_width 3284
302 {0x17, GC8034_MIRROR},
303 {0x18, 0x02},
304 {0x19, 0x17},
305 {0x1e, 0x50},
306 {0x1f, 0x80},
307 {0x21, 0x4c},
308 {0x25, 0x00},
309 {0x28, 0x4a},
310 {0x2d, 0x89},
311 {0xca, 0x02},
312 {0xcb, 0x00},
313 {0xcc, 0x39},
314 {0xce, 0xd0},
315 {0xcf, 0x93},
316 {0xd0, 0x1b},
317 {0xd1, 0xaa},
318 {0xd2, 0xcb},
319 {0xd8, 0x40},
320 {0xd9, 0xff},
321 {0xda, 0x0e},
322 {0xdb, 0xb0},
323 {0xdc, 0x0e},
324 {0xde, 0x08},
325 {0xe4, 0xc6},
326 {0xe5, 0x08},
327 {0xe6, 0x10},
328 {0xed, 0x2a},
329 {0xfe, 0x02},
330 {0x59, 0x02},
331 {0x5a, 0x04},
332 {0x5b, 0x08},
333 {0x5c, 0x20},
334 {0xfe, 0x00},
335 {0x1a, 0x09},
336 {0x1d, 0x13},
337 {0xfe, 0x10},
338 {0xfe, 0x00},
339 {0xfe, 0x10},
340 {0xfe, 0x00},
341
342 /* Gamma */
343 {0xfe, 0x00},
344 {0x20, 0x54},
345 {0x33, 0x82},
346 {0xfe, 0x01},
347 {0xdf, 0x06},
348 {0xe7, 0x18},
349 {0xe8, 0x20},
350 {0xe9, 0x16},
351 {0xea, 0x17},
352 {0xeb, 0x50},
353 {0xec, 0x6c},
354 {0xed, 0x9b},
355 {0xee, 0xd8},
356
357 /*ISP*/
358 {0xfe, 0x00},
359 {0x80, 0x13},
360 {0x84, 0x01},
361 {0x89, 0x03},
362 {0x8d, 0x03},
363 {0x8f, 0x14},
364 {0xad, 0x00},
365 {0x66, 0x0c},
366 {0xbc, 0x09},
367 {0xc2, 0x7f},
368 {0xc3, 0xff},
369
370 /*Crop window*/
371 {0x90, 0x01},
372 {0x92, FULL_STARTY},
373 {0x94, FULL_STARTX},
374 {0x95, 0x09},
375 {0x96, 0x90},
376 {0x97, 0x0c},
377 {0x98, 0xc0},
378
379 /*Gain*/
380 {0xb0, 0x90},
381 {0xb1, 0x01},
382 {0xb2, 0x00},
383 {0xb6, 0x00},
384
385 /*BLK*/
386 {0xfe, 0x00},
387 {0x40, 0x22},
388 {0x41, 0x20},
389 {0x42, 0x02},
390 {0x43, 0x08},
391 {0x4e, 0x0f},
392 {0x4f, 0xf0},
393 {0x58, 0x80},
394 {0x59, 0x80},
395 {0x5a, 0x80},
396 {0x5b, 0x80},
397 {0x5c, 0x00},
398 {0x5d, 0x00},
399 {0x5e, 0x00},
400 {0x5f, 0x00},
401 {0x6b, 0x01},
402 {0x6c, 0x00},
403 {0x6d, 0x0c},
404
405 /*WB offset*/
406 {0xfe, 0x01},
407 {0xbf, 0x40},
408
409 /*Dark Sun*/
410 {0xfe, 0x01},
411 {0x68, 0x77},
412
413 /*DPC*/
414 {0xfe, 0x01},
415 {0x60, 0x00},
416 {0x61, 0x10},
417 {0x62, 0x60},
418 {0x63, 0x30},
419 {0x64, 0x00},
420
421 /* LSC */
422 {0xfe, 0x01},
423 {0xa8, 0x60},
424 {0xa2, 0xd1},
425 {0xc8, 0x57},
426 {0xa1, 0xb8},
427 {0xa3, 0x91},
428 {0xc0, 0x50},
429 {0xd0, 0x05},
430 {0xd1, 0xb2},
431 {0xd2, 0x1f},
432 {0xd3, 0x00},
433 {0xd4, 0x00},
434 {0xd5, 0x00},
435 {0xd6, 0x00},
436 {0xd7, 0x00},
437 {0xd8, 0x00},
438 {0xd9, 0x00},
439 {0xa4, 0x10},
440 {0xa5, 0x20},
441 {0xa6, 0x60},
442 {0xa7, 0x80},
443 {0xab, 0x18},
444 {0xc7, 0xc0},
445
446 /*ABB*/
447 {0xfe, 0x01},
448 {0x20, 0x02},
449 {0x21, 0x02},
450 {0x23, 0x42},
451
452 /*MIPI*/
453 {0xfe, 0x03},
454 {0x01, 0x07},
455 {0x02, 0x04},
456 {0x04, 0x80},
457 {0x11, 0x2b},
458 {0x12, 0xf0}, //lwc 3264*5/4
459 {0x13, 0x0f},
460 {0x15, 0x10}, //LP
461 {0x16, 0x29},
462 {0x17, 0xff},
463 {0x18, 0x01},
464 {0x19, 0xaa},
465 {0x1a, 0x02},
466 {0x21, 0x0c},
467 {0x22, 0x0e},
468 {0x23, 0x45},
469 {0x24, 0x01},
470 {0x25, 0x1c},
471 {0x26, 0x0b},
472 {0x29, 0x0e},
473 {0x2a, 0x1d},
474 {0x2b, 0x0b},
475 {0xfe, 0x00},
476 //{0x3f, 0x91},
477 {0x3f, 0x00},
478 #else
479 /*SYS*/
480 {0xf2, 0x00},
481 {0xf4, 0x80},
482 {0xf5, 0x19},
483 {0xf6, 0x44},
484 {0xf7, 0x95}, //pll enable
485 {0xf8, 0x63}, //pll mode
486 {0xf9, 0x00},
487 {0xfa, 0x45},
488 {0xfc, 0xfe},
489
490 /*Cisctl&Analog*/
491 {0xfe, 0x00},
492 {0x03, 0x08},
493 {0x04, 0xc6},
494 {0x05, 0x02},
495 {0x06, 0x16},
496 {0x07, 0x00},
497 {0x08, 0x10},
498 {0x0a, 0x3a}, //row start
499 {0x0b, 0x00},
500 {0x0c, 0x04}, //col start
501 {0x0d, 0x09},
502 {0x0e, 0xa0}, //win_height 2464
503 {0x0f, 0x0c},
504 {0x10, 0xd4}, //win_width 3284
505 {0x17, GC8034_MIRROR},
506 {0x18, 0x02},
507 {0x19, 0x17},
508 {0x1e, 0x50},
509 {0x1f, 0x80},
510 {0x21, 0x4c},
511 {0x25, 0x00},
512 {0x28, 0x4a},
513 {0x2d, 0x89},
514 {0xca, 0x02},
515 {0xcb, 0x00},
516 {0xcc, 0x39},
517 {0xce, 0xd0},
518 {0xcf, 0x93},
519 {0xd0, 0x1b},
520 {0xd1, 0xaa},
521 {0xd2, 0xcb},
522 {0xd8, 0x40},
523 {0xd9, 0xff},
524 {0xda, 0x0e},
525 {0xdb, 0xb0},
526 {0xdc, 0x0e},
527 {0xde, 0x08},
528 {0xe4, 0xc6},
529 {0xe5, 0x08},
530 {0xe6, 0x10},
531 {0xed, 0x2a},
532 {0xfe, 0x02},
533 {0x59, 0x02},
534 {0x5a, 0x04},
535 {0x5b, 0x08},
536 {0x5c, 0x20},
537 {0xfe, 0x00},
538 {0x1a, 0x09},
539 {0x1d, 0x13},
540 {0xfe, 0x10},
541 {0xfe, 0x00},
542 {0xfe, 0x10},
543 {0xfe, 0x00},
544
545 /* Gamma */
546 {0xfe, 0x00},
547 {0x20, 0x54},
548 {0x33, 0x82},
549 {0xfe, 0x01},
550 {0xdf, 0x06},
551 {0xe7, 0x18},
552 {0xe8, 0x20},
553 {0xe9, 0x16},
554 {0xea, 0x17},
555 {0xeb, 0x50},
556 {0xec, 0x6c},
557 {0xed, 0x9b},
558 {0xee, 0xd8},
559
560 /*ISP*/
561 {0xfe, 0x00},
562 {0x80, 0x13},
563 {0x84, 0x01},
564 {0x89, 0x03},
565 {0x8d, 0x03},
566 {0x8f, 0x14},
567 {0xad, 0x00},
568
569 /*Crop window*/
570 {0x90, 0x01},
571 {0x92, FULL_STARTY},
572 {0x94, FULL_STARTX},
573 {0x95, 0x09},
574 {0x96, 0x90},
575 {0x97, 0x0c},
576 {0x98, 0xc0},
577
578 /*Gain*/
579 {0xb0, 0x90},
580 {0xb1, 0x01},
581 {0xb2, 0x00},
582 {0xb6, 0x00},
583
584 /*BLK*/
585 {0xfe, 0x00},
586 {0x40, 0x22},
587 {0x43, 0x03}, //add_offset
588 {0x4e, 0x00}, //row_bits[15:8]
589 {0x4f, 0x3c}, //row_bits[7:0]
590 {0x58, 0x80}, //dark current ratio
591 {0x59, 0x80},
592 {0x5a, 0x80},
593 {0x5b, 0x80},
594 {0x5c, 0x00},
595 {0x5d, 0x00},
596 {0x5e, 0x00},
597 {0x5f, 0x00},
598
599 /*WB offset*/
600 {0xfe, 0x01},
601 {0xbf, 0x40},
602
603 /*Dark Sun*/
604 {0xfe, 0x01},
605 {0x68, 0x77},
606
607 /*DPC*/
608 {0xfe, 0x01},
609 {0x60, 0x15},
610 {0x61, 0x10},
611 {0x62, 0x60},
612 {0x63, 0x48},
613 {0x64, 0x02},
614
615 /*LSC*/
616 {0xfe, 0x01},
617 {0xa0, 0x10}, //[6]segment_width[8], 0x[5:4]segment_height[9:8]
618 {0xa8, 0x60}, //segment_height[7:0]
619 {0xa2, 0xd1}, //height_ratio[7:0]
620 {0xc8, 0x5b}, //[7:4]height_ratio[11:8]
621 {0xa1, 0xb8}, //segment_width[7:0]
622 {0xa3, 0x91}, //width_ratio[7:0]
623 {0xc0, 0x50}, //[7:4]width_ratio[11:8]
624 {0xd0, 0x05}, //segment_width_end[11:8]
625 {0xd1, 0xb2}, //segment_width_end[7:0]
626 {0xd2, 0x1f}, //col_segment
627 {0xd3, 0x00}, //row_num_start[7:0]
628 {0xd4, 0x00}, //[5:4]row_num_start[9:8] [3:0]col_seg_start
629 {0xd5, 0x00}, //[7:2]col_num_start[7:2]
630 {0xd6, 0x00}, //[2:0]col_num_start[10:8]
631 {0xd7, 0x00}, //row_seg_start
632 {0xd8, 0x00}, //col_cal_start[7:0]
633 {0xd9, 0x00}, //[2:0]col_cal_start[10:8]
634
635 /*ABB*/
636 {0xfe, 0x01},
637 {0x20, 0x02},
638 {0x21, 0x02},
639 {0x23, 0x43},
640
641 /*MIPI*/
642 {0xfe, 0x03},
643 {0x01, 0x07},
644 {0x02, 0x07},
645 {0x03, 0x92},
646 {0x04, 0x80},
647 {0x11, 0x2b},
648 {0x12, 0xf0}, //lwc 3264*5/4
649 {0x13, 0x0f},
650 {0x15, 0x10}, //LP
651 {0x16, 0x29},
652 {0x17, 0xff},
653 {0x18, 0x01},
654 {0x19, 0xaa},
655 {0x1a, 0x02},
656 {0x21, 0x05},
657 {0x22, 0x05},
658 {0x23, 0x16},
659 {0x24, 0x00},
660 {0x25, 0x12},
661 {0x26, 0x07},
662 {0x29, 0x07},
663 {0x2a, 0x08},
664 {0x2b, 0x07},
665 {0xfe, 0x00},
666 //{0x3f, 0x91},
667 {0x3f, 0x00},
668 #endif
669 {REG_NULL, 0x00},
670 };
671
672 #ifndef GC8034_2LANE_30FPS
673 /*
674 * Xclk 24Mhz
675 * max_framerate 30fps
676 * mipi_datarate per lane 672Mbps
677 */
678 static const struct regval gc8034_1632x1224_regs_2lane[] = {
679 /*SYS*/
680 {0xf2, 0x00},
681 {0xf4, 0x80},
682 {0xf5, 0x19},
683 {0xf6, 0x44},
684 {0xf8, 0x63},
685 {0xfa, 0x45},
686 {0xf9, 0x00},
687 {0xf7, 0x95},
688 {0xfc, 0x00},
689 {0xfc, 0x00},
690 {0xfc, 0xea},
691 {0xfe, 0x03},
692 {0x03, 0x9a},
693 {0xfc, 0xee},
694 {0xfe, 0x10},
695 {0xfe, 0x00},
696 {0xfe, 0x10},
697 {0xfe, 0x00},
698
699 /*ISP*/
700 {0xfe, 0x00},
701 {0x80, 0x10},
702 {0xad, 0x30},
703 {0x66, 0x2c},
704 {0xbc, 0x49},
705
706 /*Crop window*/
707 {0x90, 0x01},
708 {0x92, BINNING_STARTY}, //crop y
709 {0x94, BINNING_STARTX}, //crop x
710 {0x95, 0x04},
711 {0x96, 0xc8},
712 {0x97, 0x06},
713 {0x98, 0x60},
714
715 /*MIPI*/
716 {0xfe, 0x03},
717 {0x01, 0x07},
718 {0x02, 0x03},
719 {0x04, 0x80},
720 {0x11, 0x2b},
721 {0x12, 0xf8},
722 {0x13, 0x07},
723 {0x15, 0x10}, //LP mode
724 {0x16, 0x29},
725 {0x17, 0xff},
726 {0x18, 0x01},
727 {0x19, 0xaa},
728 {0x1a, 0x02},
729 {0x21, 0x05},
730 {0x22, 0x06},
731 {0x23, 0x16},
732 {0x24, 0x00},
733 {0x25, 0x12},
734 {0x26, 0x07},
735 {0x29, 0x07},
736 {0x2a, 0x08},
737 {0x2b, 0x07},
738 {0xfe, 0x00},
739 {0x3f, 0x00},
740
741 {REG_NULL, 0x00},
742 };
743 #endif
744
745 /*
746 * Xclk 24Mhz
747 * max_framerate 15fps
748 * mipi_datarate per lane 672Mbps
749 */
750 static const struct regval gc8034_3264x2448_regs_2lane[] = {
751 #ifdef GC8034_2LANE_30FPS
752 /* SYS */
753 {0xf2, 0x00},
754 {0xf4, 0x90},
755 {0xf5, 0x3d},
756 {0xf6, 0x44},
757 {0xf8, 0x63},
758 {0xfa, 0x42},
759 {0xf9, 0x00},
760 {0xf7, 0x95},
761 {0xfc, 0x00},
762 {0xfc, 0x00},
763 {0xfc, 0xea},
764 {0xfe, 0x03},
765 {0x03, 0x9a},
766 {0xfc, 0xee},
767 {0xfe, 0x00},
768 {0x3f, 0x00},
769 {0xfe, 0x10},
770 {0xfe, 0x00},
771 {0xfe, 0x10},
772 {0xfe, 0x00},
773
774 /* ISP */
775 {0xfe, 0x00},
776 {0x80, 0x13},
777 {0xad, 0x00},
778 {0x66, 0x0c},
779 {0xbc, 0x06},
780
781 /* Crop window */
782 {0x90, 0x01},
783 {0x92, FULL_STARTY},
784 {0x94, FULL_STARTX},
785 {0x95, 0x09},
786 {0x96, 0x90},
787 {0x97, 0x0c},
788 {0x98, 0xc0},
789
790 /* MIPI */
791 {0xfe, 0x03},
792 {0x01, 0x07},
793 {0x02, 0x04},
794 {0x04, 0x80},
795 {0x11, 0x2b},
796 {0x12, 0xf0}, //lwc 3264*5/4
797 {0x13, 0x0f},
798 {0x15, 0x10}, //LP
799 {0x16, 0x29},
800 {0x17, 0xff},
801 {0x18, 0x01},
802 {0x19, 0xaa},
803 {0x1a, 0x02},
804 {0x21, 0x0c},
805 {0x22, 0x0c},
806 {0x23, 0x56},
807 {0x24, 0x00},
808 {0x25, 0x1c},
809 {0x26, 0x0b},
810 {0x29, 0x0e},
811 {0x2a, 0x1d},
812 {0x2b, 0x0b},
813 {0xfe, 0x00},
814 //{0x3f, 0x91},
815 {0x3f, 0x00},
816 #else
817 /*SYS*/
818 {0xf2, 0x00},
819 {0xf4, 0x80},
820 {0xf5, 0x19},
821 {0xf6, 0x44},
822 {0xf7, 0x95}, //pll enable
823 {0xf8, 0x63}, //pll mode
824 {0xf9, 0x00},
825 {0xfa, 0x45},
826 {0xfc, 0x00},
827 {0xfc, 0x00},
828 {0xfc, 0xfe},
829
830 /* ISP */
831 {0xfe, 0x00},
832 {0x80, 0x13},
833 {0xad, 0x00},
834 {0x66, 0x0c},
835 {0xbc, 0x09},
836
837 /* Crop window */
838 {0x90, 0x01},
839 {0x92, FULL_STARTY},
840 {0x94, FULL_STARTX},
841 {0x95, 0x09},
842 {0x96, 0x90},
843 {0x97, 0x0c},
844 {0x98, 0xc0},
845
846 /* MIPI */
847 {0xfe, 0x03},
848 {0x01, 0x07},
849 {0x02, 0x03},
850 {0x03, 0x92},
851 {0x04, 0x80},
852 {0x11, 0x2b},
853 {0x12, 0xf0}, //lwc 3264*5/4
854 {0x13, 0x0f},
855 {0x15, 0x10}, //LP
856 {0x16, 0x29},
857 {0x17, 0xff},
858 {0x18, 0x01},
859 {0x19, 0xaa},
860 {0x1a, 0x02},
861 {0x21, 0x05},
862 {0x22, 0x05},
863 {0x23, 0x16},
864 {0x24, 0x00},
865 {0x25, 0x12},
866 {0x26, 0x07},
867 {0x29, 0x07},
868 {0x2a, 0x08},
869 {0x2b, 0x07},
870 {0xfe, 0x00},
871 //{0x3f, 0x91},
872 {0x3f, 0x00},
873 #endif
874 {REG_NULL, 0x00},
875 };
876
877 /*
878 * Xclk 24Mhz
879 */
880 static const struct regval gc8034_global_regs_4lane[] = {
881 /*SYS*/
882 {0xf2, 0x00},
883 {0xf4, 0x80},
884 {0xf5, 0x19},
885 {0xf6, 0x44},
886 {0xf8, 0x63},
887 {0xfa, 0x45},
888 {0xf9, 0x00},
889 {0xf7, 0x9d},
890 {0xfc, 0x00},
891 {0xfc, 0x00},
892 {0xfc, 0xea},
893 {0xfe, 0x03},
894 {0x03, 0x9a},
895 {0x18, 0x07},
896 {0x01, 0x07},
897 {0xfc, 0xee},
898 /*Cisctl&Analog*/
899 {0xfe, 0x00},
900 {0x03, 0x08},
901 {0x04, 0xc6},
902 {0x05, 0x02},
903 {0x06, 0x16},
904 {0x07, 0x00},
905 {0x08, 0x10},
906 {0x0a, 0x3a},
907 {0x0b, 0x00},
908 {0x0c, 0x04},
909 {0x0d, 0x09},
910 {0x0e, 0xa0},
911 {0x0f, 0x0c},
912 {0x10, 0xd4},
913 {0x17, 0xc0},
914 {0x18, 0x02},
915 {0x19, 0x17},
916 {0x1e, 0x50},
917 {0x1f, 0x80},
918 {0x21, 0x4c},
919 {0x25, 0x00},
920 {0x28, 0x4a},
921 {0x2d, 0x89},
922 {0xca, 0x02},
923 {0xcb, 0x00},
924 {0xcc, 0x39},
925 {0xce, 0xd0},
926 {0xcf, 0x93},
927 {0xd0, 0x19},
928 {0xd1, 0xaa},
929 {0xd2, 0xcb},
930 {0xd8, 0x40},
931 {0xd9, 0xff},
932 {0xda, 0x0e},
933 {0xdb, 0xb0},
934 {0xdc, 0x0e},
935 {0xde, 0x08},
936 {0xe4, 0xc6},
937 {0xe5, 0x08},
938 {0xe6, 0x10},
939 {0xed, 0x2a},
940 {0xfe, 0x02},
941 {0x59, 0x02},
942 {0x5a, 0x04},
943 {0x5b, 0x08},
944 {0x5c, 0x20},
945 {0xfe, 0x00},
946 {0x1a, 0x09},
947 {0x1d, 0x13},
948 {0xfe, 0x10},
949 {0xfe, 0x00},
950 {0xfe, 0x10},
951 {0xfe, 0x00},
952 /*Gamma*/
953 {0xfe, 0x00},
954 {0x20, 0x55},
955 {0x33, 0x83},
956 {0xfe, 0x01},
957 {0xdf, 0x06},
958 {0xe7, 0x18},
959 {0xe8, 0x20},
960 {0xe9, 0x16},
961 {0xea, 0x17},
962 {0xeb, 0x50},
963 {0xec, 0x6c},
964 {0xed, 0x9b},
965 {0xee, 0xd8},
966 /*ISP*/
967 {0xfe, 0x00},
968 {0x80, 0x10},
969 {0x84, 0x01},
970 {0x88, 0x03},
971 {0x89, 0x03},
972 {0x8d, 0x03},
973 {0x8f, 0x14},
974 {0xad, 0x30},
975 {0x66, 0x2c},
976 {0xbc, 0x49},
977 {0xc2, 0x7f},
978 {0xc3, 0xff},
979 /*Crop window*/
980 {0x90, 0x01},
981 {0x92, 0x08},
982 {0x94, 0x09},
983 {0x95, 0x04},
984 {0x96, 0xc8},
985 {0x97, 0x06},
986 {0x98, 0x60},
987 /*Gain*/
988 {0xb0, 0x90},
989 {0xb1, 0x01},
990 {0xb2, 0x00},
991 {0xb6, 0x00},
992 /*BLK*/
993 {0xfe, 0x00},
994 {0x40, 0x22},
995 {0x41, 0x20},
996 {0x42, 0x02},
997 {0x43, 0x08},
998 {0x4e, 0x0f},
999 {0x4f, 0xf0},
1000 {0x58, 0x80},
1001 {0x59, 0x80},
1002 {0x5a, 0x80},
1003 {0x5b, 0x80},
1004 {0x5c, 0x00},
1005 {0x5d, 0x00},
1006 {0x5e, 0x00},
1007 {0x5f, 0x00},
1008 {0x6b, 0x01},
1009 {0x6c, 0x00},
1010 {0x6d, 0x0c},
1011 /*WB offset*/
1012 {0xfe, 0x01},
1013 {0xbf, 0x40},
1014 /*Dark Sun*/
1015 {0xfe, 0x01},
1016 {0x68, 0x77},
1017 /*DPC*/
1018 {0xfe, 0x01},
1019 {0x60, 0x00},
1020 {0x61, 0x10},
1021 {0x62, 0x28},
1022 {0x63, 0x10},
1023 {0x64, 0x02},
1024 /*LSC*/
1025 {0xfe, 0x01},
1026 {0xa8, 0x60},
1027 {0xa2, 0xd1},
1028 {0xc8, 0x57},
1029 {0xa1, 0xb8},
1030 {0xa3, 0x91},
1031 {0xc0, 0x50},
1032 {0xd0, 0x05},
1033 {0xd1, 0xb2},
1034 {0xd2, 0x1f},
1035 {0xd3, 0x00},
1036 {0xd4, 0x00},
1037 {0xd5, 0x00},
1038 {0xd6, 0x00},
1039 {0xd7, 0x00},
1040 {0xd8, 0x00},
1041 {0xd9, 0x00},
1042 {0xa4, 0x10},
1043 {0xa5, 0x20},
1044 {0xa6, 0x60},
1045 {0xa7, 0x80},
1046 {0xab, 0x18},
1047 {0xc7, 0xc0},
1048 /*ABB*/
1049 {0xfe, 0x01},
1050 {0x20, 0x02},
1051 {0x21, 0x02},
1052 {0x23, 0x42},
1053 /*MIPI*/
1054 {0xfe, 0x03},
1055 {0x02, 0x03},
1056 {0x04, 0x80},
1057 {0x11, 0x2b},
1058 {0x12, 0xf8},
1059 {0x13, 0x07},
1060 {0x15, 0x10},
1061 {0x16, 0x29},
1062 {0x17, 0xff},
1063 {0x19, 0xaa},
1064 {0x1a, 0x02},
1065 {0x21, 0x02},
1066 {0x22, 0x03},
1067 {0x23, 0x0a},
1068 {0x24, 0x00},
1069 {0x25, 0x12},
1070 {0x26, 0x04},
1071 {0x29, 0x04},
1072 {0x2a, 0x02},
1073 {0x2b, 0x04},
1074 {0xfe, 0x00},
1075 {0x3f, 0x00},
1076
1077 /*SYS*/
1078 {0xf2, 0x00},
1079 {0xf4, 0x80},
1080 {0xf5, 0x19},
1081 {0xf6, 0x44},
1082 {0xf8, 0x63},
1083 {0xfa, 0x45},
1084 {0xf9, 0x00},
1085 {0xf7, 0x95},
1086 {0xfc, 0x00},
1087 {0xfc, 0x00},
1088 {0xfc, 0xea},
1089 {0xfe, 0x03},
1090 {0x03, 0x9a},
1091 {0x18, 0x07},
1092 {0x01, 0x07},
1093 {0xfc, 0xee},
1094 /*ISP*/
1095 {0xfe, 0x00},
1096 {0x80, 0x13},
1097 {0xad, 0x00},
1098 /*Crop window*/
1099 {0x90, 0x01},
1100 {0x92, 0x08},
1101 {0x94, 0x09},
1102 {0x95, 0x09},
1103 {0x96, 0x90},
1104 {0x97, 0x0c},
1105 {0x98, 0xc0},
1106 /*DPC*/
1107 {0xfe, 0x01},
1108 {0x62, 0x60},
1109 {0x63, 0x48},
1110 /*MIPI*/
1111 {0xfe, 0x03},
1112 {0x02, 0x03},
1113 {0x04, 0x80},
1114 {0x11, 0x2b},
1115 {0x12, 0xf0},
1116 {0x13, 0x0f},
1117 {0x15, 0x10},
1118 {0x16, 0x29},
1119 {0x17, 0xff},
1120 {0x19, 0xaa},
1121 {0x1a, 0x02},
1122 {0x21, 0x05},
1123 {0x22, 0x06},
1124 {0x23, 0x2b},
1125 {0x24, 0x00},
1126 {0x25, 0x12},
1127 {0x26, 0x07},
1128 {0x29, 0x07},
1129 {0x2a, 0x12},
1130 {0x2b, 0x07},
1131 {0xfe, 0x00},
1132 {0x3f, 0x00},
1133
1134 {REG_NULL, 0x00},
1135 };
1136
1137 /*
1138 * Xclk 24Mhz
1139 * max_framerate 30fps
1140 * mipi_datarate per lane 656Mbps
1141 */
1142 static const struct regval gc8034_3264x2448_regs_4lane[] = {
1143 {REG_NULL, 0x00},
1144 };
1145
1146 static const struct gc8034_mode supported_modes_2lane[] = {
1147 #ifdef GC8034_2LANE_30FPS
1148 {
1149 .width = 3264,
1150 .height = 2448,
1151 .max_fps = {
1152 .numerator = 10000,
1153 .denominator = 300000,
1154 },
1155 .exp_def = 0x0900,
1156 .hts_def = 0x0858 * 2,
1157 .vts_def = 0x09c0,
1158 .mipi_freq_idx = 1,
1159 .global_reg_list = gc8034_global_regs_2lane,
1160 .reg_list = gc8034_3264x2448_regs_2lane,
1161 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1162 },
1163 #else
1164 {
1165 .width = 3264,
1166 .height = 2448,
1167 .max_fps = {
1168 .numerator = 10000,
1169 .denominator = 150000,
1170 },
1171 .exp_def = 0x09a0,
1172 .hts_def = 0x0858 * 2,
1173 .vts_def = 0x09c4,
1174 .mipi_freq_idx = 0,
1175 .global_reg_list = gc8034_global_regs_2lane,
1176 .reg_list = gc8034_3264x2448_regs_2lane,
1177 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1178 },
1179 {
1180 .width = 1632,
1181 .height = 1224,
1182 .max_fps = {
1183 .numerator = 10000,
1184 .denominator = 300000,
1185 },
1186 .exp_def = 0x09a0,
1187 .hts_def = 0x0858 * 2,
1188 .vts_def = 0x09c4,
1189 .mipi_freq_idx = 0,
1190 .global_reg_list = gc8034_global_regs_2lane,
1191 .reg_list = gc8034_1632x1224_regs_2lane,
1192 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1193 },
1194 #endif
1195 };
1196
1197 static const struct gc8034_mode supported_modes_4lane[] = {
1198 {
1199 .width = 3264,
1200 .height = 2448,
1201 .max_fps = {
1202 .numerator = 10000,
1203 .denominator = 300000,
1204 },
1205 .exp_def = 0x08c6,
1206 .hts_def = 0x10b0,
1207 .vts_def = 0x09c0,
1208 .mipi_freq_idx = 0,
1209 .global_reg_list = gc8034_global_regs_4lane,
1210 .reg_list = gc8034_3264x2448_regs_4lane,
1211 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1212 },
1213 };
1214
1215 static const struct gc8034_mode *supported_modes;
1216
1217 static const s64 link_freq_menu_items[] = {
1218 GC8034_MIPI_FREQ_336MHZ,
1219 GC8034_MIPI_FREQ_634MHZ
1220 };
1221
1222 /* Write registers up to 4 at a time */
gc8034_write_reg(struct i2c_client * client,u8 reg,u8 val)1223 static int gc8034_write_reg(struct i2c_client *client, u8 reg, u8 val)
1224 {
1225 struct i2c_msg msg;
1226 u8 buf[2];
1227 int ret;
1228
1229 buf[0] = reg & 0xFF;
1230 buf[1] = val;
1231
1232 msg.addr = client->addr;
1233 msg.flags = client->flags;
1234 msg.buf = buf;
1235 msg.len = sizeof(buf);
1236
1237 ret = i2c_transfer(client->adapter, &msg, 1);
1238 if (ret >= 0)
1239 return 0;
1240
1241 dev_err(&client->dev,
1242 "gc8034 write reg(0x%x val:0x%x) failed !\n", reg, val);
1243
1244 return ret;
1245 }
1246
gc8034_write_array(struct i2c_client * client,const struct regval * regs)1247 static int gc8034_write_array(struct i2c_client *client,
1248 const struct regval *regs)
1249 {
1250 u32 i = 0;
1251 int ret = 0;
1252
1253 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
1254 ret = gc8034_write_reg(client, regs[i].addr, regs[i].val);
1255
1256 return ret;
1257 }
1258
1259 /* Read registers up to 4 at a time */
gc8034_read_reg(struct i2c_client * client,u8 reg,u8 * val)1260 static int gc8034_read_reg(struct i2c_client *client, u8 reg, u8 *val)
1261 {
1262 struct i2c_msg msg[2];
1263 u8 buf[1];
1264 int ret;
1265
1266 buf[0] = reg & 0xFF;
1267
1268 msg[0].addr = client->addr;
1269 msg[0].flags = client->flags;
1270 msg[0].buf = buf;
1271 msg[0].len = sizeof(buf);
1272
1273 msg[1].addr = client->addr;
1274 msg[1].flags = client->flags | I2C_M_RD;
1275 msg[1].buf = buf;
1276 msg[1].len = 1;
1277
1278 ret = i2c_transfer(client->adapter, msg, 2);
1279 if (ret >= 0) {
1280 *val = buf[0];
1281 return 0;
1282 }
1283
1284 dev_err(&client->dev,
1285 "gc8034 read reg:0x%x failed !\n", reg);
1286
1287 return ret;
1288 }
1289
gc8034_get_reso_dist(const struct gc8034_mode * mode,struct v4l2_mbus_framefmt * framefmt)1290 static int gc8034_get_reso_dist(const struct gc8034_mode *mode,
1291 struct v4l2_mbus_framefmt *framefmt)
1292 {
1293 return abs(mode->width - framefmt->width) +
1294 abs(mode->height - framefmt->height);
1295 }
1296
1297 static const struct gc8034_mode *
gc8034_find_best_fit(struct gc8034 * gc8034,struct v4l2_subdev_format * fmt)1298 gc8034_find_best_fit(struct gc8034 *gc8034,
1299 struct v4l2_subdev_format *fmt)
1300 {
1301 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1302 int dist;
1303 int cur_best_fit = 0;
1304 int cur_best_fit_dist = -1;
1305 unsigned int i;
1306
1307 for (i = 0; i < gc8034->cfg_num; i++) {
1308 dist = gc8034_get_reso_dist(&supported_modes[i], framefmt);
1309 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1310 cur_best_fit_dist = dist;
1311 cur_best_fit = i;
1312 }
1313 }
1314
1315 return &supported_modes[cur_best_fit];
1316 }
1317
gc8034_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1318 static int gc8034_set_fmt(struct v4l2_subdev *sd,
1319 struct v4l2_subdev_pad_config *cfg,
1320 struct v4l2_subdev_format *fmt)
1321 {
1322 struct gc8034 *gc8034 = to_gc8034(sd);
1323 const struct gc8034_mode *mode;
1324 s64 h_blank, vblank_def;
1325
1326 mutex_lock(&gc8034->mutex);
1327
1328 mode = gc8034_find_best_fit(gc8034, fmt);
1329 fmt->format.code = GC8034_MEDIA_BUS_FMT;
1330 fmt->format.width = mode->width;
1331 fmt->format.height = mode->height;
1332 fmt->format.field = V4L2_FIELD_NONE;
1333 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1334 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1335 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1336 #else
1337 mutex_unlock(&gc8034->mutex);
1338 return -ENOTTY;
1339 #endif
1340 } else {
1341 gc8034->cur_mode = mode;
1342 h_blank = mode->hts_def - mode->width;
1343 __v4l2_ctrl_modify_range(gc8034->hblank, h_blank,
1344 h_blank, 1, h_blank);
1345 vblank_def = mode->vts_def - mode->height;
1346 __v4l2_ctrl_modify_range(gc8034->vblank, vblank_def,
1347 GC8034_VTS_MAX - mode->height,
1348 1, vblank_def);
1349 __v4l2_ctrl_s_ctrl(gc8034->vblank, vblank_def);
1350 __v4l2_ctrl_s_ctrl(gc8034->link_freq, mode->mipi_freq_idx);
1351 }
1352
1353 mutex_unlock(&gc8034->mutex);
1354
1355 return 0;
1356 }
1357
gc8034_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1358 static int gc8034_get_fmt(struct v4l2_subdev *sd,
1359 struct v4l2_subdev_pad_config *cfg,
1360 struct v4l2_subdev_format *fmt)
1361 {
1362 struct gc8034 *gc8034 = to_gc8034(sd);
1363 const struct gc8034_mode *mode = gc8034->cur_mode;
1364
1365 mutex_lock(&gc8034->mutex);
1366 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1367 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1368 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1369 #else
1370 mutex_unlock(&gc8034->mutex);
1371 return -ENOTTY;
1372 #endif
1373 } else {
1374 fmt->format.width = mode->width;
1375 fmt->format.height = mode->height;
1376 fmt->format.code = GC8034_MEDIA_BUS_FMT;
1377 fmt->format.field = V4L2_FIELD_NONE;
1378 }
1379 mutex_unlock(&gc8034->mutex);
1380
1381 return 0;
1382 }
1383
gc8034_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1384 static int gc8034_enum_mbus_code(struct v4l2_subdev *sd,
1385 struct v4l2_subdev_pad_config *cfg,
1386 struct v4l2_subdev_mbus_code_enum *code)
1387 {
1388 if (code->index != 0)
1389 return -EINVAL;
1390 code->code = GC8034_MEDIA_BUS_FMT;
1391
1392 return 0;
1393 }
1394
gc8034_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1395 static int gc8034_enum_frame_sizes(struct v4l2_subdev *sd,
1396 struct v4l2_subdev_pad_config *cfg,
1397 struct v4l2_subdev_frame_size_enum *fse)
1398 {
1399 struct gc8034 *gc8034 = to_gc8034(sd);
1400
1401 if (fse->index >= gc8034->cfg_num)
1402 return -EINVAL;
1403
1404 if (fse->code != GC8034_MEDIA_BUS_FMT)
1405 return -EINVAL;
1406
1407 fse->min_width = supported_modes[fse->index].width;
1408 fse->max_width = supported_modes[fse->index].width;
1409 fse->max_height = supported_modes[fse->index].height;
1410 fse->min_height = supported_modes[fse->index].height;
1411
1412 return 0;
1413 }
1414
gc8034_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1415 static int gc8034_g_frame_interval(struct v4l2_subdev *sd,
1416 struct v4l2_subdev_frame_interval *fi)
1417 {
1418 struct gc8034 *gc8034 = to_gc8034(sd);
1419 const struct gc8034_mode *mode = gc8034->cur_mode;
1420
1421 fi->interval = mode->max_fps;
1422
1423 return 0;
1424 }
1425
1426 #ifdef RK_OTP
gc8034_get_otp(struct otp_info * otp,struct rkmodule_inf * inf)1427 static void gc8034_get_otp(struct otp_info *otp,
1428 struct rkmodule_inf *inf)
1429 {
1430 u32 i, j;
1431 u32 w, h;
1432
1433 /* awb */
1434 if (otp->awb_data.flag) {
1435 inf->awb.flag = 1;
1436 inf->awb.r_value = otp->awb_data.r_ratio;
1437 inf->awb.b_value = otp->awb_data.b_ratio;
1438 inf->awb.gr_value = otp->awb_data.g_ratio;
1439 inf->awb.gb_value = 0x0;
1440
1441 inf->awb.golden_r_value = otp->awb_data.r_golden;
1442 inf->awb.golden_b_value = otp->awb_data.b_golden;
1443 inf->awb.golden_gr_value = otp->awb_data.g_golden;
1444 inf->awb.golden_gb_value = 0x0;
1445 }
1446
1447 /* lsc */
1448 if (otp->lsc_data.flag) {
1449 inf->lsc.flag = 1;
1450 inf->lsc.width = otp->basic_data.size.width;
1451 inf->lsc.height = otp->basic_data.size.height;
1452 inf->lsc.table_size = otp->lsc_data.table_size;
1453
1454 for (i = 0; i < 289; i++) {
1455 inf->lsc.lsc_r[i] = (otp->lsc_data.data[i * 2] << 8) |
1456 otp->lsc_data.data[i * 2 + 1];
1457 inf->lsc.lsc_gr[i] = (otp->lsc_data.data[i * 2 + 578] << 8) |
1458 otp->lsc_data.data[i * 2 + 579];
1459 inf->lsc.lsc_gb[i] = (otp->lsc_data.data[i * 2 + 1156] << 8) |
1460 otp->lsc_data.data[i * 2 + 1157];
1461 inf->lsc.lsc_b[i] = (otp->lsc_data.data[i * 2 + 1734] << 8) |
1462 otp->lsc_data.data[i * 2 + 1735];
1463 }
1464 }
1465
1466 /* pdaf */
1467 if (otp->pdaf_data.flag) {
1468 inf->pdaf.flag = 1;
1469 inf->pdaf.gainmap_width = otp->pdaf_data.gainmap_width;
1470 inf->pdaf.gainmap_height = otp->pdaf_data.gainmap_height;
1471 inf->pdaf.dcc_mode = otp->pdaf_data.dcc_mode;
1472 inf->pdaf.dcc_dir = otp->pdaf_data.dcc_dir;
1473 inf->pdaf.dccmap_width = otp->pdaf_data.dccmap_width;
1474 inf->pdaf.dccmap_height = otp->pdaf_data.dccmap_height;
1475 w = otp->pdaf_data.gainmap_width;
1476 h = otp->pdaf_data.gainmap_height;
1477 for (i = 0; i < h; i++) {
1478 for (j = 0; j < w; j++) {
1479 inf->pdaf.gainmap[i * w + j] =
1480 (otp->pdaf_data.gainmap[(i * w + j) * 2] << 8) |
1481 otp->pdaf_data.gainmap[(i * w + j) * 2 + 1];
1482 }
1483 }
1484 w = otp->pdaf_data.dccmap_width;
1485 h = otp->pdaf_data.dccmap_height;
1486 for (i = 0; i < h; i++) {
1487 for (j = 0; j < w; j++) {
1488 inf->pdaf.dccmap[i * w + j] =
1489 (otp->pdaf_data.dccmap[(i * w + j) * 2] << 8) |
1490 otp->pdaf_data.dccmap[(i * w + j) * 2 + 1];
1491 }
1492 }
1493 }
1494
1495 /* af */
1496 if (otp->af_data.flag) {
1497 inf->af.flag = 1;
1498 inf->af.dir_cnt = 1;
1499 inf->af.af_otp[0].vcm_start = otp->af_data.af_inf;
1500 inf->af.af_otp[0].vcm_end = otp->af_data.af_macro;
1501 inf->af.af_otp[0].vcm_dir = 0;
1502 }
1503
1504 }
1505 #else
1506 #define DD_WIDTH 3284
1507 #define DD_HEIGHT 2464
1508
1509 #define DD_PARAM_QTY 350
1510 #define WINDOW_WIDTH 0x0cd4//3284 max effective pixels
1511 #define WINDOW_HEIGHT 0x09a0//2462
1512 #define REG_ROM_START 0x4e
1513 #define INFO_ROM_START 0x70
1514 #define INFO_WIDTH 0x08
1515 #define WB_ROM_START 0x5f
1516 #define WB_WIDTH 0x04
1517 #define GOLDEN_ROM_START 0x67//golden R/G ratio
1518 #define GOLDEN_WIDTH 0x04
1519 #define LSC_NUM 99//0x63 //(7+2)*(9+2)
1520 #define VCM_START 0x3B
1521 #define VCM_WIDTH 0x04
1522
gc8034_otp_read_reg(struct i2c_client * client,int page,int address)1523 static int gc8034_otp_read_reg(struct i2c_client *client,
1524 int page, int address)
1525 {
1526 int ret = 0;
1527 u8 val = 0;
1528
1529 ret = gc8034_write_reg(client, 0xfe, 0x00);
1530 ret |= gc8034_write_reg(client, 0xD4,
1531 ((page << 2) & 0x3c) + ((address >> 5) & 0x03));
1532 ret |= gc8034_write_reg(client, 0xD5,
1533 (address << 3) & 0xff);
1534 ret |= gc8034_write_reg(client, 0xF3,
1535 0x20);
1536 ret |= gc8034_read_reg(client, 0xD7, &val);
1537 if (ret != 0)
1538 return ret;
1539 return val;
1540 }
1541
gc8034_otp_read_group(struct i2c_client * client,int page,int address,u8 * buf,int size)1542 static int gc8034_otp_read_group(struct i2c_client *client,
1543 int page, int address, u8 *buf, int size)
1544 {
1545 int i = 0;
1546 int val = 0;
1547
1548 for (i = 0; i < size; i++) {
1549 if ((address % 0x80) == 0) {
1550 page += 1;
1551 address = 0;
1552 }
1553 val = gc8034_otp_read_reg(client, page, address);
1554 if (val >= 0)
1555 buf[i] = val;
1556 else
1557 return val;
1558 address += 1;
1559 }
1560 return 0;
1561 }
1562
gc8034_otp_enable(struct gc8034 * gc8034)1563 static int gc8034_otp_enable(struct gc8034 *gc8034)
1564 {
1565 struct i2c_client *client = gc8034->client;
1566 u8 otp_clk = 0;
1567 u8 otp_en = 0;
1568 int ret = 0;
1569
1570 ret = gc8034_write_reg(client, 0xf2, 0x00);
1571 ret |= gc8034_write_reg(client, 0xf4, 0x80);
1572 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1573 ret |= gc8034_write_reg(client, 0xf7, 0x97);
1574 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1575 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1576 ret |= gc8034_write_reg(client, 0xfc, 0xee);
1577 ret |= gc8034_read_reg(client, 0xF2, &otp_clk);
1578 ret |= gc8034_read_reg(client, 0xF4, &otp_en);
1579 otp_clk |= 0x01;
1580 otp_en |= 0x08;
1581 ret |= gc8034_write_reg(client, 0xF2, otp_clk);
1582 ret |= gc8034_write_reg(client, 0xF4, otp_en);
1583 usleep_range(100, 200);
1584 return ret;
1585 }
1586
gc8034_otp_disable(struct gc8034 * gc8034)1587 static int gc8034_otp_disable(struct gc8034 *gc8034)
1588 {
1589 struct i2c_client *client = gc8034->client;
1590 u8 otp_clk = 0;
1591 u8 otp_en = 0;
1592 int ret = 0;
1593
1594 ret = gc8034_read_reg(client, 0xF2, &otp_clk);
1595 ret |= gc8034_read_reg(client, 0xF4, &otp_en);
1596 otp_clk &= 0xFE;
1597 otp_en &= 0xF7;
1598 ret |= gc8034_write_reg(client, 0xF2, otp_clk);
1599 ret |= gc8034_write_reg(client, 0xF4, otp_en);
1600 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1601 ret |= gc8034_write_reg(client, 0xf7, 0x95);
1602 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1603 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1604 ret |= gc8034_write_reg(client, 0xfc, 0xee);
1605 return ret;
1606 }
1607
gc8034_check_prsel(struct gc8034 * gc8034)1608 static void gc8034_check_prsel(struct gc8034 *gc8034)
1609 {
1610 struct i2c_client *client = gc8034->client;
1611 u8 product_level = 0;
1612
1613 gc8034_write_reg(client, 0xfe, 0x02);
1614 gc8034_read_reg(client, 0x68, &product_level);
1615 product_level &= 0x07;
1616
1617 if (product_level == 0x00 || product_level == 0x01) {
1618 gc8034_write_reg(client, 0xfe, 0x00);
1619 gc8034_write_reg(client, 0xd2, 0xcb);
1620 } else {
1621 gc8034_write_reg(client, 0xfe, 0x00);
1622 gc8034_write_reg(client, 0xd2, 0xc3);
1623 }
1624 }
1625
gc8034_otp_read(struct gc8034 * gc8034)1626 static int gc8034_otp_read(struct gc8034 *gc8034)
1627 {
1628 int otp_flag, i, j, index, temp;
1629 struct gc8034_otp_info *otp_ptr;
1630 struct device *dev = &gc8034->client->dev;
1631 struct i2c_client *client = gc8034->client;
1632 int ret = 0;
1633 int cnt = 0;
1634 int checksum = 0;
1635 u8 info[8] = {0};
1636 u8 wb[4] = {0};
1637 u8 vcm[4] = {0};
1638 u8 golden[4] = {0};
1639 int total_number = 0;
1640 u8 ddtempbuff[4 * 80] = { 0 };
1641
1642 otp_ptr = devm_kzalloc(dev, sizeof(*otp_ptr), GFP_KERNEL);
1643 if (!otp_ptr)
1644 return -ENOMEM;
1645
1646 /* OTP base information*/
1647 otp_flag = gc8034_otp_read_reg(client, 9, 0x6f);
1648 for (index = 0; index < 2; index++) {
1649 switch ((otp_flag << (2 * index)) & 0x0c) {
1650 case 0x00:
1651 dev_err(dev, "%s GC8034_OTP_INFO group %d is Empty!\n",
1652 __func__, index + 1);
1653 break;
1654 case 0x04:
1655 dev_err(dev, "%s GC8034_OTP_INFO group %d is Valid!\n",
1656 __func__, index + 1);
1657 checksum = 0;
1658 ret |= gc8034_otp_read_group(client, 9,
1659 (INFO_ROM_START + index * INFO_WIDTH),
1660 &info[0], INFO_WIDTH);
1661 if (ret < 0) {
1662 dev_err(dev, "%s read otp error!\n", __func__);
1663 return ret;
1664 }
1665 for (i = 0; i < INFO_WIDTH - 1; i++)
1666 checksum += info[i];
1667 if ((checksum % 255 + 1) == info[INFO_WIDTH - 1]) {
1668 otp_ptr->flag = 0x80;
1669 otp_ptr->module_id = info[0];
1670 otp_ptr->lens_id = info[1];
1671 otp_ptr->year = info[4];
1672 otp_ptr->month = info[5];
1673 otp_ptr->day = info[6];
1674 dev_err(dev, "fac info: module(0x%x) lens(0x%x) time(%d_%d_%d)!\n",
1675 otp_ptr->module_id,
1676 otp_ptr->lens_id,
1677 otp_ptr->year,
1678 otp_ptr->month,
1679 otp_ptr->day);
1680 } else {
1681 dev_err(dev, "%s GC8034_OTP_INFO Check sum %d Error!\n",
1682 __func__, index + 1);
1683 }
1684 break;
1685 case 0x08:
1686 case 0x0c:
1687 dev_err(dev, "%s GC8034_OTP_INFO group %d is Invalid !!\n",
1688 __func__, index + 1);
1689 break;
1690 default:
1691 break;
1692 }
1693 }
1694
1695 /* OTP WB calibration data */
1696 otp_flag = gc8034_otp_read_reg(client, 9, 0x5e);
1697 for (index = 0; index < 2; index++) {
1698 switch ((otp_flag << (2 * index)) & 0x0c) {
1699 case 0x00:
1700 dev_err(dev, "%s GC8034_OTP_WB group %d is Empty !\n",
1701 __func__, index + 1);
1702 break;
1703 case 0x04:
1704 dev_err(dev, "%s GC8034_OTP_WB group %d is Valid !!\n",
1705 __func__, index + 1);
1706 checksum = 0;
1707 ret |= gc8034_otp_read_group(client,
1708 9,
1709 (WB_ROM_START + index * WB_WIDTH),
1710 &wb[0],
1711 WB_WIDTH);
1712 if (ret < 0) {
1713 dev_err(dev, "%s read otp error!\n", __func__);
1714 return ret;
1715 }
1716 for (i = 0; i < WB_WIDTH - 1; i++)
1717 checksum += wb[i];
1718 if ((checksum % 255 + 1) == wb[WB_WIDTH - 1]) {
1719 otp_ptr->flag |= 0x40; /* valid AWB in OTP */
1720 otp_ptr->rg_ratio =
1721 ((wb[1] & 0xf0) << 4) | wb[0];
1722 otp_ptr->bg_ratio =
1723 ((wb[1] & 0x0f) << 8) | wb[2];
1724 dev_err(dev, "otp:(rg_ratio 0x%x, bg_ratio 0x%x)\n",
1725 otp_ptr->rg_ratio, otp_ptr->bg_ratio);
1726 } else {
1727 dev_err(dev, "%s GC8034_OTP_WB Check sum %d Error !!\n",
1728 __func__, index + 1);
1729 }
1730 break;
1731 case 0x08:
1732 case 0x0c:
1733 dev_err(dev, "%s GC8034_OTP_WB group %d is Invalid !!\n",
1734 __func__, index + 1);
1735 break;
1736 default:
1737 break;
1738 }
1739 switch ((otp_flag << (2 * index)) & 0xc0) {
1740 case 0x00:
1741 dev_err(dev, "%s GC8034_OTP_GOLDEN group %d is Empty!\n",
1742 __func__, index + 1);
1743 break;
1744 case 0x40:
1745 dev_err(dev, "%s GC8034_OTP_GOLDEN group %d is Valid !!\n",
1746 __func__, index + 1);
1747 checksum = 0;
1748 ret = gc8034_otp_read_group(client, 9,
1749 (GOLDEN_ROM_START + index * GOLDEN_WIDTH),
1750 &golden[0], GOLDEN_WIDTH);
1751 if (ret < 0) {
1752 dev_err(dev, "%s read otp error!\n", __func__);
1753 return ret;
1754 }
1755 for (i = 0; i < GOLDEN_WIDTH - 1; i++)
1756 checksum += golden[i];
1757 if ((checksum % 255 + 1) == golden[GOLDEN_WIDTH - 1]) {
1758 otp_ptr->golden_rg =
1759 golden[0] | ((golden[1] & 0xf0) << 4);
1760 otp_ptr->golden_bg =
1761 ((golden[1] & 0x0f) << 8) | golden[2];
1762 dev_err(dev, "otp:(golden_rg 0x%x, golden_bg 0x%x)\n",
1763 otp_ptr->golden_rg, otp_ptr->golden_bg);
1764 } else {
1765 dev_err(dev, "%s GC8034_OTP_GOLDEN Check sum %d Error !!\n",
1766 __func__, index + 1);
1767 }
1768 break;
1769 case 0x80:
1770 case 0xc0:
1771 dev_err(dev, "%s GC8034_OTP_GOLDEN group %d is Invalid !!\n",
1772 __func__, index + 1);
1773 break;
1774 default:
1775 break;
1776 }
1777 }
1778
1779 /* OTP VCM calibration data */
1780 otp_flag = gc8034_otp_read_reg(client, 3, 0x3A);
1781 for (index = 0; index < 2; index++) {
1782 switch ((otp_flag << (2 * index)) & 0x0c) {
1783 case 0x00:
1784 dev_err(dev, "%s GC8034_OTP_VCM group %d is Empty !\n",
1785 __func__, index + 1);
1786 break;
1787 case 0x04:
1788 dev_err(dev, "%s GC8034_OTP_VCM group %d is Valid !\n",
1789 __func__, index + 1);
1790 ret |= gc8034_otp_read_group(client,
1791 3,
1792 (VCM_START + index * VCM_WIDTH),
1793 &vcm[0],
1794 VCM_WIDTH);
1795 if (ret < 0) {
1796 dev_err(dev, "%s read otp error!\n", __func__);
1797 return ret;
1798 }
1799 checksum = 0;
1800 for (i = 0; i < 3; i++)
1801 checksum += vcm[i];
1802 if ((checksum % 255 + 1) == vcm[3]) {
1803 otp_ptr->flag |= 0x20; /* valid LSC in OTP */
1804 otp_ptr->vcm_dir = 0;//not dir register
1805 otp_ptr->vcm_start =
1806 ((vcm[0] & 0x0f) << 8) + vcm[2];
1807 otp_ptr->vcm_end =
1808 ((vcm[0] & 0xf0) << 4) + vcm[1];
1809 dev_err(dev, "%s GC8034_OTP_VCM check sum success\n",
1810 __func__);
1811 dev_err(dev, "vcm_info: 0x%x, 0x%x, 0x%x!\n",
1812 otp_ptr->vcm_start,
1813 otp_ptr->vcm_end,
1814 otp_ptr->vcm_dir);
1815 } else {
1816 dev_err(dev, "VCM check sum read: 0x%x, calculate:0x%x\n",
1817 vcm[3], checksum % 255 + 1);
1818 }
1819 break;
1820 case 0x08:
1821 case 0x0c:
1822 dev_err(dev, "%s GC8034_OTP_VCM group %d is Invalid !\n",
1823 __func__, index + 1);
1824 break;
1825 default:
1826 break;
1827 }
1828 }
1829
1830 /* OTP LSC calibration data */
1831 otp_flag = gc8034_otp_read_reg(client, 3, 0x43);
1832 for (index = 0; index < 2; index++) {
1833 switch ((otp_flag << (2 * index)) & 0x0c) {
1834 case 0x00:
1835 dev_err(dev, "%s GC8034_OTP_LSC group %d is Empty !\n",
1836 __func__, index + 1);
1837 break;
1838 case 0x04:
1839 dev_err(dev, "%s GC8034_OTP_LSC group %d is Valid !\n",
1840 __func__, index + 1);
1841 if (index == 0) {
1842 ret |= gc8034_otp_read_group(client,
1843 3, 0x44, otp_ptr->lsc, 396);
1844 temp = gc8034_otp_read_reg(client, 6, 0x50);
1845 } else {
1846 ret |= gc8034_otp_read_group(client,
1847 6, 0x51, otp_ptr->lsc, 396);
1848 temp = gc8034_otp_read_reg(client, 9, 0x5d);
1849 }
1850 checksum = 0;
1851 for (i = 0; i < 396; i++) {
1852 checksum += otp_ptr->lsc[i];
1853 usleep_range(100, 200);
1854 dev_err(dev, "otp lsc[%d] = %d\n",
1855 i, otp_ptr->lsc[i]);
1856 }
1857 if ((checksum % 255 + 1) == temp) {
1858 otp_ptr->flag |= 0x10; /* valid LSC in OTP */
1859 dev_err(dev, "%s GC8034_OTP_LSC check sum success\n",
1860 __func__);
1861 } else {
1862 dev_err(dev, "LSC check sum read: 0x%x, calculate:0x%x\n",
1863 temp, checksum % 255 + 1);
1864 }
1865 break;
1866 case 0x08:
1867 case 0x0c:
1868 dev_err(dev, "%s GC8034_OTP_LSC group %d is Invalid !\n",
1869 __func__, index + 1);
1870 break;
1871 default:
1872 break;
1873 }
1874 }
1875 /* OTP DD calibration data */
1876 otp_flag = gc8034_otp_read_reg(client, 0, 0x0b);
1877 for (index = 0; index < 2; index++) {
1878 switch (otp_flag & 0x03) {
1879 case 0x00:
1880 dev_err(dev, "%s GC8034 OTP:flag_dd is EMPTY!\n",
1881 __func__);
1882 break;
1883 case 0x04:
1884 dev_err(dev, "%s GC8034_OTP_DD group %d is valid!\n",
1885 __func__, index + 1);
1886 total_number = gc8034_otp_read_reg(client, 0, 0x0c) +
1887 gc8034_otp_read_reg(client, 0, 0x0d);
1888 ret |= gc8034_otp_read_group(client, 0, 0x0e,
1889 &ddtempbuff[0], 4 * total_number);
1890 for (i = 0; i < total_number; i++) {
1891 if ((ddtempbuff[4 * i + 3] & 0x80) == 0x80) {
1892 if ((ddtempbuff[4 * i + 3] & 0x03) == 0x03) {
1893 otp_ptr->dd_param[cnt].x =
1894 (((u16)ddtempbuff[4 * i + 1] & 0x0f) << 8) +
1895 ddtempbuff[4 * i];
1896 otp_ptr->dd_param[cnt].y =
1897 ((u16)ddtempbuff[4 * i + 2] << 4) +
1898 ((ddtempbuff[4 * i + 1] & 0xf0) >> 4);
1899 otp_ptr->dd_param[cnt++].t = 2;
1900 otp_ptr->dd_param[cnt].x =
1901 (((u16)ddtempbuff[4 * i + 1] & 0x0f) << 8) +
1902 ddtempbuff[4 * i];
1903 otp_ptr->dd_param[cnt].y =
1904 ((u16)ddtempbuff[4 * i + 2] << 4) +
1905 ((ddtempbuff[4 * i + 1] & 0xf0) >> 4) + 1;
1906 otp_ptr->dd_param[cnt++].t = 2;
1907 } else {
1908 otp_ptr->dd_param[cnt].x =
1909 (((u16)ddtempbuff[4 * i + 1] & 0x0f) << 8) +
1910 ddtempbuff[4 * i];
1911 otp_ptr->dd_param[cnt].y =
1912 ((u16)ddtempbuff[4 * i + 2] << 4) +
1913 ((ddtempbuff[4 * i + 1] & 0xf0) >> 4);
1914 otp_ptr->dd_param[cnt++].t =
1915 ddtempbuff[4 * i + 3] & 0x03;
1916 }
1917 }
1918 }
1919 otp_ptr->dd_cnt = total_number;
1920 otp_ptr->flag |= 0x08;
1921 dev_err(dev, "%s GC8034 OTP:total_number = %d!\n",
1922 __func__, total_number);
1923 break;
1924 case 0x08:
1925 case 0x0c:
1926 dev_err(dev, "%s GC8034_OTP_DD group %d is Invalid!\n",
1927 __func__, index + 1);
1928 break;
1929 default:
1930 break;
1931 }
1932 }
1933 /* OTP Chip Register*/
1934 otp_flag = gc8034_otp_read_reg(client, 2, 0x4e);
1935 if (otp_flag == 1) {
1936 for (i = 0; i < 5; i++) {
1937 dev_err(dev, "%s GC8034 reg is valid!\n", __func__);
1938 temp = gc8034_otp_read_reg(client, 2, (0x4f + 5 * i));
1939 for (j = 0; j < 2; j++) {
1940 if (((temp >> (4 * j + 3)) & 0x01) == 0x01) {
1941 otp_ptr->reg_page[otp_ptr->reg_num] =
1942 (temp >> (4 * j)) & 0x03;
1943 otp_ptr->reg_addr[otp_ptr->reg_num] =
1944 gc8034_otp_read_reg(client,
1945 2,
1946 0x50 + 5 * i + 2 * j);
1947 otp_ptr->reg_value[otp_ptr->reg_num] =
1948 gc8034_otp_read_reg(client,
1949 2,
1950 0x50 + 5 * i + 2 * j + 1);
1951 otp_ptr->reg_num++;
1952 }
1953 }
1954 }
1955 otp_ptr->flag |= 0x04;
1956 }
1957
1958 if (otp_ptr->flag) {
1959 gc8034->otp = otp_ptr;
1960 } else {
1961 gc8034->otp = NULL;
1962 devm_kfree(dev, otp_ptr);
1963 }
1964
1965 return 0;
1966 }
1967
gc8034_get_otp(struct gc8034_otp_info * otp,struct rkmodule_inf * inf)1968 static void gc8034_get_otp(struct gc8034_otp_info *otp,
1969 struct rkmodule_inf *inf)
1970 {
1971 u32 i;
1972
1973 /* fac */
1974 if (otp->flag & 0x80) {
1975 inf->fac.flag = 1;
1976 inf->fac.year = otp->year;
1977 inf->fac.month = otp->month;
1978 inf->fac.day = otp->day;
1979 for (i = 0; i < ARRAY_SIZE(gc8034_module_info) - 1; i++) {
1980 if (gc8034_module_info[i].id == otp->module_id)
1981 break;
1982 }
1983 strlcpy(inf->fac.module, gc8034_module_info[i].name,
1984 sizeof(inf->fac.module));
1985
1986 for (i = 0; i < ARRAY_SIZE(gc8034_lens_info) - 1; i++) {
1987 if (gc8034_lens_info[i].id == otp->lens_id)
1988 break;
1989 }
1990 strlcpy(inf->fac.lens, gc8034_lens_info[i].name,
1991 sizeof(inf->fac.lens));
1992 }
1993 /* awb */
1994 if (otp->flag & 0x40) {
1995 inf->awb.flag = 1;
1996 inf->awb.r_value = otp->rg_ratio;
1997 inf->awb.b_value = otp->bg_ratio;
1998 inf->awb.gr_value = 0;
1999 inf->awb.gb_value = 0;
2000
2001 inf->awb.golden_r_value = 0;
2002 inf->awb.golden_b_value = 0;
2003 inf->awb.golden_gr_value = 0;
2004 inf->awb.golden_gb_value = 0;
2005 }
2006 /* af */
2007 if (otp->flag & 0x20) {
2008 inf->af.flag = 1;
2009 inf->af.dir_cnt = 1;
2010 inf->af.af_otp[0].vcm_start = otp->vcm_start;
2011 inf->af.af_otp[0].vcm_end = otp->vcm_end;
2012 inf->af.af_otp[0].vcm_dir = otp->vcm_dir;
2013 }
2014 }
2015 #endif
2016
gc8034_get_module_inf(struct gc8034 * gc8034,struct rkmodule_inf * inf)2017 static void gc8034_get_module_inf(struct gc8034 *gc8034,
2018 struct rkmodule_inf *inf)
2019 {
2020 #ifdef RK_OTP
2021 struct otp_info *otp = gc8034->otp;
2022 #else
2023 struct gc8034_otp_info *otp = gc8034->otp;
2024 #endif
2025
2026 strlcpy(inf->base.sensor,
2027 GC8034_NAME,
2028 sizeof(inf->base.sensor));
2029 strlcpy(inf->base.module,
2030 gc8034->module_name,
2031 sizeof(inf->base.module));
2032 strlcpy(inf->base.lens,
2033 gc8034->len_name,
2034 sizeof(inf->base.lens));
2035 if (otp)
2036 gc8034_get_otp(otp, inf);
2037 }
2038
gc8034_set_module_inf(struct gc8034 * gc8034,struct rkmodule_awb_cfg * cfg)2039 static void gc8034_set_module_inf(struct gc8034 *gc8034,
2040 struct rkmodule_awb_cfg *cfg)
2041 {
2042 mutex_lock(&gc8034->mutex);
2043 memcpy(&gc8034->awb_cfg, cfg, sizeof(*cfg));
2044 mutex_unlock(&gc8034->mutex);
2045 }
2046
gc8034_get_channel_info(struct gc8034 * gc8034,struct rkmodule_channel_info * ch_info)2047 static int gc8034_get_channel_info(struct gc8034 *gc8034, struct rkmodule_channel_info *ch_info)
2048 {
2049 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
2050 return -EINVAL;
2051 ch_info->vc = gc8034->cur_mode->vc[ch_info->index];
2052 ch_info->width = gc8034->cur_mode->width;
2053 ch_info->height = gc8034->cur_mode->height;
2054 ch_info->bus_fmt = GC8034_MEDIA_BUS_FMT;
2055 return 0;
2056 }
2057
gc8034_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)2058 static long gc8034_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2059 {
2060 struct gc8034 *gc8034 = to_gc8034(sd);
2061 long ret = 0;
2062 u32 stream = 0;
2063 struct rkmodule_channel_info *ch_info;
2064
2065 switch (cmd) {
2066 case RKMODULE_GET_MODULE_INFO:
2067 gc8034_get_module_inf(gc8034, (struct rkmodule_inf *)arg);
2068 break;
2069 case RKMODULE_AWB_CFG:
2070 gc8034_set_module_inf(gc8034, (struct rkmodule_awb_cfg *)arg);
2071 break;
2072 case RKMODULE_SET_QUICK_STREAM:
2073
2074 stream = *((u32 *)arg);
2075
2076 if (stream) {
2077 ret = gc8034_write_reg(gc8034->client,
2078 GC8034_REG_SET_PAGE,
2079 GC8034_SET_PAGE_ZERO);
2080 if (2 == gc8034->lane_num) {
2081 ret |= gc8034_write_reg(gc8034->client,
2082 GC8034_REG_CTRL_MODE,
2083 0x91);
2084 } else {
2085 ret |= gc8034_write_reg(gc8034->client,
2086 GC8034_REG_CTRL_MODE,
2087 GC8034_MODE_STREAMING);
2088 }
2089 } else {
2090 ret = gc8034_write_reg(gc8034->client,
2091 GC8034_REG_SET_PAGE,
2092 GC8034_SET_PAGE_ZERO);
2093 ret |= gc8034_write_reg(gc8034->client,
2094 GC8034_REG_CTRL_MODE,
2095 GC8034_MODE_SW_STANDBY);
2096 }
2097 break;
2098 case RKMODULE_GET_CHANNEL_INFO:
2099 ch_info = (struct rkmodule_channel_info *)arg;
2100 ret = gc8034_get_channel_info(gc8034, ch_info);
2101 break;
2102 default:
2103 ret = -ENOTTY;
2104 break;
2105 }
2106
2107 return ret;
2108 }
2109
2110 #ifdef CONFIG_COMPAT
gc8034_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)2111 static long gc8034_compat_ioctl32(struct v4l2_subdev *sd,
2112 unsigned int cmd, unsigned long arg)
2113 {
2114 void __user *up = compat_ptr(arg);
2115 struct rkmodule_inf *inf;
2116 struct rkmodule_awb_cfg *cfg;
2117 long ret = 0;
2118 u32 stream = 0;
2119 struct rkmodule_channel_info *ch_info;
2120
2121 switch (cmd) {
2122 case RKMODULE_GET_MODULE_INFO:
2123 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
2124 if (!inf) {
2125 ret = -ENOMEM;
2126 return ret;
2127 }
2128
2129 ret = gc8034_ioctl(sd, cmd, inf);
2130 if (!ret) {
2131 ret = copy_to_user(up, inf, sizeof(*inf));
2132 if (ret)
2133 ret = -EFAULT;
2134 }
2135 kfree(inf);
2136 break;
2137 case RKMODULE_AWB_CFG:
2138 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2139 if (!cfg) {
2140 ret = -ENOMEM;
2141 return ret;
2142 }
2143
2144 ret = copy_from_user(cfg, up, sizeof(*cfg));
2145 if (!ret)
2146 ret = gc8034_ioctl(sd, cmd, cfg);
2147 else
2148 ret = -EFAULT;
2149 kfree(cfg);
2150 break;
2151 case RKMODULE_SET_QUICK_STREAM:
2152 ret = copy_from_user(&stream, up, sizeof(u32));
2153 if (!ret)
2154 ret = gc8034_ioctl(sd, cmd, &stream);
2155 else
2156 ret = -EFAULT;
2157 break;
2158 case RKMODULE_GET_CHANNEL_INFO:
2159 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
2160 if (!ch_info) {
2161 ret = -ENOMEM;
2162 return ret;
2163 }
2164
2165 ret = gc8034_ioctl(sd, cmd, ch_info);
2166 if (!ret) {
2167 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
2168 if (ret)
2169 ret = -EFAULT;
2170 }
2171 kfree(ch_info);
2172 break;
2173 default:
2174 ret = -ENOTTY;
2175 break;
2176 }
2177
2178 return ret;
2179 }
2180 #endif
2181
2182 #ifndef RK_OTP
2183 /*--------------------------------------------------------------------------*/
gc8034_apply_otp(struct gc8034 * gc8034)2184 static int gc8034_apply_otp(struct gc8034 *gc8034)
2185 {
2186 int R_gain, G_gain, B_gain, base_gain;
2187 struct i2c_client *client = gc8034->client;
2188 struct gc8034_otp_info *otp_ptr = gc8034->otp;
2189 struct rkmodule_awb_cfg *awb_cfg = &gc8034->awb_cfg;
2190 u32 golden_bg_ratio;
2191 u32 golden_rg_ratio;
2192 u32 golden_g_value;
2193 u32 i, j;
2194 u16 base = 0;
2195 u32 dd_cnt = 0;
2196 u8 temp_val0 = 0;
2197 u8 temp_val1 = 0;
2198 u8 temp_val2 = 0;
2199 struct gc8034_dd dd_temp = {0, 0, 0};
2200
2201 if (!gc8034->awb_cfg.enable)
2202 return 0;
2203
2204 golden_g_value = (awb_cfg->golden_gb_value +
2205 awb_cfg->golden_gr_value) / 2;
2206 golden_bg_ratio = awb_cfg->golden_b_value * 0x400 / golden_g_value;
2207 golden_rg_ratio = awb_cfg->golden_r_value * 0x400 / golden_g_value;
2208 /* apply OTP WB Calibration */
2209 if ((otp_ptr->flag & 0x40) && golden_bg_ratio && golden_rg_ratio) {
2210 /* calculate G gain */
2211 R_gain = golden_rg_ratio * 1000 / otp_ptr->rg_ratio;
2212 B_gain = golden_bg_ratio * 1000 / otp_ptr->bg_ratio;
2213 G_gain = 1000;
2214 base_gain = (R_gain < B_gain) ? R_gain : B_gain;
2215 base_gain = (base_gain < G_gain) ? base_gain : G_gain;
2216
2217 R_gain = 0x400 * R_gain / (base_gain);
2218 B_gain = 0x400 * B_gain / (base_gain);
2219 G_gain = 0x400 * G_gain / (base_gain);
2220
2221 /* update sensor WB gain */
2222 gc8034_write_reg(client, 0xfe, 0x01);
2223
2224 gc8034_write_reg(client, 0x84, G_gain >> 3);
2225 gc8034_write_reg(client, 0x85, R_gain >> 3);
2226 gc8034_write_reg(client, 0x86, B_gain >> 3);
2227 gc8034_write_reg(client, 0x87, G_gain >> 3);
2228 gc8034_write_reg(client, 0x88,
2229 ((G_gain & 0X07) << 4) + (R_gain & 0x07));
2230 gc8034_write_reg(client, 0x89,
2231 ((B_gain & 0X07) << 4) + (G_gain & 0x07));
2232
2233 gc8034_write_reg(client, 0xfe, 0x00);
2234
2235 dev_dbg(&client->dev, "apply awb gain: 0x%x, 0x%x, 0x%x\n",
2236 R_gain, G_gain, B_gain);
2237 }
2238 /* apply OTP Lenc Calibration */
2239 if (otp_ptr->flag & 0x10) {
2240 gc8034_write_reg(client, 0xfe, 0x01);
2241 gc8034_write_reg(client, 0xcf, 0x00);
2242 gc8034_write_reg(client, 0xc9, 0x01);
2243 for (i = 0; i < 9; i++) {
2244 gc8034_write_reg(client, 0xca, i * 0x0c);
2245 for (j = 0; j < 11; j++) {
2246 #if defined(GC8034_MIRROR_NORMAL)
2247 base = 4 * (11 * i + j);
2248 #elif defined(GC8034_MIRROR_H)
2249 base = 4 * (11 * i + 10 - j);
2250 #elif defined(GC8034_MIRROR_V)
2251 base = 4 * (11 * (8 - i) + j);
2252 #elif defined(GC8034_MIRROR_HV)
2253 base = 4 * (11 * (8 - i) + 10 - j);
2254 #endif
2255 gc8034_write_reg(client, 0xcc,
2256 otp_ptr->lsc[base + 0]);
2257 gc8034_write_reg(client, 0xcc,
2258 otp_ptr->lsc[base + 1]);
2259 gc8034_write_reg(client, 0xcc,
2260 otp_ptr->lsc[base + 2]);
2261 gc8034_write_reg(client, 0xcc,
2262 otp_ptr->lsc[base + 3]);
2263 dev_dbg(&client->dev,
2264 "apply lsc otp_ptr->lsc[%d]=%d\n",
2265 base + 0,
2266 otp_ptr->lsc[base + 0]);
2267 dev_dbg(&client->dev,
2268 "apply lsc otp_ptr->lsc[%d]=%d\n",
2269 base + 1,
2270 otp_ptr->lsc[base + 1]);
2271 dev_dbg(&client->dev,
2272 "apply lsc otp_ptr->lsc[%d]=%d\n",
2273 base + 2,
2274 otp_ptr->lsc[base + 2]);
2275 dev_dbg(&client->dev,
2276 "apply lsc otp_ptr->lsc[%d]=%d\n",
2277 base + 3,
2278 otp_ptr->lsc[base + 3]);
2279 }
2280 }
2281 gc8034_write_reg(client, 0xcf, 0x01);
2282 gc8034_write_reg(client, 0xa0, 0x13);
2283 gc8034_write_reg(client, 0xfe, 0x00);
2284 dev_err(&client->dev, "apply lsc\n");
2285 }
2286 /* apply OTP DD Calibration */
2287 if (otp_ptr->flag & 0x08) {
2288 dd_cnt = otp_ptr->dd_cnt;
2289 for (i = 0; i < dd_cnt; i++) {
2290 #if defined(GC8034_MIRROR_H) || defined(GC8034_MIRROR_HV)
2291 switch (otp_ptr->dd_param[i].t) {
2292 case 0:
2293 otp_ptr->dd_param[i].x =
2294 DD_WIDTH - otp_ptr->dd_param[i].x + 1;
2295 break;
2296 case 1:
2297 otp_ptr->dd_param[i].x =
2298 DD_WIDTH - otp_ptr->dd_param[i].x - 1;
2299 break;
2300 default:
2301 otp_ptr->dd_param[i].x =
2302 DD_WIDTH - otp_ptr->dd_param[i].x;
2303 break;
2304 }
2305 #endif
2306 #if defined(GC8034_MIRROR_V) || defined(GC8034_MIRROR_HV)
2307 otp_ptr->dd_param[i].y =
2308 DD_HEIGHT - otp_ptr->dd_param[i].y + 1;
2309 #endif
2310 }
2311 for (i = 0; i < dd_cnt - 1; i++) {
2312 for (j = i + 1; j < dd_cnt; j++) {
2313 if (otp_ptr->dd_param[i].y *
2314 DD_WIDTH + otp_ptr->dd_param[i].x >
2315 otp_ptr->dd_param[j].y * DD_WIDTH +
2316 otp_ptr->dd_param[j].x) {
2317 dd_temp.x = otp_ptr->dd_param[i].x;
2318 dd_temp.y = otp_ptr->dd_param[i].y;
2319 dd_temp.t = otp_ptr->dd_param[i].t;
2320 otp_ptr->dd_param[i].x =
2321 otp_ptr->dd_param[j].x;
2322 otp_ptr->dd_param[i].y =
2323 otp_ptr->dd_param[j].y;
2324 otp_ptr->dd_param[i].t =
2325 otp_ptr->dd_param[j].t;
2326 otp_ptr->dd_param[j].x = dd_temp.x;
2327 otp_ptr->dd_param[j].y = dd_temp.y;
2328 otp_ptr->dd_param[j].t = dd_temp.t;
2329 }
2330 }
2331 }
2332 gc8034_write_reg(client, 0xfe, 0x01);
2333 gc8034_write_reg(client, 0xbe, 0x00);
2334 gc8034_write_reg(client, 0xa9, 0x01);
2335 for (i = 0; i < dd_cnt; i++) {
2336 temp_val0 = otp_ptr->dd_param[i].x & 0x00ff;
2337 temp_val1 = ((otp_ptr->dd_param[i].y & 0x000f) << 4) +
2338 ((otp_ptr->dd_param[i].x & 0x0f00) >> 8);
2339 temp_val2 = (otp_ptr->dd_param[i].y & 0x0ff0) >> 4;
2340 gc8034_write_reg(client, 0xaa, i);
2341 gc8034_write_reg(client, 0xac, temp_val0);
2342 gc8034_write_reg(client, 0xac, temp_val1);
2343 gc8034_write_reg(client, 0xac, temp_val2);
2344 gc8034_write_reg(client, 0xac, otp_ptr->dd_param[i].t);
2345 }
2346 gc8034_write_reg(client, 0xbe, 0x01);
2347 gc8034_write_reg(client, 0xfe, 0x00);
2348 dev_err(&client->dev, "apply dd\n");
2349 }
2350
2351 if (otp_ptr->flag & 0x04) {
2352 gc8034_write_reg(client, 0xfe, 0x00);
2353 for (i = 0; i < otp_ptr->reg_num; i++) {
2354 gc8034_write_reg(client, 0xfe, otp_ptr->reg_page[i]);
2355 gc8034_write_reg(client,
2356 otp_ptr->reg_addr[i],
2357 otp_ptr->reg_value[i]);
2358 }
2359 dev_err(&client->dev, "apply chip reg\n");
2360 }
2361 return 0;
2362 }
2363 #endif
2364
__gc8034_start_stream(struct gc8034 * gc8034)2365 static int __gc8034_start_stream(struct gc8034 *gc8034)
2366 {
2367 int ret;
2368 #ifndef RK_OTP
2369 if (gc8034->otp) {
2370 ret = gc8034_otp_enable(gc8034);
2371 gc8034_check_prsel(gc8034);
2372 ret |= gc8034_apply_otp(gc8034);
2373 usleep_range(1000, 2000);
2374 ret |= gc8034_otp_disable(gc8034);
2375 if (ret)
2376 return ret;
2377 }
2378 #endif
2379 ret = gc8034_write_array(gc8034->client, gc8034->cur_mode->reg_list);
2380 if (ret)
2381 return ret;
2382
2383 /* In case these controls are set before streaming */
2384 mutex_unlock(&gc8034->mutex);
2385 ret = v4l2_ctrl_handler_setup(&gc8034->ctrl_handler);
2386 mutex_lock(&gc8034->mutex);
2387 ret |= gc8034_write_reg(gc8034->client,
2388 GC8034_REG_SET_PAGE,
2389 GC8034_SET_PAGE_ZERO);
2390 if (2 == gc8034->lane_num) {
2391 ret |= gc8034_write_reg(gc8034->client,
2392 GC8034_REG_CTRL_MODE,
2393 0x91);
2394 } else {
2395 ret |= gc8034_write_reg(gc8034->client,
2396 GC8034_REG_CTRL_MODE,
2397 GC8034_MODE_STREAMING);
2398 }
2399 return ret;
2400 }
2401
__gc8034_stop_stream(struct gc8034 * gc8034)2402 static int __gc8034_stop_stream(struct gc8034 *gc8034)
2403 {
2404 int ret;
2405
2406 ret = gc8034_write_reg(gc8034->client,
2407 GC8034_REG_SET_PAGE,
2408 GC8034_SET_PAGE_ZERO);
2409 ret |= gc8034_write_reg(gc8034->client,
2410 GC8034_REG_CTRL_MODE,
2411 GC8034_MODE_SW_STANDBY);
2412
2413 return ret;
2414 }
2415
gc8034_s_stream(struct v4l2_subdev * sd,int on)2416 static int gc8034_s_stream(struct v4l2_subdev *sd, int on)
2417 {
2418 struct gc8034 *gc8034 = to_gc8034(sd);
2419 struct i2c_client *client = gc8034->client;
2420 int ret = 0;
2421
2422 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
2423 gc8034->cur_mode->width,
2424 gc8034->cur_mode->height,
2425 DIV_ROUND_CLOSEST(gc8034->cur_mode->max_fps.denominator,
2426 gc8034->cur_mode->max_fps.numerator));
2427
2428 mutex_lock(&gc8034->mutex);
2429 on = !!on;
2430 if (on == gc8034->streaming)
2431 goto unlock_and_return;
2432
2433 if (on) {
2434 ret = pm_runtime_get_sync(&client->dev);
2435 if (ret < 0) {
2436 pm_runtime_put_noidle(&client->dev);
2437 goto unlock_and_return;
2438 }
2439
2440 ret = __gc8034_start_stream(gc8034);
2441 if (ret) {
2442 v4l2_err(sd, "start stream failed while write regs\n");
2443 pm_runtime_put(&client->dev);
2444 goto unlock_and_return;
2445 }
2446 } else {
2447 __gc8034_stop_stream(gc8034);
2448 pm_runtime_put(&client->dev);
2449 }
2450
2451 gc8034->streaming = on;
2452
2453 unlock_and_return:
2454 mutex_unlock(&gc8034->mutex);
2455
2456 return ret;
2457 }
2458
gc8034_s_power(struct v4l2_subdev * sd,int on)2459 static int gc8034_s_power(struct v4l2_subdev *sd, int on)
2460 {
2461 struct gc8034 *gc8034 = to_gc8034(sd);
2462 struct i2c_client *client = gc8034->client;
2463 const struct gc8034_mode *mode = gc8034->cur_mode;
2464 int ret = 0;
2465
2466 dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
2467 mutex_lock(&gc8034->mutex);
2468
2469 /* If the power state is not modified - no work to do. */
2470 if (gc8034->power_on == !!on)
2471 goto unlock_and_return;
2472
2473 if (on) {
2474 ret = pm_runtime_get_sync(&client->dev);
2475 if (ret < 0) {
2476 pm_runtime_put_noidle(&client->dev);
2477 goto unlock_and_return;
2478 }
2479
2480 ret = gc8034_write_array(gc8034->client, mode->global_reg_list);
2481 if (ret) {
2482 v4l2_err(sd, "could not set init registers\n");
2483 pm_runtime_put_noidle(&client->dev);
2484 goto unlock_and_return;
2485 }
2486
2487 gc8034->power_on = true;
2488 } else {
2489 pm_runtime_put(&client->dev);
2490 gc8034->power_on = false;
2491 }
2492
2493 unlock_and_return:
2494 mutex_unlock(&gc8034->mutex);
2495
2496 return ret;
2497 }
2498
2499 /* Calculate the delay in us by clock rate and clock cycles */
gc8034_cal_delay(u32 cycles)2500 static inline u32 gc8034_cal_delay(u32 cycles)
2501 {
2502 return DIV_ROUND_UP(cycles, GC8034_XVCLK_FREQ / 1000 / 1000);
2503 }
2504
gc8034_enable_regulators(struct gc8034 * gc8034,struct regulator_bulk_data * consumers)2505 static int gc8034_enable_regulators(struct gc8034 *gc8034,
2506 struct regulator_bulk_data *consumers)
2507 {
2508 int i, j;
2509 int ret = 0;
2510 struct device *dev = &gc8034->client->dev;
2511 int num_consumers = GC8034_NUM_SUPPLIES;
2512
2513 for (i = 0; i < num_consumers; i++) {
2514
2515 ret = regulator_enable(consumers[i].consumer);
2516 if (ret < 0) {
2517 dev_err(dev, "Failed to enable regulator: %s\n",
2518 consumers[i].supply);
2519 goto err;
2520 }
2521 }
2522 return 0;
2523 err:
2524 for (j = 0; j < i; j++)
2525 regulator_disable(consumers[j].consumer);
2526
2527 return ret;
2528 }
2529
__gc8034_power_on(struct gc8034 * gc8034)2530 static int __gc8034_power_on(struct gc8034 *gc8034)
2531 {
2532 int ret;
2533 u32 delay_us;
2534 struct device *dev = &gc8034->client->dev;
2535
2536 if (!IS_ERR(gc8034->power_gpio))
2537 gpiod_set_value_cansleep(gc8034->power_gpio, 1);
2538
2539 usleep_range(1000, 2000);
2540
2541 if (!IS_ERR_OR_NULL(gc8034->pins_default)) {
2542 ret = pinctrl_select_state(gc8034->pinctrl,
2543 gc8034->pins_default);
2544 if (ret < 0)
2545 dev_err(dev, "could not set pins\n");
2546 }
2547 ret = clk_set_rate(gc8034->xvclk, GC8034_XVCLK_FREQ);
2548 if (ret < 0)
2549 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
2550 if (clk_get_rate(gc8034->xvclk) != GC8034_XVCLK_FREQ)
2551 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
2552
2553 if (!IS_ERR(gc8034->reset_gpio))
2554 gpiod_set_value_cansleep(gc8034->reset_gpio, 1);
2555
2556 ret = gc8034_enable_regulators(gc8034, gc8034->supplies);
2557 if (ret < 0) {
2558 dev_err(dev, "Failed to enable regulators\n");
2559 goto disable_clk;
2560 }
2561
2562 usleep_range(100, 200);
2563 ret = clk_prepare_enable(gc8034->xvclk);
2564 if (ret < 0) {
2565 dev_err(dev, "Failed to enable xvclk\n");
2566 return ret;
2567 }
2568
2569 usleep_range(1000, 1100);
2570 if (!IS_ERR(gc8034->pwdn_gpio))
2571 gpiod_set_value_cansleep(gc8034->pwdn_gpio, 0);
2572
2573 usleep_range(500, 1000);
2574 if (!IS_ERR(gc8034->reset_gpio))
2575 gpiod_set_value_cansleep(gc8034->reset_gpio, 0);
2576
2577 /* 8192 cycles prior to first SCCB transaction */
2578 delay_us = gc8034_cal_delay(8192);
2579 usleep_range(delay_us, delay_us * 2);
2580
2581 return 0;
2582
2583 disable_clk:
2584 clk_disable_unprepare(gc8034->xvclk);
2585
2586 return ret;
2587 }
2588
__gc8034_power_off(struct gc8034 * gc8034)2589 static void __gc8034_power_off(struct gc8034 *gc8034)
2590 {
2591 int ret;
2592
2593 if (!IS_ERR(gc8034->pwdn_gpio))
2594 gpiod_set_value_cansleep(gc8034->pwdn_gpio, 1);
2595
2596 if (!IS_ERR(gc8034->reset_gpio))
2597 gpiod_set_value_cansleep(gc8034->reset_gpio, 1);
2598
2599 clk_disable_unprepare(gc8034->xvclk);
2600 if (!IS_ERR_OR_NULL(gc8034->pins_sleep)) {
2601 ret = pinctrl_select_state(gc8034->pinctrl,
2602 gc8034->pins_sleep);
2603 if (ret < 0)
2604 dev_dbg(&gc8034->client->dev, "could not set pins\n");
2605 }
2606 if (!IS_ERR(gc8034->power_gpio))
2607 gpiod_set_value_cansleep(gc8034->power_gpio, 0);
2608
2609 regulator_bulk_disable(GC8034_NUM_SUPPLIES, gc8034->supplies);
2610 }
2611
gc8034_runtime_resume(struct device * dev)2612 static int __maybe_unused gc8034_runtime_resume(struct device *dev)
2613 {
2614 struct i2c_client *client = to_i2c_client(dev);
2615 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2616 struct gc8034 *gc8034 = to_gc8034(sd);
2617
2618 return __gc8034_power_on(gc8034);
2619 }
2620
gc8034_runtime_suspend(struct device * dev)2621 static int __maybe_unused gc8034_runtime_suspend(struct device *dev)
2622 {
2623 struct i2c_client *client = to_i2c_client(dev);
2624 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2625 struct gc8034 *gc8034 = to_gc8034(sd);
2626
2627 __gc8034_power_off(gc8034);
2628
2629 return 0;
2630 }
2631
2632 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc8034_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)2633 static int gc8034_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2634 {
2635 struct gc8034 *gc8034 = to_gc8034(sd);
2636 struct v4l2_mbus_framefmt *try_fmt =
2637 v4l2_subdev_get_try_format(sd, fh->pad, 0);
2638 const struct gc8034_mode *def_mode = &supported_modes[0];
2639
2640 mutex_lock(&gc8034->mutex);
2641 /* Initialize try_fmt */
2642 try_fmt->width = def_mode->width;
2643 try_fmt->height = def_mode->height;
2644 try_fmt->code = GC8034_MEDIA_BUS_FMT;
2645 try_fmt->field = V4L2_FIELD_NONE;
2646
2647 mutex_unlock(&gc8034->mutex);
2648 /* No crop or compose */
2649
2650 return 0;
2651 }
2652 #endif
2653
gc8034_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)2654 static int gc8034_enum_frame_interval(struct v4l2_subdev *sd,
2655 struct v4l2_subdev_pad_config *cfg,
2656 struct v4l2_subdev_frame_interval_enum *fie)
2657 {
2658 struct gc8034 *gc8034 = to_gc8034(sd);
2659
2660 if (fie->index >= gc8034->cfg_num)
2661 return -EINVAL;
2662
2663 fie->code = GC8034_MEDIA_BUS_FMT;
2664 fie->width = supported_modes[fie->index].width;
2665 fie->height = supported_modes[fie->index].height;
2666 fie->interval = supported_modes[fie->index].max_fps;
2667 return 0;
2668 }
2669
gc8034_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)2670 static int gc8034_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
2671 struct v4l2_mbus_config *config)
2672 {
2673 struct gc8034 *sensor = to_gc8034(sd);
2674 struct device *dev = &sensor->client->dev;
2675
2676 dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
2677
2678 if (2 == sensor->lane_num) {
2679 config->type = V4L2_MBUS_CSI2_DPHY;
2680 config->flags = V4L2_MBUS_CSI2_2_LANE |
2681 V4L2_MBUS_CSI2_CHANNEL_0 |
2682 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
2683 } else if (4 == sensor->lane_num) {
2684 config->type = V4L2_MBUS_CSI2_DPHY;
2685 config->flags = V4L2_MBUS_CSI2_4_LANE |
2686 V4L2_MBUS_CSI2_CHANNEL_0 |
2687 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
2688 } else {
2689 dev_err(&sensor->client->dev,
2690 "unsupported lane_num(%d)\n", sensor->lane_num);
2691 }
2692 return 0;
2693 }
2694
2695 static const struct dev_pm_ops gc8034_pm_ops = {
2696 SET_RUNTIME_PM_OPS(gc8034_runtime_suspend,
2697 gc8034_runtime_resume, NULL)
2698 };
2699
2700 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2701 static const struct v4l2_subdev_internal_ops gc8034_internal_ops = {
2702 .open = gc8034_open,
2703 };
2704 #endif
2705
2706 static const struct v4l2_subdev_core_ops gc8034_core_ops = {
2707 .s_power = gc8034_s_power,
2708 .ioctl = gc8034_ioctl,
2709 #ifdef CONFIG_COMPAT
2710 .compat_ioctl32 = gc8034_compat_ioctl32,
2711 #endif
2712 };
2713
2714 static const struct v4l2_subdev_video_ops gc8034_video_ops = {
2715 .s_stream = gc8034_s_stream,
2716 .g_frame_interval = gc8034_g_frame_interval,
2717 };
2718
2719 static const struct v4l2_subdev_pad_ops gc8034_pad_ops = {
2720 .enum_mbus_code = gc8034_enum_mbus_code,
2721 .enum_frame_size = gc8034_enum_frame_sizes,
2722 .enum_frame_interval = gc8034_enum_frame_interval,
2723 .get_fmt = gc8034_get_fmt,
2724 .set_fmt = gc8034_set_fmt,
2725 .get_mbus_config = gc8034_g_mbus_config,
2726 };
2727
2728 static const struct v4l2_subdev_ops gc8034_subdev_ops = {
2729 .core = &gc8034_core_ops,
2730 .video = &gc8034_video_ops,
2731 .pad = &gc8034_pad_ops,
2732 };
2733
gc8034_set_exposure_reg(struct gc8034 * gc8034,u32 exposure)2734 static int gc8034_set_exposure_reg(struct gc8034 *gc8034, u32 exposure)
2735 {
2736 int ret = 0;
2737 u32 cal_shutter = 0;
2738
2739 cal_shutter = exposure >> 1;
2740 cal_shutter = cal_shutter << 1;
2741
2742 gc8034->Dgain_ratio = 256 * exposure / cal_shutter;
2743 ret = gc8034_write_reg(gc8034->client,
2744 GC8034_REG_SET_PAGE, GC8034_SET_PAGE_ZERO);
2745 ret |= gc8034_write_reg(gc8034->client,
2746 GC8034_REG_EXPOSURE_H,
2747 GC8034_FETCH_HIGH_BYTE_EXP(cal_shutter));
2748 ret |= gc8034_write_reg(gc8034->client,
2749 GC8034_REG_EXPOSURE_L,
2750 GC8034_FETCH_LOW_BYTE_EXP(cal_shutter));
2751 return ret;
2752 }
2753
2754 #define MAX_AG_INDEX 9
2755 #define AGC_REG_NUM 14
2756 #define MEAG_INDEX 7
2757
2758 u16 gain_level[MAX_AG_INDEX] = {
2759 0x0040, /* 1.000*/
2760 0x0058, /* 1.375*/
2761 0x007d, /* 1.950*/
2762 0x00ad, /* 2.700*/
2763 0x00f3, /* 3.800*/
2764 0x0159, /* 5.400*/
2765 0x01ea, /* 7.660*/
2766 0x02ac, /*10.688*/
2767 0x03c2, /*15.030*/
2768 };
2769
2770 u8 agc_register[MAX_AG_INDEX][AGC_REG_NUM] = {
2771 /* fullsize */
2772 { 0x00, 0x55, 0x83, 0x01, 0x06, 0x18, 0x20,
2773 0x16, 0x17, 0x50, 0x6c, 0x9b, 0xd8, 0x00 },
2774 { 0x00, 0x55, 0x83, 0x01, 0x06, 0x18, 0x20,
2775 0x16, 0x17, 0x50, 0x6c, 0x9b, 0xd8, 0x00 },
2776 { 0x00, 0x4e, 0x84, 0x01, 0x0c, 0x2e, 0x2d,
2777 0x15, 0x19, 0x47, 0x70, 0x9f, 0xd8, 0x00 },
2778 { 0x00, 0x51, 0x80, 0x01, 0x07, 0x28, 0x32,
2779 0x22, 0x20, 0x49, 0x70, 0x91, 0xd9, 0x00 },
2780 { 0x00, 0x4d, 0x83, 0x01, 0x0f, 0x3b, 0x3b,
2781 0x1c, 0x1f, 0x47, 0x6f, 0x9b, 0xd3, 0x00 },
2782 { 0x00, 0x50, 0x83, 0x01, 0x08, 0x35, 0x46,
2783 0x1e, 0x22, 0x4c, 0x70, 0x9a, 0xd2, 0x00 },
2784 { 0x00, 0x52, 0x80, 0x01, 0x0c, 0x35, 0x3a,
2785 0x2b, 0x2d, 0x4c, 0x67, 0x8d, 0xc0, 0x00 },
2786 { 0x00, 0x52, 0x80, 0x01, 0x0c, 0x35, 0x3a,
2787 0x2b, 0x2d, 0x4c, 0x67, 0x8d, 0xc0, 0x00 },
2788 { 0x00, 0x52, 0x80, 0x01, 0x0c, 0x35, 0x3a,
2789 0x2b, 0x2d, 0x4c, 0x67, 0x8d, 0xc0, 0x00 }
2790 };
2791
gc8034_set_gain_reg(struct gc8034 * gc8034,u32 a_gain)2792 static int gc8034_set_gain_reg(struct gc8034 *gc8034, u32 a_gain)
2793 {
2794 int ret = 0;
2795 u32 temp_gain = 0;
2796 int gain_index = 0;
2797 u32 Dgain_ratio = 0;
2798
2799 Dgain_ratio = gc8034->Dgain_ratio;
2800 for (gain_index = MEAG_INDEX - 1; gain_index >= 0; gain_index--) {
2801 if (a_gain >= gain_level[gain_index]) {
2802 ret = gc8034_write_reg(gc8034->client,
2803 GC8034_REG_SET_PAGE, GC8034_SET_PAGE_ZERO);
2804 ret |= gc8034_write_reg(gc8034->client,
2805 0xb6, gain_index);
2806 temp_gain = 256 * a_gain / gain_level[gain_index];
2807 temp_gain = temp_gain * Dgain_ratio / 256;
2808 ret |= gc8034_write_reg(gc8034->client,
2809 0xb1, temp_gain >> 8);
2810 ret |= gc8034_write_reg(gc8034->client,
2811 0xb2, temp_gain & 0xff);
2812
2813 ret |= gc8034_write_reg(gc8034->client, 0xfe,
2814 agc_register[gain_index][0]);
2815 ret |= gc8034_write_reg(gc8034->client, 0x20,
2816 agc_register[gain_index][1]);
2817 ret |= gc8034_write_reg(gc8034->client, 0x33,
2818 agc_register[gain_index][2]);
2819 ret |= gc8034_write_reg(gc8034->client, 0xfe,
2820 agc_register[gain_index][3]);
2821 ret |= gc8034_write_reg(gc8034->client, 0xdf,
2822 agc_register[gain_index][4]);
2823 ret |= gc8034_write_reg(gc8034->client, 0xe7,
2824 agc_register[gain_index][5]);
2825 ret |= gc8034_write_reg(gc8034->client, 0xe8,
2826 agc_register[gain_index][6]);
2827 ret |= gc8034_write_reg(gc8034->client, 0xe9,
2828 agc_register[gain_index][7]);
2829 ret |= gc8034_write_reg(gc8034->client, 0xea,
2830 agc_register[gain_index][8]);
2831 ret |= gc8034_write_reg(gc8034->client, 0xeb,
2832 agc_register[gain_index][9]);
2833 ret |= gc8034_write_reg(gc8034->client, 0xec,
2834 agc_register[gain_index][10]);
2835 ret |= gc8034_write_reg(gc8034->client, 0xed,
2836 agc_register[gain_index][11]);
2837 ret |= gc8034_write_reg(gc8034->client, 0xee,
2838 agc_register[gain_index][12]);
2839 ret |= gc8034_write_reg(gc8034->client, 0xfe,
2840 agc_register[gain_index][13]);
2841 break;
2842 }
2843 }
2844 return ret;
2845 }
2846
gc8034_set_ctrl(struct v4l2_ctrl * ctrl)2847 static int gc8034_set_ctrl(struct v4l2_ctrl *ctrl)
2848 {
2849 struct gc8034 *gc8034 = container_of(ctrl->handler,
2850 struct gc8034, ctrl_handler);
2851 struct i2c_client *client = gc8034->client;
2852 s64 max;
2853 int ret = 0;
2854 s32 temp;
2855
2856 /* Propagate change of current control to all related controls */
2857 switch (ctrl->id) {
2858 case V4L2_CID_VBLANK:
2859 /* Update max exposure while meeting expected vblanking */
2860 max = gc8034->cur_mode->height + ctrl->val - 4;
2861 __v4l2_ctrl_modify_range(gc8034->exposure,
2862 gc8034->exposure->minimum, max,
2863 gc8034->exposure->step,
2864 gc8034->exposure->default_value);
2865 break;
2866 }
2867
2868 if (!pm_runtime_get_if_in_use(&client->dev))
2869 return 0;
2870
2871 switch (ctrl->id) {
2872 case V4L2_CID_EXPOSURE:
2873 /* 4 least significant bits of expsoure are fractional part */
2874 dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val);
2875 ret = gc8034_set_exposure_reg(gc8034, ctrl->val);
2876 break;
2877 case V4L2_CID_ANALOGUE_GAIN:
2878 dev_dbg(&client->dev, "set analog gain value 0x%x\n", ctrl->val);
2879 ret = gc8034_set_gain_reg(gc8034, ctrl->val);
2880 break;
2881 case V4L2_CID_VBLANK:
2882 dev_dbg(&client->dev, "set vb value 0x%x\n", ctrl->val);
2883 /* VB = VTS - 2448 -36, according android8.1 driver */
2884 temp = ctrl->val + gc8034->cur_mode->height - 2448 - 36;
2885 ret = gc8034_write_reg(gc8034->client,
2886 GC8034_REG_SET_PAGE,
2887 GC8034_SET_PAGE_ZERO);
2888 ret |= gc8034_write_reg(gc8034->client,
2889 GC8034_REG_VTS_H,
2890 (temp >> 8) & 0xff);
2891 ret |= gc8034_write_reg(gc8034->client,
2892 GC8034_REG_VTS_L,
2893 temp & 0xff);
2894 break;
2895 default:
2896 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
2897 __func__, ctrl->id, ctrl->val);
2898 break;
2899 }
2900
2901 pm_runtime_put(&client->dev);
2902
2903 return ret;
2904 }
2905
2906 static const struct v4l2_ctrl_ops gc8034_ctrl_ops = {
2907 .s_ctrl = gc8034_set_ctrl,
2908 };
2909
gc8034_initialize_controls(struct gc8034 * gc8034)2910 static int gc8034_initialize_controls(struct gc8034 *gc8034)
2911 {
2912 const struct gc8034_mode *mode;
2913 struct v4l2_ctrl_handler *handler;
2914 s64 exposure_max, vblank_def;
2915 u32 h_blank;
2916 int ret;
2917
2918 handler = &gc8034->ctrl_handler;
2919 mode = gc8034->cur_mode;
2920 ret = v4l2_ctrl_handler_init(handler, 8);
2921 if (ret)
2922 return ret;
2923 handler->lock = &gc8034->mutex;
2924
2925 gc8034->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
2926 V4L2_CID_LINK_FREQ,
2927 ARRAY_SIZE(link_freq_menu_items) - 1, 0,
2928 link_freq_menu_items);
2929 v4l2_ctrl_s_ctrl(gc8034->link_freq, mode->mipi_freq_idx);
2930
2931 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
2932 0, gc8034->pixel_rate, 1, gc8034->pixel_rate);
2933
2934 h_blank = mode->hts_def - mode->width;
2935 gc8034->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
2936 h_blank, h_blank, 1, h_blank);
2937 if (gc8034->hblank)
2938 gc8034->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2939
2940 vblank_def = mode->vts_def - mode->height;
2941 gc8034->vblank = v4l2_ctrl_new_std(handler, &gc8034_ctrl_ops,
2942 V4L2_CID_VBLANK, vblank_def,
2943 GC8034_VTS_MAX - mode->height,
2944 1, vblank_def);
2945
2946 exposure_max = mode->vts_def - 4;
2947 gc8034->exposure = v4l2_ctrl_new_std(handler, &gc8034_ctrl_ops,
2948 V4L2_CID_EXPOSURE, GC8034_EXPOSURE_MIN,
2949 exposure_max, GC8034_EXPOSURE_STEP,
2950 mode->exp_def);
2951
2952 gc8034->anal_gain = v4l2_ctrl_new_std(handler, &gc8034_ctrl_ops,
2953 V4L2_CID_ANALOGUE_GAIN, GC8034_GAIN_MIN,
2954 GC8034_GAIN_MAX, GC8034_GAIN_STEP,
2955 GC8034_GAIN_DEFAULT);
2956 if (handler->error) {
2957 ret = handler->error;
2958 dev_err(&gc8034->client->dev,
2959 "Failed to init controls(%d)\n", ret);
2960 goto err_free_handler;
2961 }
2962
2963 gc8034->subdev.ctrl_handler = handler;
2964
2965 return 0;
2966
2967 err_free_handler:
2968 v4l2_ctrl_handler_free(handler);
2969
2970 return ret;
2971 }
2972
gc8034_check_sensor_id(struct gc8034 * gc8034,struct i2c_client * client)2973 static int gc8034_check_sensor_id(struct gc8034 *gc8034,
2974 struct i2c_client *client)
2975 {
2976 struct device *dev = &gc8034->client->dev;
2977 u16 id = 0;
2978 u8 reg_H = 0;
2979 u8 reg_L = 0;
2980 int ret;
2981
2982 ret = gc8034_read_reg(client, GC8034_REG_CHIP_ID_H, ®_H);
2983 ret |= gc8034_read_reg(client, GC8034_REG_CHIP_ID_L, ®_L);
2984 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
2985 if (id != CHIP_ID) {
2986 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
2987 return -ENODEV;
2988 }
2989 dev_info(dev, "detected gc%04x sensor\n", id);
2990 return ret;
2991 }
2992
gc8034_configure_regulators(struct gc8034 * gc8034)2993 static int gc8034_configure_regulators(struct gc8034 *gc8034)
2994 {
2995 unsigned int i;
2996
2997 for (i = 0; i < GC8034_NUM_SUPPLIES; i++)
2998 gc8034->supplies[i].supply = gc8034_supply_names[i];
2999
3000 return devm_regulator_bulk_get(&gc8034->client->dev,
3001 GC8034_NUM_SUPPLIES,
3002 gc8034->supplies);
3003 }
3004
gc8034_parse_of(struct gc8034 * gc8034)3005 static int gc8034_parse_of(struct gc8034 *gc8034)
3006 {
3007 struct device *dev = &gc8034->client->dev;
3008 struct device_node *endpoint;
3009 struct fwnode_handle *fwnode;
3010 int rval;
3011 unsigned int fps;
3012
3013 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
3014 if (!endpoint) {
3015 dev_err(dev, "Failed to get endpoint\n");
3016 return -EINVAL;
3017 }
3018 fwnode = of_fwnode_handle(endpoint);
3019 rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
3020 if (rval <= 0) {
3021 dev_warn(dev, " Get mipi lane num failed!\n");
3022 return -1;
3023 }
3024
3025 gc8034->lane_num = rval;
3026 if (4 == gc8034->lane_num) {
3027 gc8034->cur_mode = &supported_modes_4lane[0];
3028 supported_modes = supported_modes_4lane;
3029 gc8034->cfg_num = ARRAY_SIZE(supported_modes_4lane);
3030 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
3031 fps = DIV_ROUND_CLOSEST(gc8034->cur_mode->max_fps.denominator,
3032 gc8034->cur_mode->max_fps.numerator);
3033 gc8034->pixel_rate = gc8034->cur_mode->vts_def *
3034 gc8034->cur_mode->hts_def * fps;
3035
3036 dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
3037 gc8034->lane_num, gc8034->pixel_rate);
3038 } else if (2 == gc8034->lane_num) {
3039 gc8034->cur_mode = &supported_modes_2lane[0];
3040 supported_modes = supported_modes_2lane;
3041 gc8034->cfg_num = ARRAY_SIZE(supported_modes_2lane);
3042 /*pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
3043 fps = DIV_ROUND_CLOSEST(gc8034->cur_mode->max_fps.denominator,
3044 gc8034->cur_mode->max_fps.numerator);
3045 gc8034->pixel_rate = gc8034->cur_mode->vts_def *
3046 gc8034->cur_mode->hts_def * fps;
3047 dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
3048 gc8034->lane_num, gc8034->pixel_rate);
3049 } else {
3050 dev_err(dev, "unsupported lane_num(%d)\n", gc8034->lane_num);
3051 return -1;
3052 }
3053
3054 return 0;
3055 }
3056
gc8034_probe(struct i2c_client * client,const struct i2c_device_id * id)3057 static int gc8034_probe(struct i2c_client *client,
3058 const struct i2c_device_id *id)
3059 {
3060 struct device *dev = &client->dev;
3061 struct device_node *node = dev->of_node;
3062 struct gc8034 *gc8034;
3063 struct v4l2_subdev *sd;
3064 char facing[2];
3065 int ret;
3066 struct device_node *eeprom_ctrl_node;
3067 struct i2c_client *eeprom_ctrl_client;
3068 struct v4l2_subdev *eeprom_ctrl;
3069 struct otp_info *otp_ptr;
3070
3071 dev_info(dev, "driver version: %02x.%02x.%02x",
3072 DRIVER_VERSION >> 16,
3073 (DRIVER_VERSION & 0xff00) >> 8,
3074 DRIVER_VERSION & 0x00ff);
3075
3076 gc8034 = devm_kzalloc(dev, sizeof(*gc8034), GFP_KERNEL);
3077 if (!gc8034)
3078 return -ENOMEM;
3079
3080 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
3081 &gc8034->module_index);
3082 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
3083 &gc8034->module_facing);
3084 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
3085 &gc8034->module_name);
3086 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
3087 &gc8034->len_name);
3088 if (ret) {
3089 dev_err(dev, "could not get module information!\n");
3090 return -EINVAL;
3091 }
3092 gc8034->client = client;
3093
3094 gc8034->xvclk = devm_clk_get(dev, "xvclk");
3095 if (IS_ERR(gc8034->xvclk)) {
3096 dev_err(dev, "Failed to get xvclk\n");
3097 return -EINVAL;
3098 }
3099
3100 gc8034->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
3101 if (IS_ERR(gc8034->power_gpio))
3102 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
3103 gc8034->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
3104 if (IS_ERR(gc8034->reset_gpio))
3105 dev_warn(dev, "Failed to get reset-gpios\n");
3106
3107 gc8034->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
3108 if (IS_ERR(gc8034->pwdn_gpio))
3109 dev_warn(dev, "Failed to get pwdn-gpios\n");
3110
3111 ret = gc8034_configure_regulators(gc8034);
3112 if (ret) {
3113 dev_err(dev, "Failed to get power regulators\n");
3114 return ret;
3115 }
3116
3117 ret = gc8034_parse_of(gc8034);
3118 if (ret != 0)
3119 return -EINVAL;
3120
3121 gc8034->pinctrl = devm_pinctrl_get(dev);
3122 if (!IS_ERR(gc8034->pinctrl)) {
3123 gc8034->pins_default =
3124 pinctrl_lookup_state(gc8034->pinctrl,
3125 OF_CAMERA_PINCTRL_STATE_DEFAULT);
3126 if (IS_ERR(gc8034->pins_default))
3127 dev_err(dev, "could not get default pinstate\n");
3128
3129 gc8034->pins_sleep =
3130 pinctrl_lookup_state(gc8034->pinctrl,
3131 OF_CAMERA_PINCTRL_STATE_SLEEP);
3132 if (IS_ERR(gc8034->pins_sleep))
3133 dev_err(dev, "could not get sleep pinstate\n");
3134 }
3135
3136 mutex_init(&gc8034->mutex);
3137
3138 sd = &gc8034->subdev;
3139 v4l2_i2c_subdev_init(sd, client, &gc8034_subdev_ops);
3140 ret = gc8034_initialize_controls(gc8034);
3141 if (ret)
3142 goto err_destroy_mutex;
3143
3144 ret = __gc8034_power_on(gc8034);
3145 if (ret)
3146 goto err_free_handler;
3147
3148 ret = gc8034_check_sensor_id(gc8034, client);
3149 if (ret)
3150 goto err_power_off;
3151 #ifdef RK_OTP
3152 eeprom_ctrl_node = of_parse_phandle(node, "eeprom-ctrl", 0);
3153 if (eeprom_ctrl_node) {
3154 eeprom_ctrl_client =
3155 of_find_i2c_device_by_node(eeprom_ctrl_node);
3156 of_node_put(eeprom_ctrl_node);
3157 if (IS_ERR_OR_NULL(eeprom_ctrl_client)) {
3158 dev_err(dev, "can not get node\n");
3159 goto continue_probe;
3160 }
3161 eeprom_ctrl = i2c_get_clientdata(eeprom_ctrl_client);
3162 if (IS_ERR_OR_NULL(eeprom_ctrl)) {
3163 dev_err(dev, "can not get eeprom i2c client\n");
3164 } else {
3165 otp_ptr = devm_kzalloc(dev, sizeof(*otp_ptr), GFP_KERNEL);
3166 if (!otp_ptr)
3167 return -ENOMEM;
3168 ret = v4l2_subdev_call(eeprom_ctrl,
3169 core, ioctl, 0, otp_ptr);
3170 if (!ret) {
3171 gc8034->otp = otp_ptr;
3172 } else {
3173 gc8034->otp = NULL;
3174 devm_kfree(dev, otp_ptr);
3175 dev_warn(dev, "can not get otp info, skip!\n");
3176 }
3177 }
3178 }
3179 continue_probe:
3180 #else
3181 gc8034_otp_enable(gc8034);
3182 gc8034_otp_read(gc8034);
3183 gc8034_otp_disable(gc8034);
3184 #endif
3185
3186 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
3187 sd->internal_ops = &gc8034_internal_ops;
3188 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
3189 V4L2_SUBDEV_FL_HAS_EVENTS;
3190 #endif
3191 #if defined(CONFIG_MEDIA_CONTROLLER)
3192 gc8034->pad.flags = MEDIA_PAD_FL_SOURCE;
3193 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
3194 ret = media_entity_pads_init(&sd->entity, 1, &gc8034->pad);
3195 if (ret < 0)
3196 goto err_power_off;
3197 #endif
3198
3199 memset(facing, 0, sizeof(facing));
3200 if (strcmp(gc8034->module_facing, "back") == 0)
3201 facing[0] = 'b';
3202 else
3203 facing[0] = 'f';
3204
3205 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
3206 gc8034->module_index, facing,
3207 GC8034_NAME, dev_name(sd->dev));
3208 ret = v4l2_async_register_subdev_sensor_common(sd);
3209 if (ret) {
3210 dev_err(dev, "v4l2 async register subdev failed\n");
3211 goto err_clean_entity;
3212 }
3213
3214 pm_runtime_set_active(dev);
3215 pm_runtime_enable(dev);
3216 pm_runtime_idle(dev);
3217
3218 return 0;
3219
3220 err_clean_entity:
3221 #if defined(CONFIG_MEDIA_CONTROLLER)
3222 media_entity_cleanup(&sd->entity);
3223 #endif
3224 err_power_off:
3225 __gc8034_power_off(gc8034);
3226 err_free_handler:
3227 v4l2_ctrl_handler_free(&gc8034->ctrl_handler);
3228 err_destroy_mutex:
3229 mutex_destroy(&gc8034->mutex);
3230
3231 return ret;
3232 }
3233
gc8034_remove(struct i2c_client * client)3234 static int gc8034_remove(struct i2c_client *client)
3235 {
3236 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3237 struct gc8034 *gc8034 = to_gc8034(sd);
3238
3239 v4l2_async_unregister_subdev(sd);
3240 #if defined(CONFIG_MEDIA_CONTROLLER)
3241 media_entity_cleanup(&sd->entity);
3242 #endif
3243 v4l2_ctrl_handler_free(&gc8034->ctrl_handler);
3244 mutex_destroy(&gc8034->mutex);
3245
3246 pm_runtime_disable(&client->dev);
3247 if (!pm_runtime_status_suspended(&client->dev))
3248 __gc8034_power_off(gc8034);
3249 pm_runtime_set_suspended(&client->dev);
3250
3251 return 0;
3252 }
3253
3254 #if IS_ENABLED(CONFIG_OF)
3255 static const struct of_device_id gc8034_of_match[] = {
3256 { .compatible = "galaxycore,gc8034" },
3257 {},
3258 };
3259 MODULE_DEVICE_TABLE(of, gc8034_of_match);
3260 #endif
3261
3262 static const struct i2c_device_id gc8034_match_id[] = {
3263 { "galaxycore,gc8034", 0},
3264 { },
3265 };
3266
3267 static struct i2c_driver gc8034_i2c_driver = {
3268 .driver = {
3269 .name = GC8034_NAME,
3270 .pm = &gc8034_pm_ops,
3271 .of_match_table = of_match_ptr(gc8034_of_match),
3272 },
3273 .probe = &gc8034_probe,
3274 .remove = &gc8034_remove,
3275 .id_table = gc8034_match_id,
3276 };
3277
sensor_mod_init(void)3278 static int __init sensor_mod_init(void)
3279 {
3280 return i2c_add_driver(&gc8034_i2c_driver);
3281 }
3282
sensor_mod_exit(void)3283 static void __exit sensor_mod_exit(void)
3284 {
3285 i2c_del_driver(&gc8034_i2c_driver);
3286 }
3287
3288 device_initcall_sync(sensor_mod_init);
3289 module_exit(sensor_mod_exit);
3290
3291 MODULE_DESCRIPTION("GalaxyCore gc8034 sensor driver");
3292 MODULE_LICENSE("GPL v2");
3293