1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc5025 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 add enum_frame_interval function.
10 * V0.0X01.0X04 add quick stream on/off
11 */
12
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/sysfs.h>
22 #include <linux/version.h>
23 #include <linux/rk-camera-module.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/slab.h>
30
31 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
32
33 #ifndef V4L2_CID_DIGITAL_GAIN
34 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35 #endif
36
37 #define GC5025_LANES 2
38 #define GC5025_BITS_PER_SAMPLE 10
39 #define GC5025_LINK_FREQ_MHZ 432000000
40 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
41 #define GC5025_PIXEL_RATE (GC5025_LINK_FREQ_MHZ * 2 * 2 / 10)
42 #define GC5025_XVCLK_FREQ 24000000
43
44 #define CHIP_ID 0x5025
45 #define GC5025_REG_CHIP_ID_H 0xf0
46 #define GC5025_REG_CHIP_ID_L 0xf1
47
48 #define GC5025_REG_SET_PAGE 0xfe
49 #define GC5025_SET_PAGE_ONE 0x00
50
51 #define GC5025_REG_CTRL_MODE 0x3f
52 #define GC5025_MODE_SW_STANDBY 0x01
53 #define GC5025_MODE_STREAMING 0x91
54
55 #define GC5025_REG_EXPOSURE_H 0x03
56 #define GC5025_REG_EXPOSURE_L 0x04
57 #define GC5025_EXPOSURE_MIN 4
58 #define GC5025_EXPOSURE_STEP 1
59 #define GC5025_VTS_MAX 0x1fff
60
61 #define GC5025_REG_AGAIN 0xb6
62 #define GC5025_REG_DGAIN_INT 0xb1
63 #define GC5025_REG_DGAIN_FRAC 0xb2
64 #define GC5025_GAIN_MIN 64
65 #define GC5025_GAIN_MAX 1024
66 #define GC5025_GAIN_STEP 1
67 #define GC5025_GAIN_DEFAULT 64
68
69 #define GC5025_REG_VTS_H 0x07
70 #define GC5025_REG_VTS_L 0x08
71
72 #define REG_NULL 0xFF
73
74 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
75 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
76
77 #define GC5025_NAME "gc5025"
78
79 static const char * const gc5025_supply_names[] = {
80 "avdd", /* Analog power */
81 "dovdd", /* Digital I/O power */
82 "dvdd", /* Digital core power */
83 };
84
85 #define GC5025_NUM_SUPPLIES ARRAY_SIZE(gc5025_supply_names)
86
87 #define IMAGE_NORMAL_MIRROR
88 #define DD_PARAM_QTY_5025 200
89 #define INFO_ROM_START_5025 0x08
90 #define INFO_WIDTH_5025 0x08
91 #define WB_ROM_START_5025 0x88
92 #define WB_WIDTH_5025 0x05
93 #define GOLDEN_ROM_START_5025 0xe0
94 #define GOLDEN_WIDTH_5025 0x05
95 #define WINDOW_WIDTH 0x0a30
96 #define WINDOW_HEIGHT 0x079c
97
98 struct gc5025_otp_info {
99 u32 flag; //bit[7]: info bit[6]:wb bit[3]:dd
100 u32 module_id;
101 u32 lens_id;
102 u16 vcm_id;
103 u16 vcm_driver_id;
104 u32 year;
105 u32 month;
106 u32 day;
107 u32 rg_ratio;
108 u32 bg_ratio;
109 u32 golden_rg;
110 u32 golden_bg;
111 u16 dd_param_x[DD_PARAM_QTY_5025];
112 u16 dd_param_y[DD_PARAM_QTY_5025];
113 u16 dd_param_type[DD_PARAM_QTY_5025];
114 u16 dd_cnt;
115 };
116
117 struct gc5025_id_name {
118 u32 id;
119 char name[RKMODULE_NAME_LEN];
120 };
121
122 static const struct gc5025_id_name gc5025_module_info[] = {
123 {0x0d, "CameraKing"},
124 {0x00, "Unknown"}
125 };
126
127 static const struct gc5025_id_name gc5025_lens_info[] = {
128 {0xa9, "CK5502"},
129 {0x00, "Unknown"}
130 };
131
132 struct regval {
133 u8 addr;
134 u8 val;
135 };
136
137 struct gc5025_mode {
138 u32 width;
139 u32 height;
140 struct v4l2_fract max_fps;
141 u32 hts_def;
142 u32 vts_def;
143 u32 exp_def;
144 const struct regval *reg_list;
145 };
146
147 struct gc5025 {
148 struct i2c_client *client;
149 struct clk *xvclk;
150 struct gpio_desc *reset_gpio;
151 struct gpio_desc *pwdn_gpio;
152 struct gpio_desc *power_gpio;
153 struct regulator_bulk_data supplies[GC5025_NUM_SUPPLIES];
154
155 struct pinctrl *pinctrl;
156 struct pinctrl_state *pins_default;
157 struct pinctrl_state *pins_sleep;
158
159 struct v4l2_subdev subdev;
160 struct media_pad pad;
161 struct v4l2_ctrl_handler ctrl_handler;
162 struct v4l2_ctrl *exposure;
163 struct v4l2_ctrl *anal_gain;
164 struct v4l2_ctrl *digi_gain;
165 struct v4l2_ctrl *hblank;
166 struct v4l2_ctrl *vblank;
167 struct mutex mutex;
168 bool streaming;
169 bool power_on;
170 const struct gc5025_mode *cur_mode;
171 u32 module_index;
172 const char *module_facing;
173 const char *module_name;
174 const char *len_name;
175 u32 Dgain_ratio;
176 bool DR_State;
177 struct gc5025_otp_info *otp;
178 struct rkmodule_inf module_inf;
179 struct rkmodule_awb_cfg awb_cfg;
180 };
181
182 #define to_gc5025(sd) container_of(sd, struct gc5025, subdev)
183
184 /*
185 * Xclk 24Mhz
186 */
187 static const struct regval gc5025_2592x1944_regs[] = {
188 {REG_NULL, 0x00},
189 };
190
191 /*
192 * Xclk 24Mhz
193 * max_framerate 30fps
194 * mipi_datarate per lane 656Mbps
195 */
196 static const struct regval gc5025_global_regs[] = {
197 {0xfe, 0x00},
198 {0xfe, 0x00},
199 {0xfe, 0x00},
200 {0xf7, 0x01},
201 {0xf8, 0x11},
202 {0xf9, 0x00},
203 {0xfa, 0xa0},
204 {0xfc, 0x2a},
205 {0xfe, 0x03},
206 {0x01, 0x07},
207 {0xfc, 0x2e},
208 {0xfe, 0x00},
209 {0x88, 0x03},
210 {0x03, 0x07},
211 {0x04, 0xC0},
212 {0x05, 0x02},
213 {0x06, 0x58},
214 {0x08, 0x20},
215 {0x0a, 0x1c},
216 {0x0c, 0x04},
217 {0x0d, 0x07},
218 {0x0e, 0x9c},
219 {0x0f, 0x0a},
220 {0x10, 0x30},
221 {0x17, 0xc0},
222 {0x18, 0x02},
223 {0x19, 0x17},
224 {0x1a, 0x1a},
225 {0x1e, 0x90},
226 {0x1f, 0xb0},
227 {0x20, 0x2b},
228 {0x21, 0x2b},
229 {0x26, 0x2b},
230 {0x25, 0xc1},
231 {0x27, 0x64},
232 {0x28, 0x00},
233 {0x29, 0x3f},
234 {0x2b, 0x80},
235 {0x30, 0x11},
236 {0x31, 0x20},
237 {0x32, 0xa0},
238 {0x33, 0x00},
239 {0x34, 0x55},
240 {0x3a, 0x00},
241 {0x3b, 0x00},
242 {0x81, 0x60},
243 {0xcb, 0x02},
244 {0xcd, 0x2d},
245 {0xcf, 0x50},
246 {0xd0, 0xb3},
247 {0xd1, 0x18},
248 {0xd9, 0xaa},
249 {0xdc, 0x03},
250 {0xdd, 0xaa},
251 {0xe0, 0x00},
252 {0xe1, 0x0a},
253 {0xe3, 0x2a},
254 {0xe4, 0xa0},
255 {0xe5, 0x06},
256 {0xe6, 0x10},
257 {0xe7, 0xc2},
258 {0xfe, 0x10},
259 {0xfe, 0x00},
260 {0xfe, 0x10},
261 {0xfe, 0x00},
262 {0x80, 0x10},
263 {0x89, 0x03},
264 {0xfe, 0x01},
265 {0x88, 0xf7},
266 {0x8a, 0x03},
267 {0x8e, 0xc7},
268 {0xfe, 0x00},
269 {0x40, 0x22},
270 {0x41, 0x28},
271 {0x42, 0x04},
272 {0x4e, 0x0f},
273 {0x4f, 0xf0},
274 {0x67, 0x0c},
275 {0xae, 0x40},
276 {0xaf, 0x04},
277 {0x60, 0x00},
278 {0x61, 0x80},
279 {0xb0, 0x58},
280 {0xb1, 0x01},
281 {0xb2, 0x00},
282 {0xb6, 0x00},
283 {0x91, 0x00},
284 {0x92, 0x02},
285 {0x94, 0x03},
286 {0xfe, 0x03},
287 {0x02, 0x03},
288 {0x03, 0x8e},
289 {0x06, 0x80},
290 {0x15, 0x00},
291 {0x16, 0x09},
292 {0x18, 0x0a},
293 {0x21, 0x10},
294 {0x22, 0x05},
295 {0x23, 0x20},
296 {0x24, 0x02},
297 {0x25, 0x20},
298 {0x26, 0x08},
299 {0x29, 0x06},
300 {0x2a, 0x0a},
301 {0x2b, 0x08},
302 {0xfe, 0x00},
303 {REG_NULL, 0x00},
304 };
305
306 static const struct regval gc5025_doublereset_reg[] = {
307 {0xfe, 0x00},
308 {0x1c, 0x1c},
309 {0x2f, 0x4a},
310 {0x38, 0x02},
311 {0x39, 0x00},
312 {0x3c, 0x02},
313 {0x3d, 0x02},
314 {0xd3, 0xcc},
315 {0x43, 0x03},
316 {0x1d, 0x13},
317 {REG_NULL, 0x00},
318 };
319
320 static const struct regval gc5025_disable_doublereset_reg[] = {
321 {0xfe, 0x00},
322 {0x1c, 0x2c},
323 {0x2f, 0x4d},
324 {0x38, 0x04},
325 {0x39, 0x02},
326 {0x3c, 0x08},
327 {0x3d, 0x0f},
328 {0xd3, 0xc4},
329 {0x43, 0x08},
330 {0x1d, 0x00},
331 {REG_NULL, 0x00},
332 };
333
334 static const struct gc5025_mode supported_modes[] = {
335 {
336 .width = 2592,
337 .height = 1944,
338 .max_fps = {
339 .numerator = 10000,
340 .denominator = 300000,
341 },
342 .exp_def = 0x07C0,
343 .hts_def = 0x12C0,
344 .vts_def = 0x07D0,
345 .reg_list = gc5025_2592x1944_regs,
346 },
347 };
348
349 static const s64 link_freq_menu_items[] = {
350 GC5025_LINK_FREQ_MHZ
351 };
352
353 /* Write registers up to 4 at a time */
gc5025_write_reg(struct i2c_client * client,u8 reg,u8 val)354 static int gc5025_write_reg(struct i2c_client *client, u8 reg, u8 val)
355 {
356 struct i2c_msg msg;
357 u8 buf[2];
358 int ret;
359
360 buf[0] = reg & 0xFF;
361 buf[1] = val;
362
363 msg.addr = client->addr;
364 msg.flags = client->flags;
365 msg.buf = buf;
366 msg.len = sizeof(buf);
367
368 ret = i2c_transfer(client->adapter, &msg, 1);
369 if (ret >= 0)
370 return 0;
371
372 dev_err(&client->dev,
373 "gc5025 write reg(0x%x val:0x%x) failed !\n", reg, val);
374
375 return ret;
376 }
377
gc5025_write_array(struct i2c_client * client,const struct regval * regs)378 static int gc5025_write_array(struct i2c_client *client,
379 const struct regval *regs)
380 {
381 u32 i = 0;
382 int ret = 0;
383
384 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
385 ret = gc5025_write_reg(client, regs[i].addr, regs[i].val);
386
387 return ret;
388 }
389
390 /* Read registers up to 4 at a time */
gc5025_read_reg(struct i2c_client * client,u8 reg,u8 * val)391 static int gc5025_read_reg(struct i2c_client *client, u8 reg, u8 *val)
392 {
393 struct i2c_msg msg[2];
394 u8 buf[1];
395 int ret;
396
397 buf[0] = reg & 0xFF;
398
399 msg[0].addr = client->addr;
400 msg[0].flags = client->flags;
401 msg[0].buf = buf;
402 msg[0].len = sizeof(buf);
403
404 msg[1].addr = client->addr;
405 msg[1].flags = client->flags | I2C_M_RD;
406 msg[1].buf = buf;
407 msg[1].len = 1;
408
409 ret = i2c_transfer(client->adapter, msg, 2);
410 if (ret >= 0) {
411 *val = buf[0];
412 return 0;
413 }
414
415 dev_err(&client->dev,
416 "gc5025 read reg:0x%x failed !\n", reg);
417
418 return ret;
419 }
420
gc5025_get_reso_dist(const struct gc5025_mode * mode,struct v4l2_mbus_framefmt * framefmt)421 static int gc5025_get_reso_dist(const struct gc5025_mode *mode,
422 struct v4l2_mbus_framefmt *framefmt)
423 {
424 return abs(mode->width - framefmt->width) +
425 abs(mode->height - framefmt->height);
426 }
427
428 static const struct gc5025_mode *
gc5025_find_best_fit(struct v4l2_subdev_format * fmt)429 gc5025_find_best_fit(struct v4l2_subdev_format *fmt)
430 {
431 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
432 int dist;
433 int cur_best_fit = 0;
434 int cur_best_fit_dist = -1;
435 unsigned int i;
436
437 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
438 dist = gc5025_get_reso_dist(&supported_modes[i], framefmt);
439 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
440 cur_best_fit_dist = dist;
441 cur_best_fit = i;
442 }
443 }
444
445 return &supported_modes[cur_best_fit];
446 }
447
gc5025_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)448 static int gc5025_set_fmt(struct v4l2_subdev *sd,
449 struct v4l2_subdev_pad_config *cfg,
450 struct v4l2_subdev_format *fmt)
451 {
452 struct gc5025 *gc5025 = to_gc5025(sd);
453 const struct gc5025_mode *mode;
454 s64 h_blank, vblank_def;
455
456 mutex_lock(&gc5025->mutex);
457
458 mode = gc5025_find_best_fit(fmt);
459 fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
460 fmt->format.width = mode->width;
461 fmt->format.height = mode->height;
462 fmt->format.field = V4L2_FIELD_NONE;
463 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
464 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
465 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
466 #else
467 mutex_unlock(&gc5025->mutex);
468 return -ENOTTY;
469 #endif
470 } else {
471 gc5025->cur_mode = mode;
472 h_blank = mode->hts_def - mode->width;
473 __v4l2_ctrl_modify_range(gc5025->hblank, h_blank,
474 h_blank, 1, h_blank);
475 vblank_def = mode->vts_def - mode->height;
476 __v4l2_ctrl_modify_range(gc5025->vblank, vblank_def,
477 GC5025_VTS_MAX - mode->height,
478 1, vblank_def);
479 }
480
481 mutex_unlock(&gc5025->mutex);
482
483 return 0;
484 }
485
gc5025_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)486 static int gc5025_get_fmt(struct v4l2_subdev *sd,
487 struct v4l2_subdev_pad_config *cfg,
488 struct v4l2_subdev_format *fmt)
489 {
490 struct gc5025 *gc5025 = to_gc5025(sd);
491 const struct gc5025_mode *mode = gc5025->cur_mode;
492
493 mutex_lock(&gc5025->mutex);
494 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
495 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
496 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
497 #else
498 mutex_unlock(&gc5025->mutex);
499 return -ENOTTY;
500 #endif
501 } else {
502 fmt->format.width = mode->width;
503 fmt->format.height = mode->height;
504 fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
505 fmt->format.field = V4L2_FIELD_NONE;
506 }
507 mutex_unlock(&gc5025->mutex);
508
509 return 0;
510 }
511
gc5025_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)512 static int gc5025_enum_mbus_code(struct v4l2_subdev *sd,
513 struct v4l2_subdev_pad_config *cfg,
514 struct v4l2_subdev_mbus_code_enum *code)
515 {
516 if (code->index != 0)
517 return -EINVAL;
518 code->code = MEDIA_BUS_FMT_SRGGB10_1X10;
519
520 return 0;
521 }
522
gc5025_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)523 static int gc5025_enum_frame_sizes(struct v4l2_subdev *sd,
524 struct v4l2_subdev_pad_config *cfg,
525 struct v4l2_subdev_frame_size_enum *fse)
526 {
527 if (fse->index >= ARRAY_SIZE(supported_modes))
528 return -EINVAL;
529
530 if (fse->code != MEDIA_BUS_FMT_SRGGB10_1X10)
531 return -EINVAL;
532
533 fse->min_width = supported_modes[fse->index].width;
534 fse->max_width = supported_modes[fse->index].width;
535 fse->max_height = supported_modes[fse->index].height;
536 fse->min_height = supported_modes[fse->index].height;
537
538 return 0;
539 }
540
gc5025_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)541 static int gc5025_g_frame_interval(struct v4l2_subdev *sd,
542 struct v4l2_subdev_frame_interval *fi)
543 {
544 struct gc5025 *gc5025 = to_gc5025(sd);
545 const struct gc5025_mode *mode = gc5025->cur_mode;
546
547 fi->interval = mode->max_fps;
548
549 return 0;
550 }
551
gc5025_otp_read_reg(struct i2c_client * client,int page,int address)552 static int gc5025_otp_read_reg(struct i2c_client *client,
553 int page,
554 int address)
555 {
556 int ret = 0;
557 u8 val = 0;
558 u8 addr_high = 0;
559
560 ret = gc5025_write_reg(client, 0xfe, 0x00);
561 ret |= gc5025_read_reg(client, 0xd4, &addr_high);
562 switch (page) {
563 case 0:
564 addr_high &= 0xfb;
565 break;
566 case 1:
567 addr_high |= 0x04;
568 break;
569 default:
570 break;
571 }
572 addr_high &= 0xfc;
573 addr_high |= (address & 0x300) >> 8;
574 ret |= gc5025_write_reg(client, 0xD4, addr_high);
575 ret |= gc5025_write_reg(client, 0xD5, address & 0xff);
576 ret |= gc5025_write_reg(client, 0xF3, 0x20);
577 ret |= gc5025_read_reg(client, 0xD7, &val);
578 if (ret != 0)
579 return ret;
580 return val;
581 }
582
gc5025_otp_enable(struct gc5025 * gc5025)583 static int gc5025_otp_enable(struct gc5025 *gc5025)
584 {
585 struct i2c_client *client = gc5025->client;
586 u8 otp_clk = 0;
587 u8 otp_en = 0;
588 int ret = 0;
589
590 ret = gc5025_write_reg(client, 0xfe, 0x00);
591 ret |= gc5025_write_reg(client, 0xf7, 0x01);
592 ret |= gc5025_write_reg(client, 0xf8, 0x11);
593 ret |= gc5025_write_reg(client, 0xf9, 0x00);
594 ret |= gc5025_write_reg(client, 0xfa, 0xa0);
595 ret |= gc5025_write_reg(client, 0xfc, 0x2a);
596 ret |= gc5025_write_reg(client, 0xfe, 0x03);
597 ret |= gc5025_write_reg(client, 0x01, 0x07);
598 ret |= gc5025_write_reg(client, 0xfc, 0x2e);
599 ret |= gc5025_write_reg(client, 0xfe, 0x00);
600 usleep_range(10, 20);
601 ret |= gc5025_write_reg(client, 0x88, 0x03);
602 ret |= gc5025_write_reg(client, 0xe7, 0xcc);
603 ret |= gc5025_write_reg(client, 0xfc, 0x2e);
604 ret |= gc5025_write_reg(client, 0xfa, 0xb0);
605
606 ret |= gc5025_read_reg(client, 0xfa, &otp_clk);
607 ret |= gc5025_read_reg(client, 0xd4, &otp_en);
608 otp_clk |= 0x10;
609 otp_en |= 0x80;
610 ret |= gc5025_write_reg(client, 0xfa, otp_clk);
611 ret |= gc5025_write_reg(client, 0xd4, otp_en);
612 usleep_range(100, 200);
613 return ret;
614 }
615
gc5025_otp_disable(struct gc5025 * gc5025)616 static int gc5025_otp_disable(struct gc5025 *gc5025)
617 {
618 struct i2c_client *client = gc5025->client;
619 u8 otp_clk = 0;
620 u8 otp_en = 0;
621 int ret = 0;
622
623 ret = gc5025_read_reg(client, 0xfa, &otp_clk);
624 ret |= gc5025_read_reg(client, 0xd4, &otp_en);
625 otp_clk &= 0xef;
626 otp_en &= 0x7f;
627 ret |= gc5025_write_reg(client, 0xfa, otp_clk);
628 ret |= gc5025_write_reg(client, 0xd4, otp_en);
629 return ret;
630 }
631
gc5025_otp_read(struct gc5025 * gc5025)632 static int gc5025_otp_read(struct gc5025 *gc5025)
633 {
634 int otp_flag, i, j, index, temp, tmpH, tmpL;
635 struct gc5025_otp_info *otp_p;
636 struct device *dev = &gc5025->client->dev;
637 struct i2c_client *client = gc5025->client;
638 int checksum = 0;
639 int page = 0;
640 int total_number = 0;
641 u8 m_DD_Otp_Value[182];
642 u16 dd_rom_start, offset;
643 u8 info_start_add, wb_start_add, golden_start_add;
644 u8 check_dd_flag, type;
645 u8 dd0 = 0, dd1 = 0, dd2 = 0;
646 u16 x, y;
647 int cnt = 0;
648
649 otp_p = devm_kzalloc(dev, sizeof(*otp_p), GFP_KERNEL);
650 if (!otp_p)
651 return -ENOMEM;
652
653 /* OTP info and awb*/
654 otp_flag = gc5025_otp_read_reg(client, 1, 0x00);
655 for (index = 0; index < 2; index++) {
656 switch ((otp_flag >> (4 + 2 * index)) & 0x03) {
657 case 0x00:
658 dev_err(dev, "%s GC5025_OTP_INFO group %d is Empty!\n",
659 __func__, index + 1);
660 break;
661 case 0x01:
662 dev_dbg(dev, "%s GC5025_OTP_INFO group %d is Valid!\n",
663 __func__, index + 1);
664 checksum = 0;
665 info_start_add =
666 INFO_ROM_START_5025 + 8 * index * INFO_WIDTH_5025;
667 otp_p->module_id = gc5025_otp_read_reg(client,
668 1, info_start_add);
669 checksum += otp_p->module_id;
670 otp_p->lens_id = gc5025_otp_read_reg(client,
671 1, info_start_add + 8 * 1);
672 checksum += otp_p->lens_id;
673 otp_p->vcm_driver_id = gc5025_otp_read_reg(client,
674 1, info_start_add + 8 * 2);
675 checksum += otp_p->vcm_driver_id;
676 otp_p->vcm_id = gc5025_otp_read_reg(client, 1,
677 info_start_add + 8 * 3);
678 checksum += otp_p->vcm_id;
679 otp_p->year = gc5025_otp_read_reg(client, 1,
680 info_start_add + 8 * 4);
681 checksum += otp_p->year;
682 otp_p->month = gc5025_otp_read_reg(client,
683 1, info_start_add + 8 * 5);
684 checksum += otp_p->month;
685 otp_p->day = gc5025_otp_read_reg(client,
686 1, info_start_add + 8 * 6);
687 checksum += otp_p->day;
688 checksum = checksum % 255 + 1;
689 temp = gc5025_otp_read_reg(client,
690 1, 0x40 + 8 * index * INFO_WIDTH_5025);
691 if (checksum == temp) {
692 otp_p->flag = 0x80;
693 dev_dbg(dev, "fac info: module(0x%x) lens(0x%x) time(%d_%d_%d)\n",
694 otp_p->module_id,
695 otp_p->lens_id,
696 otp_p->year,
697 otp_p->month,
698 otp_p->day);
699 } else {
700 dev_err(dev, "otp module info check sum error\n");
701 }
702 break;
703 case 0x02:
704 case 0x03:
705 dev_err(dev, "%s GC5025_OTP_INFO group %d is Invalid !!\n",
706 __func__, index + 1);
707 break;
708 default:
709 break;
710 }
711 switch ((otp_flag >> (2 * index)) & 0x03) {
712 case 0x00:
713 dev_err(dev, "%s GC5025_OTP_WB group %d is Empty !\n",
714 __func__, index + 1);
715 break;
716 case 0x01:
717 dev_dbg(dev, "%s GC5025_OTP_WB group %d is Valid !!\n",
718 __func__, index + 1);
719 checksum = 0;
720 wb_start_add =
721 WB_ROM_START_5025 + 8 * index * WB_WIDTH_5025;
722 tmpH = gc5025_otp_read_reg(client,
723 1, wb_start_add);
724 checksum += tmpH;
725 tmpL = gc5025_otp_read_reg(client,
726 1, wb_start_add + 8 * 1);
727 checksum += tmpL;
728 otp_p->rg_ratio = (tmpH << 8) | tmpL;
729 tmpH = gc5025_otp_read_reg(client,
730 1, wb_start_add + 8 * 2);
731 checksum += tmpH;
732 tmpL = gc5025_otp_read_reg(client,
733 1, wb_start_add + 8 * 3);
734 checksum += tmpL;
735 otp_p->bg_ratio = (tmpH << 8) | tmpL;
736 checksum = checksum % 255 + 1;
737 temp = gc5025_otp_read_reg(client,
738 1, 0xa8 + 8 * index * WB_WIDTH_5025);
739 if (checksum == temp) {
740 otp_p->flag = 0x40;
741 dev_dbg(dev, "otp:(rg_ratio 0x%x, bg_ratio 0x%x)\n",
742 otp_p->rg_ratio, otp_p->bg_ratio);
743 }
744 break;
745 case 0x02:
746 case 0x03:
747 dev_err(dev, "%s GC5025_OTP_WB group %d is Invalid !!\n",
748 __func__, index + 1);
749 break;
750 default:
751 break;
752 }
753 }
754 /* OTP awb golden*/
755 otp_flag = gc5025_otp_read_reg(client, 1, 0xd8);
756 for (index = 0; index < 2; index++) {
757 switch ((otp_flag >> (2 * index)) & 0x03) {
758 case 0x00:
759 dev_err(dev, "%s GC5025_OTP_GOLDEN group %d is Empty !\n",
760 __func__, index + 1);
761 break;
762 case 0x01:
763 dev_dbg(dev, "%s GC5025_OTP_GOLDEN group %d is Valid !!\n",
764 __func__, index + 1);
765 checksum = 0;
766 golden_start_add =
767 GOLDEN_ROM_START_5025 + 8 * index * GOLDEN_WIDTH_5025;
768 tmpH = gc5025_otp_read_reg(client,
769 1, golden_start_add);
770 checksum += tmpH;
771 tmpL = gc5025_otp_read_reg(client,
772 1, golden_start_add + 8 * 1);
773 checksum += tmpL;
774 otp_p->golden_rg = (tmpH << 8) | tmpL;
775 tmpH = gc5025_otp_read_reg(client,
776 1, golden_start_add + 8 * 2);
777 checksum += tmpH;
778 tmpL = gc5025_otp_read_reg(client,
779 1, golden_start_add + 8 * 3);
780 checksum += tmpL;
781 otp_p->golden_bg = (tmpH << 8) | tmpL;
782 checksum = checksum % 255 + 1;
783 temp = gc5025_otp_read_reg(client,
784 1,
785 0x100 + 8 * index * GOLDEN_WIDTH_5025);
786 if (checksum == temp) {
787 dev_dbg(dev, "otp:(golden_rg 0x%x, golden_bg 0x%x)\n",
788 otp_p->golden_rg, otp_p->golden_bg);
789 }
790 break;
791 case 0x02:
792 case 0x03:
793 dev_err(dev, "%s GC5025_OTP_GOLDEN group %d is Invalid !!\n",
794 __func__, index + 1);
795 break;
796 default:
797 break;
798 }
799 }
800
801 /* OTP DD calibration data */
802 otp_flag = gc5025_otp_read_reg(client, 0, 0);
803 switch (otp_flag & 0x03) {
804 case 0x00:
805 dev_err(dev, "%s GC5025 OTP:flag_dd is EMPTY!\n",
806 __func__);
807 break;
808 case 0x01:
809 dev_dbg(dev, "%s GC5025 OTP:flag_dd is Valid!\n",
810 __func__);
811 checksum = 0;
812 total_number = gc5025_otp_read_reg(client, 0, 0x08) +
813 gc5025_otp_read_reg(client, 0, 0x10);
814 for (i = 0; i < 126; i++) {
815 m_DD_Otp_Value[i] =
816 gc5025_otp_read_reg(client,
817 0, 0x08 + 8 * i);
818 checksum += m_DD_Otp_Value[i];
819 }
820 for (i = 0; i < 56; i++) {
821 m_DD_Otp_Value[126 + i] =
822 gc5025_otp_read_reg(client,
823 1, 0x148 + 8 * i);
824 checksum += m_DD_Otp_Value[126 + i];
825 }
826 checksum = checksum % 255 + 1;
827 temp = gc5025_otp_read_reg(client, 1, 0x308);
828 if (checksum == temp) {
829 for (i = 0; i < total_number; i++) {
830 if (i < 31) {
831 page = 0;
832 dd_rom_start = 0x18;
833 offset = 0;
834 } else {
835 page = 1;
836 dd_rom_start = 0x148;
837 offset = 124;//31*4
838 }
839 check_dd_flag = gc5025_otp_read_reg(client,
840 page,
841 dd_rom_start + 8 * (4 * i - offset + 3));
842 if (check_dd_flag & 0x10) {
843 //Read OTP
844 type = check_dd_flag & 0x0f;
845 dd0 = gc5025_otp_read_reg(client, page,
846 dd_rom_start + 8 * (4 * i - offset));
847 dd1 = gc5025_otp_read_reg(client,
848 page,
849 dd_rom_start + 8 * (4 * i - offset + 1));
850 dd2 = gc5025_otp_read_reg(client,
851 page,
852 dd_rom_start + 8 * (4 * i - offset + 2));
853 x = ((dd1 & 0x0f) << 8) + dd0;
854 y = (dd2 << 4) + ((dd1 & 0xf0) >> 4);
855
856 if (type == 3) {
857 for (j = 0; j < 4; j++) {
858 otp_p->dd_param_x[cnt] = x;
859 otp_p->dd_param_y[cnt] = y + j;
860 otp_p->dd_param_type[cnt++] = 2;
861 }
862 } else if (type == 4) {
863 for (j = 0; j < 2; j++) {
864 otp_p->dd_param_x[cnt] = x;
865 otp_p->dd_param_y[cnt] = y + j;
866 otp_p->dd_param_type[cnt++] = 2;
867 }
868 } else {
869 otp_p->dd_param_x[cnt] = x;
870 otp_p->dd_param_y[cnt] = y;
871 otp_p->dd_param_type[cnt++] = type;
872 }
873 } else {
874 dev_err(dev, "%s GC5025_OTP_DD:check_id[%d] = %x,checkid error!!\n",
875 __func__, i, check_dd_flag);
876 }
877 }
878 otp_p->dd_cnt = cnt;
879 otp_p->flag |= 0x08;
880 }
881 break;
882 case 0x02:
883 case 0x03:
884 dev_err(dev, "%s GC5025 OTP:flag_dd is Invalid!\n",
885 __func__);
886 break;
887 default:
888 break;
889 }
890
891 if (otp_p->flag) {
892 gc5025->otp = otp_p;
893 } else {
894 gc5025->otp = NULL;
895 devm_kfree(dev, otp_p);
896 }
897
898 return 0;
899 }
900
gc5025_get_otp(struct gc5025_otp_info * otp,struct rkmodule_inf * inf)901 static void gc5025_get_otp(struct gc5025_otp_info *otp,
902 struct rkmodule_inf *inf)
903 {
904 u32 i;
905
906 /* fac */
907 if (otp->flag & 0x80) {
908 inf->fac.flag = 1;
909 inf->fac.year = otp->year;
910 inf->fac.month = otp->month;
911 inf->fac.day = otp->day;
912 for (i = 0; i < ARRAY_SIZE(gc5025_module_info) - 1; i++) {
913 if (gc5025_module_info[i].id == otp->module_id)
914 break;
915 }
916 strlcpy(inf->fac.module, gc5025_module_info[i].name,
917 sizeof(inf->fac.module));
918
919 for (i = 0; i < ARRAY_SIZE(gc5025_lens_info) - 1; i++) {
920 if (gc5025_lens_info[i].id == otp->lens_id)
921 break;
922 }
923 strlcpy(inf->fac.lens, gc5025_lens_info[i].name,
924 sizeof(inf->fac.lens));
925 }
926 /* awb */
927 if (otp->flag & 0x40) {
928 inf->awb.flag = 1;
929 inf->awb.r_value = otp->rg_ratio;
930 inf->awb.b_value = otp->bg_ratio;
931 inf->awb.gr_value = 0;
932 inf->awb.gb_value = 0;
933
934 inf->awb.golden_r_value = 0;
935 inf->awb.golden_b_value = 0;
936 inf->awb.golden_gr_value = 0;
937 inf->awb.golden_gb_value = 0;
938 }
939 }
940
gc5025_get_module_inf(struct gc5025 * gc5025,struct rkmodule_inf * inf)941 static void gc5025_get_module_inf(struct gc5025 *gc5025,
942 struct rkmodule_inf *inf)
943 {
944 struct gc5025_otp_info *otp = gc5025->otp;
945
946 strlcpy(inf->base.sensor,
947 GC5025_NAME,
948 sizeof(inf->base.sensor));
949 strlcpy(inf->base.module,
950 gc5025->module_name,
951 sizeof(inf->base.module));
952 strlcpy(inf->base.lens,
953 gc5025->len_name,
954 sizeof(inf->base.lens));
955 if (otp)
956 gc5025_get_otp(otp, inf);
957 }
958
gc5025_set_module_inf(struct gc5025 * gc5025,struct rkmodule_awb_cfg * cfg)959 static void gc5025_set_module_inf(struct gc5025 *gc5025,
960 struct rkmodule_awb_cfg *cfg)
961 {
962 mutex_lock(&gc5025->mutex);
963 memcpy(&gc5025->awb_cfg, cfg, sizeof(*cfg));
964 mutex_unlock(&gc5025->mutex);
965 }
966
gc5025_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)967 static long gc5025_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
968 {
969 struct gc5025 *gc5025 = to_gc5025(sd);
970 long ret = 0;
971 u32 stream = 0;
972
973 switch (cmd) {
974 case RKMODULE_GET_MODULE_INFO:
975 gc5025_get_module_inf(gc5025, (struct rkmodule_inf *)arg);
976 break;
977 case RKMODULE_AWB_CFG:
978 gc5025_set_module_inf(gc5025, (struct rkmodule_awb_cfg *)arg);
979 break;
980 case RKMODULE_SET_QUICK_STREAM:
981
982 stream = *((u32 *)arg);
983
984 if (stream) {
985 ret = gc5025_write_reg(gc5025->client,
986 GC5025_REG_SET_PAGE,
987 GC5025_SET_PAGE_ONE);
988 ret |= gc5025_write_reg(gc5025->client,
989 GC5025_REG_CTRL_MODE,
990 GC5025_MODE_STREAMING);
991 } else {
992 ret = gc5025_write_reg(gc5025->client,
993 GC5025_REG_SET_PAGE,
994 GC5025_SET_PAGE_ONE);
995 ret |= gc5025_write_reg(gc5025->client,
996 GC5025_REG_CTRL_MODE,
997 GC5025_MODE_SW_STANDBY);
998 }
999 break;
1000 default:
1001 ret = -ENOTTY;
1002 break;
1003 }
1004
1005 return ret;
1006 }
1007
1008 #ifdef CONFIG_COMPAT
gc5025_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1009 static long gc5025_compat_ioctl32(struct v4l2_subdev *sd,
1010 unsigned int cmd, unsigned long arg)
1011 {
1012 void __user *up = compat_ptr(arg);
1013 struct rkmodule_inf *inf;
1014 struct rkmodule_awb_cfg *cfg;
1015 long ret = 0;
1016 u32 stream = 0;
1017
1018 switch (cmd) {
1019 case RKMODULE_GET_MODULE_INFO:
1020 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1021 if (!inf) {
1022 ret = -ENOMEM;
1023 return ret;
1024 }
1025
1026 ret = gc5025_ioctl(sd, cmd, inf);
1027 if (!ret)
1028 ret = copy_to_user(up, inf, sizeof(*inf));
1029 kfree(inf);
1030 break;
1031 case RKMODULE_AWB_CFG:
1032 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1033 if (!cfg) {
1034 ret = -ENOMEM;
1035 return ret;
1036 }
1037
1038 ret = copy_from_user(cfg, up, sizeof(*cfg));
1039 if (!ret)
1040 ret = gc5025_ioctl(sd, cmd, cfg);
1041 kfree(cfg);
1042 break;
1043 case RKMODULE_SET_QUICK_STREAM:
1044 ret = copy_from_user(&stream, up, sizeof(u32));
1045 if (!ret)
1046 ret = gc5025_ioctl(sd, cmd, &stream);
1047 break;
1048 default:
1049 ret = -ENOTTY;
1050 break;
1051 }
1052
1053 return ret;
1054 }
1055 #endif
1056
1057 /*--------------------------------------------------------------------------*/
gc5025_apply_otp(struct gc5025 * gc5025)1058 static int gc5025_apply_otp(struct gc5025 *gc5025)
1059 {
1060 int R_gain, G_gain, B_gain, base_gain;
1061 struct i2c_client *client = gc5025->client;
1062 struct gc5025_otp_info *otp_p = gc5025->otp;
1063 struct rkmodule_awb_cfg *awb_cfg = &gc5025->awb_cfg;
1064 u32 golden_bg_ratio;
1065 u32 golden_rg_ratio;
1066 u32 golden_g_value;
1067 u16 i, j;
1068 u16 temp_x = 0, temp_y = 0;
1069 u8 temp_type = 0;
1070 u8 temp_val0, temp_val1, temp_val2;
1071 u16 column, ii, iii, jj;
1072
1073 if (!gc5025->awb_cfg.enable)
1074 return 0;
1075
1076 golden_g_value = (awb_cfg->golden_gb_value +
1077 awb_cfg->golden_gr_value) / 2;
1078 golden_bg_ratio =
1079 awb_cfg->golden_b_value * 0x400 / golden_g_value;
1080 golden_rg_ratio =
1081 awb_cfg->golden_r_value * 0x400 / golden_g_value;
1082 /* apply OTP WB Calibration */
1083 if ((otp_p->flag & 0x40) && golden_bg_ratio && golden_rg_ratio) {
1084 /* calculate G gain */
1085 R_gain = golden_rg_ratio * 1000 / otp_p->rg_ratio;
1086 B_gain = golden_bg_ratio * 1000 / otp_p->bg_ratio;
1087 G_gain = 1000;
1088 base_gain = (R_gain < B_gain) ? R_gain : B_gain;
1089 base_gain = (base_gain < G_gain) ? base_gain : G_gain;
1090
1091 R_gain = 0x400 * R_gain / (base_gain);
1092 B_gain = 0x400 * B_gain / (base_gain);
1093 G_gain = 0x400 * G_gain / (base_gain);
1094
1095 /* update sensor WB gain */
1096 gc5025_write_reg(client, 0xfe, 0x00);
1097 gc5025_write_reg(client, 0xc6,
1098 (G_gain & 0x7f8) >> 3);
1099 gc5025_write_reg(client, 0xc7,
1100 (R_gain & 0x7f8) >> 3);
1101 gc5025_write_reg(client, 0xc8,
1102 (B_gain & 0x7f8) >> 3);
1103 gc5025_write_reg(client, 0xc9,
1104 (G_gain & 0x7f8) >> 3);
1105 gc5025_write_reg(client, 0xc4,
1106 ((G_gain & 0X07) << 4) | (R_gain & 0x07));
1107 gc5025_write_reg(client, 0xc5,
1108 ((B_gain & 0X07) << 4) | (G_gain & 0x07));
1109 dev_dbg(&client->dev, "apply awb gain: 0x%x, 0x%x, 0x%x\n",
1110 R_gain, G_gain, B_gain);
1111 }
1112
1113 /* apply OTP DD Calibration */
1114 if (otp_p->flag & 0x08) {
1115 #if defined IMAGE_NORMAL_MIRROR
1116 #elif defined IMAGE_H_MIRROR
1117 for (i = 0; i < otp_p->dd_cnt; i++) {
1118 if (otp_p->dd_param_type[i] == 0) {
1119 otp_p->dd_param_x[i] =
1120 WINDOW_WIDTH - otp_p->dd_param_x[i] + 1;
1121 } else if (otp_p->dd_param_type[i] == 1) {
1122 otp_p->dd_param_x[i] =
1123 WINDOW_WIDTH - otp_p->dd_param_x[i] - 1;
1124 } else {
1125 otp_p->dd_param_x[i] =
1126 WINDOW_WIDTH - otp_p->dd_param_x[i];
1127 }
1128 }
1129 #elif defined IMAGE_V_MIRROR
1130 for (i = 0; i < otp_p->dd_cnt; i++) {
1131 otp_p->dd_param_y[i] =
1132 WINDOW_HEIGHT - otp_p->dd_param_y[i] + 1;
1133 }
1134 #elif defined IMAGE_HV_MIRROR
1135 for (i = 0; i < otp_p->dd_cnt; i++) {
1136 if (otp_p->dd_param_type[i] == 0) {
1137 otp_p->dd_param_x[i] =
1138 WINDOW_WIDTH - otp_p->dd_param_x[i] + 1;
1139 otp_p->dd_param_y[i] =
1140 WINDOW_HEIGHT - otp_p->dd_param_y[i] + 1;
1141 } else if (otp_p->dd_param_type[i] == 1) {
1142 otp_p->dd_param_x[i] =
1143 WINDOW_WIDTH - otp_p->dd_param_x[i] - 1;
1144 otp_p->dd_param_y[i] =
1145 WINDOW_HEIGHT - otp_p->dd_param_y[i] + 1;
1146 } else {
1147 otp_p->dd_param_x[i] =
1148 WINDOW_WIDTH - otp_p->dd_param_x[i];
1149 otp_p->dd_param_y[i] =
1150 WINDOW_HEIGHT - otp_p->dd_param_y[i] + 1;
1151 }
1152 }
1153 #endif
1154 //y
1155 for (i = 0; i < otp_p->dd_cnt - 1; i++) {
1156 for (j = 0; j < otp_p->dd_cnt - 1 - i; j++) {
1157 if (otp_p->dd_param_y[j] >
1158 otp_p->dd_param_y[j + 1]) {
1159 temp_x = otp_p->dd_param_x[j];
1160 otp_p->dd_param_x[j] =
1161 otp_p->dd_param_x[j + 1];
1162 otp_p->dd_param_x[j + 1] =
1163 temp_x;
1164 temp_y =
1165 otp_p->dd_param_y[j];
1166 otp_p->dd_param_y[j] =
1167 otp_p->dd_param_y[j + 1];
1168 otp_p->dd_param_y[j + 1] =
1169 temp_y;
1170 temp_type =
1171 otp_p->dd_param_type[j];
1172 otp_p->dd_param_type[j] =
1173 otp_p->dd_param_type[j + 1];
1174 otp_p->dd_param_type[j + 1] =
1175 temp_type;
1176 }
1177 }
1178 }
1179 //x
1180 column = 0;
1181 for (i = 0 ; i < otp_p->dd_cnt - 1; ++i) {
1182 if (otp_p->dd_param_y[i] == otp_p->dd_param_y[i + 1]) {
1183 column++;
1184 if (otp_p->dd_cnt - 2 != i)
1185 continue;
1186 }
1187 if (otp_p->dd_cnt - 2 == i &&
1188 otp_p->dd_param_y[i] == otp_p->dd_param_y[i + 1]) {
1189 i = otp_p->dd_cnt - 1;
1190 }
1191 iii = i - column;
1192 for (ii = i - column; ii < i ; ++ii) {
1193 for (jj = i - column; jj <
1194 i - (ii - iii); ++jj) {
1195 if (otp_p->dd_param_x[jj] >
1196 otp_p->dd_param_x[jj + 1]) {
1197 temp_x = otp_p->dd_param_x[jj];
1198 otp_p->dd_param_x[jj] =
1199 otp_p->dd_param_x[jj + 1];
1200 otp_p->dd_param_x[jj + 1] =
1201 temp_x;
1202 temp_y =
1203 otp_p->dd_param_y[jj];
1204 otp_p->dd_param_y[jj] =
1205 otp_p->dd_param_y[jj + 1];
1206 otp_p->dd_param_y[jj + 1] =
1207 temp_y;
1208 temp_type =
1209 otp_p->dd_param_type[jj];
1210 otp_p->dd_param_type[jj] =
1211 otp_p->dd_param_type[jj + 1];
1212 otp_p->dd_param_type[jj + 1] =
1213 temp_type;
1214 }
1215 }
1216 }
1217 column = 0;
1218 }
1219
1220 //write SRAM
1221 gc5025_write_reg(client, 0xfe, 0x00);
1222 gc5025_write_reg(client, 0x80, 0x50);
1223 gc5025_write_reg(client, 0xfe, 0x01);
1224 gc5025_write_reg(client, 0xa8, 0x00);
1225 gc5025_write_reg(client, 0x9d, 0x04);
1226 gc5025_write_reg(client, 0xbe, 0x00);
1227 gc5025_write_reg(client, 0xa9, 0x01);
1228
1229 for (i = 0; i < otp_p->dd_cnt; i++) {
1230 temp_val0 = otp_p->dd_param_x[i] & 0x00ff;
1231 temp_val1 = ((otp_p->dd_param_y[i] << 4) & 0x00f0) +
1232 ((otp_p->dd_param_x[i] >> 8) & 0x000f);
1233 temp_val2 = (otp_p->dd_param_y[i] >> 4) & 0xff;
1234 gc5025_write_reg(client, 0xaa, i);
1235 gc5025_write_reg(client, 0xac, temp_val0);
1236 gc5025_write_reg(client, 0xac, temp_val1);
1237 gc5025_write_reg(client, 0xac, temp_val2);
1238 gc5025_write_reg(client, 0xac,
1239 otp_p->dd_param_type[i]);
1240 }
1241 gc5025_write_reg(client, 0xbe, 0x01);
1242 gc5025_write_reg(client, 0xfe, 0x00);
1243 }
1244 return 0;
1245 }
1246
__gc5025_start_stream(struct gc5025 * gc5025)1247 static int __gc5025_start_stream(struct gc5025 *gc5025)
1248 {
1249 int ret;
1250
1251 ret = gc5025_write_array(gc5025->client, gc5025->cur_mode->reg_list);
1252 if (ret)
1253 return ret;
1254
1255 if (gc5025->DR_State) {
1256 ret = gc5025_write_array(gc5025->client,
1257 gc5025_doublereset_reg);
1258 } else {
1259 ret = gc5025_write_array(gc5025->client,
1260 gc5025_disable_doublereset_reg);
1261 }
1262 if (ret)
1263 return ret;
1264 /* In case these controls are set before streaming */
1265 mutex_unlock(&gc5025->mutex);
1266 ret = v4l2_ctrl_handler_setup(&gc5025->ctrl_handler);
1267 mutex_lock(&gc5025->mutex);
1268 if (ret)
1269 return ret;
1270 if (gc5025->otp) {
1271 ret = gc5025_otp_enable(gc5025);
1272 ret |= gc5025_apply_otp(gc5025);
1273 ret |= gc5025_otp_disable(gc5025);
1274 if (ret)
1275 return ret;
1276 }
1277 ret = gc5025_write_reg(gc5025->client,
1278 GC5025_REG_SET_PAGE,
1279 GC5025_SET_PAGE_ONE);
1280 ret |= gc5025_write_reg(gc5025->client,
1281 GC5025_REG_CTRL_MODE,
1282 GC5025_MODE_STREAMING);
1283 return ret;
1284 }
1285
__gc5025_stop_stream(struct gc5025 * gc5025)1286 static int __gc5025_stop_stream(struct gc5025 *gc5025)
1287 {
1288 int ret;
1289
1290 ret = gc5025_write_reg(gc5025->client,
1291 GC5025_REG_SET_PAGE,
1292 GC5025_SET_PAGE_ONE);
1293 ret |= gc5025_write_reg(gc5025->client,
1294 GC5025_REG_CTRL_MODE,
1295 GC5025_MODE_SW_STANDBY);
1296 return ret;
1297 }
1298
gc5025_s_stream(struct v4l2_subdev * sd,int on)1299 static int gc5025_s_stream(struct v4l2_subdev *sd, int on)
1300 {
1301 struct gc5025 *gc5025 = to_gc5025(sd);
1302 struct i2c_client *client = gc5025->client;
1303 int ret = 0;
1304
1305 mutex_lock(&gc5025->mutex);
1306 on = !!on;
1307 if (on == gc5025->streaming)
1308 goto unlock_and_return;
1309
1310 if (on) {
1311 ret = pm_runtime_get_sync(&client->dev);
1312 if (ret < 0) {
1313 pm_runtime_put_noidle(&client->dev);
1314 goto unlock_and_return;
1315 }
1316
1317 ret = __gc5025_start_stream(gc5025);
1318 if (ret) {
1319 v4l2_err(sd, "start stream failed while write regs\n");
1320 pm_runtime_put(&client->dev);
1321 goto unlock_and_return;
1322 }
1323 } else {
1324 __gc5025_stop_stream(gc5025);
1325 pm_runtime_put(&client->dev);
1326 }
1327
1328 gc5025->streaming = on;
1329
1330 unlock_and_return:
1331 mutex_unlock(&gc5025->mutex);
1332
1333 return ret;
1334 }
1335
gc5025_s_power(struct v4l2_subdev * sd,int on)1336 static int gc5025_s_power(struct v4l2_subdev *sd, int on)
1337 {
1338 struct gc5025 *gc5025 = to_gc5025(sd);
1339 struct i2c_client *client = gc5025->client;
1340 int ret = 0;
1341
1342 mutex_lock(&gc5025->mutex);
1343
1344 /* If the power state is not modified - no work to do. */
1345 if (gc5025->power_on == !!on)
1346 goto unlock_and_return;
1347
1348 if (on) {
1349 ret = pm_runtime_get_sync(&client->dev);
1350 if (ret < 0) {
1351 pm_runtime_put_noidle(&client->dev);
1352 goto unlock_and_return;
1353 }
1354
1355 ret = gc5025_write_array(gc5025->client, gc5025_global_regs);
1356 if (ret) {
1357 v4l2_err(sd, "could not set init registers\n");
1358 pm_runtime_put_noidle(&client->dev);
1359 goto unlock_and_return;
1360 }
1361
1362 gc5025->power_on = true;
1363 } else {
1364 pm_runtime_put(&client->dev);
1365 gc5025->power_on = false;
1366 }
1367
1368 unlock_and_return:
1369 mutex_unlock(&gc5025->mutex);
1370
1371 return ret;
1372 }
1373
1374 /* Calculate the delay in us by clock rate and clock cycles */
gc5025_cal_delay(u32 cycles)1375 static inline u32 gc5025_cal_delay(u32 cycles)
1376 {
1377 return DIV_ROUND_UP(cycles, GC5025_XVCLK_FREQ / 1000 / 1000);
1378 }
1379
__gc5025_power_on(struct gc5025 * gc5025)1380 static int __gc5025_power_on(struct gc5025 *gc5025)
1381 {
1382 int ret;
1383 u32 delay_us;
1384 struct device *dev = &gc5025->client->dev;
1385
1386 if (!IS_ERR(gc5025->power_gpio)) {
1387 gpiod_set_value_cansleep(gc5025->power_gpio, 1);
1388 usleep_range(5000, 5100);
1389 }
1390
1391 if (!IS_ERR_OR_NULL(gc5025->pins_default)) {
1392 ret = pinctrl_select_state(gc5025->pinctrl,
1393 gc5025->pins_default);
1394 if (ret < 0)
1395 dev_err(dev, "could not set pins\n");
1396 }
1397 ret = clk_set_rate(gc5025->xvclk, GC5025_XVCLK_FREQ);
1398 if (ret < 0)
1399 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1400 if (clk_get_rate(gc5025->xvclk) != GC5025_XVCLK_FREQ)
1401 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1402 ret = clk_prepare_enable(gc5025->xvclk);
1403 if (ret < 0) {
1404 dev_err(dev, "Failed to enable xvclk\n");
1405 return ret;
1406 }
1407 if (!IS_ERR(gc5025->reset_gpio))
1408 gpiod_set_value_cansleep(gc5025->reset_gpio, 1);
1409
1410 ret = regulator_bulk_enable(GC5025_NUM_SUPPLIES, gc5025->supplies);
1411 if (ret < 0) {
1412 dev_err(dev, "Failed to enable regulators\n");
1413 goto disable_clk;
1414 }
1415
1416 usleep_range(1000, 1100);
1417 if (!IS_ERR(gc5025->reset_gpio))
1418 gpiod_set_value_cansleep(gc5025->reset_gpio, 0);
1419
1420 usleep_range(500, 1000);
1421 if (!IS_ERR(gc5025->pwdn_gpio))
1422 gpiod_set_value_cansleep(gc5025->pwdn_gpio, 0);
1423
1424 /* 8192 cycles prior to first SCCB transaction */
1425 delay_us = gc5025_cal_delay(8192);
1426 usleep_range(delay_us, delay_us * 2);
1427
1428 return 0;
1429
1430 disable_clk:
1431 clk_disable_unprepare(gc5025->xvclk);
1432
1433 return ret;
1434 }
1435
__gc5025_power_off(struct gc5025 * gc5025)1436 static void __gc5025_power_off(struct gc5025 *gc5025)
1437 {
1438 int ret;
1439
1440 if (!IS_ERR(gc5025->pwdn_gpio))
1441 gpiod_set_value_cansleep(gc5025->pwdn_gpio, 1);
1442 clk_disable_unprepare(gc5025->xvclk);
1443 if (!IS_ERR(gc5025->reset_gpio))
1444 gpiod_set_value_cansleep(gc5025->reset_gpio, 1);
1445 if (!IS_ERR_OR_NULL(gc5025->pins_sleep)) {
1446 ret = pinctrl_select_state(gc5025->pinctrl,
1447 gc5025->pins_sleep);
1448 if (ret < 0)
1449 dev_dbg(&gc5025->client->dev, "could not set pins\n");
1450 }
1451 regulator_bulk_disable(GC5025_NUM_SUPPLIES, gc5025->supplies);
1452 }
1453
gc5025_runtime_resume(struct device * dev)1454 static int gc5025_runtime_resume(struct device *dev)
1455 {
1456 struct i2c_client *client = to_i2c_client(dev);
1457 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1458 struct gc5025 *gc5025 = to_gc5025(sd);
1459
1460 return __gc5025_power_on(gc5025);
1461 }
1462
gc5025_runtime_suspend(struct device * dev)1463 static int gc5025_runtime_suspend(struct device *dev)
1464 {
1465 struct i2c_client *client = to_i2c_client(dev);
1466 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1467 struct gc5025 *gc5025 = to_gc5025(sd);
1468
1469 __gc5025_power_off(gc5025);
1470
1471 return 0;
1472 }
1473
1474 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc5025_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1475 static int gc5025_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1476 {
1477 struct gc5025 *gc5025 = to_gc5025(sd);
1478 struct v4l2_mbus_framefmt *try_fmt =
1479 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1480 const struct gc5025_mode *def_mode = &supported_modes[0];
1481
1482 mutex_lock(&gc5025->mutex);
1483 /* Initialize try_fmt */
1484 try_fmt->width = def_mode->width;
1485 try_fmt->height = def_mode->height;
1486 try_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
1487 try_fmt->field = V4L2_FIELD_NONE;
1488
1489 mutex_unlock(&gc5025->mutex);
1490 /* No crop or compose */
1491
1492 return 0;
1493 }
1494 #endif
1495
gc5025_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1496 static int gc5025_enum_frame_interval(struct v4l2_subdev *sd,
1497 struct v4l2_subdev_pad_config *cfg,
1498 struct v4l2_subdev_frame_interval_enum *fie)
1499 {
1500 if (fie->index >= ARRAY_SIZE(supported_modes))
1501 return -EINVAL;
1502
1503 fie->code = MEDIA_BUS_FMT_SRGGB10_1X10;
1504 fie->width = supported_modes[fie->index].width;
1505 fie->height = supported_modes[fie->index].height;
1506 fie->interval = supported_modes[fie->index].max_fps;
1507 return 0;
1508 }
1509
gc5025_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1510 static int gc5025_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1511 struct v4l2_mbus_config *config)
1512 {
1513 u32 val = 0;
1514
1515 val = 1 << (GC5025_LANES - 1) |
1516 V4L2_MBUS_CSI2_CHANNEL_0 |
1517 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1518
1519 config->type = V4L2_MBUS_CSI2_DPHY;
1520 config->flags = val;
1521
1522 return 0;
1523 }
1524
gc5025_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1525 static int gc5025_get_selection(struct v4l2_subdev *sd,
1526 struct v4l2_subdev_pad_config *cfg,
1527 struct v4l2_subdev_selection *sel)
1528 {
1529
1530 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1531 sel->r.left = 0;
1532 sel->r.width = 2592;
1533 sel->r.top = 0;
1534 sel->r.height = 1944;
1535 return 0;
1536 }
1537 return -EINVAL;
1538 }
1539
1540 static const struct dev_pm_ops gc5025_pm_ops = {
1541 SET_RUNTIME_PM_OPS(gc5025_runtime_suspend,
1542 gc5025_runtime_resume, NULL)
1543 };
1544
1545 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1546 static const struct v4l2_subdev_internal_ops gc5025_internal_ops = {
1547 .open = gc5025_open,
1548 };
1549 #endif
1550
1551 static const struct v4l2_subdev_core_ops gc5025_core_ops = {
1552 .s_power = gc5025_s_power,
1553 .ioctl = gc5025_ioctl,
1554 #ifdef CONFIG_COMPAT
1555 .compat_ioctl32 = gc5025_compat_ioctl32,
1556 #endif
1557 };
1558
1559 static const struct v4l2_subdev_video_ops gc5025_video_ops = {
1560 .s_stream = gc5025_s_stream,
1561 .g_frame_interval = gc5025_g_frame_interval,
1562 };
1563
1564 static const struct v4l2_subdev_pad_ops gc5025_pad_ops = {
1565 .enum_mbus_code = gc5025_enum_mbus_code,
1566 .enum_frame_size = gc5025_enum_frame_sizes,
1567 .enum_frame_interval = gc5025_enum_frame_interval,
1568 .get_fmt = gc5025_get_fmt,
1569 .set_fmt = gc5025_set_fmt,
1570 .get_selection = gc5025_get_selection,
1571 .get_mbus_config = gc5025_g_mbus_config,
1572 };
1573
1574 static const struct v4l2_subdev_ops gc5025_subdev_ops = {
1575 .core = &gc5025_core_ops,
1576 .video = &gc5025_video_ops,
1577 .pad = &gc5025_pad_ops,
1578 };
1579
gc5025_set_exposure_reg(struct gc5025 * gc5025,u32 exposure)1580 static int gc5025_set_exposure_reg(struct gc5025 *gc5025, u32 exposure)
1581 {
1582 u32 caltime = 0;
1583 int ret = 0;
1584
1585 caltime = exposure / 2;
1586 caltime = caltime * 2;
1587 gc5025->Dgain_ratio = 256 * exposure / caltime;
1588 ret = gc5025_write_reg(gc5025->client,
1589 GC5025_REG_SET_PAGE,
1590 GC5025_SET_PAGE_ONE);
1591 if (!gc5025->DR_State) {
1592 if (caltime <= 10)
1593 ret |= gc5025_write_reg(gc5025->client, 0xd9, 0xdd);
1594 else
1595 ret |= gc5025_write_reg(gc5025->client, 0xd9, 0xaa);
1596 }
1597 ret |= gc5025_write_reg(gc5025->client,
1598 GC5025_REG_EXPOSURE_H,
1599 (caltime >> 8) & 0x3F);
1600 ret |= gc5025_write_reg(gc5025->client,
1601 GC5025_REG_EXPOSURE_L,
1602 caltime & 0xFF);
1603 return ret;
1604 }
1605
1606 #define GC5025_ANALOG_GAIN_1 64 /*1.00x*/
1607 #define GC5025_ANALOG_GAIN_2 92 // 1.445x
1608
gc5025_set_gain_reg(struct gc5025 * gc5025,u32 a_gain)1609 static int gc5025_set_gain_reg(struct gc5025 *gc5025, u32 a_gain)
1610 {
1611 int ret = 0;
1612 u32 temp = 0;
1613
1614 if (a_gain < 0x40)
1615 a_gain = 0x40;
1616 ret = gc5025_write_reg(gc5025->client,
1617 GC5025_REG_SET_PAGE,
1618 GC5025_SET_PAGE_ONE);
1619 if (a_gain >= GC5025_ANALOG_GAIN_1 &&
1620 a_gain < GC5025_ANALOG_GAIN_2) {
1621 ret |= gc5025_write_reg(gc5025->client,
1622 GC5025_REG_AGAIN, 0x0);
1623 temp = a_gain;
1624 } else {
1625 ret |= gc5025_write_reg(gc5025->client,
1626 GC5025_REG_AGAIN, 0x1);
1627 temp = 64 * a_gain / GC5025_ANALOG_GAIN_2;
1628 }
1629 temp = temp * gc5025->Dgain_ratio / 256;
1630 ret |= gc5025_write_reg(gc5025->client,
1631 GC5025_REG_DGAIN_INT,
1632 temp >> 6);
1633 ret |= gc5025_write_reg(gc5025->client,
1634 GC5025_REG_DGAIN_FRAC,
1635 (temp << 2) & 0xfc);
1636 return ret;
1637 }
1638
gc5025_set_ctrl(struct v4l2_ctrl * ctrl)1639 static int gc5025_set_ctrl(struct v4l2_ctrl *ctrl)
1640 {
1641 struct gc5025 *gc5025 = container_of(ctrl->handler,
1642 struct gc5025, ctrl_handler);
1643 struct i2c_client *client = gc5025->client;
1644 s64 max;
1645 int ret = 0;
1646
1647 /* Propagate change of current control to all related controls */
1648 switch (ctrl->id) {
1649 case V4L2_CID_VBLANK:
1650 /* Update max exposure while meeting expected vblanking */
1651 max = gc5025->cur_mode->height + ctrl->val - 4;
1652 __v4l2_ctrl_modify_range(gc5025->exposure,
1653 gc5025->exposure->minimum, max,
1654 gc5025->exposure->step,
1655 gc5025->exposure->default_value);
1656 break;
1657 }
1658
1659 if (!pm_runtime_get_if_in_use(&client->dev))
1660 return 0;
1661
1662 switch (ctrl->id) {
1663 case V4L2_CID_EXPOSURE:
1664 /* 4 least significant bits of expsoure are fractional part */
1665 ret = gc5025_set_exposure_reg(gc5025, ctrl->val);
1666 break;
1667 case V4L2_CID_ANALOGUE_GAIN:
1668 ret = gc5025_set_gain_reg(gc5025, ctrl->val);
1669 break;
1670 case V4L2_CID_VBLANK:
1671 ret = gc5025_write_reg(gc5025->client,
1672 GC5025_REG_SET_PAGE,
1673 GC5025_SET_PAGE_ONE);
1674 ret |= gc5025_write_reg(gc5025->client,
1675 GC5025_REG_VTS_H,
1676 ((ctrl->val - 24) >> 8) & 0xff);
1677 ret |= gc5025_write_reg(gc5025->client,
1678 GC5025_REG_VTS_L,
1679 (ctrl->val - 24) & 0xff);
1680 break;
1681 default:
1682 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1683 __func__, ctrl->id, ctrl->val);
1684 break;
1685 }
1686
1687 pm_runtime_put(&client->dev);
1688
1689 return ret;
1690 }
1691
1692 static const struct v4l2_ctrl_ops gc5025_ctrl_ops = {
1693 .s_ctrl = gc5025_set_ctrl,
1694 };
1695
gc5025_initialize_controls(struct gc5025 * gc5025)1696 static int gc5025_initialize_controls(struct gc5025 *gc5025)
1697 {
1698 const struct gc5025_mode *mode;
1699 struct v4l2_ctrl_handler *handler;
1700 struct v4l2_ctrl *ctrl;
1701 s64 exposure_max, vblank_def;
1702 u32 h_blank;
1703 int ret;
1704
1705 handler = &gc5025->ctrl_handler;
1706 mode = gc5025->cur_mode;
1707 ret = v4l2_ctrl_handler_init(handler, 8);
1708 if (ret)
1709 return ret;
1710 handler->lock = &gc5025->mutex;
1711
1712 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1713 0, 0, link_freq_menu_items);
1714 if (ctrl)
1715 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1716
1717 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1718 0, GC5025_PIXEL_RATE, 1, GC5025_PIXEL_RATE);
1719
1720 h_blank = mode->hts_def - mode->width;
1721 gc5025->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1722 h_blank, h_blank, 1, h_blank);
1723 if (gc5025->hblank)
1724 gc5025->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1725
1726 vblank_def = mode->vts_def - mode->height;
1727 gc5025->vblank = v4l2_ctrl_new_std(handler, &gc5025_ctrl_ops,
1728 V4L2_CID_VBLANK, vblank_def,
1729 GC5025_VTS_MAX - mode->height,
1730 1, vblank_def);
1731
1732 exposure_max = mode->vts_def - 4;
1733 gc5025->exposure = v4l2_ctrl_new_std(handler, &gc5025_ctrl_ops,
1734 V4L2_CID_EXPOSURE, GC5025_EXPOSURE_MIN,
1735 exposure_max, GC5025_EXPOSURE_STEP,
1736 mode->exp_def);
1737
1738 gc5025->anal_gain = v4l2_ctrl_new_std(handler, &gc5025_ctrl_ops,
1739 V4L2_CID_ANALOGUE_GAIN, GC5025_GAIN_MIN,
1740 GC5025_GAIN_MAX, GC5025_GAIN_STEP,
1741 GC5025_GAIN_DEFAULT);
1742
1743 if (handler->error) {
1744 ret = handler->error;
1745 dev_err(&gc5025->client->dev,
1746 "Failed to init controls(%d)\n", ret);
1747 goto err_free_handler;
1748 }
1749
1750 gc5025->subdev.ctrl_handler = handler;
1751
1752 return 0;
1753
1754 err_free_handler:
1755 v4l2_ctrl_handler_free(handler);
1756
1757 return ret;
1758 }
1759
gc5025_check_sensor_id(struct gc5025 * gc5025,struct i2c_client * client)1760 static int gc5025_check_sensor_id(struct gc5025 *gc5025,
1761 struct i2c_client *client)
1762 {
1763 struct device *dev = &gc5025->client->dev;
1764 u16 id = 0;
1765 u8 reg_H = 0;
1766 u8 reg_L = 0;
1767 u8 flag_doublereset = 0;
1768 u8 flag_GC5025A = 0;
1769 int ret;
1770
1771 ret = gc5025_read_reg(client, GC5025_REG_CHIP_ID_H, ®_H);
1772 ret |= gc5025_read_reg(client, GC5025_REG_CHIP_ID_L, ®_L);
1773 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
1774 if (id != CHIP_ID) {
1775 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1776 return -ENODEV;
1777 }
1778
1779 ret |= gc5025_read_reg(client, 0x26, &flag_doublereset);
1780 ret |= gc5025_read_reg(client, 0x27, &flag_GC5025A);
1781 if ((flag_GC5025A & 0x01) == 0x01) {
1782 dev_warn(dev, "GC5025A sensor!\n");
1783 gc5025->DR_State = false;
1784 } else {
1785 if ((flag_doublereset & 0x03) == 0x01) {
1786 gc5025->DR_State = false;
1787 dev_warn(dev, "GC5025 double reset off\n");
1788 } else {
1789 gc5025->DR_State = true;
1790 dev_warn(dev, "GC5025 double reset on\n");
1791 }
1792 }
1793 return ret;
1794 }
1795
gc5025_configure_regulators(struct gc5025 * gc5025)1796 static int gc5025_configure_regulators(struct gc5025 *gc5025)
1797 {
1798 unsigned int i;
1799
1800 for (i = 0; i < GC5025_NUM_SUPPLIES; i++)
1801 gc5025->supplies[i].supply = gc5025_supply_names[i];
1802
1803 return devm_regulator_bulk_get(&gc5025->client->dev,
1804 GC5025_NUM_SUPPLIES,
1805 gc5025->supplies);
1806 }
1807
gc5025_probe(struct i2c_client * client,const struct i2c_device_id * id)1808 static int gc5025_probe(struct i2c_client *client,
1809 const struct i2c_device_id *id)
1810 {
1811 struct device *dev = &client->dev;
1812 struct device_node *node = dev->of_node;
1813 struct gc5025 *gc5025;
1814 struct v4l2_subdev *sd;
1815 char facing[2];
1816 int ret;
1817
1818 dev_info(dev, "driver version: %02x.%02x.%02x",
1819 DRIVER_VERSION >> 16,
1820 (DRIVER_VERSION & 0xff00) >> 8,
1821 DRIVER_VERSION & 0x00ff);
1822
1823 gc5025 = devm_kzalloc(dev, sizeof(*gc5025), GFP_KERNEL);
1824 if (!gc5025)
1825 return -ENOMEM;
1826
1827 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1828 &gc5025->module_index);
1829 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1830 &gc5025->module_facing);
1831 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1832 &gc5025->module_name);
1833 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1834 &gc5025->len_name);
1835 if (ret) {
1836 dev_err(dev, "could not get module information!\n");
1837 return -EINVAL;
1838 }
1839 gc5025->client = client;
1840 gc5025->cur_mode = &supported_modes[0];
1841
1842 gc5025->xvclk = devm_clk_get(dev, "xvclk");
1843 if (IS_ERR(gc5025->xvclk)) {
1844 dev_err(dev, "Failed to get xvclk\n");
1845 return -EINVAL;
1846 }
1847
1848 gc5025->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1849 if (IS_ERR(gc5025->power_gpio))
1850 dev_warn(dev, "Failed to get power-gpios\n");
1851
1852 gc5025->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1853 if (IS_ERR(gc5025->reset_gpio))
1854 dev_warn(dev, "Failed to get reset-gpios\n");
1855
1856 gc5025->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1857 if (IS_ERR(gc5025->pwdn_gpio))
1858 dev_warn(dev, "Failed to get pwdn-gpios\n");
1859
1860 ret = gc5025_configure_regulators(gc5025);
1861 if (ret) {
1862 dev_err(dev, "Failed to get power regulators\n");
1863 return ret;
1864 }
1865
1866 gc5025->pinctrl = devm_pinctrl_get(dev);
1867 if (!IS_ERR(gc5025->pinctrl)) {
1868 gc5025->pins_default =
1869 pinctrl_lookup_state(gc5025->pinctrl,
1870 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1871 if (IS_ERR(gc5025->pins_default))
1872 dev_err(dev, "could not get default pinstate\n");
1873
1874 gc5025->pins_sleep =
1875 pinctrl_lookup_state(gc5025->pinctrl,
1876 OF_CAMERA_PINCTRL_STATE_SLEEP);
1877 if (IS_ERR(gc5025->pins_sleep))
1878 dev_err(dev, "could not get sleep pinstate\n");
1879 }
1880
1881 mutex_init(&gc5025->mutex);
1882
1883 sd = &gc5025->subdev;
1884 v4l2_i2c_subdev_init(sd, client, &gc5025_subdev_ops);
1885 ret = gc5025_initialize_controls(gc5025);
1886 if (ret)
1887 goto err_destroy_mutex;
1888
1889 ret = __gc5025_power_on(gc5025);
1890 if (ret)
1891 goto err_free_handler;
1892
1893 ret = gc5025_check_sensor_id(gc5025, client);
1894 if (ret)
1895 goto err_power_off;
1896
1897 gc5025_otp_enable(gc5025);
1898 gc5025_otp_read(gc5025);
1899 gc5025_otp_disable(gc5025);
1900
1901 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1902 sd->internal_ops = &gc5025_internal_ops;
1903 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1904 V4L2_SUBDEV_FL_HAS_EVENTS;
1905 #endif
1906 #if defined(CONFIG_MEDIA_CONTROLLER)
1907 gc5025->pad.flags = MEDIA_PAD_FL_SOURCE;
1908 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1909 ret = media_entity_pads_init(&sd->entity, 1, &gc5025->pad);
1910 if (ret < 0)
1911 goto err_power_off;
1912 #endif
1913
1914 memset(facing, 0, sizeof(facing));
1915 if (strcmp(gc5025->module_facing, "back") == 0)
1916 facing[0] = 'b';
1917 else
1918 facing[0] = 'f';
1919
1920 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1921 gc5025->module_index, facing,
1922 GC5025_NAME, dev_name(sd->dev));
1923 ret = v4l2_async_register_subdev_sensor_common(sd);
1924 if (ret) {
1925 dev_err(dev, "v4l2 async register subdev failed\n");
1926 goto err_clean_entity;
1927 }
1928
1929 pm_runtime_set_active(dev);
1930 pm_runtime_enable(dev);
1931 pm_runtime_idle(dev);
1932
1933 return 0;
1934
1935 err_clean_entity:
1936 #if defined(CONFIG_MEDIA_CONTROLLER)
1937 media_entity_cleanup(&sd->entity);
1938 #endif
1939 err_power_off:
1940 __gc5025_power_off(gc5025);
1941 err_free_handler:
1942 v4l2_ctrl_handler_free(&gc5025->ctrl_handler);
1943 err_destroy_mutex:
1944 mutex_destroy(&gc5025->mutex);
1945
1946 return ret;
1947 }
1948
gc5025_remove(struct i2c_client * client)1949 static int gc5025_remove(struct i2c_client *client)
1950 {
1951 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1952 struct gc5025 *gc5025 = to_gc5025(sd);
1953
1954 v4l2_async_unregister_subdev(sd);
1955 #if defined(CONFIG_MEDIA_CONTROLLER)
1956 media_entity_cleanup(&sd->entity);
1957 #endif
1958 v4l2_ctrl_handler_free(&gc5025->ctrl_handler);
1959 mutex_destroy(&gc5025->mutex);
1960
1961 pm_runtime_disable(&client->dev);
1962 if (!pm_runtime_status_suspended(&client->dev))
1963 __gc5025_power_off(gc5025);
1964 pm_runtime_set_suspended(&client->dev);
1965
1966 return 0;
1967 }
1968
1969 #if IS_ENABLED(CONFIG_OF)
1970 static const struct of_device_id gc5025_of_match[] = {
1971 { .compatible = "galaxycore,gc5025" },
1972 {},
1973 };
1974 MODULE_DEVICE_TABLE(of, gc5025_of_match);
1975 #endif
1976
1977 static const struct i2c_device_id gc5025_match_id[] = {
1978 { "galaxycore,gc5025", 0 },
1979 { },
1980 };
1981
1982 static struct i2c_driver gc5025_i2c_driver = {
1983 .driver = {
1984 .name = GC5025_NAME,
1985 .pm = &gc5025_pm_ops,
1986 .of_match_table = of_match_ptr(gc5025_of_match),
1987 },
1988 .probe = &gc5025_probe,
1989 .remove = &gc5025_remove,
1990 .id_table = gc5025_match_id,
1991 };
1992
sensor_mod_init(void)1993 static int __init sensor_mod_init(void)
1994 {
1995 return i2c_add_driver(&gc5025_i2c_driver);
1996 }
1997
sensor_mod_exit(void)1998 static void __exit sensor_mod_exit(void)
1999 {
2000 i2c_del_driver(&gc5025_i2c_driver);
2001 }
2002
2003 device_initcall_sync(sensor_mod_init);
2004 module_exit(sensor_mod_exit);
2005
2006 MODULE_DESCRIPTION("GalaxyCore gc5025 sensor driver");
2007 MODULE_LICENSE("GPL v2");
2008