1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc4c33 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 fix gain range.
10 * V0.0X01.0X04 add enum_frame_interval function.
11 * V0.0X01.0X05 fix gain reg, add otp and dpc.
12 * V0.0X01.0X06 add set dpc cfg.
13 * V0.0X01.0X07 support enum sensor fmt
14 * V0.0X01.0X08 support mirror and flip
15 * V0.0X01.0X09 add quick stream on/off
16 */
17
18 #include <linux/clk.h>
19 #include <linux/device.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/i2c.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/sysfs.h>
27 #include <linux/slab.h>
28 #include <linux/version.h>
29 #include <linux/rk-camera-module.h>
30 #include <linux/rk-preisp.h>
31 #include <media/media-entity.h>
32 #include <media/v4l2-async.h>
33 #include <media/v4l2-ctrls.h>
34 #include <media/v4l2-subdev.h>
35 #include <linux/pinctrl/consumer.h>
36
37 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x09)
38
39 #ifndef V4L2_CID_DIGITAL_GAIN
40 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
41 #endif
42
43 #define GC4C33_LANES 2
44 #define GC4C33_BITS_PER_SAMPLE 10
45 #define GC4C33_LINK_FREQ 315000000 //2560*1440
46 //#define GC4C33_LINK_FREQ 157500000 //1920*1080
47 //#define GC4C33_LINK_FREQ 261000000 //1280*720
48 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
49 #define GC4C33_PIXEL_RATE (GC4C33_LINK_FREQ * 2 * \
50 GC4C33_LANES / GC4C33_BITS_PER_SAMPLE)
51 #define GC4C33_XVCLK_FREQ 27000000
52
53 #define CHIP_ID 0x46c3
54 #define GC4C33_REG_CHIP_ID_H 0x03f0
55 #define GC4C33_REG_CHIP_ID_L 0x03f1
56
57 #define GC4C33_REG_CTRL_MODE 0x0100
58 #define GC4C33_MODE_SW_STANDBY 0x00
59 #define GC4C33_MODE_STREAMING 0x09
60
61 #define GC4C33_REG_EXPOSURE_H 0x0202
62 #define GC4C33_REG_EXPOSURE_L 0x0203
63 #define GC4C33_EXPOSURE_MIN 4
64 #define GC4C33_EXPOSURE_STEP 1
65 #define GC4C33_VTS_MAX 0x7fff
66
67 #define GC4C33_GAIN_MIN 64
68 #define GC4C33_GAIN_MAX 0xffff
69 #define GC4C33_GAIN_STEP 1
70 #define GC4C33_GAIN_DEFAULT 256
71
72 #define GC4C33_REG_TEST_PATTERN 0x008c
73 #define GC4C33_TEST_PATTERN_ENABLE 0x11
74 #define GC4C33_TEST_PATTERN_DISABLE 0x0
75
76 #define GC4C33_REG_VTS_H 0x0340
77 #define GC4C33_REG_VTS_L 0x0341
78
79 #define GC4C33_REG_DPCC_ENABLE 0x00aa
80 #define GC4C33_REG_DPCC_SINGLE 0x00a1
81 #define GC4C33_REG_DPCC_DOUBLE 0x00a2
82
83 #define GC4C33_FLIP_MIRROR_REG 0x0101
84 #define GC4C33_MIRROR_BIT_MASK BIT(0)
85 #define GC4C33_FLIP_BIT_MASK BIT(1)
86
87 #define REG_NULL 0xFFFF
88
89 #define GC4C33_REG_VALUE_08BIT 1
90 #define GC4C33_REG_VALUE_16BIT 2
91 #define GC4C33_REG_VALUE_24BIT 3
92
93 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
94 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
95 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
96 #define GC4C33_NAME "gc4c33"
97
98 #define GC4C33_ENABLE_DPCC
99 #define GC4C33_ENABLE_OTP
100 //#define GC4C33_ENABLE_HIGHLIGHT
101
102 static const char * const gc4c33_supply_names[] = {
103 "dovdd", /* Digital I/O power */
104 "dvdd", /* Digital core power */
105 "avdd", /* Analog power */
106 };
107
108 #define GC4C33_NUM_SUPPLIES ARRAY_SIZE(gc4c33_supply_names)
109
110 struct regval {
111 u16 addr;
112 u8 val;
113 };
114
115 struct gc4c33_mode {
116 u32 bus_fmt;
117 u32 width;
118 u32 height;
119 struct v4l2_fract max_fps;
120 u32 hts_def;
121 u32 vts_def;
122 u32 exp_def;
123 const struct regval *reg_list;
124 u32 hdr_mode;
125 u32 vc[PAD_MAX];
126 };
127
128 struct gc4c33 {
129 struct i2c_client *client;
130 struct clk *xvclk;
131 struct gpio_desc *reset_gpio;
132 struct gpio_desc *pwdn_gpio;
133 struct gpio_desc *pwren_gpio;
134 struct regulator_bulk_data supplies[GC4C33_NUM_SUPPLIES];
135
136 struct pinctrl *pinctrl;
137 struct pinctrl_state *pins_default;
138 struct pinctrl_state *pins_sleep;
139
140 struct v4l2_subdev subdev;
141 struct media_pad pad;
142 struct v4l2_ctrl_handler ctrl_handler;
143 struct v4l2_ctrl *exposure;
144 struct v4l2_ctrl *anal_gain;
145 struct v4l2_ctrl *digi_gain;
146 struct v4l2_ctrl *hblank;
147 struct v4l2_ctrl *vblank;
148 struct v4l2_ctrl *h_flip;
149 struct v4l2_ctrl *v_flip;
150 struct v4l2_ctrl *test_pattern;
151 struct mutex mutex;
152 bool streaming;
153 bool power_on;
154 const struct gc4c33_mode *cur_mode;
155 u32 cfg_num;
156 u32 module_index;
157 const char *module_facing;
158 const char *module_name;
159 const char *len_name;
160 u8 flip;
161 };
162
163 #define to_gc4c33(sd) container_of(sd, struct gc4c33, subdev)
164
165 /*
166 * Xclk 24Mhz
167 */
168 static const struct regval gc4c33_global_regs[] = {
169 {REG_NULL, 0x00},
170 };
171
172 static const u32 reg_val_table[43][9] = {
173 {0x00, 0x39, 0x00, 0x39, 0x00, 0x00, 0x01, 0x00, 0x20},
174 {0x00, 0x39, 0x00, 0x39, 0x08, 0x00, 0x01, 0x0B, 0x20},
175 {0x00, 0x39, 0x00, 0x39, 0x01, 0x00, 0x01, 0x1B, 0x1e},
176 {0x00, 0x39, 0x00, 0x39, 0x09, 0x00, 0x01, 0x2A, 0x1c},
177 {0x00, 0x39, 0x00, 0x39, 0x10, 0x00, 0x01, 0x3E, 0x1a},
178 {0x00, 0x39, 0x00, 0x39, 0x18, 0x00, 0x02, 0x13, 0x18},
179 {0x00, 0x39, 0x00, 0x39, 0x11, 0x00, 0x02, 0x33, 0x18},
180 {0x00, 0x39, 0x00, 0x39, 0x19, 0x00, 0x03, 0x11, 0x16},
181 {0x00, 0x39, 0x00, 0x39, 0x30, 0x00, 0x03, 0x3B, 0x16},
182 {0x00, 0x39, 0x00, 0x39, 0x38, 0x00, 0x04, 0x26, 0x14},
183 {0x00, 0x39, 0x00, 0x39, 0x31, 0x00, 0x05, 0x24, 0x14},
184 {0x00, 0x39, 0x00, 0x39, 0x39, 0x00, 0x06, 0x21, 0x12},
185 {0x00, 0x39, 0x00, 0x39, 0x32, 0x00, 0x07, 0x28, 0x12},
186 {0x00, 0x39, 0x00, 0x39, 0x3a, 0x00, 0x08, 0x3C, 0x12},
187 {0x00, 0x39, 0x00, 0x39, 0x33, 0x00, 0x0A, 0x3F, 0x10},
188 {0x00, 0x39, 0x00, 0x39, 0x3b, 0x00, 0x0C, 0x38, 0x10},
189 {0x00, 0x39, 0x00, 0x39, 0x34, 0x00, 0x0F, 0x17, 0x0e},
190 {0x00, 0x39, 0x00, 0x39, 0x3c, 0x00, 0x11, 0x3F, 0x0c},
191 {0x00, 0x39, 0x00, 0x39, 0xb4, 0x00, 0x15, 0x34, 0x0a},
192 {0x00, 0x39, 0x00, 0x39, 0xbc, 0x00, 0x19, 0x22, 0x08},
193 {0x00, 0x39, 0x00, 0x39, 0x34, 0x01, 0x1E, 0x09, 0x06},
194 {0x00, 0x39, 0x00, 0x39, 0x3c, 0x11, 0x1A, 0x31, 0x14},
195 {0x00, 0x32, 0x00, 0x32, 0x3c, 0x11, 0x20, 0x12, 0x13},
196 {0x00, 0x3a, 0x00, 0x3a, 0x3c, 0x11, 0x25, 0x28, 0x12},
197 {0x00, 0x33, 0x00, 0x33, 0x3c, 0x11, 0x2D, 0x28, 0x11},
198 {0x00, 0x3b, 0x00, 0x3b, 0x3c, 0x11, 0x35, 0x0A, 0x10},
199 {0x00, 0x34, 0x00, 0x34, 0x3c, 0x11, 0x3F, 0x22, 0x0e},
200 {0x00, 0x3c, 0x00, 0x3c, 0x3c, 0x11, 0x4A, 0x02, 0x0c},
201 {0x00, 0xb4, 0x00, 0xb4, 0x3c, 0x11, 0x5A, 0x36, 0x0a},
202 {0x00, 0xbc, 0x00, 0xbc, 0x3c, 0x11, 0x69, 0x37, 0x0a},
203 {0x01, 0x34, 0x10, 0x34, 0x3c, 0x11, 0x7E, 0x13, 0x08},
204 {0x01, 0x3c, 0x10, 0x3c, 0x3c, 0x11, 0x93, 0x0B, 0x06},
205 {0x01, 0xb4, 0x10, 0xb4, 0x3c, 0x11, 0xB4, 0x19, 0x04},
206 {0x01, 0xbc, 0x10, 0xbc, 0x3c, 0x11, 0xD2, 0x0E, 0x02},
207 {0x02, 0x34, 0x20, 0x34, 0x3c, 0x11, 0xFC, 0x0B, 0x02},
208 {0x02, 0x3c, 0x20, 0x3c, 0x3c, 0x11, 0xff, 0xff, 0x02},
209 {0x01, 0xf4, 0x10, 0xf4, 0x3c, 0x11, 0xff, 0xff, 0x02},
210 {0x01, 0xfc, 0x10, 0xfc, 0x3c, 0x11, 0xff, 0xff, 0x02},
211 {0x02, 0x74, 0x20, 0x74, 0x3c, 0x11, 0xff, 0xff, 0x02},
212 {0x02, 0x7c, 0x20, 0x7c, 0x3c, 0x11, 0xff, 0xff, 0x02},
213 {0x02, 0x75, 0x20, 0x75, 0x3c, 0x11, 0xff, 0xff, 0x02},
214 {0x02, 0x7d, 0x20, 0x7d, 0x3c, 0x11, 0xff, 0xff, 0x02},
215 {0x02, 0xf5, 0x20, 0xf5, 0x3c, 0x11, 0xff, 0xff, 0x02},
216 };
217
218 static const u32 gain_level_table[44] = {
219 64,
220 75,
221 91,
222 106,
223 126,
224 147,
225 179,
226 209,
227 251,
228 294,
229 356,
230 417,
231 488,
232 572,
233 703,
234 824,
235 983,
236 1151,
237 1396,
238 1634,
239 1929,
240 1702,
241 2066,
242 2377,
243 2957,
244 3402,
245 4096,
246 4738,
247 5814,
248 6775,
249 8083,
250 9419,
251 11545,
252 13454,
253 16139,
254 18808,
255 22695,
256 26447,
257 31725,
258 36971,
259 44784,
260 52188,
261 62977,
262 0xffffffff
263 };
264
265 static const u32 reg_Val_Table_720P[32][5] = {
266 {0x00, 0x00, 0x01, 0x00, 0x20},
267 {0x08, 0x00, 0x01, 0x0A, 0x20},
268 {0x01, 0x00, 0x01, 0x19, 0x1E},
269 {0x09, 0x00, 0x01, 0x26, 0x1C},
270 {0x10, 0x00, 0x01, 0x3F, 0x1A},
271 {0x18, 0x00, 0x02, 0x13, 0x18},
272 {0x11, 0x00, 0x02, 0x31, 0x18},
273 {0x19, 0x00, 0x03, 0x0B, 0x16},
274 {0x30, 0x00, 0x04, 0x04, 0x16},
275 {0x38, 0x00, 0x04, 0x2C, 0x14},
276 {0x31, 0x00, 0x05, 0x29, 0x13},
277 {0x39, 0x00, 0x06, 0x1F, 0x12},
278 {0x32, 0x00, 0x07, 0x38, 0x12},
279 {0x3a, 0x00, 0x09, 0x05, 0x12},
280 {0x33, 0x00, 0x0B, 0x12, 0x10},
281 {0x3b, 0x00, 0x0D, 0x00, 0x10},
282 {0x34, 0x00, 0x10, 0x03, 0x0e},
283 {0x3c, 0x00, 0x12, 0x1E, 0x0c},
284 {0xb4, 0x00, 0x16, 0x00, 0x0a},
285 {0xbc, 0x00, 0x19, 0x15, 0x08},
286 {0x34, 0x01, 0x1F, 0x06, 0x06},
287 {0x3c, 0x01, 0x23, 0x33, 0x04},
288 {0xb4, 0x01, 0x2C, 0x22, 0x02},
289 {0xbc, 0x01, 0x33, 0x12, 0x02},
290 {0x34, 0x02, 0x3F, 0x10, 0x02},
291 {0x3c, 0x02, 0x48, 0x34, 0x02},
292 {0xf4, 0x01, 0x5F, 0x06, 0x02},
293 {0xfc, 0x01, 0x6D, 0x1E, 0x02},
294 {0x74, 0x02, 0x87, 0x00, 0x02},
295 {0x7c, 0x02, 0x9B, 0x19, 0x02},
296 {0x75, 0x02, 0xC7, 0x07, 0x02},
297 {0x7d, 0x02, 0xE5, 0x0B, 0x02},
298 };
299
300 static const u32 gain_Level_Table_720P[32] = {
301 64,
302 74,
303 89,
304 102,
305 127,
306 147,
307 177,
308 203,
309 260,
310 300,
311 361,
312 415,
313 504,
314 581,
315 722,
316 832,
317 1027,
318 1182,
319 1408,
320 1621,
321 1990,
322 2291,
323 2850,
324 3282,
325 4048,
326 4660,
327 6086,
328 7006,
329 8640,
330 9945,
331 12743,
332 14667,
333 };
334
335 /*
336 * Xclk 27Mhz
337 * max_framerate 30fps
338 * mipi_datarate per lane 630Mbps, 2lane
339 */
340 static const struct regval gc4c33_linear10bit_2560x1440_regs[] = {
341 {0x03fe, 0xf0},
342 {0x03fe, 0xf0},
343 {0x03fe, 0xf0},
344 {0x03fe, 0xf0},
345 {0x03fe, 0x00},
346 {0x03fe, 0x00},
347 {0x03fe, 0x00},
348 {0x03fe, 0x00},
349 {0x031c, 0x01},
350 {0x0317, 0x24},
351 {0x0320, 0x77},
352 {0x0106, 0x78},
353 {0x0324, 0x84},
354 {0x0327, 0x05},
355 {0x0325, 0x08},
356 {0x0326, 0x2d},
357 {0x031a, 0x00},
358 {0x0314, 0x30},
359 {0x0315, 0x23},
360 {0x0334, 0x00},
361 {0x0337, 0x02},
362 {0x0335, 0x02},
363 {0x0336, 0x1f},
364 {0x0324, 0xc4},
365 {0x0334, 0x40},
366 {0x031c, 0x03},
367 {0x031c, 0xd2},
368 {0x0180, 0x26},
369 {0x031c, 0xd6},
370 {0x0287, 0x18},
371 {0x02ee, 0x70},
372 {0x0202, 0x05},
373 {0x0203, 0xd0},
374 {0x0213, 0x1c},
375 {0x0214, 0x04},
376 {0x0290, 0x00},
377 {0x029d, 0x08},
378 {0x0340, 0x05},
379 {0x0341, 0xdc},
380 {0x0342, 0x01},
381 {0x0343, 0xfe},
382 {0x00f2, 0x04},
383 {0x00f1, 0x0a},
384 {0x00f0, 0xa0},
385 {0x00c1, 0x05},
386 {0x00c2, 0xa0},
387 {0x00c3, 0x0a},
388 {0x00c4, 0x00},
389 {0x00da, 0x05},
390 {0x00db, 0xa0},//1440
391 {0x00d8, 0x0a},
392 {0x00d9, 0x00},//2560
393 {0x00c5, 0x0a},
394 {0x00c6, 0xa0},
395 {0x00bf, 0x17},
396 {0x00ce, 0x0a},
397 {0x00cd, 0x01},
398 {0x00cf, 0x89},
399 {0x023c, 0x06},
400 {0x02d1, 0xc2},
401 {0x027d, 0xcc},
402 {0x0238, 0xa4},
403 {0x02ce, 0x1f},
404 {0x02f9, 0x00},
405 {0x0227, 0x74},
406 {0x0232, 0xc8},
407 {0x0245, 0xa8},
408 {0x027d, 0xcc},
409 {0x02fa, 0xb0},
410 {0x02e7, 0x23},
411 {0x02e8, 0x50},
412 {0x021d, 0x03},
413 {0x0220, 0x43},
414 {0x0228, 0x10},
415 {0x022c, 0x2c},
416 {0x024b, 0x11},
417 {0x024e, 0x11},
418 {0x024d, 0x11},
419 {0x0255, 0x11},
420 {0x025b, 0x11},
421 {0x0262, 0x01},
422 {0x02d4, 0x10},
423 {0x0540, 0x10},
424 {0x0239, 0x00},
425 {0x0231, 0xc4},
426 {0x024f, 0x11},
427 {0x028c, 0x1a},
428 {0x02d3, 0x01},
429 {0x02da, 0x35},
430 {0x02db, 0xd0},
431 {0x02e6, 0x30},
432 {0x0512, 0x00},
433 {0x0513, 0x00},
434 {0x0515, 0x20},
435 {0x0518, 0x00},
436 {0x0519, 0x00},
437 {0x051d, 0x50},
438 {0x0211, 0x00},
439 {0x0216, 0x00},
440 {0x0221, 0x50},
441 {0x0223, 0xcc},
442 {0x0225, 0x07},
443 {0x0229, 0x36},
444 {0x022b, 0x0c},
445 {0x022e, 0x0c},
446 {0x0230, 0x03},
447 {0x023a, 0x38},
448 {0x027b, 0x3c},
449 {0x027c, 0x0c},
450 {0x0298, 0x13},
451 {0x02a4, 0x07},
452 {0x02ab, 0x00},
453 {0x02ac, 0x00},
454 {0x02ad, 0x07},
455 {0x02af, 0x01},
456 {0x02cd, 0x3c},
457 {0x02d2, 0xe8},
458 {0x02e4, 0x00},
459 {0x0530, 0x04},
460 {0x0531, 0x04},
461 {0x0243, 0x36},
462 {0x0219, 0x07},
463 {0x02e5, 0x28},
464 {0x0338, 0xaa},
465 {0x0339, 0xaa},
466 {0x033a, 0x02},
467 {0x023b, 0x20},
468 {0x0212, 0x48},
469 {0x0523, 0x02},
470 {0x0347, 0x06},
471 {0x0348, 0x0a},
472 {0x0349, 0x10},
473 {0x034a, 0x05},
474 {0x034b, 0xb4},
475 {0x0097, 0x0a},
476 {0x0098, 0x10},
477 {0x0099, 0x05},
478 {0x009a, 0xb0},
479 {0x034c, 0x0a},
480 {0x034d, 0x00},
481 {0x034e, 0x05},
482 {0x034f, 0xa0},
483 {0x0354, 0x03},
484 {0x0352, 0x02},
485 {0x0295, 0xff},
486 {0x0296, 0xff},
487 {0x02f0, 0x22},
488 {0x02f1, 0x22},
489 {0x02f2, 0xff},
490 {0x02f4, 0x32},
491 {0x02f5, 0x20},
492 {0x02f6, 0x1c},
493 {0x02f7, 0x1f},
494 {0x02f8, 0x00},
495 {0x0291, 0x04},
496 {0x0292, 0x22},
497 {0x0297, 0x22},
498 {0x02d5, 0xfe},
499 {0x02d6, 0xd0},
500 {0x02d7, 0x35},
501 {0x0268, 0x3b},
502 {0x0269, 0x3b},
503 {0x0272, 0x80},
504 {0x0273, 0x80},
505 {0x0274, 0x80},
506 {0x0275, 0x80},
507 {0x0276, 0x80},
508 {0x0277, 0x80},
509 {0x0278, 0x80},
510 {0x0279, 0x80},
511 {0x0555, 0x50},
512 {0x0556, 0x23},
513 {0x0557, 0x50},
514 {0x0558, 0x23},
515 {0x0559, 0x50},
516 {0x055a, 0x23},
517 {0x055b, 0x50},
518 {0x055c, 0x23},
519 {0x055d, 0x50},
520 {0x055e, 0x23},
521 {0x0550, 0x28},
522 {0x0551, 0x28},
523 {0x0552, 0x28},
524 {0x0553, 0x28},
525 {0x0554, 0x28},
526 {0x0220, 0x43},
527 {0x021f, 0x03},
528 {0x0233, 0x01},
529 {0x0234, 0x80},
530 {0x02be, 0x81},
531 {0x00a0, 0x5d},
532 {0x00c7, 0x94},
533 {0x00c8, 0x15},
534 {0x00df, 0x0a},
535 {0x00de, 0xfe},
536 {0x00c0, 0x0a},
537 {0x031c, 0x80},
538 {0x031f, 0x10},
539 {0x031f, 0x00},
540 {0x031c, 0xd2},
541 {0x031c, 0xd2},
542 {0x031c, 0xd2},
543 {0x031c, 0xd2},
544 {0x031c, 0x80},
545 {0x031f, 0x10},
546 {0x031f, 0x00},
547 {0x031c, 0xd6},
548 {0x0053, 0x00},
549 {0x008e, 0x55},
550 {0x0205, 0xc0},
551 {0x02b0, 0xe0},
552 {0x02b1, 0xe0},
553 {0x02b3, 0x00},
554 {0x02b4, 0x00},
555 {0x02fc, 0x00},
556 {0x02fd, 0x00},
557 {0x0263, 0x00},
558 {0x0267, 0x00},
559 {0x0451, 0x21},
560 {0x0455, 0x05},
561 {0x0452, 0xE6},
562 {0x0456, 0x04},
563 {0x0450, 0xAB},
564 {0x0454, 0x02},
565 {0x0453, 0xAB},
566 {0x0457, 0x02},
567 {0x0226, 0x30},
568 {0x0042, 0x20},
569 {0x0458, 0x01},
570 {0x0459, 0x01},
571 {0x045a, 0x01},
572 {0x045b, 0x01},
573 {0x044c, 0x80},
574 {0x044d, 0x80},
575 {0x044e, 0x80},
576 {0x044f, 0x80},
577 {0x0060, 0x40},
578 {0x00e1, 0x81},
579 {0x00e2, 0x1c},
580 {0x00e4, 0x01},
581 {0x00e5, 0x01},
582 {0x00e6, 0x01},
583 {0x00e7, 0x00},
584 {0x00e8, 0x00},
585 {0x00e9, 0x00},
586 {0x00ea, 0xf0},
587 {0x00ef, 0x04},
588 {0x00a9, 0x20},
589 {0x00b3, 0x00},
590 {0x00b4, 0x10},
591 {0x00b5, 0x20},
592 {0x00b6, 0x30},
593 {0x00b7, 0x40},
594 {0x00d1, 0x06},
595 {0x00d2, 0x04},
596 {0x00d4, 0x02},
597 {0x00d5, 0x04},
598 {0x0089, 0x03},
599 {0x008c, 0x10},
600 {0x0080, 0x04},
601 {0x0180, 0x66},
602 {0x0181, 0x30},
603 {0x0182, 0x55},
604 {0x0185, 0x01},
605 {0x0114, 0x01},
606 {0x0115, 0x12},
607 {0x0103, 0x00},
608 {0x0104, 0x20},
609 {0x00aa, 0x38},
610 {0x00a7, 0x18},
611 {0x00a8, 0x10},
612 {0x00a1, 0xFF},
613 {0x00a2, 0xFF},
614 {REG_NULL, 0x00},
615 };
616
617 /*
618 * Xclk 27Mhz
619 * max_framerate 30fps
620 * mipi_datarate per lane 522Mbps, 2lane
621 */
622 static const struct regval gc4c33_linear10bit_1280x720_regs[] = {
623 {0x031c, 0x01},
624 {0x0317, 0x24},
625 {0x0320, 0x77},
626 {0x0106, 0x78},
627 {0x0324, 0x04},
628 {0x0327, 0x03},
629 {0x0325, 0x00},
630 {0x0326, 0x20},
631 {0x031a, 0x00},
632 {0x0314, 0x30},
633 {0x0315, 0x32},
634 {0x0334, 0x40},
635 {0x0337, 0x03},
636 {0x0335, 0x05},
637 {0x0336, 0x3a},
638 {0x0324, 0x44},
639 {0x0334, 0x40},
640 {0x031c, 0x03},
641 {0x031c, 0xd2},
642 {0x0180, 0x26},
643 {0x031c, 0xd6},
644 {0x0287, 0x18},
645 {0x02ee, 0x70},
646 {0x0202, 0x02},
647 {0x0203, 0xa6},
648 {0x0213, 0x1c},
649 {0x0214, 0x04},
650 {0x0290, 0x00},
651 {0x029d, 0x08},
652 {0x0340, 0x05},
653 {0x0341, 0xdc},
654 {0x0342, 0x03},
655 {0x0343, 0x20},
656 {0x023c, 0x06},
657 {0x02d1, 0xe2},
658 {0x027d, 0xcc},
659 {0x0238, 0xa4},
660 {0x02ce, 0x1f},
661 {0x02f9, 0x00},
662 {0x0227, 0x74},
663 {0x0232, 0xc8},
664 {0x0245, 0xa8},
665 {0x027d, 0xcc},
666 {0x02fa, 0xb0},
667 {0x02e7, 0x23},
668 {0x02e8, 0x50},
669 {0x021d, 0x13},
670 {0x0220, 0x43},
671 {0x0228, 0x10},
672 {0x022c, 0x2c},
673 {0x02c0, 0x11},
674 {0x024b, 0x11},
675 {0x024e, 0x11},
676 {0x024d, 0x11},
677 {0x0255, 0x11},
678 {0x025b, 0x11},
679 {0x0262, 0x01},
680 {0x02d4, 0x10},
681 {0x0540, 0x10},
682 {0x0239, 0x00},
683 {0x0231, 0xc4},
684 {0x024f, 0x11},
685 {0x028c, 0x1a},
686 {0x02d3, 0x01},
687 {0x02da, 0x35},
688 {0x02db, 0xd0},
689 {0x02e6, 0x30},
690 {0x0512, 0x00},
691 {0x0513, 0x00},
692 {0x0515, 0x20},
693 {0x0518, 0x00},
694 {0x0519, 0x00},
695 {0x051d, 0x50},
696 {0x0211, 0x00},
697 {0x0216, 0x00},
698 {0x0221, 0x20},
699 {0x0223, 0xcc},
700 {0x0225, 0x07},
701 {0x0229, 0x36},
702 {0x022b, 0x0c},
703 {0x022e, 0x0c},
704 {0x0230, 0x03},
705 {0x023a, 0x38},
706 {0x027b, 0x3c},
707 {0x027c, 0x0c},
708 {0x0298, 0x13},
709 {0x02a4, 0x07},
710 {0x02ab, 0x00},
711 {0x02ac, 0x00},
712 {0x02ad, 0x07},
713 {0x02af, 0x01},
714 {0x02cd, 0x3c},
715 {0x02d2, 0xe8},
716 {0x02e4, 0x00},
717 {0x0530, 0x04},
718 {0x0531, 0x04},
719 {0x0243, 0x36},
720 {0x0219, 0x07},
721 {0x02e5, 0x28},
722 {0x0338, 0xaa},
723 {0x0339, 0xaa},
724 {0x033a, 0x02},
725 {0x023b, 0x20},
726 {0x0212, 0x48},
727 {0x0523, 0x02},
728 {0x0347, 0x06},
729 {0x0348, 0x0a},
730 {0x0349, 0x10},
731 {0x034a, 0x05},
732 {0x034b, 0xb0},
733 {0x034c, 0x05},
734 {0x034d, 0x00},
735 {0x034e, 0x02},
736 {0x034f, 0xd0},
737 {0x0354, 0x01},
738 {0x0295, 0xff},
739 {0x0296, 0xff},
740 {0x02f0, 0x22},
741 {0x02f1, 0x22},
742 {0x02f2, 0xff},
743 {0x02f4, 0x32},
744 {0x02f5, 0x20},
745 {0x02f6, 0x1c},
746 {0x02f7, 0x1f},
747 {0x02f8, 0x00},
748 {0x0291, 0x04},
749 {0x0292, 0x22},
750 {0x0297, 0x22},
751 {0x02d5, 0xfe},
752 {0x02d6, 0xd0},
753 {0x02d7, 0x35},
754 {0x021f, 0x10},
755 {0x0233, 0x01},
756 {0x0234, 0x03},
757 {0x0224, 0x01},
758 {0x031c, 0x80},
759 {0x031f, 0x10},
760 {0x031f, 0x00},
761 {0x031c, 0xd2},
762 {0x031c, 0xd2},
763 {0x031c, 0xd2},
764 {0x031c, 0xd2},
765 {0x031c, 0x80},
766 {0x031f, 0x10},
767 {0x031f, 0x00},
768 {0x031c, 0xd6},
769 {0x0053, 0x00},
770 {0x008e, 0x55},
771 {0x0205, 0xc0},
772 {0x02b0, 0xf2},
773 {0x02b1, 0xf2},
774 {0x02b3, 0x00},
775 {0x02b4, 0x00},
776 {0x0451, 0x21},
777 {0x0455, 0x05},
778 {0x0452, 0xE6},
779 {0x0456, 0x04},
780 {0x0450, 0xAB},
781 {0x0454, 0x02},
782 {0x0453, 0xAB},
783 {0x0457, 0x02},
784 {0x0226, 0x30},
785 {0x0042, 0x20},
786 {0x0458, 0x01},
787 {0x0459, 0x01},
788 {0x045a, 0x01},
789 {0x045b, 0x01},
790 {0x044c, 0x80},
791 {0x044d, 0x80},
792 {0x044e, 0x80},
793 {0x044f, 0x80},
794 {0x0060, 0x40},
795 {0x00a0, 0x15},
796 {0x00c7, 0x90},
797 {0x00c8, 0x15},
798 {0x00e1, 0x81},
799 {0x00e2, 0x1c},
800 {0x00e4, 0x01},
801 {0x00e5, 0x01},
802 {0x00e6, 0x01},
803 {0x00e7, 0x00},
804 {0x00e8, 0x00},
805 {0x00e9, 0x00},
806 {0x00ea, 0xf0},
807 {0x00ef, 0x04},
808 {0x0089, 0x03},
809 {0x008c, 0x10},
810 {0x0080, 0x04},
811 {0x0180, 0x66},
812 {0x0181, 0x30},
813 {0x0182, 0x55},
814 {0x0185, 0x01},
815 {0x0114, 0x01},
816 {0x0115, 0x12},
817 {0x0103, 0x00},
818 {0x0104, 0x20},
819 {0x00aa, 0x3a},
820 {0x00a7, 0x18},
821 {0x00a8, 0x10},
822 {0x00a1, 0xFF},
823 {0x00a2, 0xFF},
824 {REG_NULL, 0x00},
825 };
826
827 /*
828 * Xclk 27Mhz
829 * max_framerate 30fps
830 * mipi_datarate per lane 630Mbps, 2lane
831 */
832 static const struct regval gc4c33_linear10bit_1920x1080_regs[] = {
833 {0x031c, 0x01},
834 {0x0317, 0x24},
835 {0x0320, 0x77},
836 {0x0106, 0x78},
837 {0x0324, 0x84},
838 {0x0327, 0x30},
839 {0x0325, 0x04},
840 {0x0326, 0x22},
841 {0x031a, 0x00},
842 {0x0314, 0x30},
843 {0x0315, 0x23},
844 {0x0334, 0x00},
845 {0x0337, 0x03},
846 {0x0335, 0x01},
847 {0x0336, 0x46},
848 {0x0324, 0xc4},
849 {0x0334, 0x40},
850 {0x031c, 0x03},
851 {0x031c, 0xd2},
852 {0x0180, 0x26},
853 {0x031c, 0xd6},
854 {0x0287, 0x18},
855 {0x02ee, 0x70},
856 {0x0202, 0x05},
857 {0x0203, 0xd0},
858 {0x0213, 0x1c},
859 {0x0214, 0x04},
860 {0x0290, 0x00},
861 {0x029d, 0x08},
862 {0x0340, 0x05},
863 {0x0341, 0xdc},
864 {0x0342, 0x01},
865 {0x0343, 0xfe},
866 {0x00f2, 0x03},
867 {0x00f1, 0x0e},
868 {0x00f0, 0x2c},
869 {0x00c5, 0x0e},
870 {0x00c6, 0x2a},
871 {0x00bf, 0x16},
872 {0x00ce, 0x00},
873 {0x00cd, 0x01},
874 {0x00cf, 0xe9},
875 {0x023c, 0x06},
876 {0x02d1, 0xc2},
877 {0x027d, 0xcc},
878 {0x0238, 0xa4},
879 {0x02ce, 0x1f},
880 {0x02f9, 0x00},
881 {0x0227, 0x74},
882 {0x0232, 0xc8},
883 {0x0245, 0xa8},
884 {0x027d, 0xcc},
885 {0x02fa, 0xb0},
886 {0x02e7, 0x23},
887 {0x02e8, 0x50},
888 {0x021d, 0x03},
889 {0x0220, 0x43},
890 {0x0228, 0x10},
891 {0x022c, 0x2c},
892 {0x024b, 0x11},
893 {0x024e, 0x11},
894 {0x024d, 0x11},
895 {0x0255, 0x11},
896 {0x025b, 0x11},
897 {0x0262, 0x01},
898 {0x02d4, 0x10},
899 {0x0540, 0x10},
900 {0x0239, 0x00},
901 {0x0231, 0xc4},
902 {0x024f, 0x11},
903 {0x028c, 0x1a},
904 {0x02d3, 0x01},
905 {0x02da, 0x35},
906 {0x02db, 0xd0},
907 {0x02e6, 0x30},
908 {0x0512, 0x00},
909 {0x0513, 0x00},
910 {0x0515, 0x02},
911 {0x0518, 0x00},
912 {0x0519, 0x00},
913 {0x051d, 0x50},
914 {0x0211, 0x00},
915 {0x0216, 0x00},
916 {0x0221, 0x50},
917 {0x0223, 0xcc},
918 {0x0225, 0x07},
919 {0x0229, 0x36},
920 {0x022b, 0x0c},
921 {0x022e, 0x0c},
922 {0x0230, 0x03},
923 {0x023a, 0x38},
924 {0x027b, 0x3c},
925 {0x027c, 0x0c},
926 {0x0298, 0x13},
927 {0x02a4, 0x07},
928 {0x02ab, 0x00},
929 {0x02ac, 0x00},
930 {0x02ad, 0x07},
931 {0x02af, 0x01},
932 {0x02cd, 0x3c},
933 {0x02d2, 0xe8},
934 {0x02e4, 0x00},
935 {0x0530, 0x04},
936 {0x0531, 0x04},
937 {0x0243, 0x36},
938 {0x0219, 0x07},
939 {0x02e5, 0x28},
940 {0x0338, 0xaa},
941 {0x0339, 0xaa},
942 {0x033a, 0x02},
943 {0x023b, 0x20},
944 {0x0212, 0x48},
945 {0x0523, 0x02},
946 {0x0347, 0x06},
947 {0x0348, 0x0a},
948 {0x0349, 0x10},
949 {0x034a, 0x05},
950 {0x034b, 0xb0},
951 {0x034c, 0x07},
952 {0x034d, 0x80},
953 {0x034e, 0x04},
954 {0x034f, 0x38},
955 {0x0354, 0x01},
956 {0x0295, 0xff},
957 {0x0296, 0xff},
958 {0x02f0, 0x22},
959 {0x02f1, 0x22},
960 {0x02f2, 0xff},
961 {0x02f4, 0x32},
962 {0x02f5, 0x20},
963 {0x02f6, 0x1c},
964 {0x02f7, 0x1f},
965 {0x02f8, 0x00},
966 {0x0291, 0x04},
967 {0x0292, 0x22},
968 {0x0297, 0x22},
969 {0x02d5, 0xfe},
970 {0x02d6, 0xd0},
971 {0x02d7, 0x35},
972 {0x0268, 0x3b},
973 {0x0269, 0x3b},
974 {0x0272, 0x80},
975 {0x0273, 0x80},
976 {0x0274, 0x80},
977 {0x0275, 0x80},
978 {0x0276, 0x80},
979 {0x0277, 0x80},
980 {0x0278, 0x80},
981 {0x0279, 0x80},
982 {0x0555, 0x50},
983 {0x0556, 0x23},
984 {0x0557, 0x50},
985 {0x0558, 0x23},
986 {0x0559, 0x50},
987 {0x055a, 0x23},
988 {0x055b, 0x50},
989 {0x055c, 0x23},
990 {0x055d, 0x50},
991 {0x055e, 0x23},
992 {0x0550, 0x28},
993 {0x0551, 0x28},
994 {0x0552, 0x28},
995 {0x0553, 0x28},
996 {0x0554, 0x28},
997 {0x0220, 0x43},
998 {0x021f, 0x03},
999 {0x0233, 0x01},
1000 {0x0234, 0x80},
1001 {0x02be, 0x81},
1002 {0x00a0, 0x5d},
1003 {0x00c7, 0x12},
1004 {0x00c8, 0x15},
1005 {0x00df, 0x0a},
1006 {0x00de, 0xfe},
1007 {0x00aa, 0x3a},
1008 {0x00c0, 0x0a},
1009 {0x00c1, 0x04},
1010 {0x00c2, 0x38},
1011 {0x00c3, 0x07},
1012 {0x00c4, 0x80},
1013 {0x031c, 0x80},
1014 {0x031f, 0x10},
1015 {0x031f, 0x00},
1016 {0x031c, 0xd2},
1017 {0x031c, 0xd2},
1018 {0x031c, 0xd2},
1019 {0x031c, 0xd2},
1020 {0x031c, 0x80},
1021 {0x031f, 0x10},
1022 {0x031f, 0x00},
1023 {0x031c, 0xd6},
1024 {0x0053, 0x00},
1025 {0x008e, 0x55},
1026 {0x0205, 0xc0},
1027 {0x02b0, 0xe0},
1028 {0x02b1, 0xe0},
1029 {0x02b3, 0x00},
1030 {0x02b4, 0x00},
1031 {0x02fc, 0x00},
1032 {0x02fd, 0x00},
1033 {0x0263, 0x00},
1034 {0x0267, 0x00},
1035 {0x0451, 0x00},
1036 {0x0455, 0x04},
1037 {0x0452, 0x00},
1038 {0x0456, 0x04},
1039 {0x0450, 0x00},
1040 {0x0454, 0x04},
1041 {0x0453, 0x20},
1042 {0x0457, 0x04},
1043 {0x0226, 0x30},
1044 {0x0042, 0x20},
1045 {0x0458, 0x01},
1046 {0x0459, 0x01},
1047 {0x045a, 0x01},
1048 {0x045b, 0x01},
1049 {0x044c, 0x80},
1050 {0x044d, 0x80},
1051 {0x044e, 0x80},
1052 {0x044f, 0x80},
1053 {0x0060, 0x40},
1054 {0x00e1, 0x81},
1055 {0x00e2, 0x1c},
1056 {0x00e4, 0x01},
1057 {0x00e5, 0x01},
1058 {0x00e6, 0x01},
1059 {0x00e7, 0x00},
1060 {0x00e8, 0x00},
1061 {0x00e9, 0x00},
1062 {0x00ea, 0xf0},
1063 {0x00ef, 0x04},
1064 {0x00a1, 0x05},
1065 {0x00a2, 0x05},
1066 {0x00a7, 0x00},
1067 {0x00a8, 0x20},
1068 {0x00a9, 0x20},
1069 {0x00b3, 0x00},
1070 {0x00b4, 0x10},
1071 {0x00b5, 0x20},
1072 {0x00b6, 0x30},
1073 {0x00b7, 0x40},
1074 {0x00d1, 0x06},
1075 {0x00d2, 0x04},
1076 {0x00d4, 0x02},
1077 {0x00d5, 0x04},
1078 {0x0089, 0x03},
1079 {0x008c, 0x10},
1080 {0x0080, 0x04},
1081 {0x0180, 0x66},
1082 {0x0181, 0x30},
1083 {0x0182, 0x55},
1084 {0x0185, 0x01},
1085 {0x0114, 0x01},
1086 {0x0115, 0x12},
1087 {0x0103, 0x00},
1088 {0x0104, 0x20},
1089 {0x00aa, 0x3a},
1090 {0x00a7, 0x18},
1091 {0x00a8, 0x10},
1092 {0x00a1, 0xFF},
1093 {0x00a2, 0xFF},
1094 {REG_NULL, 0x00},
1095 };
1096
1097 static const struct gc4c33_mode supported_modes[] = {
1098 {
1099 .width = 2560,
1100 .height = 1440,
1101 .max_fps = {
1102 .numerator = 10000,
1103 .denominator = 300000,
1104 },
1105 .exp_def = 0x0100,
1106 .hts_def = 0x0AA0,
1107 .vts_def = 0x05DC,
1108 .reg_list = gc4c33_linear10bit_2560x1440_regs,
1109 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
1110 .hdr_mode = NO_HDR,
1111 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1112 }, {
1113 .width = 1920,
1114 .height = 1080,
1115 .max_fps = {
1116 .numerator = 10000,
1117 .denominator = 300000,
1118 },
1119 .exp_def = 0x0400,
1120 .hts_def = 0x0E2B,
1121 .vts_def = 0x0465,
1122 .reg_list = gc4c33_linear10bit_1920x1080_regs,
1123 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
1124 .hdr_mode = NO_HDR,
1125 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1126 }, {
1127 .width = 1280,
1128 .height = 720,
1129 .max_fps = {
1130 .numerator = 10000,
1131 .denominator = 300000,
1132 },
1133 .exp_def = 0x0200,
1134 .hts_def = 0x0855,
1135 .vts_def = 0x02EE,
1136 .reg_list = gc4c33_linear10bit_1280x720_regs,
1137 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
1138 .hdr_mode = NO_HDR,
1139 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1140 },
1141 };
1142
1143 static const s64 link_freq_menu_items[] = {
1144 GC4C33_LINK_FREQ
1145 };
1146
1147 static const char * const gc4c33_test_pattern_menu[] = {
1148 "Disabled",
1149 "Vertical Color Bar Type 1",
1150 "Vertical Color Bar Type 2",
1151 "Vertical Color Bar Type 3",
1152 "Vertical Color Bar Type 4"
1153 };
1154
1155 /* Write registers up to 4 at a time */
gc4c33_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)1156 static int gc4c33_write_reg(struct i2c_client *client, u16 reg,
1157 u32 len, u32 val)
1158 {
1159 u32 buf_i, val_i;
1160 u8 buf[6];
1161 u8 *val_p;
1162 __be32 val_be;
1163
1164 if (len > 4)
1165 return -EINVAL;
1166
1167 buf[0] = reg >> 8;
1168 buf[1] = reg & 0xff;
1169
1170 val_be = cpu_to_be32(val);
1171 val_p = (u8 *)&val_be;
1172 buf_i = 2;
1173 val_i = 4 - len;
1174
1175 while (val_i < 4)
1176 buf[buf_i++] = val_p[val_i++];
1177
1178 if (i2c_master_send(client, buf, len + 2) != len + 2)
1179 return -EIO;
1180
1181 return 0;
1182 }
1183
gc4c33_write_array(struct i2c_client * client,const struct regval * regs)1184 static int gc4c33_write_array(struct i2c_client *client,
1185 const struct regval *regs)
1186 {
1187 u32 i;
1188 int ret = 0;
1189
1190 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
1191 ret = gc4c33_write_reg(client, regs[i].addr,
1192 GC4C33_REG_VALUE_08BIT, regs[i].val);
1193
1194 return ret;
1195 }
1196
1197 /* Read registers up to 4 at a time */
gc4c33_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)1198 static int gc4c33_read_reg(struct i2c_client *client, u16 reg,
1199 unsigned int len, u32 *val)
1200 {
1201 struct i2c_msg msgs[2];
1202 u8 *data_be_p;
1203 __be32 data_be = 0;
1204 __be16 reg_addr_be = cpu_to_be16(reg);
1205 int ret;
1206
1207 if (len > 4 || !len)
1208 return -EINVAL;
1209
1210 data_be_p = (u8 *)&data_be;
1211 /* Write register address */
1212 msgs[0].addr = client->addr;
1213 msgs[0].flags = 0;
1214 msgs[0].len = 2;
1215 msgs[0].buf = (u8 *)®_addr_be;
1216
1217 /* Read data from register */
1218 msgs[1].addr = client->addr;
1219 msgs[1].flags = I2C_M_RD;
1220 msgs[1].len = len;
1221 msgs[1].buf = &data_be_p[4 - len];
1222
1223 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1224 if (ret != ARRAY_SIZE(msgs))
1225 return -EIO;
1226
1227 *val = be32_to_cpu(data_be);
1228
1229 return 0;
1230 }
1231
gc4c33_get_reso_dist(const struct gc4c33_mode * mode,struct v4l2_mbus_framefmt * framefmt)1232 static int gc4c33_get_reso_dist(const struct gc4c33_mode *mode,
1233 struct v4l2_mbus_framefmt *framefmt)
1234 {
1235 return abs(mode->width - framefmt->width) +
1236 abs(mode->height - framefmt->height);
1237 }
1238
1239 static const struct gc4c33_mode *
gc4c33_find_best_fit(struct gc4c33 * gc4c33,struct v4l2_subdev_format * fmt)1240 gc4c33_find_best_fit(struct gc4c33 *gc4c33, struct v4l2_subdev_format *fmt)
1241 {
1242 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1243 int dist;
1244 int cur_best_fit = 0;
1245 int cur_best_fit_dist = -1;
1246 unsigned int i;
1247
1248 for (i = 0; i < gc4c33->cfg_num; i++) {
1249 dist = gc4c33_get_reso_dist(&supported_modes[i], framefmt);
1250 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1251 cur_best_fit_dist = dist;
1252 cur_best_fit = i;
1253 }
1254 }
1255
1256 return &supported_modes[cur_best_fit];
1257 }
1258
gc4c33_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1259 static int gc4c33_set_fmt(struct v4l2_subdev *sd,
1260 struct v4l2_subdev_pad_config *cfg,
1261 struct v4l2_subdev_format *fmt)
1262 {
1263 struct gc4c33 *gc4c33 = to_gc4c33(sd);
1264 const struct gc4c33_mode *mode;
1265 s64 h_blank, vblank_def;
1266
1267 mutex_lock(&gc4c33->mutex);
1268
1269 mode = gc4c33_find_best_fit(gc4c33, fmt);
1270 fmt->format.code = mode->bus_fmt;
1271 fmt->format.width = mode->width;
1272 fmt->format.height = mode->height;
1273 fmt->format.field = V4L2_FIELD_NONE;
1274 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1275 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1276 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1277 #else
1278 mutex_unlock(&gc4c33->mutex);
1279 return -ENOTTY;
1280 #endif
1281 } else {
1282 gc4c33->cur_mode = mode;
1283 h_blank = mode->hts_def - mode->width;
1284 __v4l2_ctrl_modify_range(gc4c33->hblank, h_blank,
1285 h_blank, 1, h_blank);
1286 vblank_def = mode->vts_def - mode->height;
1287 __v4l2_ctrl_modify_range(gc4c33->vblank, vblank_def,
1288 GC4C33_VTS_MAX - mode->height,
1289 1, vblank_def);
1290 }
1291
1292 mutex_unlock(&gc4c33->mutex);
1293
1294 return 0;
1295 }
1296
gc4c33_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1297 static int gc4c33_get_fmt(struct v4l2_subdev *sd,
1298 struct v4l2_subdev_pad_config *cfg,
1299 struct v4l2_subdev_format *fmt)
1300 {
1301 struct gc4c33 *gc4c33 = to_gc4c33(sd);
1302 const struct gc4c33_mode *mode = gc4c33->cur_mode;
1303
1304 mutex_lock(&gc4c33->mutex);
1305 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1306 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1307 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1308 #else
1309 mutex_unlock(&gc4c33->mutex);
1310 return -ENOTTY;
1311 #endif
1312 } else {
1313 fmt->format.width = mode->width;
1314 fmt->format.height = mode->height;
1315 fmt->format.code = mode->bus_fmt;
1316 fmt->format.field = V4L2_FIELD_NONE;
1317 }
1318 mutex_unlock(&gc4c33->mutex);
1319
1320 return 0;
1321 }
1322
gc4c33_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1323 static int gc4c33_enum_mbus_code(struct v4l2_subdev *sd,
1324 struct v4l2_subdev_pad_config *cfg,
1325 struct v4l2_subdev_mbus_code_enum *code)
1326 {
1327 struct gc4c33 *gc4c33 = to_gc4c33(sd);
1328
1329 if (code->index != 0)
1330 return -EINVAL;
1331 code->code = gc4c33->cur_mode->bus_fmt;
1332
1333 return 0;
1334 }
1335
gc4c33_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1336 static int gc4c33_enum_frame_sizes(struct v4l2_subdev *sd,
1337 struct v4l2_subdev_pad_config *cfg,
1338 struct v4l2_subdev_frame_size_enum *fse)
1339 {
1340 struct gc4c33 *gc4c33 = to_gc4c33(sd);
1341
1342 if (fse->index >= gc4c33->cfg_num)
1343 return -EINVAL;
1344
1345 if (fse->code != supported_modes[0].bus_fmt)
1346 return -EINVAL;
1347
1348 fse->min_width = supported_modes[fse->index].width;
1349 fse->max_width = supported_modes[fse->index].width;
1350 fse->max_height = supported_modes[fse->index].height;
1351 fse->min_height = supported_modes[fse->index].height;
1352
1353 return 0;
1354 }
1355
gc4c33_enable_test_pattern(struct gc4c33 * gc4c33,u32 pattern)1356 static int gc4c33_enable_test_pattern(struct gc4c33 *gc4c33, u32 pattern)
1357 {
1358 u32 val;
1359
1360 if (pattern)
1361 val = (pattern - 1) | GC4C33_TEST_PATTERN_ENABLE;
1362 else
1363 val = GC4C33_TEST_PATTERN_DISABLE;
1364
1365 return gc4c33_write_reg(gc4c33->client, GC4C33_REG_TEST_PATTERN,
1366 GC4C33_REG_VALUE_08BIT, val);
1367 }
1368
gc4c33_set_gain_reg(struct gc4c33 * gc4c33,u32 gain)1369 static int gc4c33_set_gain_reg(struct gc4c33 *gc4c33, u32 gain)
1370 {
1371 int i;
1372 int total;
1373 u32 tol_dig_gain = 0;
1374
1375 if (gain < 64)
1376 gain = 64;
1377 total = sizeof(gain_level_table) / sizeof(u32) - 1;
1378 for (i = 0; i < total; i++) {
1379 if (gain_level_table[i] <= gain &&
1380 gain < gain_level_table[i + 1])
1381 break;
1382 }
1383 tol_dig_gain = gain * 64 / gain_level_table[i];
1384 if (i >= total)
1385 i = total - 1;
1386 gc4c33_write_reg(gc4c33->client, 0x31d, GC4C33_REG_VALUE_08BIT, 0x2a);
1387 gc4c33_write_reg(gc4c33->client, 0x2fd,
1388 GC4C33_REG_VALUE_08BIT, reg_val_table[i][0]);
1389 gc4c33_write_reg(gc4c33->client, 0x2fc,
1390 GC4C33_REG_VALUE_08BIT, reg_val_table[i][1]);
1391 gc4c33_write_reg(gc4c33->client, 0x263,
1392 GC4C33_REG_VALUE_08BIT, reg_val_table[i][2]);
1393 gc4c33_write_reg(gc4c33->client, 0x267,
1394 GC4C33_REG_VALUE_08BIT, reg_val_table[i][3]);
1395
1396 gc4c33_write_reg(gc4c33->client, 0x31d, GC4C33_REG_VALUE_08BIT, 0x28);
1397
1398 gc4c33_write_reg(gc4c33->client, 0x2b3,
1399 GC4C33_REG_VALUE_08BIT, reg_val_table[i][4]);
1400 gc4c33_write_reg(gc4c33->client, 0x2b4,
1401 GC4C33_REG_VALUE_08BIT, reg_val_table[i][5]);
1402 gc4c33_write_reg(gc4c33->client, 0x2b8,
1403 GC4C33_REG_VALUE_08BIT, reg_val_table[i][6]);
1404 gc4c33_write_reg(gc4c33->client, 0x2b9,
1405 GC4C33_REG_VALUE_08BIT, reg_val_table[i][7]);
1406 gc4c33_write_reg(gc4c33->client, 0x515,
1407 GC4C33_REG_VALUE_08BIT, reg_val_table[i][8]);
1408
1409 gc4c33_write_reg(gc4c33->client, 0x20e,
1410 GC4C33_REG_VALUE_08BIT, (tol_dig_gain >> 6));
1411 gc4c33_write_reg(gc4c33->client, 0x20f,
1412 GC4C33_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f) << 2));
1413 return 0;
1414 }
1415
gc4c33_set_gain_reg_720P(struct gc4c33 * gc4c33,u32 gain)1416 static int gc4c33_set_gain_reg_720P(struct gc4c33 *gc4c33, u32 gain)
1417 {
1418 int i;
1419 int total;
1420 u32 tol_dig_gain = 0;
1421
1422 total = sizeof(gain_Level_Table_720P) / sizeof(u32) - 1;
1423 for (i = 0; i < total; i++) {
1424 if (gain_Level_Table_720P[i] <= gain &&
1425 gain < gain_Level_Table_720P[i + 1])
1426 break;
1427 }
1428 if (gain == gain_Level_Table_720P[total])
1429 i = total;
1430 tol_dig_gain = gain * 64 / gain_Level_Table_720P[i];
1431 gc4c33_write_reg(gc4c33->client, 0x2b3,
1432 GC4C33_REG_VALUE_08BIT, reg_Val_Table_720P[i][0]);
1433 gc4c33_write_reg(gc4c33->client, 0x2b4,
1434 GC4C33_REG_VALUE_08BIT, reg_Val_Table_720P[i][1]);
1435 gc4c33_write_reg(gc4c33->client, 0x2b8,
1436 GC4C33_REG_VALUE_08BIT, reg_Val_Table_720P[i][2]);
1437 gc4c33_write_reg(gc4c33->client, 0x2b9,
1438 GC4C33_REG_VALUE_08BIT, reg_Val_Table_720P[i][3]);
1439 gc4c33_write_reg(gc4c33->client, 0x515,
1440 GC4C33_REG_VALUE_08BIT, reg_Val_Table_720P[i][4]);
1441 gc4c33_write_reg(gc4c33->client, 0x20e,
1442 GC4C33_REG_VALUE_08BIT, (tol_dig_gain >> 6));
1443 gc4c33_write_reg(gc4c33->client, 0x20f,
1444 GC4C33_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f) << 2));
1445 return 0;
1446 }
1447
gc4c33_set_dpcc_cfg(struct gc4c33 * gc4c33,struct rkmodule_dpcc_cfg * dpcc)1448 static int gc4c33_set_dpcc_cfg(struct gc4c33 *gc4c33,
1449 struct rkmodule_dpcc_cfg *dpcc)
1450 {
1451 int ret = 0;
1452
1453 #ifdef GC4C33_ENABLE_DPCC
1454 if (dpcc->enable) {
1455 ret = gc4c33_write_reg(gc4c33->client,
1456 GC4C33_REG_DPCC_ENABLE,
1457 GC4C33_REG_VALUE_08BIT,
1458 0x38 | (dpcc->enable & 0x03));
1459
1460 ret |= gc4c33_write_reg(gc4c33->client,
1461 GC4C33_REG_DPCC_SINGLE,
1462 GC4C33_REG_VALUE_08BIT,
1463 255 - dpcc->cur_single_dpcc *
1464 255 / dpcc->total_dpcc);
1465
1466 ret |= gc4c33_write_reg(gc4c33->client,
1467 GC4C33_REG_DPCC_DOUBLE,
1468 GC4C33_REG_VALUE_08BIT,
1469 255 - dpcc->cur_multiple_dpcc *
1470 255 / dpcc->total_dpcc);
1471 } else {
1472 ret = gc4c33_write_reg(gc4c33->client,
1473 GC4C33_REG_DPCC_ENABLE,
1474 GC4C33_REG_VALUE_08BIT,
1475 0x38);
1476
1477 ret |= gc4c33_write_reg(gc4c33->client,
1478 GC4C33_REG_DPCC_SINGLE,
1479 GC4C33_REG_VALUE_08BIT,
1480 0xff);
1481
1482 ret |= gc4c33_write_reg(gc4c33->client,
1483 GC4C33_REG_DPCC_DOUBLE,
1484 GC4C33_REG_VALUE_08BIT,
1485 0xff);
1486 }
1487 #else
1488 ret = gc4c33_write_reg(gc4c33->client,
1489 GC4C33_REG_DPCC_ENABLE,
1490 GC4C33_REG_VALUE_08BIT,
1491 0x38);
1492
1493 ret |= gc4c33_write_reg(gc4c33->client,
1494 GC4C33_REG_DPCC_SINGLE,
1495 GC4C33_REG_VALUE_08BIT,
1496 0xff);
1497
1498 ret |= gc4c33_write_reg(gc4c33->client,
1499 GC4C33_REG_DPCC_DOUBLE,
1500 GC4C33_REG_VALUE_08BIT,
1501 0xff);
1502 #endif
1503
1504 return ret;
1505 }
1506
gc4c33_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1507 static int gc4c33_g_frame_interval(struct v4l2_subdev *sd,
1508 struct v4l2_subdev_frame_interval *fi)
1509 {
1510 struct gc4c33 *gc4c33 = to_gc4c33(sd);
1511 const struct gc4c33_mode *mode = gc4c33->cur_mode;
1512
1513 fi->interval = mode->max_fps;
1514
1515 return 0;
1516 }
1517
gc4c33_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1518 static int gc4c33_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1519 struct v4l2_mbus_config *config)
1520 {
1521 struct gc4c33 *gc4c33 = to_gc4c33(sd);
1522 const struct gc4c33_mode *mode = gc4c33->cur_mode;
1523 u32 val = 1 << (GC4C33_LANES - 1) |
1524 V4L2_MBUS_CSI2_CHANNEL_0 |
1525 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1526
1527 if (mode->hdr_mode != NO_HDR)
1528 val |= V4L2_MBUS_CSI2_CHANNEL_1;
1529 if (mode->hdr_mode == HDR_X3)
1530 val |= V4L2_MBUS_CSI2_CHANNEL_2;
1531
1532 config->type = V4L2_MBUS_CSI2_DPHY;
1533 config->flags = val;
1534
1535 return 0;
1536 }
1537
gc4c33_get_module_inf(struct gc4c33 * gc4c33,struct rkmodule_inf * inf)1538 static void gc4c33_get_module_inf(struct gc4c33 *gc4c33,
1539 struct rkmodule_inf *inf)
1540 {
1541 memset(inf, 0, sizeof(*inf));
1542 strlcpy(inf->base.sensor, GC4C33_NAME, sizeof(inf->base.sensor));
1543 strlcpy(inf->base.module, gc4c33->module_name,
1544 sizeof(inf->base.module));
1545 strlcpy(inf->base.lens, gc4c33->len_name, sizeof(inf->base.lens));
1546 }
1547
gc4c33_get_channel_info(struct gc4c33 * gc4c33,struct rkmodule_channel_info * ch_info)1548 static int gc4c33_get_channel_info(struct gc4c33 *gc4c33, struct rkmodule_channel_info *ch_info)
1549 {
1550 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1551 return -EINVAL;
1552 ch_info->vc = gc4c33->cur_mode->vc[ch_info->index];
1553 ch_info->width = gc4c33->cur_mode->width;
1554 ch_info->height = gc4c33->cur_mode->height;
1555 ch_info->bus_fmt = gc4c33->cur_mode->bus_fmt;
1556 return 0;
1557 }
1558
gc4c33_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1559 static long gc4c33_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1560 {
1561 struct gc4c33 *gc4c33 = to_gc4c33(sd);
1562 struct rkmodule_hdr_cfg *hdr;
1563 struct rkmodule_nr_switch_threshold *nr_switch;
1564 u32 i, h, w;
1565 long ret = 0;
1566 u32 stream = 0;
1567 struct rkmodule_channel_info *ch_info;
1568
1569 switch (cmd) {
1570 case RKMODULE_GET_MODULE_INFO:
1571 gc4c33_get_module_inf(gc4c33, (struct rkmodule_inf *)arg);
1572 break;
1573 case RKMODULE_GET_HDR_CFG:
1574 hdr = (struct rkmodule_hdr_cfg *)arg;
1575 hdr->esp.mode = HDR_NORMAL_VC;
1576 hdr->hdr_mode = gc4c33->cur_mode->hdr_mode;
1577 break;
1578 case RKMODULE_SET_HDR_CFG:
1579 hdr = (struct rkmodule_hdr_cfg *)arg;
1580 w = gc4c33->cur_mode->width;
1581 h = gc4c33->cur_mode->height;
1582 for (i = 0; i < gc4c33->cfg_num; i++) {
1583 if (w == supported_modes[i].width &&
1584 h == supported_modes[i].height &&
1585 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1586 gc4c33->cur_mode = &supported_modes[i];
1587 break;
1588 }
1589 }
1590 if (i == gc4c33->cfg_num) {
1591 dev_err(&gc4c33->client->dev,
1592 "not find hdr mode:%d %dx%d config\n",
1593 hdr->hdr_mode, w, h);
1594 ret = -EINVAL;
1595 } else {
1596 w = gc4c33->cur_mode->hts_def -
1597 gc4c33->cur_mode->width;
1598 h = gc4c33->cur_mode->vts_def -
1599 gc4c33->cur_mode->height;
1600 __v4l2_ctrl_modify_range(gc4c33->hblank, w, w, 1, w);
1601 __v4l2_ctrl_modify_range(gc4c33->vblank, h,
1602 GC4C33_VTS_MAX -
1603 gc4c33->cur_mode->height,
1604 1, h);
1605 }
1606 break;
1607 case PREISP_CMD_SET_HDRAE_EXP:
1608 break;
1609 case RKMODULE_SET_DPCC_CFG:
1610 ret = gc4c33_set_dpcc_cfg(gc4c33, (struct rkmodule_dpcc_cfg *)arg);
1611 break;
1612 case RKMODULE_GET_NR_SWITCH_THRESHOLD:
1613 nr_switch = (struct rkmodule_nr_switch_threshold *)arg;
1614 nr_switch->direct = 0;
1615 nr_switch->up_thres = 3014;
1616 nr_switch->down_thres = 3014;
1617 nr_switch->div_coeff = 100;
1618 ret = 0;
1619 break;
1620 case RKMODULE_SET_QUICK_STREAM:
1621 stream = *((u32 *)arg);
1622 if (stream)
1623 ret = gc4c33_write_reg(gc4c33->client, GC4C33_REG_CTRL_MODE,
1624 GC4C33_REG_VALUE_08BIT, GC4C33_MODE_STREAMING);
1625 else
1626 ret = gc4c33_write_reg(gc4c33->client, GC4C33_REG_CTRL_MODE,
1627 GC4C33_REG_VALUE_08BIT, GC4C33_MODE_SW_STANDBY);
1628 break;
1629 case RKMODULE_GET_CHANNEL_INFO:
1630 ch_info = (struct rkmodule_channel_info *)arg;
1631 ret = gc4c33_get_channel_info(gc4c33, ch_info);
1632 break;
1633 default:
1634 ret = -ENOIOCTLCMD;
1635 break;
1636 }
1637
1638 return ret;
1639 }
1640
1641 #ifdef CONFIG_COMPAT
gc4c33_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1642 static long gc4c33_compat_ioctl32(struct v4l2_subdev *sd,
1643 unsigned int cmd, unsigned long arg)
1644 {
1645 void __user *up = compat_ptr(arg);
1646 struct rkmodule_inf *inf;
1647 struct rkmodule_awb_cfg *cfg;
1648 struct rkmodule_hdr_cfg *hdr;
1649 struct rkmodule_dpcc_cfg *dpcc;
1650 struct preisp_hdrae_exp_s *hdrae;
1651 struct rkmodule_nr_switch_threshold *nr_switch;
1652 long ret;
1653 u32 stream = 0;
1654 struct rkmodule_channel_info *ch_info;
1655
1656 switch (cmd) {
1657 case RKMODULE_GET_MODULE_INFO:
1658 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1659 if (!inf) {
1660 ret = -ENOMEM;
1661 return ret;
1662 }
1663
1664 ret = gc4c33_ioctl(sd, cmd, inf);
1665 if (!ret) {
1666 ret = copy_to_user(up, inf, sizeof(*inf));
1667 if (ret)
1668 ret = -EFAULT;
1669 }
1670 kfree(inf);
1671 break;
1672 case RKMODULE_AWB_CFG:
1673 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1674 if (!cfg) {
1675 ret = -ENOMEM;
1676 return ret;
1677 }
1678
1679 ret = copy_from_user(cfg, up, sizeof(*cfg));
1680 if (!ret)
1681 ret = gc4c33_ioctl(sd, cmd, cfg);
1682 else
1683 ret = -EFAULT;
1684 kfree(cfg);
1685 break;
1686 case RKMODULE_GET_HDR_CFG:
1687 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1688 if (!hdr) {
1689 ret = -ENOMEM;
1690 return ret;
1691 }
1692
1693 ret = gc4c33_ioctl(sd, cmd, hdr);
1694 if (!ret) {
1695 ret = copy_to_user(up, hdr, sizeof(*hdr));
1696 if (ret)
1697 ret = -EFAULT;
1698 }
1699 kfree(hdr);
1700 break;
1701 case RKMODULE_SET_HDR_CFG:
1702 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1703 if (!hdr) {
1704 ret = -ENOMEM;
1705 return ret;
1706 }
1707
1708 ret = copy_from_user(hdr, up, sizeof(*hdr));
1709 if (!ret)
1710 ret = gc4c33_ioctl(sd, cmd, hdr);
1711 else
1712 ret = -EFAULT;
1713 kfree(hdr);
1714 break;
1715 case RKMODULE_SET_DPCC_CFG:
1716 dpcc = kzalloc(sizeof(*dpcc), GFP_KERNEL);
1717 if (!dpcc) {
1718 ret = -ENOMEM;
1719 return ret;
1720 }
1721
1722 ret = copy_from_user(dpcc, up, sizeof(*dpcc));
1723 if (!ret)
1724 ret = gc4c33_ioctl(sd, cmd, dpcc);
1725 else
1726 ret = -EFAULT;
1727 kfree(dpcc);
1728 break;
1729 case PREISP_CMD_SET_HDRAE_EXP:
1730 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1731 if (!hdrae) {
1732 ret = -ENOMEM;
1733 return ret;
1734 }
1735
1736 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1737 if (!ret)
1738 ret = gc4c33_ioctl(sd, cmd, hdrae);
1739 else
1740 ret = -EFAULT;
1741 kfree(hdrae);
1742 break;
1743 case RKMODULE_GET_NR_SWITCH_THRESHOLD:
1744 nr_switch = kzalloc(sizeof(*nr_switch), GFP_KERNEL);
1745 if (!nr_switch) {
1746 ret = -ENOMEM;
1747 return ret;
1748 }
1749
1750 ret = gc4c33_ioctl(sd, cmd, nr_switch);
1751 if (!ret) {
1752 ret = copy_to_user(up, nr_switch, sizeof(*nr_switch));
1753 if (ret)
1754 ret = -EFAULT;
1755 }
1756 kfree(nr_switch);
1757 break;
1758 case RKMODULE_SET_QUICK_STREAM:
1759 ret = copy_from_user(&stream, up, sizeof(u32));
1760 if (!ret)
1761 ret = gc4c33_ioctl(sd, cmd, &stream);
1762 else
1763 ret = -EFAULT;
1764 break;
1765 case RKMODULE_GET_CHANNEL_INFO:
1766 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1767 if (!ch_info) {
1768 ret = -ENOMEM;
1769 return ret;
1770 }
1771
1772 ret = gc4c33_ioctl(sd, cmd, ch_info);
1773 if (!ret) {
1774 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1775 if (ret)
1776 ret = -EFAULT;
1777 }
1778 kfree(ch_info);
1779 break;
1780 default:
1781 ret = -ENOIOCTLCMD;
1782 break;
1783 }
1784
1785 return ret;
1786 }
1787 #endif
1788
1789 #ifdef GC4C33_ENABLE_OTP
gc4c33_sensor_dpc_otp_dd(struct gc4c33 * gc4c33)1790 static int gc4c33_sensor_dpc_otp_dd(struct gc4c33 *gc4c33)
1791 {
1792 u32 num = 0;
1793 int ret;
1794
1795 ret = gc4c33_write_reg(gc4c33->client, 0x0a70,
1796 GC4C33_REG_VALUE_08BIT, 0x00);
1797 ret |= gc4c33_write_reg(gc4c33->client, 0x0317,
1798 GC4C33_REG_VALUE_08BIT, 0x2c);
1799 ret |= gc4c33_write_reg(gc4c33->client, 0x0a67,
1800 GC4C33_REG_VALUE_08BIT, 0x80);
1801 ret |= gc4c33_write_reg(gc4c33->client, 0x0a4f,
1802 GC4C33_REG_VALUE_08BIT, 0x00);
1803 ret |= gc4c33_write_reg(gc4c33->client, 0x0a54,
1804 GC4C33_REG_VALUE_08BIT, 0x80);
1805 ret |= gc4c33_write_reg(gc4c33->client, 0x0a66,
1806 GC4C33_REG_VALUE_08BIT, 0x03);
1807 ret |= gc4c33_write_reg(gc4c33->client, 0x0a69,
1808 GC4C33_REG_VALUE_08BIT, 0x00);
1809 ret |= gc4c33_write_reg(gc4c33->client, 0x0a6a,
1810 GC4C33_REG_VALUE_08BIT, 0x70);
1811 ret |= gc4c33_write_reg(gc4c33->client, 0x0313,
1812 GC4C33_REG_VALUE_08BIT, 0x20);
1813 ret |= gc4c33_read_reg(gc4c33->client, 0x0a6c,
1814 GC4C33_REG_VALUE_08BIT, &num);
1815 ret |= gc4c33_write_reg(gc4c33->client, 0x0a69,
1816 GC4C33_REG_VALUE_08BIT, 0x00);
1817 ret |= gc4c33_write_reg(gc4c33->client, 0x0a6a,
1818 GC4C33_REG_VALUE_08BIT, 0x10);
1819 ret |= gc4c33_write_reg(gc4c33->client, 0x0313,
1820 GC4C33_REG_VALUE_08BIT, 0x20);
1821
1822 if (num != 0) {
1823 ret |= gc4c33_write_reg(gc4c33->client, 0x0317,
1824 GC4C33_REG_VALUE_08BIT, 0x2c);
1825 ret |= gc4c33_write_reg(gc4c33->client, 0x0a67,
1826 GC4C33_REG_VALUE_08BIT, 0x80);
1827 ret |= gc4c33_write_reg(gc4c33->client, 0x0a66,
1828 GC4C33_REG_VALUE_08BIT, 0x03);
1829 ret |= gc4c33_write_reg(gc4c33->client, 0x0a70,
1830 GC4C33_REG_VALUE_08BIT, 0x05);
1831 ret |= gc4c33_write_reg(gc4c33->client, 0x0a71,
1832 GC4C33_REG_VALUE_08BIT, 0x00);
1833 ret |= gc4c33_write_reg(gc4c33->client, 0x0a72,
1834 GC4C33_REG_VALUE_08BIT, 0x08);
1835 ret |= gc4c33_write_reg(gc4c33->client, 0x0a73,
1836 GC4C33_REG_VALUE_08BIT, num);
1837 ret |= gc4c33_write_reg(gc4c33->client, 0x0a74,
1838 GC4C33_REG_VALUE_08BIT, 0x00);
1839 ret |= gc4c33_write_reg(gc4c33->client, 0x0a75,
1840 GC4C33_REG_VALUE_08BIT, 0x80);
1841 ret |= gc4c33_write_reg(gc4c33->client, 0x05be,
1842 GC4C33_REG_VALUE_08BIT, 0x00);
1843 ret |= gc4c33_write_reg(gc4c33->client, 0x05a9,
1844 GC4C33_REG_VALUE_08BIT, 0x01);
1845 usleep_range(30 * 1000, 30 * 1000 * 2);
1846 ret |= gc4c33_write_reg(gc4c33->client, 0x0313,
1847 GC4C33_REG_VALUE_08BIT, 0x80);
1848 usleep_range(120 * 1000, 120 * 1000 * 2);
1849
1850 ret |= gc4c33_write_reg(gc4c33->client, 0x0080,
1851 GC4C33_REG_VALUE_08BIT, 0x06);
1852 ret |= gc4c33_write_reg(gc4c33->client, 0x05be,
1853 GC4C33_REG_VALUE_08BIT, 0x01);
1854 ret |= gc4c33_write_reg(gc4c33->client, 0x0a70,
1855 GC4C33_REG_VALUE_08BIT, 0x00);
1856 ret |= gc4c33_write_reg(gc4c33->client, 0x0a69,
1857 GC4C33_REG_VALUE_08BIT, 0x00);
1858 ret |= gc4c33_write_reg(gc4c33->client, 0x0a6a,
1859 GC4C33_REG_VALUE_08BIT, 0x10);
1860 ret |= gc4c33_write_reg(gc4c33->client, 0x0313,
1861 GC4C33_REG_VALUE_08BIT, 0x20);
1862 } else {
1863 ret |= gc4c33_write_reg(gc4c33->client, 0x0317,
1864 GC4C33_REG_VALUE_08BIT, 0x2c);
1865 ret |= gc4c33_write_reg(gc4c33->client, 0x0a67,
1866 GC4C33_REG_VALUE_08BIT, 0x80);
1867 ret |= gc4c33_write_reg(gc4c33->client, 0x0a4f,
1868 GC4C33_REG_VALUE_08BIT, 0x00);
1869 ret |= gc4c33_write_reg(gc4c33->client, 0x0a54,
1870 GC4C33_REG_VALUE_08BIT, 0x80);
1871 ret |= gc4c33_write_reg(gc4c33->client, 0x0a66,
1872 GC4C33_REG_VALUE_08BIT, 0x03);
1873 ret |= gc4c33_write_reg(gc4c33->client, 0x0a69,
1874 GC4C33_REG_VALUE_08BIT, 0x00);
1875 ret |= gc4c33_write_reg(gc4c33->client, 0x0a6a,
1876 GC4C33_REG_VALUE_08BIT, 0x10);
1877 ret |= gc4c33_write_reg(gc4c33->client, 0x0313,
1878 GC4C33_REG_VALUE_08BIT, 0x20);
1879 }
1880
1881 #ifdef GC4C33_ENABLE_HIGHLIGHT
1882 ret |= gc4c33_write_reg(gc4c33->client, 0x0080,
1883 GC4C33_REG_VALUE_08BIT, 0x04);
1884 ret |= gc4c33_write_reg(gc4c33->client, 0x0090,
1885 GC4C33_REG_VALUE_08BIT, 0x49);
1886 ret |= gc4c33_write_reg(gc4c33->client, 0x05be,
1887 GC4C33_REG_VALUE_08BIT, 0x01);
1888 #endif
1889
1890 return ret;
1891 }
1892 #endif
1893
__gc4c33_start_stream(struct gc4c33 * gc4c33)1894 static int __gc4c33_start_stream(struct gc4c33 *gc4c33)
1895 {
1896 int ret;
1897
1898 ret = gc4c33_write_array(gc4c33->client, gc4c33->cur_mode->reg_list);
1899 if (ret)
1900 return ret;
1901
1902 #ifdef GC4C33_ENABLE_OTP
1903 ret = gc4c33_sensor_dpc_otp_dd(gc4c33);
1904 if (ret)
1905 return ret;
1906 #endif
1907
1908 /* In case these controls are set before streaming */
1909 mutex_unlock(&gc4c33->mutex);
1910 ret = v4l2_ctrl_handler_setup(&gc4c33->ctrl_handler);
1911 mutex_lock(&gc4c33->mutex);
1912 if (ret)
1913 return ret;
1914
1915 return gc4c33_write_reg(gc4c33->client, GC4C33_REG_CTRL_MODE,
1916 GC4C33_REG_VALUE_08BIT, GC4C33_MODE_STREAMING);
1917 }
1918
__gc4c33_stop_stream(struct gc4c33 * gc4c33)1919 static int __gc4c33_stop_stream(struct gc4c33 *gc4c33)
1920 {
1921 return gc4c33_write_reg(gc4c33->client, GC4C33_REG_CTRL_MODE,
1922 GC4C33_REG_VALUE_08BIT, GC4C33_MODE_SW_STANDBY);
1923 }
1924
gc4c33_s_stream(struct v4l2_subdev * sd,int on)1925 static int gc4c33_s_stream(struct v4l2_subdev *sd, int on)
1926 {
1927 struct gc4c33 *gc4c33 = to_gc4c33(sd);
1928 struct i2c_client *client = gc4c33->client;
1929 int ret = 0;
1930
1931 mutex_lock(&gc4c33->mutex);
1932 on = !!on;
1933 if (on == gc4c33->streaming)
1934 goto unlock_and_return;
1935
1936 if (on) {
1937 ret = pm_runtime_get_sync(&client->dev);
1938 if (ret < 0) {
1939 pm_runtime_put_noidle(&client->dev);
1940 goto unlock_and_return;
1941 }
1942
1943 ret = __gc4c33_start_stream(gc4c33);
1944 if (ret) {
1945 v4l2_err(sd, "start stream failed while write regs\n");
1946 pm_runtime_put(&client->dev);
1947 goto unlock_and_return;
1948 }
1949 } else {
1950 __gc4c33_stop_stream(gc4c33);
1951 pm_runtime_put(&client->dev);
1952 }
1953
1954 gc4c33->streaming = on;
1955
1956 unlock_and_return:
1957 mutex_unlock(&gc4c33->mutex);
1958
1959 return ret;
1960 }
1961
gc4c33_s_power(struct v4l2_subdev * sd,int on)1962 static int gc4c33_s_power(struct v4l2_subdev *sd, int on)
1963 {
1964 struct gc4c33 *gc4c33 = to_gc4c33(sd);
1965 struct i2c_client *client = gc4c33->client;
1966 int ret = 0;
1967
1968 mutex_lock(&gc4c33->mutex);
1969
1970 /* If the power state is not modified - no work to do. */
1971 if (gc4c33->power_on == !!on)
1972 goto unlock_and_return;
1973
1974 if (on) {
1975 ret = pm_runtime_get_sync(&client->dev);
1976 if (ret < 0) {
1977 pm_runtime_put_noidle(&client->dev);
1978 goto unlock_and_return;
1979 }
1980
1981 ret = gc4c33_write_array(gc4c33->client, gc4c33_global_regs);
1982 if (ret) {
1983 v4l2_err(sd, "could not set init registers\n");
1984 pm_runtime_put_noidle(&client->dev);
1985 goto unlock_and_return;
1986 }
1987
1988 gc4c33->power_on = true;
1989 } else {
1990 pm_runtime_put(&client->dev);
1991 gc4c33->power_on = false;
1992 }
1993
1994 unlock_and_return:
1995 mutex_unlock(&gc4c33->mutex);
1996
1997 return ret;
1998 }
1999
2000 /* Calculate the delay in us by clock rate and clock cycles */
gc4c33_cal_delay(u32 cycles)2001 static inline u32 gc4c33_cal_delay(u32 cycles)
2002 {
2003 return DIV_ROUND_UP(cycles, GC4C33_XVCLK_FREQ / 1000 / 1000);
2004 }
2005
__gc4c33_power_on(struct gc4c33 * gc4c33)2006 static int __gc4c33_power_on(struct gc4c33 *gc4c33)
2007 {
2008 int ret;
2009 u32 delay_us;
2010 struct device *dev = &gc4c33->client->dev;
2011
2012 if (!IS_ERR_OR_NULL(gc4c33->pins_default)) {
2013 ret = pinctrl_select_state(gc4c33->pinctrl,
2014 gc4c33->pins_default);
2015 if (ret < 0)
2016 dev_err(dev, "could not set pins\n");
2017 }
2018 ret = clk_set_rate(gc4c33->xvclk, GC4C33_XVCLK_FREQ);
2019 if (ret < 0)
2020 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
2021 if (clk_get_rate(gc4c33->xvclk) != GC4C33_XVCLK_FREQ)
2022 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
2023 ret = clk_prepare_enable(gc4c33->xvclk);
2024 if (ret < 0) {
2025 dev_err(dev, "Failed to enable xvclk\n");
2026 return ret;
2027 }
2028 if (!IS_ERR(gc4c33->reset_gpio))
2029 gpiod_set_value_cansleep(gc4c33->reset_gpio, 0);
2030
2031 if (!IS_ERR(gc4c33->pwdn_gpio))
2032 gpiod_set_value_cansleep(gc4c33->pwdn_gpio, 0);
2033
2034 usleep_range(500, 1000);
2035 ret = regulator_bulk_enable(GC4C33_NUM_SUPPLIES, gc4c33->supplies);
2036
2037 if (ret < 0) {
2038 dev_err(dev, "Failed to enable regulators\n");
2039 goto disable_clk;
2040 }
2041
2042 if (!IS_ERR(gc4c33->pwren_gpio))
2043 gpiod_set_value_cansleep(gc4c33->pwren_gpio, 1);
2044
2045 usleep_range(1000, 1100);
2046 if (!IS_ERR(gc4c33->pwdn_gpio))
2047 gpiod_set_value_cansleep(gc4c33->pwdn_gpio, 1);
2048 usleep_range(100, 150);
2049 if (!IS_ERR(gc4c33->reset_gpio))
2050 gpiod_set_value_cansleep(gc4c33->reset_gpio, 1);
2051
2052 /* 8192 cycles prior to first SCCB transaction */
2053 delay_us = gc4c33_cal_delay(8192);
2054 usleep_range(delay_us, delay_us * 2);
2055
2056 return 0;
2057
2058 disable_clk:
2059 clk_disable_unprepare(gc4c33->xvclk);
2060
2061 return ret;
2062 }
2063
__gc4c33_power_off(struct gc4c33 * gc4c33)2064 static void __gc4c33_power_off(struct gc4c33 *gc4c33)
2065 {
2066 int ret;
2067 struct device *dev = &gc4c33->client->dev;
2068
2069 if (!IS_ERR(gc4c33->pwdn_gpio))
2070 gpiod_set_value_cansleep(gc4c33->pwdn_gpio, 0);
2071 clk_disable_unprepare(gc4c33->xvclk);
2072 if (!IS_ERR(gc4c33->reset_gpio))
2073 gpiod_set_value_cansleep(gc4c33->reset_gpio, 0);
2074 if (!IS_ERR_OR_NULL(gc4c33->pins_sleep)) {
2075 ret = pinctrl_select_state(gc4c33->pinctrl,
2076 gc4c33->pins_sleep);
2077 if (ret < 0)
2078 dev_dbg(dev, "could not set pins\n");
2079 }
2080 regulator_bulk_disable(GC4C33_NUM_SUPPLIES, gc4c33->supplies);
2081 if (!IS_ERR(gc4c33->pwren_gpio))
2082 gpiod_set_value_cansleep(gc4c33->pwren_gpio, 0);
2083 }
2084
gc4c33_runtime_resume(struct device * dev)2085 static int __maybe_unused gc4c33_runtime_resume(struct device *dev)
2086 {
2087 struct i2c_client *client = to_i2c_client(dev);
2088 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2089 struct gc4c33 *gc4c33 = to_gc4c33(sd);
2090
2091 return __gc4c33_power_on(gc4c33);
2092 }
2093
gc4c33_runtime_suspend(struct device * dev)2094 static int __maybe_unused gc4c33_runtime_suspend(struct device *dev)
2095 {
2096 struct i2c_client *client = to_i2c_client(dev);
2097 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2098 struct gc4c33 *gc4c33 = to_gc4c33(sd);
2099
2100 __gc4c33_power_off(gc4c33);
2101
2102 return 0;
2103 }
2104
2105 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc4c33_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)2106 static int gc4c33_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2107 {
2108 struct gc4c33 *gc4c33 = to_gc4c33(sd);
2109 struct v4l2_mbus_framefmt *try_fmt =
2110 v4l2_subdev_get_try_format(sd, fh->pad, 0);
2111 const struct gc4c33_mode *def_mode = &supported_modes[0];
2112
2113 mutex_lock(&gc4c33->mutex);
2114 /* Initialize try_fmt */
2115 try_fmt->width = def_mode->width;
2116 try_fmt->height = def_mode->height;
2117 try_fmt->code = def_mode->bus_fmt;
2118 try_fmt->field = V4L2_FIELD_NONE;
2119
2120 mutex_unlock(&gc4c33->mutex);
2121 /* No crop or compose */
2122
2123 return 0;
2124 }
2125 #endif
2126
gc4c33_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)2127 static int gc4c33_enum_frame_interval(struct v4l2_subdev *sd,
2128 struct v4l2_subdev_pad_config *cfg,
2129 struct v4l2_subdev_frame_interval_enum *fie)
2130 {
2131 struct gc4c33 *gc4c33 = to_gc4c33(sd);
2132
2133 if (fie->index >= gc4c33->cfg_num)
2134 return -EINVAL;
2135
2136 fie->code = supported_modes[fie->index].bus_fmt;
2137 fie->width = supported_modes[fie->index].width;
2138 fie->height = supported_modes[fie->index].height;
2139 fie->interval = supported_modes[fie->index].max_fps;
2140 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
2141 return 0;
2142 }
2143
2144 static const struct dev_pm_ops gc4c33_pm_ops = {
2145 SET_RUNTIME_PM_OPS(gc4c33_runtime_suspend,
2146 gc4c33_runtime_resume, NULL)
2147 };
2148
2149 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2150 static const struct v4l2_subdev_internal_ops gc4c33_internal_ops = {
2151 .open = gc4c33_open,
2152 };
2153 #endif
2154
2155 static const struct v4l2_subdev_core_ops gc4c33_core_ops = {
2156 .s_power = gc4c33_s_power,
2157 .ioctl = gc4c33_ioctl,
2158 #ifdef CONFIG_COMPAT
2159 .compat_ioctl32 = gc4c33_compat_ioctl32,
2160 #endif
2161 };
2162
2163 static const struct v4l2_subdev_video_ops gc4c33_video_ops = {
2164 .s_stream = gc4c33_s_stream,
2165 .g_frame_interval = gc4c33_g_frame_interval,
2166 };
2167
2168 static const struct v4l2_subdev_pad_ops gc4c33_pad_ops = {
2169 .enum_mbus_code = gc4c33_enum_mbus_code,
2170 .enum_frame_size = gc4c33_enum_frame_sizes,
2171 .enum_frame_interval = gc4c33_enum_frame_interval,
2172 .get_fmt = gc4c33_get_fmt,
2173 .set_fmt = gc4c33_set_fmt,
2174 .get_mbus_config = gc4c33_g_mbus_config,
2175 };
2176
2177 static const struct v4l2_subdev_ops gc4c33_subdev_ops = {
2178 .core = &gc4c33_core_ops,
2179 .video = &gc4c33_video_ops,
2180 .pad = &gc4c33_pad_ops,
2181 };
2182
gc4c33_set_ctrl(struct v4l2_ctrl * ctrl)2183 static int gc4c33_set_ctrl(struct v4l2_ctrl *ctrl)
2184 {
2185 struct gc4c33 *gc4c33 = container_of(ctrl->handler,
2186 struct gc4c33, ctrl_handler);
2187 struct i2c_client *client = gc4c33->client;
2188 s64 max;
2189 int ret = 0;
2190 u32 val = 0;
2191
2192 /*Propagate change of current control to all related controls*/
2193 switch (ctrl->id) {
2194 case V4L2_CID_VBLANK:
2195 /*Update max exposure while meeting expected vblanking*/
2196 max = gc4c33->cur_mode->height + ctrl->val - 4;
2197 __v4l2_ctrl_modify_range(gc4c33->exposure,
2198 gc4c33->exposure->minimum,
2199 max,
2200 gc4c33->exposure->step,
2201 gc4c33->exposure->default_value);
2202 break;
2203 }
2204
2205 if (!pm_runtime_get_if_in_use(&client->dev))
2206 return 0;
2207
2208 switch (ctrl->id) {
2209 case V4L2_CID_EXPOSURE:
2210 /* 4 least significant bits of expsoure are fractional part */
2211 ret = gc4c33_write_reg(gc4c33->client, GC4C33_REG_EXPOSURE_H,
2212 GC4C33_REG_VALUE_08BIT,
2213 ctrl->val >> 8);
2214 ret |= gc4c33_write_reg(gc4c33->client, GC4C33_REG_EXPOSURE_L,
2215 GC4C33_REG_VALUE_08BIT,
2216 ctrl->val & 0xfe);
2217 break;
2218 case V4L2_CID_ANALOGUE_GAIN:
2219 if (gc4c33->cur_mode->height == 720)
2220 ret = gc4c33_set_gain_reg_720P(gc4c33, ctrl->val);
2221 else
2222 ret = gc4c33_set_gain_reg(gc4c33, ctrl->val);
2223 break;
2224 case V4L2_CID_VBLANK:
2225 ret = gc4c33_write_reg(gc4c33->client, GC4C33_REG_VTS_H,
2226 GC4C33_REG_VALUE_08BIT,
2227 (ctrl->val + gc4c33->cur_mode->height)
2228 >> 8);
2229 ret |= gc4c33_write_reg(gc4c33->client, GC4C33_REG_VTS_L,
2230 GC4C33_REG_VALUE_08BIT,
2231 (ctrl->val + gc4c33->cur_mode->height)
2232 & 0xff);
2233 break;
2234 case V4L2_CID_HFLIP:
2235 ret = gc4c33_read_reg(gc4c33->client, GC4C33_FLIP_MIRROR_REG,
2236 GC4C33_REG_VALUE_08BIT, &val);
2237 if (ctrl->val)
2238 val |= GC4C33_MIRROR_BIT_MASK;
2239 else
2240 val &= ~GC4C33_MIRROR_BIT_MASK;
2241 ret |= gc4c33_write_reg(gc4c33->client, GC4C33_FLIP_MIRROR_REG,
2242 GC4C33_REG_VALUE_08BIT, val);
2243 if (ret == 0)
2244 gc4c33->flip = val;
2245 break;
2246 case V4L2_CID_VFLIP:
2247 ret = gc4c33_read_reg(gc4c33->client, GC4C33_FLIP_MIRROR_REG,
2248 GC4C33_REG_VALUE_08BIT, &val);
2249 if (ctrl->val)
2250 val |= GC4C33_FLIP_BIT_MASK;
2251 else
2252 val &= ~GC4C33_FLIP_BIT_MASK;
2253 ret |= gc4c33_write_reg(gc4c33->client, GC4C33_FLIP_MIRROR_REG,
2254 GC4C33_REG_VALUE_08BIT, val);
2255 if (ret == 0)
2256 gc4c33->flip = val;
2257 break;
2258 case V4L2_CID_TEST_PATTERN:
2259 ret = gc4c33_enable_test_pattern(gc4c33, ctrl->val);
2260 break;
2261 default:
2262 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
2263 __func__, ctrl->id, ctrl->val);
2264 break;
2265 }
2266
2267 pm_runtime_put(&client->dev);
2268
2269 return ret;
2270 }
2271
2272 static const struct v4l2_ctrl_ops gc4c33_ctrl_ops = {
2273 .s_ctrl = gc4c33_set_ctrl,
2274 };
2275
gc4c33_initialize_controls(struct gc4c33 * gc4c33)2276 static int gc4c33_initialize_controls(struct gc4c33 *gc4c33)
2277 {
2278 const struct gc4c33_mode *mode;
2279 struct v4l2_ctrl_handler *handler;
2280 struct v4l2_ctrl *ctrl;
2281 s64 exposure_max, vblank_def;
2282 u32 h_blank;
2283 int ret;
2284
2285 handler = &gc4c33->ctrl_handler;
2286 mode = gc4c33->cur_mode;
2287 ret = v4l2_ctrl_handler_init(handler, 9);
2288 if (ret)
2289 return ret;
2290 handler->lock = &gc4c33->mutex;
2291
2292 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
2293 0, 0, link_freq_menu_items);
2294 if (ctrl)
2295 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2296
2297 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
2298 0, GC4C33_PIXEL_RATE, 1, GC4C33_PIXEL_RATE);
2299
2300 h_blank = mode->hts_def - mode->width;
2301 gc4c33->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
2302 h_blank, h_blank, 1, h_blank);
2303 if (gc4c33->hblank)
2304 gc4c33->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2305
2306 vblank_def = mode->vts_def - mode->height;
2307 gc4c33->vblank = v4l2_ctrl_new_std(handler, &gc4c33_ctrl_ops,
2308 V4L2_CID_VBLANK, vblank_def,
2309 GC4C33_VTS_MAX - mode->height,
2310 1, vblank_def);
2311
2312 exposure_max = mode->vts_def - 4;
2313 gc4c33->exposure = v4l2_ctrl_new_std(handler, &gc4c33_ctrl_ops,
2314 V4L2_CID_EXPOSURE,
2315 GC4C33_EXPOSURE_MIN,
2316 exposure_max,
2317 GC4C33_EXPOSURE_STEP,
2318 mode->exp_def);
2319
2320 gc4c33->anal_gain = v4l2_ctrl_new_std(handler, &gc4c33_ctrl_ops,
2321 V4L2_CID_ANALOGUE_GAIN,
2322 GC4C33_GAIN_MIN,
2323 GC4C33_GAIN_MAX,
2324 GC4C33_GAIN_STEP,
2325 GC4C33_GAIN_DEFAULT);
2326
2327 gc4c33->test_pattern =
2328 v4l2_ctrl_new_std_menu_items(handler,
2329 &gc4c33_ctrl_ops,
2330 V4L2_CID_TEST_PATTERN,
2331 ARRAY_SIZE(gc4c33_test_pattern_menu) - 1,
2332 0, 0, gc4c33_test_pattern_menu);
2333 gc4c33->h_flip = v4l2_ctrl_new_std(handler, &gc4c33_ctrl_ops,
2334 V4L2_CID_HFLIP, 0, 1, 1, 0);
2335
2336 gc4c33->v_flip = v4l2_ctrl_new_std(handler, &gc4c33_ctrl_ops,
2337 V4L2_CID_VFLIP, 0, 1, 1, 0);
2338 gc4c33->flip = 0;
2339
2340 if (handler->error) {
2341 ret = handler->error;
2342 dev_err(&gc4c33->client->dev,
2343 "Failed to init controls(%d)\n", ret);
2344 goto err_free_handler;
2345 }
2346
2347 gc4c33->subdev.ctrl_handler = handler;
2348
2349 return 0;
2350
2351 err_free_handler:
2352 v4l2_ctrl_handler_free(handler);
2353
2354 return ret;
2355 }
2356
gc4c33_check_sensor_id(struct gc4c33 * gc4c33,struct i2c_client * client)2357 static int gc4c33_check_sensor_id(struct gc4c33 *gc4c33,
2358 struct i2c_client *client)
2359 {
2360 struct device *dev = &gc4c33->client->dev;
2361 u16 id = 0;
2362 u32 reg_H = 0;
2363 u32 reg_L = 0;
2364 int ret;
2365
2366 ret = gc4c33_read_reg(client, GC4C33_REG_CHIP_ID_H,
2367 GC4C33_REG_VALUE_08BIT, ®_H);
2368 ret |= gc4c33_read_reg(client, GC4C33_REG_CHIP_ID_L,
2369 GC4C33_REG_VALUE_08BIT, ®_L);
2370 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
2371 if (!(reg_H == (CHIP_ID >> 8) || reg_L == (CHIP_ID & 0xff))) {
2372 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
2373 return -ENODEV;
2374 }
2375 dev_info(dev, "detected gc%04x sensor\n", id);
2376 return 0;
2377 }
2378
gc4c33_configure_regulators(struct gc4c33 * gc4c33)2379 static int gc4c33_configure_regulators(struct gc4c33 *gc4c33)
2380 {
2381 unsigned int i;
2382
2383 for (i = 0; i < GC4C33_NUM_SUPPLIES; i++)
2384 gc4c33->supplies[i].supply = gc4c33_supply_names[i];
2385
2386 return devm_regulator_bulk_get(&gc4c33->client->dev,
2387 GC4C33_NUM_SUPPLIES,
2388 gc4c33->supplies);
2389 }
2390
gc4c33_probe(struct i2c_client * client,const struct i2c_device_id * id)2391 static int gc4c33_probe(struct i2c_client *client,
2392 const struct i2c_device_id *id)
2393 {
2394 struct device *dev = &client->dev;
2395 struct device_node *node = dev->of_node;
2396 struct gc4c33 *gc4c33;
2397 struct v4l2_subdev *sd;
2398 char facing[2];
2399 int ret;
2400 u32 i, hdr_mode = 0;
2401
2402 dev_info(dev, "driver version: %02x.%02x.%02x",
2403 DRIVER_VERSION >> 16,
2404 (DRIVER_VERSION & 0xff00) >> 8,
2405 DRIVER_VERSION & 0x00ff);
2406
2407 gc4c33 = devm_kzalloc(dev, sizeof(*gc4c33), GFP_KERNEL);
2408 if (!gc4c33)
2409 return -ENOMEM;
2410
2411 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
2412 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2413 &gc4c33->module_index);
2414 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2415 &gc4c33->module_facing);
2416 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2417 &gc4c33->module_name);
2418 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2419 &gc4c33->len_name);
2420 if (ret) {
2421 dev_err(dev, "could not get module information!\n");
2422 return -EINVAL;
2423 }
2424
2425 gc4c33->client = client;
2426 gc4c33->cfg_num = ARRAY_SIZE(supported_modes);
2427 for (i = 0; i < gc4c33->cfg_num; i++) {
2428 if (hdr_mode == supported_modes[i].hdr_mode) {
2429 gc4c33->cur_mode = &supported_modes[i];
2430 break;
2431 }
2432 }
2433 if (i == gc4c33->cfg_num)
2434 gc4c33->cur_mode = &supported_modes[0];
2435
2436 gc4c33->xvclk = devm_clk_get(dev, "xvclk");
2437 if (IS_ERR(gc4c33->xvclk)) {
2438 dev_err(dev, "Failed to get xvclk\n");
2439 return -EINVAL;
2440 }
2441
2442 gc4c33->pwren_gpio = devm_gpiod_get(dev, "pwren", GPIOD_OUT_LOW);
2443 if (IS_ERR(gc4c33->pwren_gpio))
2444 dev_warn(dev, "Failed to get pwren-gpios\n");
2445
2446 gc4c33->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2447 if (IS_ERR(gc4c33->reset_gpio))
2448 dev_warn(dev, "Failed to get reset-gpios\n");
2449
2450 gc4c33->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
2451 if (IS_ERR(gc4c33->pwdn_gpio))
2452 dev_warn(dev, "Failed to get pwdn-gpios\n");
2453
2454 gc4c33->pinctrl = devm_pinctrl_get(dev);
2455 if (!IS_ERR(gc4c33->pinctrl)) {
2456 gc4c33->pins_default =
2457 pinctrl_lookup_state(gc4c33->pinctrl,
2458 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2459 if (IS_ERR(gc4c33->pins_default))
2460 dev_err(dev, "could not get default pinstate\n");
2461
2462 gc4c33->pins_sleep =
2463 pinctrl_lookup_state(gc4c33->pinctrl,
2464 OF_CAMERA_PINCTRL_STATE_SLEEP);
2465 if (IS_ERR(gc4c33->pins_sleep))
2466 dev_err(dev, "could not get sleep pinstate\n");
2467 } else {
2468 dev_err(dev, "no pinctrl\n");
2469 }
2470
2471 ret = gc4c33_configure_regulators(gc4c33);
2472 if (ret) {
2473 dev_err(dev, "Failed to get power regulators\n");
2474 return ret;
2475 }
2476
2477 mutex_init(&gc4c33->mutex);
2478
2479 sd = &gc4c33->subdev;
2480 v4l2_i2c_subdev_init(sd, client, &gc4c33_subdev_ops);
2481 ret = gc4c33_initialize_controls(gc4c33);
2482 if (ret)
2483 goto err_destroy_mutex;
2484
2485 ret = __gc4c33_power_on(gc4c33);
2486 if (ret)
2487 goto err_free_handler;
2488
2489 ret = gc4c33_check_sensor_id(gc4c33, client);
2490 if (ret)
2491 goto err_power_off;
2492
2493 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2494 sd->internal_ops = &gc4c33_internal_ops;
2495 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2496 V4L2_SUBDEV_FL_HAS_EVENTS;
2497 #endif
2498 #if defined(CONFIG_MEDIA_CONTROLLER)
2499 gc4c33->pad.flags = MEDIA_PAD_FL_SOURCE;
2500 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2501 ret = media_entity_pads_init(&sd->entity, 1, &gc4c33->pad);
2502 if (ret < 0)
2503 goto err_power_off;
2504 #endif
2505
2506 memset(facing, 0, sizeof(facing));
2507 if (strcmp(gc4c33->module_facing, "back") == 0)
2508 facing[0] = 'b';
2509 else
2510 facing[0] = 'f';
2511
2512 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2513 gc4c33->module_index, facing,
2514 GC4C33_NAME, dev_name(sd->dev));
2515 ret = v4l2_async_register_subdev_sensor_common(sd);
2516 if (ret) {
2517 dev_err(dev, "v4l2 async register subdev failed\n");
2518 goto err_clean_entity;
2519 }
2520
2521 pm_runtime_set_active(dev);
2522 pm_runtime_enable(dev);
2523 pm_runtime_idle(dev);
2524
2525 return 0;
2526
2527 err_clean_entity:
2528 #if defined(CONFIG_MEDIA_CONTROLLER)
2529 media_entity_cleanup(&sd->entity);
2530 #endif
2531 err_power_off:
2532 __gc4c33_power_off(gc4c33);
2533 err_free_handler:
2534 v4l2_ctrl_handler_free(&gc4c33->ctrl_handler);
2535 err_destroy_mutex:
2536 mutex_destroy(&gc4c33->mutex);
2537
2538 return ret;
2539 }
2540
gc4c33_remove(struct i2c_client * client)2541 static int gc4c33_remove(struct i2c_client *client)
2542 {
2543 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2544 struct gc4c33 *gc4c33 = to_gc4c33(sd);
2545
2546 v4l2_async_unregister_subdev(sd);
2547 #if defined(CONFIG_MEDIA_CONTROLLER)
2548 media_entity_cleanup(&sd->entity);
2549 #endif
2550 v4l2_ctrl_handler_free(&gc4c33->ctrl_handler);
2551 mutex_destroy(&gc4c33->mutex);
2552
2553 pm_runtime_disable(&client->dev);
2554 if (!pm_runtime_status_suspended(&client->dev))
2555 __gc4c33_power_off(gc4c33);
2556 pm_runtime_set_suspended(&client->dev);
2557
2558 return 0;
2559 }
2560
2561 #if IS_ENABLED(CONFIG_OF)
2562 static const struct of_device_id gc4c33_of_match[] = {
2563 { .compatible = "galaxycore,gc4c33" },
2564 {},
2565 };
2566 MODULE_DEVICE_TABLE(of, gc4c33_of_match);
2567 #endif
2568
2569 static const struct i2c_device_id gc4c33_match_id[] = {
2570 { "galaxycore,gc4c33", 0 },
2571 { },
2572 };
2573
2574 static struct i2c_driver gc4c33_i2c_driver = {
2575 .driver = {
2576 .name = GC4C33_NAME,
2577 .pm = &gc4c33_pm_ops,
2578 .of_match_table = of_match_ptr(gc4c33_of_match),
2579 },
2580 .probe = &gc4c33_probe,
2581 .remove = &gc4c33_remove,
2582 .id_table = gc4c33_match_id,
2583 };
2584
sensor_mod_init(void)2585 static int __init sensor_mod_init(void)
2586 {
2587 return i2c_add_driver(&gc4c33_i2c_driver);
2588 }
2589
sensor_mod_exit(void)2590 static void __exit sensor_mod_exit(void)
2591 {
2592 i2c_del_driver(&gc4c33_i2c_driver);
2593 }
2594
2595 device_initcall_sync(sensor_mod_init);
2596 module_exit(sensor_mod_exit);
2597
2598 MODULE_DESCRIPTION("galaxycore gc4c33 sensor driver");
2599 MODULE_LICENSE("GPL v2");
2600