1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * GC4663 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 fix gain range.
10 * V0.0X01.0X04 add enum_frame_interval function.
11 * V0.0X01.0X05 support enum sensor fmt
12 * V0.0X01.0X06 support mirror and flip
13 * V0.0X01.0X07 add quick stream on/off
14 */
15
16 #include <linux/clk.h>
17 #include <linux/device.h>
18 #include <linux/delay.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/i2c.h>
21 #include <linux/module.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/sysfs.h>
25 #include <linux/slab.h>
26 #include <linux/version.h>
27 #include <linux/rk-camera-module.h>
28 #include <linux/rk-preisp.h>
29 #include <media/media-entity.h>
30 #include <media/v4l2-async.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-subdev.h>
33 #include <linux/pinctrl/consumer.h>
34
35 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x07)
36
37 #ifndef V4L2_CID_DIGITAL_GAIN
38 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
39 #endif
40
41 #define GC4663_LANES 2
42 #define GC4663_BITS_PER_SAMPLE 10
43 #define GC4663_LINK_FREQ_LINEAR 324000000 //2560*1440
44 #define GC4663_LINK_FREQ_HDR 672000000
45
46 #define GC4663_PIXEL_RATE_LINEAR (GC4663_LINK_FREQ_LINEAR * 2 / 10 * 2)
47 #define GC4663_PIXEL_RATE_HDR (GC4663_LINK_FREQ_HDR * 2 / 10 * 2)
48
49 #define GC4663_XVCLK_FREQ 24000000
50
51 #define CHIP_ID 0x4653
52 #define GC4663_REG_CHIP_ID_H 0x03f0
53 #define GC4663_REG_CHIP_ID_L 0x03f1
54
55 #define GC4663_REG_CTRL_MODE 0x0100
56 #define GC4663_MODE_SW_STANDBY 0x00
57 #define GC4663_MODE_STREAMING 0x09
58
59 #define GC4663_REG_SEXPOSURE_H 0x0200
60 #define GC4663_REG_SEXPOSURE_L 0x0201
61 #define GC4663_REG_EXPOSURE_H 0x0202
62 #define GC4663_REG_EXPOSURE_L 0x0203
63 #define GC4663_EXPOSURE_MIN 4
64 #define GC4663_EXPOSURE_STEP 1
65 #define GC4663_VTS_MAX 0x7fff
66
67 #define GC4663_GAIN_MIN 64
68 #define GC4663_GAIN_MAX 0xffff
69 #define GC4663_GAIN_STEP 1
70 #define GC4663_GAIN_DEFAULT 256
71
72 #define GC4663_REG_TEST_PATTERN 0x008c
73 #define GC4663_TEST_PATTERN_ENABLE 0x11
74 #define GC4663_TEST_PATTERN_DISABLE 0x0
75
76 #define GC4663_REG_VTS_H 0x0340
77 #define GC4663_REG_VTS_L 0x0341
78
79 #define GC4663_FLIP_MIRROR_REG 0x0101
80 #define GC4663_MIRROR_BIT_MASK BIT(0)
81 #define GC4663_FLIP_BIT_MASK BIT(1)
82
83 #define REG_NULL 0xFFFF
84
85 #define GC4663_REG_VALUE_08BIT 1
86 #define GC4663_REG_VALUE_16BIT 2
87 #define GC4663_REG_VALUE_24BIT 3
88
89 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
90 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
91 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
92 #define GC4663_NAME "gc4663"
93
94 static const char * const gc4663_supply_names[] = {
95 "dovdd", /* Digital I/O power */
96 "dvdd", /* Digital core power */
97 "avdd", /* Analog power */
98 };
99
100 #define GC4663_NUM_SUPPLIES ARRAY_SIZE(gc4663_supply_names)
101
102 struct regval {
103 u16 addr;
104 u8 val;
105 };
106
107 struct gc4663_mode {
108 u32 bus_fmt;
109 u32 width;
110 u32 height;
111 struct v4l2_fract max_fps;
112 u32 hts_def;
113 u32 vts_def;
114 u32 exp_def;
115 const struct regval *reg_list;
116 u32 hdr_mode;
117 u32 vc[PAD_MAX];
118 };
119
120 struct gc4663 {
121 struct i2c_client *client;
122 struct clk *xvclk;
123 struct gpio_desc *reset_gpio;
124 struct gpio_desc *pwdn_gpio;
125 struct gpio_desc *pwren_gpio;
126 struct regulator_bulk_data supplies[GC4663_NUM_SUPPLIES];
127
128 struct pinctrl *pinctrl;
129 struct pinctrl_state *pins_default;
130 struct pinctrl_state *pins_sleep;
131
132 struct v4l2_subdev subdev;
133 struct media_pad pad;
134 struct v4l2_ctrl_handler ctrl_handler;
135 struct v4l2_ctrl *exposure;
136 struct v4l2_ctrl *anal_gain;
137 struct v4l2_ctrl *digi_gain;
138 struct v4l2_ctrl *hblank;
139 struct v4l2_ctrl *vblank;
140 struct v4l2_ctrl *pixel_rate;
141 struct v4l2_ctrl *link_freq;
142 struct v4l2_ctrl *h_flip;
143 struct v4l2_ctrl *v_flip;
144 struct v4l2_ctrl *test_pattern;
145 struct mutex mutex;
146 bool streaming;
147 bool power_on;
148 const struct gc4663_mode *cur_mode;
149 u32 cfg_num;
150 u32 module_index;
151 u32 cur_vts;
152 u32 cur_pixel_rate;
153 u32 cur_link_freq;
154 struct preisp_hdrae_exp_s init_hdrae_exp;
155 const char *module_facing;
156 const char *module_name;
157 const char *len_name;
158 bool has_init_exp;
159 };
160
161 #define to_gc4663(sd) container_of(sd, struct gc4663, subdev)
162
163 /*
164 * Xclk 24Mhz
165 */
166 static const struct regval gc4663_global_regs[] = {
167 {REG_NULL, 0x00},
168 };
169
170 static const u32 reg_val_table_hdr[26][7] = {
171 //2b3 2b4 2b8 2b9 515 519 2d9
172 {0x00, 0x00, 0x01, 0x00, 0x30, 0x28, 0x66},
173 {0x20, 0x00, 0x01, 0x0B, 0x30, 0x2a, 0x68},
174 {0x01, 0x00, 0x01, 0x19, 0x30, 0x27, 0x65},
175 {0x21, 0x00, 0x01, 0x2A, 0x30, 0x29, 0x67},
176 {0x02, 0x00, 0x02, 0x00, 0x30, 0x27, 0x65},
177 {0x22, 0x00, 0x02, 0x17, 0x30, 0x29, 0x67},
178 {0x03, 0x00, 0x02, 0x33, 0x30, 0x28, 0x66},
179 {0x23, 0x00, 0x03, 0x14, 0x30, 0x2a, 0x68},
180 {0x04, 0x00, 0x04, 0x00, 0x30, 0x2a, 0x68},
181 {0x24, 0x00, 0x04, 0x2F, 0x30, 0x2b, 0x69},
182 {0x05, 0x00, 0x05, 0x26, 0x30, 0x2c, 0x6A},
183 {0x25, 0x00, 0x06, 0x28, 0x30, 0x2e, 0x6C},
184 {0x06, 0x00, 0x08, 0x00, 0x30, 0x2f, 0x6D},
185 {0x26, 0x00, 0x09, 0x1E, 0x30, 0x31, 0x6F},
186 {0x46, 0x00, 0x0B, 0x0C, 0x30, 0x34, 0x72},
187 {0x66, 0x00, 0x0D, 0x11, 0x30, 0x37, 0x75},
188 {0x0e, 0x00, 0x10, 0x00, 0x30, 0x3a, 0x78},
189 {0x2e, 0x00, 0x12, 0x3D, 0x30, 0x3e, 0x7C},
190 {0x4e, 0x00, 0x16, 0x19, 0x30, 0x41, 0x7F},
191 {0x6e, 0x00, 0x1A, 0x22, 0x30, 0x45, 0x83},
192 {0x1e, 0x00, 0x20, 0x00, 0x30, 0x49, 0x87},
193 {0x3e, 0x00, 0x25, 0x3A, 0x30, 0x4d, 0x8B},
194 {0x5e, 0x00, 0x2C, 0x33, 0x30, 0x53, 0x91},
195 {0x7e, 0x00, 0x35, 0x05, 0x30, 0x5a, 0x98},
196 {0x9e, 0x00, 0x40, 0x00, 0x30, 0x60, 0x9E},
197 {0xbe, 0x00, 0x4B, 0x35, 0x30, 0x67, 0xA5},
198
199 };
200
201 static const u32 reg_val_table_liner[26][7] = {
202 //2b3 2b4 2b8 2b9 515 519 2d9
203 {0x00, 0x00, 0x01, 0x00, 0x30, 0x1e, 0x5C},
204 {0x20, 0x00, 0x01, 0x0B, 0x30, 0x1e, 0x5C},
205 {0x01, 0x00, 0x01, 0x19, 0x30, 0x1d, 0x5B},
206 {0x21, 0x00, 0x01, 0x2A, 0x30, 0x1e, 0x5C},
207 {0x02, 0x00, 0x02, 0x00, 0x30, 0x1e, 0x5C},
208 {0x22, 0x00, 0x02, 0x17, 0x30, 0x1d, 0x5B},
209 {0x03, 0x00, 0x02, 0x33, 0x20, 0x16, 0x54},
210 {0x23, 0x00, 0x03, 0x14, 0x20, 0x17, 0x55},
211 {0x04, 0x00, 0x04, 0x00, 0x20, 0x17, 0x55},
212 {0x24, 0x00, 0x04, 0x2F, 0x20, 0x19, 0x57},
213 {0x05, 0x00, 0x05, 0x26, 0x20, 0x19, 0x57},
214 {0x25, 0x00, 0x06, 0x28, 0x20, 0x1b, 0x59},
215 {0x0c, 0x00, 0x08, 0x00, 0x20, 0x1d, 0x5B},
216 {0x2C, 0x00, 0x09, 0x1E, 0x20, 0x1f, 0x5D},
217 {0x0D, 0x00, 0x0B, 0x0C, 0x20, 0x21, 0x5F},
218 {0x2D, 0x00, 0x0D, 0x11, 0x20, 0x24, 0x62},
219 {0x1C, 0x00, 0x10, 0x00, 0x20, 0x26, 0x64},
220 {0x3C, 0x00, 0x12, 0x3D, 0x18, 0x2a, 0x68},
221 {0x5C, 0x00, 0x16, 0x19, 0x18, 0x2c, 0x6A},
222 {0x7C, 0x00, 0x1A, 0x22, 0x18, 0x2e, 0x6C},
223 {0x9C, 0x00, 0x20, 0x00, 0x18, 0x32, 0x70},
224 {0xBC, 0x00, 0x25, 0x3A, 0x18, 0x35, 0x73},
225 {0xDC, 0x00, 0x2C, 0x33, 0x10, 0x36, 0x74},
226 {0xFC, 0x00, 0x35, 0x05, 0x10, 0x38, 0x76},
227 {0x1C, 0x01, 0x40, 0x00, 0x10, 0x3c, 0x7A},
228 {0x3C, 0x01, 0x4B, 0x35, 0x10, 0x42, 0x80},
229 };
230
231 static const u32 gain_level_table[27] = {
232 64,
233 75,
234 89,
235 106,
236 128,
237 151,
238 179,
239 212,
240 256,
241 303,
242 358,
243 424,
244 512,
245 606,
246 716,
247 849,
248 1024,
249 1213,
250 1433,
251 1698,
252 2048,
253 2426,
254 2867,
255 3397,
256 4096,
257 4853,
258 0xffff,
259 };
260
261 /*
262 * Xclk 24Mhz
263 * max_framerate 30fps
264 * mipi_datarate per lane 648Mbps, 2lane
265 */
266 static const struct regval gc4663_linear10bit_2560x1440_regs[] = {
267 {0x03fe, 0xf0},
268 {0x03fe, 0x00},
269 {0x0317, 0x00},
270 {0x0320, 0x77},
271 {0x0324, 0xc8},
272 {0x0325, 0x06},
273 {0x0326, 0x60},
274 {0x0327, 0x03},
275 {0x0334, 0x40},
276 {0x0336, 0x60},
277 {0x0337, 0x82},
278 {0x0315, 0x25},
279 {0x031c, 0xc6},
280 {0x0287, 0x18},
281 {0x0084, 0x00},
282 {0x0087, 0x50},
283 {0x029d, 0x08},
284 {0x0290, 0x00},
285 {0x0340, 0x05},
286 {0x0341, 0xdc},
287 {0x0345, 0x06},
288 {0x034b, 0xb0},
289 {0x0352, 0x08},
290 {0x0354, 0x08},
291 {0x02d1, 0xe0},
292 {0x0223, 0xf2},
293 {0x0238, 0xb4},
294 {0x02ce, 0x7f},
295 {0x0232, 0xc4},
296 {0x02d3, 0x05},
297 {0x0243, 0x06},
298 {0x02ee, 0x30},
299 {0x026f, 0x70},
300 {0x0257, 0x09},
301 {0x0211, 0x02},
302 {0x0219, 0x09},
303 {0x023f, 0x2d},
304 {0x0518, 0x00},
305 {0x0519, 0x01},
306 {0x0515, 0x08},
307 {0x02d9, 0x3f},
308 {0x02da, 0x02},
309 {0x02db, 0xe8},
310 {0x02e6, 0x20},
311 {0x021b, 0x10},
312 {0x0252, 0x22},
313 {0x024e, 0x22},
314 {0x02c4, 0x01},
315 {0x021d, 0x17},
316 {0x024a, 0x01},
317 {0x02ca, 0x02},
318 {0x0262, 0x10},
319 {0x029a, 0x20},
320 {0x021c, 0x0e},
321 {0x0298, 0x03},
322 {0x029c, 0x00},
323 {0x027e, 0x14},
324 {0x02c2, 0x10},
325 {0x0540, 0x20},
326 {0x0546, 0x01},
327 {0x0548, 0x01},
328 {0x0544, 0x01},
329 {0x0242, 0x1b},
330 {0x02c0, 0x1b},
331 {0x02c3, 0x20},
332 {0x02e4, 0x10},
333 {0x022e, 0x00},
334 {0x027b, 0x3f},
335 {0x0269, 0x0f},
336 {0x000f, 0x00},
337 {0x02d2, 0x40},
338 {0x027c, 0x08},
339 {0x023a, 0x2e},
340 {0x0245, 0xce},
341 {0x0530, 0x20},
342 {0x0531, 0x02},
343 {0x0228, 0x50},
344 {0x02ab, 0x00},
345 {0x0250, 0x00},
346 {0x0221, 0x50},
347 {0x02ac, 0x00},
348 {0x02a5, 0x02},
349 {0x0260, 0x0b},
350 {0x0216, 0x04},
351 {0x0299, 0x1C},
352 {0x02bb, 0x0d},
353 {0x02a3, 0x02},
354 {0x02a4, 0x02},
355 {0x021e, 0x02},
356 {0x024f, 0x08},
357 {0x028c, 0x08},
358 {0x0532, 0x3f},
359 {0x0533, 0x02},
360 {0x0277, 0xc0},
361 {0x0276, 0xc0},
362 {0x0239, 0xc0},
363 {0x0202, 0x05},
364 {0x0203, 0xd0},
365 {0x0205, 0xc0},
366 {0x02b0, 0x68},
367 {0x0002, 0xa9},
368 {0x0004, 0x01},
369 {0x021a, 0x98},
370 {0x0266, 0xa0},
371 {0x0020, 0x01},
372 {0x0021, 0x03},
373 {0x0022, 0x00},
374 {0x0023, 0x04},
375 {0x0342, 0x06},
376 {0x0343, 0x40},
377 {0x03fe, 0x10},
378 {0x03fe, 0x00},
379 {0x0106, 0x78},
380 {0x0108, 0x0c},
381 {0x0114, 0x01},
382 {0x0115, 0x10},
383 {0x0180, 0x46},
384 {0x0181, 0x30},
385 {0x0182, 0x05},
386 {0x0185, 0x01},
387 {0x03fe, 0x10},
388 {0x03fe, 0x00},
389 {REG_NULL, 0x00},
390 };
391
392 static const struct regval gc4663_linear_global_regs[] = {
393 {0x0080, 0x02},
394 {0x0097, 0x0a},
395 {0x0098, 0x10},
396 {0x0099, 0x05},
397 {0x009a, 0xb0},
398 {0x0317, 0x08},
399 {0x0a67, 0x80},
400 {0x0a70, 0x03},
401 {0x0a82, 0x00},
402 {0x0a83, 0x10},
403 {0x0a80, 0x2b},
404 {0x05be, 0x00},
405 {0x05a9, 0x01},
406 {0x0313, 0x80},
407 {0x05be, 0x01},
408 {0x0317, 0x00},
409 {0x0a67, 0x00},
410 {REG_NULL, 0x00},
411 };
412
413 /*
414 * Xclk 24Mhz
415 * max_framerate 30fps
416 * mipiclk 1309.5Mhz, 2lane
417 */
418 static const struct regval gc4663_hdr10bit_2560x1440_regs[] = {
419 {0x03fe, 0xf0},
420 {0x03fe, 0x00},
421 {0x0317, 0x00},
422 {0x0320, 0x77},
423 {0x0324, 0xc4},
424 {0x0326, 0x42},
425 {0x0327, 0x03},
426 {0x0321, 0x10},
427 {0x0314, 0x50},
428 {0x0334, 0x40},
429 {0x0335, 0xd1},
430 {0x0336, 0x70},
431 {0x0337, 0x82},
432 {0x0315, 0x33},
433 {0x031c, 0xce},
434 {0x0287, 0x18},
435 {0x0084, 0x00},
436 {0x0087, 0x50},
437 {0x029d, 0x08},
438 {0x0290, 0x00},
439 {0x0340, 0x06},
440 {0x0341, 0x40},
441 {0x0345, 0x06},
442 {0x034b, 0xb0},
443 {0x0352, 0x08},
444 {0x0354, 0x08},
445 {0x02d1, 0xc0},
446 {0x023c, 0x04},
447 {0x0238, 0xb4},//0xa4
448 {0x0223, 0xfb},
449 {0x0232, 0xc4},
450 {0x0279, 0x53},
451 {0x02d3, 0x01},
452 {0x0243, 0x06},
453 {0x02ce, 0xbf},
454 {0x02ee, 0x30},
455 {0x026f, 0x70},
456 {0x0257, 0x09},
457 {0x0211, 0x02},
458 {0x0219, 0x09},
459 {0x023f, 0x2d},
460 {0x0518, 0x00},
461 {0x0519, 0x14},
462 {0x0515, 0x18},
463 {0x02d9, 0x50},
464 {0x02da, 0x02},
465 {0x02db, 0xe8},
466 {0x02e6, 0x20},
467 {0x021b, 0x10},
468 {0x0252, 0x22},
469 {0x024e, 0x22},
470 {0x02c4, 0x01},
471 {0x021d, 0x17},
472 {0x024a, 0x01},
473 {0x02ca, 0x02},
474 {0x0262, 0x10},
475 {0x029a, 0x20},
476 {0x021c, 0x0e},
477 {0x0298, 0x03},
478 {0x029c, 0x00},
479 {0x027e, 0x14},
480 {0x02c2, 0x10},
481 {0x0540, 0x20},
482 {0x0546, 0x01},
483 {0x0548, 0x01},
484 {0x0544, 0x01},
485 {0x0242, 0x36},
486 {0x02c0, 0x36},
487 {0x02c3, 0x4d},
488 {0x02e4, 0x10},
489 {0x022e, 0x00},
490 {0x027b, 0x3f},
491 {0x0269, 0x0f},
492 {0x02d2, 0x40},
493 {0x027c, 0x08},
494 {0x023a, 0x2e},
495 {0x0245, 0xce},
496 {0x0530, 0x3f},
497 {0x0531, 0x02},
498 {0x0228, 0x50},
499 {0x02ab, 0x00},
500 {0x0250, 0x00},
501 {0x0221, 0x50},
502 {0x02ac, 0x00},
503 {0x02a5, 0x02},
504 {0x0260, 0x0b},
505 {0x0216, 0x04},
506 {0x0299, 0x1C},
507 {0x021a, 0x98},
508 {0x0266, 0xd0},
509 {0x0020, 0x01},
510 {0x0021, 0x05},
511 {0x0022, 0xc0},
512 {0x0023, 0x08},
513 {0x02bb, 0x0d},
514 {0x02a3, 0x02},
515 {0x02a4, 0x02},
516 {0x021e, 0x02},
517 {0x024f, 0x08},
518 {0x028c, 0x08},
519 {0x0532, 0x3f},
520 {0x0533, 0x02},
521 {0x0277, 0x70}, //tx_width
522 {0x0276, 0xc0},
523 {0x0239, 0xc0},
524 {0x0200, 0x00},
525 {0x0201, 0x5f},
526 {0x0202, 0x05},
527 {0x0203, 0xf0},
528 {0x0205, 0xc0},
529 {0x02b0, 0x68},
530 {0x000f, 0x00},
531 {0x0006, 0xe0},
532 {0x0002, 0xa9},
533 {0x0004, 0x01},
534 {0x0060, 0x40},
535 {0x0218, 0x12},
536 {0x0342, 0x05},
537 {0x0343, 0x5f},
538 {0x03fe, 0x10},
539 {0x03fe, 0x00},
540 {0x0106, 0x78},
541 {0x0107, 0x89},
542 {0x0108, 0x0c},
543 {0x0114, 0x01},
544 {0x0115, 0x10},
545 {0x0180, 0x4f},
546 {0x0181, 0x30},
547 {0x0182, 0x05},
548 {0x0185, 0x01},
549 {0x03fe, 0x10},
550 {0x03fe, 0x00},
551 {REG_NULL, 0x00},
552 };
553 static const struct gc4663_mode supported_modes[] = {
554 {
555 .width = 2560,
556 .height = 1440,
557 .max_fps = {
558 .numerator = 10000,
559 .denominator = 300000,
560 },
561 .exp_def = 0x0100,
562 .hts_def = 0x0AA0,
563 .vts_def = 0x05DC,
564 .bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
565 .reg_list = gc4663_linear10bit_2560x1440_regs,
566 .hdr_mode = NO_HDR,
567 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
568 }, {
569 .width = 2560,
570 .height = 1440,
571 .max_fps = {
572 .numerator = 10000,
573 .denominator = 300000,
574 },
575 .exp_def = 0x0100,
576 .hts_def = 0x0AA0,
577 .vts_def = 0x0640,
578 .bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
579 .reg_list = gc4663_hdr10bit_2560x1440_regs,
580 .hdr_mode = HDR_X2,
581 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
582 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
583 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
584 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
585 },
586 };
587
588 static const s64 link_freq_menu_items[] = {
589 GC4663_LINK_FREQ_LINEAR,
590 GC4663_LINK_FREQ_HDR,
591 };
592
593 static const char * const gc4663_test_pattern_menu[] = {
594 "Disabled",
595 "Vertical Color Bar Type 1",
596 "Vertical Color Bar Type 2",
597 "Vertical Color Bar Type 3",
598 "Vertical Color Bar Type 4"
599 };
600
601 /* Write registers up to 4 at a time */
gc4663_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)602 static int gc4663_write_reg(struct i2c_client *client, u16 reg,
603 u32 len, u32 val)
604 {
605 u32 buf_i, val_i;
606 u8 buf[6];
607 u8 *val_p;
608 __be32 val_be;
609
610 if (len > 4)
611 return -EINVAL;
612
613 buf[0] = reg >> 8;
614 buf[1] = reg & 0xff;
615
616 val_be = cpu_to_be32(val);
617 val_p = (u8 *)&val_be;
618 buf_i = 2;
619 val_i = 4 - len;
620
621 while (val_i < 4)
622 buf[buf_i++] = val_p[val_i++];
623
624 if (i2c_master_send(client, buf, len + 2) != len + 2)
625 return -EIO;
626
627 return 0;
628 }
629
gc4663_write_array(struct i2c_client * client,const struct regval * regs)630 static int gc4663_write_array(struct i2c_client *client,
631 const struct regval *regs)
632 {
633 u32 i;
634 int ret = 0;
635
636 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
637 ret = gc4663_write_reg(client, regs[i].addr,
638 GC4663_REG_VALUE_08BIT, regs[i].val);
639
640 return ret;
641 }
642
643 /* Read registers up to 4 at a time */
gc4663_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)644 static int gc4663_read_reg(struct i2c_client *client, u16 reg,
645 unsigned int len, u32 *val)
646 {
647 struct i2c_msg msgs[2];
648 u8 *data_be_p;
649 __be32 data_be = 0;
650 __be16 reg_addr_be = cpu_to_be16(reg);
651 int ret;
652
653 if (len > 4 || !len)
654 return -EINVAL;
655
656 data_be_p = (u8 *)&data_be;
657 /* Write register address */
658 msgs[0].addr = client->addr;
659 msgs[0].flags = 0;
660 msgs[0].len = 2;
661 msgs[0].buf = (u8 *)®_addr_be;
662
663 /* Read data from register */
664 msgs[1].addr = client->addr;
665 msgs[1].flags = I2C_M_RD;
666 msgs[1].len = len;
667 msgs[1].buf = &data_be_p[4 - len];
668
669 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
670 if (ret != ARRAY_SIZE(msgs))
671 return -EIO;
672
673 *val = be32_to_cpu(data_be);
674
675 return 0;
676 }
677
gc4663_get_reso_dist(const struct gc4663_mode * mode,struct v4l2_mbus_framefmt * framefmt)678 static int gc4663_get_reso_dist(const struct gc4663_mode *mode,
679 struct v4l2_mbus_framefmt *framefmt)
680 {
681 return abs(mode->width - framefmt->width) +
682 abs(mode->height - framefmt->height);
683 }
684
685 static const struct gc4663_mode *
gc4663_find_best_fit(struct gc4663 * gc4663,struct v4l2_subdev_format * fmt)686 gc4663_find_best_fit(struct gc4663 *gc4663, struct v4l2_subdev_format *fmt)
687 {
688 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
689 int dist;
690 int cur_best_fit = 0;
691 int cur_best_fit_dist = -1;
692 unsigned int i;
693
694 for (i = 0; i < gc4663->cfg_num; i++) {
695 dist = gc4663_get_reso_dist(&supported_modes[i], framefmt);
696 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
697 cur_best_fit_dist = dist;
698 cur_best_fit = i;
699 }
700 }
701
702 return &supported_modes[cur_best_fit];
703 }
704
gc4663_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)705 static int gc4663_set_fmt(struct v4l2_subdev *sd,
706 struct v4l2_subdev_pad_config *cfg,
707 struct v4l2_subdev_format *fmt)
708 {
709 struct gc4663 *gc4663 = to_gc4663(sd);
710 const struct gc4663_mode *mode;
711 s64 h_blank, vblank_def;
712
713 mutex_lock(&gc4663->mutex);
714
715 mode = gc4663_find_best_fit(gc4663, fmt);
716 fmt->format.code = mode->bus_fmt;
717 fmt->format.width = mode->width;
718 fmt->format.height = mode->height;
719 fmt->format.field = V4L2_FIELD_NONE;
720 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
721 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
722 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
723 #else
724 mutex_unlock(&gc4663->mutex);
725 return -ENOTTY;
726 #endif
727 } else {
728 gc4663->cur_mode = mode;
729 h_blank = mode->hts_def - mode->width;
730 __v4l2_ctrl_modify_range(gc4663->hblank, h_blank,
731 h_blank, 1, h_blank);
732 vblank_def = mode->vts_def - mode->height;
733 __v4l2_ctrl_modify_range(gc4663->vblank, vblank_def,
734 GC4663_VTS_MAX - mode->height,
735 1, vblank_def);
736
737 if (mode->hdr_mode == HDR_X2) {
738 gc4663->cur_link_freq = 1;
739 gc4663->cur_pixel_rate = GC4663_PIXEL_RATE_HDR;
740 } else {
741 gc4663->cur_link_freq = 0;
742 gc4663->cur_pixel_rate = GC4663_PIXEL_RATE_LINEAR;
743 }
744
745 __v4l2_ctrl_s_ctrl_int64(gc4663->pixel_rate,
746 gc4663->cur_pixel_rate);
747 __v4l2_ctrl_s_ctrl(gc4663->link_freq,
748 gc4663->cur_link_freq);
749 gc4663->cur_vts = mode->vts_def;
750 }
751 mutex_unlock(&gc4663->mutex);
752
753 return 0;
754 }
755
gc4663_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)756 static int gc4663_get_fmt(struct v4l2_subdev *sd,
757 struct v4l2_subdev_pad_config *cfg,
758 struct v4l2_subdev_format *fmt)
759 {
760 struct gc4663 *gc4663 = to_gc4663(sd);
761 const struct gc4663_mode *mode = gc4663->cur_mode;
762
763 mutex_lock(&gc4663->mutex);
764 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
765 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
766 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
767 #else
768 mutex_unlock(&gc4663->mutex);
769 return -ENOTTY;
770 #endif
771 } else {
772 fmt->format.width = mode->width;
773 fmt->format.height = mode->height;
774 fmt->format.code = mode->bus_fmt;
775 fmt->format.field = V4L2_FIELD_NONE;
776 }
777 mutex_unlock(&gc4663->mutex);
778
779 return 0;
780 }
781
gc4663_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)782 static int gc4663_enum_mbus_code(struct v4l2_subdev *sd,
783 struct v4l2_subdev_pad_config *cfg,
784 struct v4l2_subdev_mbus_code_enum *code)
785 {
786 struct gc4663 *gc4663 = to_gc4663(sd);
787
788 if (code->index != 0)
789 return -EINVAL;
790 code->code = gc4663->cur_mode->bus_fmt;
791
792 return 0;
793 }
794
gc4663_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)795 static int gc4663_enum_frame_sizes(struct v4l2_subdev *sd,
796 struct v4l2_subdev_pad_config *cfg,
797 struct v4l2_subdev_frame_size_enum *fse)
798 {
799 struct gc4663 *gc4663 = to_gc4663(sd);
800
801 if (fse->index >= gc4663->cfg_num)
802 return -EINVAL;
803
804 if (fse->code != supported_modes[0].bus_fmt)
805 return -EINVAL;
806
807 fse->min_width = supported_modes[fse->index].width;
808 fse->max_width = supported_modes[fse->index].width;
809 fse->max_height = supported_modes[fse->index].height;
810 fse->min_height = supported_modes[fse->index].height;
811
812 return 0;
813 }
814
gc4663_enable_test_pattern(struct gc4663 * gc4663,u32 pattern)815 static int gc4663_enable_test_pattern(struct gc4663 *gc4663, u32 pattern)
816 {
817 u32 val;
818
819 if (pattern)
820 val = GC4663_TEST_PATTERN_ENABLE;
821 else
822 val = GC4663_TEST_PATTERN_DISABLE;
823
824 return gc4663_write_reg(gc4663->client, GC4663_REG_TEST_PATTERN,
825 GC4663_REG_VALUE_08BIT, val);
826 }
827
gc4663_set_gain_reg_hdr(struct gc4663 * gc4663,u32 gain)828 static int gc4663_set_gain_reg_hdr(struct gc4663 *gc4663, u32 gain)
829 {
830 int i;
831 int total;
832 u32 tol_dig_gain = 0;
833
834 if (gain < 64)
835 gain = 64;
836 total = sizeof(gain_level_table) / sizeof(u32) - 1;
837 for (i = 0; i < total; i++) {
838 if (gain_level_table[i] <= gain &&
839 gain < gain_level_table[i + 1])
840 break;
841 }
842
843 if (i >= total)
844 i = total - 1;
845
846 tol_dig_gain = gain * 64 / gain_level_table[i];
847
848 gc4663_write_reg(gc4663->client, 0x2b3,
849 GC4663_REG_VALUE_08BIT, reg_val_table_hdr[i][0]);
850 gc4663_write_reg(gc4663->client, 0x2b4,
851 GC4663_REG_VALUE_08BIT, reg_val_table_hdr[i][1]);
852 gc4663_write_reg(gc4663->client, 0x2b8,
853 GC4663_REG_VALUE_08BIT, reg_val_table_hdr[i][2]);
854 gc4663_write_reg(gc4663->client, 0x2b9,
855 GC4663_REG_VALUE_08BIT, reg_val_table_hdr[i][3]);
856 gc4663_write_reg(gc4663->client, 0x515,
857 GC4663_REG_VALUE_08BIT, reg_val_table_hdr[i][4]);
858 gc4663_write_reg(gc4663->client, 0x519,
859 GC4663_REG_VALUE_08BIT, reg_val_table_hdr[i][5]);
860 gc4663_write_reg(gc4663->client, 0x2d9,
861 GC4663_REG_VALUE_08BIT, reg_val_table_hdr[i][6]);
862
863 gc4663_write_reg(gc4663->client, 0x20e,
864 GC4663_REG_VALUE_08BIT, (tol_dig_gain >> 6));
865 gc4663_write_reg(gc4663->client, 0x20f,
866 GC4663_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f) << 2));
867 return 0;
868 }
869
gc4663_set_gain_reg(struct gc4663 * gc4663,u32 gain)870 static int gc4663_set_gain_reg(struct gc4663 *gc4663, u32 gain)
871 {
872 int i;
873 int total;
874 u32 tol_dig_gain = 0;
875
876 if (gain < 64)
877 gain = 64;
878 total = sizeof(gain_level_table) / sizeof(u32) - 1;
879 for (i = 0; i < total; i++) {
880 if (gain_level_table[i] <= gain &&
881 gain < gain_level_table[i + 1])
882 break;
883 }
884 tol_dig_gain = gain * 64 / gain_level_table[i];
885 if (i >= total)
886 i = total - 1;
887
888 gc4663_write_reg(gc4663->client, 0x2b3,
889 GC4663_REG_VALUE_08BIT, reg_val_table_liner[i][0]);
890 gc4663_write_reg(gc4663->client, 0x2b4,
891 GC4663_REG_VALUE_08BIT, reg_val_table_liner[i][1]);
892 gc4663_write_reg(gc4663->client, 0x2b8,
893 GC4663_REG_VALUE_08BIT, reg_val_table_liner[i][2]);
894 gc4663_write_reg(gc4663->client, 0x2b9,
895 GC4663_REG_VALUE_08BIT, reg_val_table_liner[i][3]);
896 gc4663_write_reg(gc4663->client, 0x515,
897 GC4663_REG_VALUE_08BIT, reg_val_table_liner[i][4]);
898 gc4663_write_reg(gc4663->client, 0x519,
899 GC4663_REG_VALUE_08BIT, reg_val_table_liner[i][5]);
900 gc4663_write_reg(gc4663->client, 0x2d9,
901 GC4663_REG_VALUE_08BIT, reg_val_table_liner[i][6]);
902
903
904 gc4663_write_reg(gc4663->client, 0x20e,
905 GC4663_REG_VALUE_08BIT, (tol_dig_gain >> 6));
906 gc4663_write_reg(gc4663->client, 0x20f,
907 GC4663_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f) << 2));
908 return 0;
909 }
910
911 /* window_heigth = 1472
912 * dummy = 20
913 * frame_length = window_heigth + dummy + vb = 1492 + vb
914 * s_exp_time < VB
915 * s_exp_time + l_exp_time < frame_length
916 */
gc4663_set_hdrae(struct gc4663 * gc4663,struct preisp_hdrae_exp_s * ae)917 static int gc4663_set_hdrae(struct gc4663 *gc4663,
918 struct preisp_hdrae_exp_s *ae)
919 {
920 int ret = 0;
921 u32 l_exp_time, m_exp_time, s_exp_time;
922 u32 l_a_gain, m_a_gain, s_a_gain;
923 u32 intt_long_l, intt_long_h;
924 u32 intt_short_l, intt_short_h;
925 u32 gain;
926
927 if (!gc4663->has_init_exp && !gc4663->streaming) {
928 gc4663->init_hdrae_exp = *ae;
929 gc4663->has_init_exp = true;
930 dev_dbg(&gc4663->client->dev, "gc4663 don't stream, record exp for hdr!\n");
931 return ret;
932 }
933 l_exp_time = ae->long_exp_reg;
934 m_exp_time = ae->middle_exp_reg;
935 s_exp_time = ae->short_exp_reg;
936 l_a_gain = ae->long_gain_reg;
937 m_a_gain = ae->middle_gain_reg;
938 s_a_gain = ae->short_gain_reg;
939
940 dev_dbg(&gc4663->client->dev,
941 "rev exp req: L_exp: 0x%x, M_exp: 0x%x, S_exp 0x%x,l_gain:0x%x, m_gain: 0x%x, s_gain: 0x%x\n",
942 l_exp_time, m_exp_time, s_exp_time,
943 l_a_gain, m_a_gain, s_a_gain);
944
945 if (gc4663->cur_mode->hdr_mode == HDR_X2)
946 l_exp_time = m_exp_time;
947
948 gain = s_a_gain;
949
950 if (l_exp_time <= 1)
951 l_exp_time = 1;
952
953 if (s_exp_time < 1)
954 s_exp_time = 1;
955
956 if (s_exp_time > gc4663->cur_vts - 1492) {
957 dev_err(&gc4663->client->dev, "the s_exp_time is too large.\n");
958 s_exp_time = gc4663->cur_vts - 1492;
959 }
960
961 if (l_exp_time > gc4663->cur_vts - s_exp_time) {
962 dev_err(&gc4663->client->dev, "the l_exp_time is too large.\n");
963 l_exp_time = gc4663->cur_vts - s_exp_time;
964 }
965
966 if (s_exp_time * 16 == l_exp_time) {
967 if (s_exp_time > 94)
968 s_exp_time = 94;
969 if (l_exp_time > 1504)
970 l_exp_time = 1504;
971 }
972
973 intt_long_l = l_exp_time & 0xff;
974 intt_long_h = (l_exp_time >> 8) & 0x3f;
975
976 intt_short_l = s_exp_time & 0xff;
977 intt_short_h = (s_exp_time >> 8) & 0x3f;
978
979 ret |= gc4663_write_reg(gc4663->client, GC4663_REG_EXPOSURE_H,
980 GC4663_REG_VALUE_08BIT,
981 intt_long_h);
982 ret |= gc4663_write_reg(gc4663->client, GC4663_REG_EXPOSURE_L,
983 GC4663_REG_VALUE_08BIT,
984 intt_long_l);
985 ret |= gc4663_write_reg(gc4663->client, GC4663_REG_SEXPOSURE_H,
986 GC4663_REG_VALUE_08BIT,
987 intt_short_h);
988 ret |= gc4663_write_reg(gc4663->client, GC4663_REG_SEXPOSURE_L,
989 GC4663_REG_VALUE_08BIT,
990 intt_short_l);
991
992 ret |= gc4663_set_gain_reg_hdr(gc4663, gain);
993 return ret;
994 }
995
gc4663_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)996 static int gc4663_g_frame_interval(struct v4l2_subdev *sd,
997 struct v4l2_subdev_frame_interval *fi)
998 {
999 struct gc4663 *gc4663 = to_gc4663(sd);
1000 const struct gc4663_mode *mode = gc4663->cur_mode;
1001
1002 fi->interval = mode->max_fps;
1003
1004 return 0;
1005 }
1006
gc4663_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1007 static int gc4663_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1008 struct v4l2_mbus_config *config)
1009 {
1010 struct gc4663 *gc4663 = to_gc4663(sd);
1011 const struct gc4663_mode *mode = gc4663->cur_mode;
1012 u32 val = 0;
1013
1014 if (mode->hdr_mode == NO_HDR)
1015 val = 1 << (GC4663_LANES - 1) |
1016 V4L2_MBUS_CSI2_CHANNEL_0 |
1017 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1018 if (mode->hdr_mode == HDR_X2)
1019 val = 1 << (GC4663_LANES - 1) |
1020 V4L2_MBUS_CSI2_CHANNEL_0 |
1021 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
1022 V4L2_MBUS_CSI2_CHANNEL_1;
1023
1024 config->type = V4L2_MBUS_CSI2_DPHY;
1025 config->flags = val;
1026
1027 return 0;
1028 }
1029
gc4663_get_module_inf(struct gc4663 * gc4663,struct rkmodule_inf * inf)1030 static void gc4663_get_module_inf(struct gc4663 *gc4663,
1031 struct rkmodule_inf *inf)
1032 {
1033 memset(inf, 0, sizeof(*inf));
1034 strlcpy(inf->base.sensor, GC4663_NAME, sizeof(inf->base.sensor));
1035 strlcpy(inf->base.module, gc4663->module_name,
1036 sizeof(inf->base.module));
1037 strlcpy(inf->base.lens, gc4663->len_name, sizeof(inf->base.lens));
1038 }
1039
gc4663_get_channel_info(struct gc4663 * gc4663,struct rkmodule_channel_info * ch_info)1040 static int gc4663_get_channel_info(struct gc4663 *gc4663, struct rkmodule_channel_info *ch_info)
1041 {
1042 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1043 return -EINVAL;
1044 ch_info->vc = gc4663->cur_mode->vc[ch_info->index];
1045 ch_info->width = gc4663->cur_mode->width;
1046 ch_info->height = gc4663->cur_mode->height;
1047 ch_info->bus_fmt = gc4663->cur_mode->bus_fmt;
1048 return 0;
1049 }
1050
gc4663_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1051 static long gc4663_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1052 {
1053 struct gc4663 *gc4663 = to_gc4663(sd);
1054 struct rkmodule_hdr_cfg *hdr;
1055 u32 i, h, w;
1056 long ret = 0;
1057 u32 stream = 0;
1058 struct rkmodule_channel_info *ch_info;
1059
1060 switch (cmd) {
1061 case RKMODULE_GET_MODULE_INFO:
1062 gc4663_get_module_inf(gc4663, (struct rkmodule_inf *)arg);
1063 break;
1064 case RKMODULE_GET_HDR_CFG:
1065 hdr = (struct rkmodule_hdr_cfg *)arg;
1066 hdr->esp.mode = HDR_NORMAL_VC;
1067 hdr->hdr_mode = gc4663->cur_mode->hdr_mode;
1068 break;
1069 case RKMODULE_SET_HDR_CFG:
1070 hdr = (struct rkmodule_hdr_cfg *)arg;
1071 w = gc4663->cur_mode->width;
1072 h = gc4663->cur_mode->height;
1073 for (i = 0; i < gc4663->cfg_num; i++) {
1074 if (w == supported_modes[i].width &&
1075 h == supported_modes[i].height &&
1076 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1077 gc4663->cur_mode = &supported_modes[i];
1078 break;
1079 }
1080 }
1081 if (i == gc4663->cfg_num) {
1082 dev_err(&gc4663->client->dev,
1083 "not find hdr mode:%d %dx%d config\n",
1084 hdr->hdr_mode, w, h);
1085 ret = -EINVAL;
1086 } else {
1087 w = gc4663->cur_mode->hts_def -
1088 gc4663->cur_mode->width;
1089 h = gc4663->cur_mode->vts_def -
1090 gc4663->cur_mode->height;
1091 __v4l2_ctrl_modify_range(gc4663->hblank, w, w, 1, w);
1092 __v4l2_ctrl_modify_range(gc4663->vblank, h,
1093 GC4663_VTS_MAX -
1094 gc4663->cur_mode->height,
1095 1, h);
1096 if (gc4663->cur_mode->hdr_mode == HDR_X2) {
1097 gc4663->cur_link_freq = 1;
1098 gc4663->cur_pixel_rate = GC4663_PIXEL_RATE_HDR;
1099 } else {
1100 gc4663->cur_link_freq = 0;
1101 gc4663->cur_pixel_rate = GC4663_PIXEL_RATE_LINEAR;
1102 }
1103
1104 __v4l2_ctrl_s_ctrl_int64(gc4663->pixel_rate,
1105 gc4663->cur_pixel_rate);
1106 __v4l2_ctrl_s_ctrl(gc4663->link_freq,
1107 gc4663->cur_link_freq);
1108 gc4663->cur_vts = gc4663->cur_mode->vts_def;
1109 }
1110 break;
1111 case PREISP_CMD_SET_HDRAE_EXP:
1112 ret = gc4663_set_hdrae(gc4663, arg);
1113 break;
1114 case RKMODULE_SET_QUICK_STREAM:
1115 stream = *((u32 *)arg);
1116 if (stream)
1117 ret = gc4663_write_reg(gc4663->client, GC4663_REG_CTRL_MODE,
1118 GC4663_REG_VALUE_08BIT, GC4663_MODE_STREAMING);
1119 else
1120 ret = gc4663_write_reg(gc4663->client, GC4663_REG_CTRL_MODE,
1121 GC4663_REG_VALUE_08BIT, GC4663_MODE_SW_STANDBY);
1122 break;
1123 case RKMODULE_GET_CHANNEL_INFO:
1124 ch_info = (struct rkmodule_channel_info *)arg;
1125 ret = gc4663_get_channel_info(gc4663, ch_info);
1126 break;
1127 default:
1128 ret = -ENOIOCTLCMD;
1129 break;
1130 }
1131
1132 return ret;
1133 }
1134
1135 #ifdef CONFIG_COMPAT
gc4663_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1136 static long gc4663_compat_ioctl32(struct v4l2_subdev *sd,
1137 unsigned int cmd, unsigned long arg)
1138 {
1139 void __user *up = compat_ptr(arg);
1140 struct rkmodule_inf *inf;
1141 struct rkmodule_awb_cfg *cfg;
1142 struct rkmodule_hdr_cfg *hdr;
1143 struct preisp_hdrae_exp_s *hdrae;
1144 long ret;
1145 u32 stream = 0;
1146 struct rkmodule_channel_info *ch_info;
1147
1148 switch (cmd) {
1149 case RKMODULE_GET_MODULE_INFO:
1150 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1151 if (!inf) {
1152 ret = -ENOMEM;
1153 return ret;
1154 }
1155
1156 ret = gc4663_ioctl(sd, cmd, inf);
1157 if (!ret) {
1158 ret = copy_to_user(up, inf, sizeof(*inf));
1159 if (ret)
1160 ret = -EFAULT;
1161 }
1162 kfree(inf);
1163 break;
1164 case RKMODULE_AWB_CFG:
1165 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1166 if (!cfg) {
1167 ret = -ENOMEM;
1168 return ret;
1169 }
1170
1171 ret = copy_from_user(cfg, up, sizeof(*cfg));
1172 if (!ret)
1173 ret = gc4663_ioctl(sd, cmd, cfg);
1174 else
1175 ret = -EFAULT;
1176 kfree(cfg);
1177 break;
1178 case RKMODULE_GET_HDR_CFG:
1179 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1180 if (!hdr) {
1181 ret = -ENOMEM;
1182 return ret;
1183 }
1184
1185 ret = gc4663_ioctl(sd, cmd, hdr);
1186 if (!ret) {
1187 ret = copy_to_user(up, hdr, sizeof(*hdr));
1188 if (ret)
1189 ret = -EFAULT;
1190 }
1191 kfree(hdr);
1192 break;
1193 case RKMODULE_SET_HDR_CFG:
1194 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1195 if (!hdr) {
1196 ret = -ENOMEM;
1197 return ret;
1198 }
1199
1200 ret = copy_from_user(hdr, up, sizeof(*hdr));
1201 if (!ret)
1202 ret = gc4663_ioctl(sd, cmd, hdr);
1203 else
1204 ret = -EFAULT;
1205 kfree(hdr);
1206 break;
1207 case PREISP_CMD_SET_HDRAE_EXP:
1208 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1209 if (!hdrae) {
1210 ret = -ENOMEM;
1211 return ret;
1212 }
1213
1214 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1215 if (!ret)
1216 ret = gc4663_ioctl(sd, cmd, hdrae);
1217 else
1218 ret = -EFAULT;
1219 kfree(hdrae);
1220 break;
1221 case RKMODULE_SET_QUICK_STREAM:
1222 ret = copy_from_user(&stream, up, sizeof(u32));
1223 if (!ret)
1224 ret = gc4663_ioctl(sd, cmd, &stream);
1225 else
1226 ret = -EFAULT;
1227 break;
1228 case RKMODULE_GET_CHANNEL_INFO:
1229 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1230 if (!ch_info) {
1231 ret = -ENOMEM;
1232 return ret;
1233 }
1234
1235 ret = gc4663_ioctl(sd, cmd, ch_info);
1236 if (!ret) {
1237 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1238 if (ret)
1239 ret = -EFAULT;
1240 }
1241 kfree(ch_info);
1242 break;
1243 default:
1244 ret = -ENOIOCTLCMD;
1245 break;
1246 }
1247
1248 return ret;
1249 }
1250 #endif
1251
__gc4663_start_stream(struct gc4663 * gc4663)1252 static int __gc4663_start_stream(struct gc4663 *gc4663)
1253 {
1254 int ret;
1255
1256 ret = gc4663_write_array(gc4663->client, gc4663->cur_mode->reg_list);
1257 if (ret)
1258 return ret;
1259
1260 /* In case these controls are set before streaming */
1261 ret = __v4l2_ctrl_handler_setup(&gc4663->ctrl_handler);
1262 if (gc4663->has_init_exp && gc4663->cur_mode->hdr_mode != NO_HDR) {
1263 ret = gc4663_ioctl(&gc4663->subdev, PREISP_CMD_SET_HDRAE_EXP,
1264 &gc4663->init_hdrae_exp);
1265 if (ret) {
1266 dev_err(&gc4663->client->dev,
1267 "init exp fail in hdr mode\n");
1268 return ret;
1269 }
1270 }
1271 if (ret)
1272 return ret;
1273
1274 ret |= gc4663_write_reg(gc4663->client, GC4663_REG_CTRL_MODE,
1275 GC4663_REG_VALUE_08BIT, GC4663_MODE_STREAMING);
1276 if (gc4663->cur_mode->hdr_mode == NO_HDR)
1277 ret |= gc4663_write_array(gc4663->client, gc4663_linear_global_regs);
1278 return ret;
1279 }
1280
__gc4663_stop_stream(struct gc4663 * gc4663)1281 static int __gc4663_stop_stream(struct gc4663 *gc4663)
1282 {
1283 gc4663->has_init_exp = false;
1284 return gc4663_write_reg(gc4663->client, GC4663_REG_CTRL_MODE,
1285 GC4663_REG_VALUE_08BIT, GC4663_MODE_SW_STANDBY);
1286 }
1287
gc4663_s_stream(struct v4l2_subdev * sd,int on)1288 static int gc4663_s_stream(struct v4l2_subdev *sd, int on)
1289 {
1290 struct gc4663 *gc4663 = to_gc4663(sd);
1291 struct i2c_client *client = gc4663->client;
1292 int ret = 0;
1293
1294 mutex_lock(&gc4663->mutex);
1295 on = !!on;
1296 if (on == gc4663->streaming)
1297 goto unlock_and_return;
1298
1299 if (on) {
1300 ret = pm_runtime_get_sync(&client->dev);
1301 if (ret < 0) {
1302 pm_runtime_put_noidle(&client->dev);
1303 goto unlock_and_return;
1304 }
1305
1306 ret = __gc4663_start_stream(gc4663);
1307 if (ret) {
1308 v4l2_err(sd, "start stream failed while write regs\n");
1309 pm_runtime_put(&client->dev);
1310 goto unlock_and_return;
1311 }
1312 } else {
1313 __gc4663_stop_stream(gc4663);
1314 pm_runtime_put(&client->dev);
1315 }
1316
1317 gc4663->streaming = on;
1318
1319 unlock_and_return:
1320 mutex_unlock(&gc4663->mutex);
1321
1322 return ret;
1323 }
1324
gc4663_s_power(struct v4l2_subdev * sd,int on)1325 static int gc4663_s_power(struct v4l2_subdev *sd, int on)
1326 {
1327 struct gc4663 *gc4663 = to_gc4663(sd);
1328 struct i2c_client *client = gc4663->client;
1329 int ret = 0;
1330
1331 mutex_lock(&gc4663->mutex);
1332
1333 /* If the power state is not modified - no work to do. */
1334 if (gc4663->power_on == !!on)
1335 goto unlock_and_return;
1336
1337 if (on) {
1338 ret = pm_runtime_get_sync(&client->dev);
1339 if (ret < 0) {
1340 pm_runtime_put_noidle(&client->dev);
1341 goto unlock_and_return;
1342 }
1343
1344 ret = gc4663_write_array(gc4663->client, gc4663_global_regs);
1345 if (ret) {
1346 v4l2_err(sd, "could not set init registers\n");
1347 pm_runtime_put_noidle(&client->dev);
1348 goto unlock_and_return;
1349 }
1350
1351 gc4663->power_on = true;
1352 } else {
1353 pm_runtime_put(&client->dev);
1354 gc4663->power_on = false;
1355 }
1356
1357 unlock_and_return:
1358 mutex_unlock(&gc4663->mutex);
1359
1360 return ret;
1361 }
1362
1363 /* Calculate the delay in us by clock rate and clock cycles */
gc4663_cal_delay(u32 cycles)1364 static inline u32 gc4663_cal_delay(u32 cycles)
1365 {
1366 return DIV_ROUND_UP(cycles, GC4663_XVCLK_FREQ / 1000 / 1000);
1367 }
1368
__gc4663_power_on(struct gc4663 * gc4663)1369 static int __gc4663_power_on(struct gc4663 *gc4663)
1370 {
1371 int ret;
1372 u32 delay_us;
1373 struct device *dev = &gc4663->client->dev;
1374
1375 if (!IS_ERR_OR_NULL(gc4663->pins_default)) {
1376 ret = pinctrl_select_state(gc4663->pinctrl,
1377 gc4663->pins_default);
1378 if (ret < 0)
1379 dev_err(dev, "could not set pins\n");
1380 }
1381 ret = clk_set_rate(gc4663->xvclk, GC4663_XVCLK_FREQ);
1382 if (ret < 0)
1383 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1384 if (clk_get_rate(gc4663->xvclk) != GC4663_XVCLK_FREQ)
1385 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1386 ret = clk_prepare_enable(gc4663->xvclk);
1387 if (ret < 0) {
1388 dev_err(dev, "Failed to enable xvclk\n");
1389 return ret;
1390 }
1391 if (!IS_ERR(gc4663->reset_gpio))
1392 gpiod_set_value_cansleep(gc4663->reset_gpio, 0);
1393
1394 if (!IS_ERR(gc4663->pwdn_gpio))
1395 gpiod_set_value_cansleep(gc4663->pwdn_gpio, 0);
1396
1397 usleep_range(500, 1000);
1398 ret = regulator_bulk_enable(GC4663_NUM_SUPPLIES, gc4663->supplies);
1399
1400 if (ret < 0) {
1401 dev_err(dev, "Failed to enable regulators\n");
1402 goto disable_clk;
1403 }
1404
1405 if (!IS_ERR(gc4663->pwren_gpio))
1406 gpiod_set_value_cansleep(gc4663->pwren_gpio, 1);
1407
1408 usleep_range(1000, 1100);
1409 if (!IS_ERR(gc4663->pwdn_gpio))
1410 gpiod_set_value_cansleep(gc4663->pwdn_gpio, 1);
1411 usleep_range(100, 150);
1412 if (!IS_ERR(gc4663->reset_gpio))
1413 gpiod_set_value_cansleep(gc4663->reset_gpio, 1);
1414
1415 /* 8192 cycles prior to first SCCB transaction */
1416 delay_us = gc4663_cal_delay(8192);
1417 usleep_range(delay_us, delay_us * 2);
1418
1419 return 0;
1420
1421 disable_clk:
1422 clk_disable_unprepare(gc4663->xvclk);
1423
1424 return ret;
1425 }
1426
__gc4663_power_off(struct gc4663 * gc4663)1427 static void __gc4663_power_off(struct gc4663 *gc4663)
1428 {
1429 int ret;
1430 struct device *dev = &gc4663->client->dev;
1431
1432 if (!IS_ERR(gc4663->pwdn_gpio))
1433 gpiod_set_value_cansleep(gc4663->pwdn_gpio, 0);
1434 clk_disable_unprepare(gc4663->xvclk);
1435 if (!IS_ERR(gc4663->reset_gpio))
1436 gpiod_set_value_cansleep(gc4663->reset_gpio, 0);
1437 if (!IS_ERR_OR_NULL(gc4663->pins_sleep)) {
1438 ret = pinctrl_select_state(gc4663->pinctrl,
1439 gc4663->pins_sleep);
1440 if (ret < 0)
1441 dev_dbg(dev, "could not set pins\n");
1442 }
1443 regulator_bulk_disable(GC4663_NUM_SUPPLIES, gc4663->supplies);
1444 if (!IS_ERR(gc4663->pwren_gpio))
1445 gpiod_set_value_cansleep(gc4663->pwren_gpio, 0);
1446 }
1447
gc4663_runtime_resume(struct device * dev)1448 static int gc4663_runtime_resume(struct device *dev)
1449 {
1450 struct i2c_client *client = to_i2c_client(dev);
1451 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1452 struct gc4663 *gc4663 = to_gc4663(sd);
1453
1454 return __gc4663_power_on(gc4663);
1455 }
1456
gc4663_runtime_suspend(struct device * dev)1457 static int gc4663_runtime_suspend(struct device *dev)
1458 {
1459 struct i2c_client *client = to_i2c_client(dev);
1460 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1461 struct gc4663 *gc4663 = to_gc4663(sd);
1462
1463 __gc4663_power_off(gc4663);
1464
1465 return 0;
1466 }
1467
1468 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc4663_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1469 static int gc4663_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1470 {
1471 struct gc4663 *gc4663 = to_gc4663(sd);
1472 struct v4l2_mbus_framefmt *try_fmt =
1473 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1474 const struct gc4663_mode *def_mode = &supported_modes[0];
1475
1476 mutex_lock(&gc4663->mutex);
1477 /* Initialize try_fmt */
1478 try_fmt->width = def_mode->width;
1479 try_fmt->height = def_mode->height;
1480 try_fmt->code = def_mode->bus_fmt;
1481 try_fmt->field = V4L2_FIELD_NONE;
1482
1483 mutex_unlock(&gc4663->mutex);
1484 /* No crop or compose */
1485
1486 return 0;
1487 }
1488 #endif
1489
gc4663_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1490 static int gc4663_enum_frame_interval(struct v4l2_subdev *sd,
1491 struct v4l2_subdev_pad_config *cfg,
1492 struct v4l2_subdev_frame_interval_enum *fie)
1493 {
1494 struct gc4663 *gc4663 = to_gc4663(sd);
1495
1496 if (fie->index >= gc4663->cfg_num)
1497 return -EINVAL;
1498
1499 fie->code = supported_modes[fie->index].bus_fmt;
1500 fie->width = supported_modes[fie->index].width;
1501 fie->height = supported_modes[fie->index].height;
1502 fie->interval = supported_modes[fie->index].max_fps;
1503 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1504 return 0;
1505 }
1506
1507 static const struct dev_pm_ops gc4663_pm_ops = {
1508 SET_RUNTIME_PM_OPS(gc4663_runtime_suspend,
1509 gc4663_runtime_resume, NULL)
1510 };
1511
1512 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1513 static const struct v4l2_subdev_internal_ops gc4663_internal_ops = {
1514 .open = gc4663_open,
1515 };
1516 #endif
1517
1518 static const struct v4l2_subdev_core_ops gc4663_core_ops = {
1519 .s_power = gc4663_s_power,
1520 .ioctl = gc4663_ioctl,
1521 #ifdef CONFIG_COMPAT
1522 .compat_ioctl32 = gc4663_compat_ioctl32,
1523 #endif
1524 };
1525
1526 static const struct v4l2_subdev_video_ops gc4663_video_ops = {
1527 .s_stream = gc4663_s_stream,
1528 .g_frame_interval = gc4663_g_frame_interval,
1529 };
1530
1531 static const struct v4l2_subdev_pad_ops gc4663_pad_ops = {
1532 .enum_mbus_code = gc4663_enum_mbus_code,
1533 .enum_frame_size = gc4663_enum_frame_sizes,
1534 .enum_frame_interval = gc4663_enum_frame_interval,
1535 .get_fmt = gc4663_get_fmt,
1536 .set_fmt = gc4663_set_fmt,
1537 .get_mbus_config = gc4663_g_mbus_config,
1538 };
1539
1540 static const struct v4l2_subdev_ops gc4663_subdev_ops = {
1541 .core = &gc4663_core_ops,
1542 .video = &gc4663_video_ops,
1543 .pad = &gc4663_pad_ops,
1544 };
1545
gc4663_set_ctrl(struct v4l2_ctrl * ctrl)1546 static int gc4663_set_ctrl(struct v4l2_ctrl *ctrl)
1547 {
1548 struct gc4663 *gc4663 = container_of(ctrl->handler,
1549 struct gc4663, ctrl_handler);
1550 struct i2c_client *client = gc4663->client;
1551 s64 max;
1552 int ret = 0;
1553 int val = 0;
1554
1555 /*Propagate change of current control to all related controls*/
1556 switch (ctrl->id) {
1557 case V4L2_CID_VBLANK:
1558 /*Update max exposure while meeting expected vblanking*/
1559 max = gc4663->cur_mode->height + ctrl->val - 4;
1560 __v4l2_ctrl_modify_range(gc4663->exposure,
1561 gc4663->exposure->minimum,
1562 max,
1563 gc4663->exposure->step,
1564 gc4663->exposure->default_value);
1565 break;
1566 }
1567
1568 if (!pm_runtime_get_if_in_use(&client->dev))
1569 return 0;
1570
1571 switch (ctrl->id) {
1572 case V4L2_CID_EXPOSURE:
1573 /* 4 least significant bits of expsoure are fractional part */
1574 ret = gc4663_write_reg(gc4663->client, GC4663_REG_EXPOSURE_H,
1575 GC4663_REG_VALUE_08BIT,
1576 ctrl->val >> 8);
1577 ret |= gc4663_write_reg(gc4663->client, GC4663_REG_EXPOSURE_L,
1578 GC4663_REG_VALUE_08BIT,
1579 ctrl->val & 0xfe);
1580 break;
1581 case V4L2_CID_ANALOGUE_GAIN:
1582 ret = gc4663_set_gain_reg(gc4663, ctrl->val);
1583 break;
1584 case V4L2_CID_VBLANK:
1585 gc4663->cur_vts = ctrl->val + gc4663->cur_mode->height;
1586 ret = gc4663_write_reg(gc4663->client, GC4663_REG_VTS_H,
1587 GC4663_REG_VALUE_08BIT,
1588 gc4663->cur_vts >> 8);
1589 ret |= gc4663_write_reg(gc4663->client, GC4663_REG_VTS_L,
1590 GC4663_REG_VALUE_08BIT,
1591 gc4663->cur_vts & 0xff);
1592 break;
1593 case V4L2_CID_TEST_PATTERN:
1594 ret = gc4663_enable_test_pattern(gc4663, ctrl->val);
1595 break;
1596 case V4L2_CID_HFLIP:
1597 ret = gc4663_read_reg(gc4663->client, GC4663_FLIP_MIRROR_REG,
1598 GC4663_REG_VALUE_08BIT, &val);
1599 if (ctrl->val)
1600 val |= GC4663_MIRROR_BIT_MASK;
1601 else
1602 val &= ~GC4663_MIRROR_BIT_MASK;
1603 ret |= gc4663_write_reg(gc4663->client, GC4663_FLIP_MIRROR_REG,
1604 GC4663_REG_VALUE_08BIT, val);
1605 break;
1606 case V4L2_CID_VFLIP:
1607 ret = gc4663_read_reg(gc4663->client, GC4663_FLIP_MIRROR_REG,
1608 GC4663_REG_VALUE_08BIT, &val);
1609 if (ctrl->val)
1610 val |= GC4663_FLIP_BIT_MASK;
1611 else
1612 val &= ~GC4663_FLIP_BIT_MASK;
1613 ret |= gc4663_write_reg(gc4663->client, GC4663_FLIP_MIRROR_REG,
1614 GC4663_REG_VALUE_08BIT, val);
1615 break;
1616 default:
1617 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1618 __func__, ctrl->id, ctrl->val);
1619 break;
1620 }
1621
1622 pm_runtime_put(&client->dev);
1623
1624 return ret;
1625 }
1626
1627 static const struct v4l2_ctrl_ops gc4663_ctrl_ops = {
1628 .s_ctrl = gc4663_set_ctrl,
1629 };
1630
gc4663_initialize_controls(struct gc4663 * gc4663)1631 static int gc4663_initialize_controls(struct gc4663 *gc4663)
1632 {
1633 const struct gc4663_mode *mode;
1634 struct v4l2_ctrl_handler *handler;
1635 s64 exposure_max, vblank_def;
1636 u32 h_blank;
1637 int ret;
1638
1639 handler = &gc4663->ctrl_handler;
1640 mode = gc4663->cur_mode;
1641 ret = v4l2_ctrl_handler_init(handler, 9);
1642 if (ret)
1643 return ret;
1644 handler->lock = &gc4663->mutex;
1645
1646 gc4663->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1647 1, 0, link_freq_menu_items);
1648 if (mode->hdr_mode == HDR_X2) {
1649 gc4663->cur_link_freq = 1;
1650 gc4663->cur_pixel_rate = GC4663_PIXEL_RATE_HDR;
1651 } else {
1652 gc4663->cur_link_freq = 0;
1653 gc4663->cur_pixel_rate = GC4663_PIXEL_RATE_LINEAR;
1654 }
1655
1656 __v4l2_ctrl_s_ctrl(gc4663->link_freq,
1657 gc4663->cur_link_freq);
1658
1659 gc4663->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1660 0, GC4663_PIXEL_RATE_HDR, 1, GC4663_PIXEL_RATE_HDR);
1661
1662 h_blank = mode->hts_def - mode->width;
1663 gc4663->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1664 h_blank, h_blank, 1, h_blank);
1665 if (gc4663->hblank)
1666 gc4663->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1667
1668 vblank_def = mode->vts_def - mode->height;
1669 gc4663->cur_vts = mode->vts_def;
1670 gc4663->vblank = v4l2_ctrl_new_std(handler, &gc4663_ctrl_ops,
1671 V4L2_CID_VBLANK, vblank_def,
1672 GC4663_VTS_MAX - mode->height,
1673 1, vblank_def);
1674
1675 exposure_max = mode->vts_def - 4;
1676 gc4663->exposure = v4l2_ctrl_new_std(handler, &gc4663_ctrl_ops,
1677 V4L2_CID_EXPOSURE,
1678 GC4663_EXPOSURE_MIN,
1679 exposure_max,
1680 GC4663_EXPOSURE_STEP,
1681 mode->exp_def);
1682
1683 gc4663->anal_gain = v4l2_ctrl_new_std(handler, &gc4663_ctrl_ops,
1684 V4L2_CID_ANALOGUE_GAIN,
1685 GC4663_GAIN_MIN,
1686 GC4663_GAIN_MAX,
1687 GC4663_GAIN_STEP,
1688 GC4663_GAIN_DEFAULT);
1689
1690 gc4663->test_pattern =
1691 v4l2_ctrl_new_std_menu_items(handler,
1692 &gc4663_ctrl_ops,
1693 V4L2_CID_TEST_PATTERN,
1694 ARRAY_SIZE(gc4663_test_pattern_menu) - 1,
1695 0, 0, gc4663_test_pattern_menu);
1696
1697 gc4663->h_flip = v4l2_ctrl_new_std(handler, &gc4663_ctrl_ops,
1698 V4L2_CID_HFLIP, 0, 1, 1, 0);
1699
1700 gc4663->v_flip = v4l2_ctrl_new_std(handler, &gc4663_ctrl_ops,
1701 V4L2_CID_VFLIP, 0, 1, 1, 0);
1702 if (handler->error) {
1703 ret = handler->error;
1704 dev_err(&gc4663->client->dev,
1705 "Failed to init controls(%d)\n", ret);
1706 goto err_free_handler;
1707 }
1708
1709 gc4663->subdev.ctrl_handler = handler;
1710 gc4663->has_init_exp = false;
1711
1712 return 0;
1713
1714 err_free_handler:
1715 v4l2_ctrl_handler_free(handler);
1716
1717 return ret;
1718 }
1719
gc4663_check_sensor_id(struct gc4663 * gc4663,struct i2c_client * client)1720 static int gc4663_check_sensor_id(struct gc4663 *gc4663,
1721 struct i2c_client *client)
1722 {
1723 struct device *dev = &gc4663->client->dev;
1724 u16 id = 0;
1725 u32 reg_H = 0;
1726 u32 reg_L = 0;
1727 int ret;
1728
1729 ret = gc4663_read_reg(client, GC4663_REG_CHIP_ID_H,
1730 GC4663_REG_VALUE_08BIT, ®_H);
1731 ret |= gc4663_read_reg(client, GC4663_REG_CHIP_ID_L,
1732 GC4663_REG_VALUE_08BIT, ®_L);
1733
1734 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
1735 if (!(reg_H == (CHIP_ID >> 8) || reg_L == (CHIP_ID & 0xff))) {
1736 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1737 return -ENODEV;
1738 }
1739 dev_info(dev, "detected gc%04x sensor\n", id);
1740 return 0;
1741 }
1742
gc4663_configure_regulators(struct gc4663 * gc4663)1743 static int gc4663_configure_regulators(struct gc4663 *gc4663)
1744 {
1745 unsigned int i;
1746
1747 for (i = 0; i < GC4663_NUM_SUPPLIES; i++)
1748 gc4663->supplies[i].supply = gc4663_supply_names[i];
1749
1750 return devm_regulator_bulk_get(&gc4663->client->dev,
1751 GC4663_NUM_SUPPLIES,
1752 gc4663->supplies);
1753 }
1754
gc4663_probe(struct i2c_client * client,const struct i2c_device_id * id)1755 static int gc4663_probe(struct i2c_client *client,
1756 const struct i2c_device_id *id)
1757 {
1758 struct device *dev = &client->dev;
1759 struct device_node *node = dev->of_node;
1760 struct gc4663 *gc4663;
1761 struct v4l2_subdev *sd;
1762 char facing[2];
1763 int ret;
1764 u32 i, hdr_mode = 0;
1765
1766 dev_info(dev, "driver version: %02x.%02x.%02x",
1767 DRIVER_VERSION >> 16,
1768 (DRIVER_VERSION & 0xff00) >> 8,
1769 DRIVER_VERSION & 0x00ff);
1770
1771 gc4663 = devm_kzalloc(dev, sizeof(*gc4663), GFP_KERNEL);
1772 if (!gc4663)
1773 return -ENOMEM;
1774
1775 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1776 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1777 &gc4663->module_index);
1778 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1779 &gc4663->module_facing);
1780 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1781 &gc4663->module_name);
1782 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1783 &gc4663->len_name);
1784 if (ret) {
1785 dev_err(dev, "could not get module information!\n");
1786 return -EINVAL;
1787 }
1788
1789 gc4663->client = client;
1790 gc4663->cfg_num = ARRAY_SIZE(supported_modes);
1791 for (i = 0; i < gc4663->cfg_num; i++) {
1792 if (hdr_mode == supported_modes[i].hdr_mode) {
1793 gc4663->cur_mode = &supported_modes[i];
1794 break;
1795 }
1796 }
1797 if (i == gc4663->cfg_num)
1798 gc4663->cur_mode = &supported_modes[0];
1799
1800 gc4663->xvclk = devm_clk_get(dev, "xvclk");
1801 if (IS_ERR(gc4663->xvclk)) {
1802 dev_err(dev, "Failed to get xvclk\n");
1803 return -EINVAL;
1804 }
1805
1806 gc4663->pwren_gpio = devm_gpiod_get(dev, "pwren", GPIOD_OUT_LOW);
1807 if (IS_ERR(gc4663->pwren_gpio))
1808 dev_warn(dev, "Failed to get pwren-gpios\n");
1809
1810 gc4663->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1811 if (IS_ERR(gc4663->reset_gpio))
1812 dev_warn(dev, "Failed to get reset-gpios\n");
1813
1814 gc4663->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1815 if (IS_ERR(gc4663->pwdn_gpio))
1816 dev_warn(dev, "Failed to get pwdn-gpios\n");
1817
1818 gc4663->pinctrl = devm_pinctrl_get(dev);
1819 if (!IS_ERR(gc4663->pinctrl)) {
1820 gc4663->pins_default =
1821 pinctrl_lookup_state(gc4663->pinctrl,
1822 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1823 if (IS_ERR(gc4663->pins_default))
1824 dev_err(dev, "could not get default pinstate\n");
1825
1826 gc4663->pins_sleep =
1827 pinctrl_lookup_state(gc4663->pinctrl,
1828 OF_CAMERA_PINCTRL_STATE_SLEEP);
1829 if (IS_ERR(gc4663->pins_sleep))
1830 dev_err(dev, "could not get sleep pinstate\n");
1831 } else {
1832 dev_err(dev, "no pinctrl\n");
1833 }
1834
1835 ret = gc4663_configure_regulators(gc4663);
1836 if (ret) {
1837 dev_err(dev, "Failed to get power regulators\n");
1838 return ret;
1839 }
1840
1841 mutex_init(&gc4663->mutex);
1842
1843 sd = &gc4663->subdev;
1844 v4l2_i2c_subdev_init(sd, client, &gc4663_subdev_ops);
1845 ret = gc4663_initialize_controls(gc4663);
1846 if (ret)
1847 goto err_destroy_mutex;
1848
1849 ret = __gc4663_power_on(gc4663);
1850 if (ret)
1851 goto err_free_handler;
1852
1853 usleep_range(3000, 4000);
1854
1855 ret = gc4663_check_sensor_id(gc4663, client);
1856 if (ret)
1857 goto err_power_off;
1858
1859 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1860 sd->internal_ops = &gc4663_internal_ops;
1861 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1862 V4L2_SUBDEV_FL_HAS_EVENTS;
1863 #endif
1864 #if defined(CONFIG_MEDIA_CONTROLLER)
1865 gc4663->pad.flags = MEDIA_PAD_FL_SOURCE;
1866 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1867 ret = media_entity_pads_init(&sd->entity, 1, &gc4663->pad);
1868 if (ret < 0)
1869 goto err_power_off;
1870 #endif
1871
1872 memset(facing, 0, sizeof(facing));
1873 if (strcmp(gc4663->module_facing, "back") == 0)
1874 facing[0] = 'b';
1875 else
1876 facing[0] = 'f';
1877
1878 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1879 gc4663->module_index, facing,
1880 GC4663_NAME, dev_name(sd->dev));
1881 ret = v4l2_async_register_subdev_sensor_common(sd);
1882 if (ret) {
1883 dev_err(dev, "v4l2 async register subdev failed\n");
1884 goto err_clean_entity;
1885 }
1886
1887 pm_runtime_set_active(dev);
1888 pm_runtime_enable(dev);
1889 pm_runtime_idle(dev);
1890
1891 return 0;
1892
1893 err_clean_entity:
1894 #if defined(CONFIG_MEDIA_CONTROLLER)
1895 media_entity_cleanup(&sd->entity);
1896 #endif
1897 err_power_off:
1898 __gc4663_power_off(gc4663);
1899 err_free_handler:
1900 v4l2_ctrl_handler_free(&gc4663->ctrl_handler);
1901 err_destroy_mutex:
1902 mutex_destroy(&gc4663->mutex);
1903
1904 return ret;
1905 }
1906
gc4663_remove(struct i2c_client * client)1907 static int gc4663_remove(struct i2c_client *client)
1908 {
1909 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1910 struct gc4663 *gc4663 = to_gc4663(sd);
1911
1912 v4l2_async_unregister_subdev(sd);
1913 #if defined(CONFIG_MEDIA_CONTROLLER)
1914 media_entity_cleanup(&sd->entity);
1915 #endif
1916 v4l2_ctrl_handler_free(&gc4663->ctrl_handler);
1917 mutex_destroy(&gc4663->mutex);
1918
1919 pm_runtime_disable(&client->dev);
1920 if (!pm_runtime_status_suspended(&client->dev))
1921 __gc4663_power_off(gc4663);
1922 pm_runtime_set_suspended(&client->dev);
1923
1924 return 0;
1925 }
1926
1927 #if IS_ENABLED(CONFIG_OF)
1928 static const struct of_device_id gc4663_of_match[] = {
1929 { .compatible = "galaxycore,gc4663" },
1930 {},
1931 };
1932 MODULE_DEVICE_TABLE(of, gc4663_of_match);
1933 #endif
1934
1935 static const struct i2c_device_id gc4663_match_id[] = {
1936 { "galaxycore,gc4663", 0 },
1937 { },
1938 };
1939
1940 static struct i2c_driver gc4663_i2c_driver = {
1941 .driver = {
1942 .name = GC4663_NAME,
1943 .pm = &gc4663_pm_ops,
1944 .of_match_table = of_match_ptr(gc4663_of_match),
1945 },
1946 .probe = &gc4663_probe,
1947 .remove = &gc4663_remove,
1948 .id_table = gc4663_match_id,
1949 };
1950
sensor_mod_init(void)1951 static int __init sensor_mod_init(void)
1952 {
1953 return i2c_add_driver(&gc4663_i2c_driver);
1954 }
1955
sensor_mod_exit(void)1956 static void __exit sensor_mod_exit(void)
1957 {
1958 i2c_del_driver(&gc4663_i2c_driver);
1959 }
1960
1961 device_initcall_sync(sensor_mod_init);
1962 module_exit(sensor_mod_exit);
1963
1964 MODULE_DESCRIPTION("galaxycore gc4663 sensor driver");
1965 MODULE_LICENSE("GPL v2");
1966