1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * GC4653 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 fix gain range.
10 * V0.0X01.0X04 add enum_frame_interval function.
11 * V0.0X01.0X05 support enum sensor fmt
12 * V0.0X01.0X06 support mirror and flip
13 * V0.0X01.0X07 add quick stream on/off
14 */
15
16 #include <linux/clk.h>
17 #include <linux/device.h>
18 #include <linux/delay.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/i2c.h>
21 #include <linux/module.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/sysfs.h>
25 #include <linux/slab.h>
26 #include <linux/version.h>
27 #include <linux/rk-camera-module.h>
28 #include <linux/rk-preisp.h>
29 #include <media/media-entity.h>
30 #include <media/v4l2-async.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-subdev.h>
33 #include <linux/pinctrl/consumer.h>
34
35 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x07)
36
37 #ifndef V4L2_CID_DIGITAL_GAIN
38 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
39 #endif
40
41 #define GC4653_LANES 2
42 #define GC4653_BITS_PER_SAMPLE 10
43 #define GC4653_LINK_FREQ_LINEAR 324000000 //2560*1440
44
45 #define GC4653_PIXEL_RATE_LINEAR (GC4653_LINK_FREQ_LINEAR * 2 / 10 * 2)
46
47 #define GC4653_XVCLK_FREQ 24000000
48
49 #define CHIP_ID 0x4653
50 #define GC4653_REG_CHIP_ID_H 0x03f0
51 #define GC4653_REG_CHIP_ID_L 0x03f1
52
53 #define GC4653_REG_CTRL_MODE 0x0100
54 #define GC4653_MODE_SW_STANDBY 0x00
55 #define GC4653_MODE_STREAMING 0x09
56
57 #define GC4653_REG_EXPOSURE_H 0x0202
58 #define GC4653_REG_EXPOSURE_L 0x0203
59 #define GC4653_EXPOSURE_MIN 4
60 #define GC4653_EXPOSURE_STEP 1
61 #define GC4653_VTS_MAX 0x7fff
62
63 #define GC4653_GAIN_MIN 64
64 #define GC4653_GAIN_MAX 0xffff
65 #define GC4653_GAIN_STEP 1
66 #define GC4653_GAIN_DEFAULT 256
67
68 #define GC4653_REG_TEST_PATTERN 0x008c
69 #define GC4653_TEST_PATTERN_ENABLE 0x11
70 #define GC4653_TEST_PATTERN_DISABLE 0x0
71
72 #define GC4653_REG_VTS_H 0x0340
73 #define GC4653_REG_VTS_L 0x0341
74
75 #define GC4653_FLIP_MIRROR_REG 0x0101
76 #define GC4653_MIRROR_BIT_MASK BIT(0)
77 #define GC4653_FLIP_BIT_MASK BIT(1)
78
79 #define GC4653_FRAME_BUFFER_REG 0x031d
80 #define GC4653_FRAME_BUFFER_START 0x2d
81 #define GC4653_FRAME_BUFFER_END 0x28
82
83 #define REG_NULL 0xFFFF
84
85 #define GC4653_REG_VALUE_08BIT 1
86 #define GC4653_REG_VALUE_16BIT 2
87 #define GC4653_REG_VALUE_24BIT 3
88
89 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
90 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
91 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
92 #define GC4653_NAME "gc4653"
93
94 static const char * const gc4653_supply_names[] = {
95 "dovdd", /* Digital I/O power */
96 "dvdd", /* Digital core power */
97 "avdd", /* Analog power */
98 };
99
100 #define GC4653_NUM_SUPPLIES ARRAY_SIZE(gc4653_supply_names)
101
102 struct regval {
103 u16 addr;
104 u8 val;
105 };
106
107 struct gc4653_mode {
108 u32 bus_fmt;
109 u32 width;
110 u32 height;
111 struct v4l2_fract max_fps;
112 u32 hts_def;
113 u32 vts_def;
114 u32 exp_def;
115 const struct regval *reg_list;
116 u32 hdr_mode;
117 u32 vc[PAD_MAX];
118 };
119
120 struct gc4653 {
121 struct i2c_client *client;
122 struct clk *xvclk;
123 struct gpio_desc *reset_gpio;
124 struct gpio_desc *pwdn_gpio;
125 struct gpio_desc *pwren_gpio;
126 struct regulator_bulk_data supplies[GC4653_NUM_SUPPLIES];
127
128 struct pinctrl *pinctrl;
129 struct pinctrl_state *pins_default;
130 struct pinctrl_state *pins_sleep;
131
132 struct v4l2_subdev subdev;
133 struct media_pad pad;
134 struct v4l2_ctrl_handler ctrl_handler;
135 struct v4l2_ctrl *exposure;
136 struct v4l2_ctrl *anal_gain;
137 struct v4l2_ctrl *digi_gain;
138 struct v4l2_ctrl *hblank;
139 struct v4l2_ctrl *vblank;
140 struct v4l2_ctrl *pixel_rate;
141 struct v4l2_ctrl *link_freq;
142 struct v4l2_ctrl *h_flip;
143 struct v4l2_ctrl *v_flip;
144 struct v4l2_ctrl *test_pattern;
145 struct mutex mutex;
146 bool streaming;
147 bool power_on;
148 const struct gc4653_mode *cur_mode;
149 u32 cfg_num;
150 u32 module_index;
151 u32 cur_vts;
152 u32 cur_pixel_rate;
153 u32 cur_link_freq;
154 struct preisp_hdrae_exp_s init_hdrae_exp;
155 const char *module_facing;
156 const char *module_name;
157 const char *len_name;
158 bool has_init_exp;
159 };
160
161 #define to_gc4653(sd) container_of(sd, struct gc4653, subdev)
162
163 /*
164 * Xclk 24Mhz
165 */
166 static const struct regval gc4653_global_regs[] = {
167 {REG_NULL, 0x00},
168 };
169
170 static const u32 reg_val_table_liner[21][7] = {
171 //2b3 2b4 2b8 2b9 515 519 2d9
172 {0x00, 0x00, 0x01, 0x00, 0x30, 0x1e, 0x5C},
173 {0x20, 0x00, 0x01, 0x0B, 0x30, 0x1e, 0x5C},
174 {0x01, 0x00, 0x01, 0x19, 0x30, 0x1d, 0x5B},
175 {0x21, 0x00, 0x01, 0x2A, 0x30, 0x1e, 0x5C},
176 {0x02, 0x00, 0x02, 0x00, 0x30, 0x1e, 0x5C},
177 {0x22, 0x00, 0x02, 0x17, 0x30, 0x1d, 0x5B},
178 {0x03, 0x00, 0x02, 0x33, 0x20, 0x16, 0x54},
179 {0x23, 0x00, 0x03, 0x14, 0x20, 0x17, 0x55},
180 {0x04, 0x00, 0x04, 0x00, 0x20, 0x17, 0x55},
181 {0x24, 0x00, 0x04, 0x2F, 0x20, 0x19, 0x57},
182 {0x05, 0x00, 0x05, 0x26, 0x20, 0x19, 0x57},
183 {0x25, 0x00, 0x06, 0x28, 0x20, 0x1b, 0x59},
184 {0x0c, 0x00, 0x08, 0x00, 0x20, 0x1d, 0x5B},
185 {0x2C, 0x00, 0x09, 0x1E, 0x20, 0x1f, 0x5D},
186 {0x0D, 0x00, 0x0B, 0x0C, 0x20, 0x21, 0x5F},
187 {0x2D, 0x00, 0x0D, 0x11, 0x20, 0x24, 0x62},
188 {0x1C, 0x00, 0x10, 0x00, 0x20, 0x26, 0x64},
189 {0x3C, 0x00, 0x12, 0x3D, 0x18, 0x2a, 0x68},
190 {0x5C, 0x00, 0x16, 0x19, 0x18, 0x2c, 0x6A},
191 {0x7C, 0x00, 0x1A, 0x22, 0x18, 0x2e, 0x6C},
192 {0x9C, 0x00, 0x20, 0x00, 0x18, 0x32, 0x70},
193 };
194
195 static const u32 gain_level_table[22] = {
196 64,
197 75,
198 89,
199 106,
200 128,
201 151,
202 179,
203 212,
204 256,
205 303,
206 358,
207 424,
208 512,
209 606,
210 716,
211 849,
212 1024,
213 1213,
214 1433,
215 1698,
216 2048,
217 0xffffffff,
218 };
219
220 /*
221 * Xclk 24Mhz
222 * max_framerate 30fps
223 * mipi_datarate per lane 648Mbps, 2lane
224 */
225 static const struct regval gc4653_linear10bit_2560x1440_regs[] = {
226 {0x03fe, 0xf0},
227 {0x03fe, 0x00},
228 {0x0317, 0x00},
229 {0x0320, 0x77},
230 {0x0324, 0xc8},
231 {0x0325, 0x06},
232 {0x0326, 0x6c},
233 {0x0327, 0x03},
234 {0x0334, 0x40},
235 {0x0336, 0x6c},
236 {0x0337, 0x82},
237 {0x0315, 0x25},
238 {0x031c, 0xc6},
239 {0x0287, 0x18},
240 {0x0084, 0x00},
241 {0x0087, 0x50},
242 {0x029d, 0x08},
243 {0x0290, 0x00},
244 {0x0340, 0x05},
245 {0x0341, 0xdc},
246 {0x0345, 0x06},
247 {0x034b, 0xb0},
248 {0x0352, 0x08},
249 {0x0354, 0x08},
250 {0x02d1, 0xe0},
251 {0x0223, 0xf2},
252 {0x0238, 0xa4},
253 {0x02ce, 0x7f},
254 {0x0232, 0xc4},
255 {0x02d3, 0x05},
256 {0x0243, 0x06},
257 {0x02ee, 0x30},
258 {0x026f, 0x70},
259 {0x0257, 0x09},
260 {0x0211, 0x02},
261 {0x0219, 0x09},
262 {0x023f, 0x2d},
263 {0x0518, 0x00},
264 {0x0519, 0x01},
265 {0x0515, 0x08},
266 {0x02d9, 0x3f},
267 {0x02da, 0x02},
268 {0x02db, 0xe8},
269 {0x02e6, 0x20},
270 {0x021b, 0x10},
271 {0x0252, 0x22},
272 {0x024e, 0x22},
273 {0x02c4, 0x01},
274 {0x021d, 0x17},
275 {0x024a, 0x01},
276 {0x02ca, 0x02},
277 {0x0262, 0x10},
278 {0x029a, 0x20},
279 {0x021c, 0x0e},
280 {0x0298, 0x03},
281 {0x029c, 0x00},
282 {0x027e, 0x14},
283 {0x02c2, 0x10},
284 {0x0540, 0x20},
285 {0x0546, 0x01},
286 {0x0548, 0x01},
287 {0x0544, 0x01},
288 {0x0242, 0x1b},
289 {0x02c0, 0x1b},
290 {0x02c3, 0x20},
291 {0x02e4, 0x10},
292 {0x022e, 0x00},
293 {0x027b, 0x3f},
294 {0x0269, 0x0f},
295 {0x02d2, 0x40},
296 {0x027c, 0x08},
297 {0x023a, 0x2e},
298 {0x0245, 0xce},
299 {0x0530, 0x20},
300 {0x0531, 0x02},
301 {0x0228, 0x50},
302 {0x02ab, 0x00},
303 {0x0250, 0x00},
304 {0x0221, 0x50},
305 {0x02ac, 0x00},
306 {0x02a5, 0x02},
307 {0x0260, 0x0b},
308 {0x0216, 0x04},
309 {0x0299, 0x1C},
310 {0x02bb, 0x0d},
311 {0x02a3, 0x02},
312 {0x02a4, 0x02},
313 {0x021e, 0x02},
314 {0x024f, 0x08},
315 {0x028c, 0x08},
316 {0x0532, 0x3f},
317 {0x0533, 0x02},
318 {0x0277, 0xc0},
319 {0x0276, 0xc0},
320 {0x0239, 0xc0},
321 {0x0202, 0x05},
322 {0x0203, 0xd0},
323 {0x0205, 0xc0},
324 {0x02b0, 0x68},
325 {0x0002, 0xa9},
326 {0x0004, 0x01},
327 {0x021a, 0x98},
328 {0x0266, 0xa0},
329 {0x0020, 0x01},
330 {0x0021, 0x03},
331 {0x0022, 0x00},
332 {0x0023, 0x04},
333 {0x0342, 0x06},
334 {0x0343, 0x40},
335 {0x03fe, 0x10},
336 {0x03fe, 0x00},
337 {0x0106, 0x78},
338 {0x0108, 0x0c},
339 {0x0114, 0x01},
340 {0x0115, 0x12},
341 {0x0180, 0x46},
342 {0x0181, 0x30},
343 {0x0182, 0x05},
344 {0x0185, 0x01},
345 {0x03fe, 0x10},
346 {0x03fe, 0x00},
347 {0x000f, 0x00},
348 {REG_NULL, 0x00},
349 };
350
351 static const struct regval gc4653_otp_regs[] = {
352 {0x0080, 0x02},
353 {0x0097, 0x0a},
354 {0x0098, 0x10},
355 {0x0099, 0x05},
356 {0x009a, 0xb0},
357 {0x0317, 0x08},
358 {0x0a67, 0x80},
359 {0x0a70, 0x03},
360 {0x0a82, 0x00},
361 {0x0a83, 0x10},
362 {0x0a80, 0x2b},
363 {0x05be, 0x00},
364 {0x05a9, 0x01},
365 {0x0313, 0x80},
366 {0x05be, 0x01},
367 {0x0317, 0x00},
368 {0x0a67, 0x00},
369 {REG_NULL, 0x00},
370 };
371
372 static const struct gc4653_mode supported_modes[] = {
373 {
374 .width = 2560,
375 .height = 1440,
376 .max_fps = {
377 .numerator = 10000,
378 .denominator = 300000,
379 },
380 .exp_def = 0x0100,
381 .hts_def = 0x12C0,
382 .vts_def = 0x05DC,
383 .bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
384 .reg_list = gc4653_linear10bit_2560x1440_regs,
385 .hdr_mode = NO_HDR,
386 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
387 },
388 };
389
390 static const s64 link_freq_menu_items[] = {
391 GC4653_LINK_FREQ_LINEAR,
392 };
393
394 static const char * const gc4653_test_pattern_menu[] = {
395 "Disabled",
396 "Vertical Color Bar Type 1",
397 "Vertical Color Bar Type 2",
398 "Vertical Color Bar Type 3",
399 "Vertical Color Bar Type 4"
400 };
401
402 /* Write registers up to 4 at a time */
gc4653_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)403 static int gc4653_write_reg(struct i2c_client *client, u16 reg,
404 u32 len, u32 val)
405 {
406 u32 buf_i, val_i;
407 u8 buf[6];
408 u8 *val_p;
409 __be32 val_be;
410
411 if (len > 4)
412 return -EINVAL;
413
414 buf[0] = reg >> 8;
415 buf[1] = reg & 0xff;
416
417 val_be = cpu_to_be32(val);
418 val_p = (u8 *)&val_be;
419 buf_i = 2;
420 val_i = 4 - len;
421
422 while (val_i < 4)
423 buf[buf_i++] = val_p[val_i++];
424
425 if (i2c_master_send(client, buf, len + 2) != len + 2)
426 return -EIO;
427
428 return 0;
429 }
430
gc4653_write_array(struct i2c_client * client,const struct regval * regs)431 static int gc4653_write_array(struct i2c_client *client,
432 const struct regval *regs)
433 {
434 u32 i;
435 int ret = 0;
436
437 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
438 ret = gc4653_write_reg(client, regs[i].addr,
439 GC4653_REG_VALUE_08BIT, regs[i].val);
440
441 return ret;
442 }
443
444 /* Read registers up to 4 at a time */
gc4653_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)445 static int gc4653_read_reg(struct i2c_client *client, u16 reg,
446 unsigned int len, u32 *val)
447 {
448 struct i2c_msg msgs[2];
449 u8 *data_be_p;
450 __be32 data_be = 0;
451 __be16 reg_addr_be = cpu_to_be16(reg);
452 int ret;
453
454 if (len > 4 || !len)
455 return -EINVAL;
456
457 data_be_p = (u8 *)&data_be;
458 /* Write register address */
459 msgs[0].addr = client->addr;
460 msgs[0].flags = 0;
461 msgs[0].len = 2;
462 msgs[0].buf = (u8 *)®_addr_be;
463
464 /* Read data from register */
465 msgs[1].addr = client->addr;
466 msgs[1].flags = I2C_M_RD;
467 msgs[1].len = len;
468 msgs[1].buf = &data_be_p[4 - len];
469
470 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
471 if (ret != ARRAY_SIZE(msgs))
472 return -EIO;
473
474 *val = be32_to_cpu(data_be);
475
476 return 0;
477 }
478
gc4653_get_reso_dist(const struct gc4653_mode * mode,struct v4l2_mbus_framefmt * framefmt)479 static int gc4653_get_reso_dist(const struct gc4653_mode *mode,
480 struct v4l2_mbus_framefmt *framefmt)
481 {
482 return abs(mode->width - framefmt->width) +
483 abs(mode->height - framefmt->height);
484 }
485
486 static const struct gc4653_mode *
gc4653_find_best_fit(struct gc4653 * gc4653,struct v4l2_subdev_format * fmt)487 gc4653_find_best_fit(struct gc4653 *gc4653, struct v4l2_subdev_format *fmt)
488 {
489 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
490 int dist;
491 int cur_best_fit = 0;
492 int cur_best_fit_dist = -1;
493 unsigned int i;
494
495 for (i = 0; i < gc4653->cfg_num; i++) {
496 dist = gc4653_get_reso_dist(&supported_modes[i], framefmt);
497 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
498 cur_best_fit_dist = dist;
499 cur_best_fit = i;
500 }
501 }
502
503 return &supported_modes[cur_best_fit];
504 }
505
gc4653_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)506 static int gc4653_set_fmt(struct v4l2_subdev *sd,
507 struct v4l2_subdev_pad_config *cfg,
508 struct v4l2_subdev_format *fmt)
509 {
510 struct gc4653 *gc4653 = to_gc4653(sd);
511 const struct gc4653_mode *mode;
512 s64 h_blank, vblank_def;
513
514 mutex_lock(&gc4653->mutex);
515
516 mode = gc4653_find_best_fit(gc4653, fmt);
517 fmt->format.code = mode->bus_fmt;
518 fmt->format.width = mode->width;
519 fmt->format.height = mode->height;
520 fmt->format.field = V4L2_FIELD_NONE;
521 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
522 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
523 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
524 #else
525 mutex_unlock(&gc4653->mutex);
526 return -ENOTTY;
527 #endif
528 } else {
529 gc4653->cur_mode = mode;
530 h_blank = mode->hts_def - mode->width;
531 __v4l2_ctrl_modify_range(gc4653->hblank, h_blank,
532 h_blank, 1, h_blank);
533 vblank_def = mode->vts_def - mode->height;
534 __v4l2_ctrl_modify_range(gc4653->vblank, vblank_def,
535 GC4653_VTS_MAX - mode->height,
536 1, vblank_def);
537
538 gc4653->cur_link_freq = 0;
539 gc4653->cur_pixel_rate = GC4653_PIXEL_RATE_LINEAR;
540
541 __v4l2_ctrl_s_ctrl_int64(gc4653->pixel_rate,
542 gc4653->cur_pixel_rate);
543 __v4l2_ctrl_s_ctrl(gc4653->link_freq,
544 gc4653->cur_link_freq);
545 gc4653->cur_vts = mode->vts_def;
546 }
547 mutex_unlock(&gc4653->mutex);
548
549 return 0;
550 }
551
gc4653_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)552 static int gc4653_get_fmt(struct v4l2_subdev *sd,
553 struct v4l2_subdev_pad_config *cfg,
554 struct v4l2_subdev_format *fmt)
555 {
556 struct gc4653 *gc4653 = to_gc4653(sd);
557 const struct gc4653_mode *mode = gc4653->cur_mode;
558
559 mutex_lock(&gc4653->mutex);
560 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
561 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
562 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
563 #else
564 mutex_unlock(&gc4653->mutex);
565 return -ENOTTY;
566 #endif
567 } else {
568 fmt->format.width = mode->width;
569 fmt->format.height = mode->height;
570 fmt->format.code = mode->bus_fmt;
571 fmt->format.field = V4L2_FIELD_NONE;
572 }
573 mutex_unlock(&gc4653->mutex);
574
575 return 0;
576 }
577
gc4653_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)578 static int gc4653_enum_mbus_code(struct v4l2_subdev *sd,
579 struct v4l2_subdev_pad_config *cfg,
580 struct v4l2_subdev_mbus_code_enum *code)
581 {
582 struct gc4653 *gc4653 = to_gc4653(sd);
583
584 if (code->index != 0)
585 return -EINVAL;
586 code->code = gc4653->cur_mode->bus_fmt;
587
588 return 0;
589 }
590
gc4653_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)591 static int gc4653_enum_frame_sizes(struct v4l2_subdev *sd,
592 struct v4l2_subdev_pad_config *cfg,
593 struct v4l2_subdev_frame_size_enum *fse)
594 {
595 struct gc4653 *gc4653 = to_gc4653(sd);
596
597 if (fse->index >= gc4653->cfg_num)
598 return -EINVAL;
599
600 if (fse->code != supported_modes[0].bus_fmt)
601 return -EINVAL;
602
603 fse->min_width = supported_modes[fse->index].width;
604 fse->max_width = supported_modes[fse->index].width;
605 fse->max_height = supported_modes[fse->index].height;
606 fse->min_height = supported_modes[fse->index].height;
607
608 return 0;
609 }
610
gc4653_enable_test_pattern(struct gc4653 * gc4653,u32 pattern)611 static int gc4653_enable_test_pattern(struct gc4653 *gc4653, u32 pattern)
612 {
613 u32 val;
614
615 if (pattern)
616 val = GC4653_TEST_PATTERN_ENABLE;
617 else
618 val = GC4653_TEST_PATTERN_DISABLE;
619
620 return gc4653_write_reg(gc4653->client, GC4653_REG_TEST_PATTERN,
621 GC4653_REG_VALUE_08BIT, val);
622 }
623
gc4653_set_gain_reg(struct gc4653 * gc4653,u32 gain)624 static int gc4653_set_gain_reg(struct gc4653 *gc4653, u32 gain)
625 {
626 int i;
627 int total;
628 u32 tol_dig_gain = 0;
629
630 if (gain < 64)
631 gain = 64;
632 total = sizeof(gain_level_table) / sizeof(u32) - 1;
633 for (i = 0; i < total; i++) {
634 if (gain_level_table[i] <= gain &&
635 gain < gain_level_table[i + 1])
636 break;
637 }
638 tol_dig_gain = gain * 64 / gain_level_table[i];
639 if (i >= total)
640 i = total - 1;
641
642 gc4653_write_reg(gc4653->client, 0x2b3,
643 GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][0]);
644 gc4653_write_reg(gc4653->client, 0x2b4,
645 GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][1]);
646 gc4653_write_reg(gc4653->client, 0x2b8,
647 GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][2]);
648 gc4653_write_reg(gc4653->client, 0x2b9,
649 GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][3]);
650 gc4653_write_reg(gc4653->client, 0x515,
651 GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][4]);
652 gc4653_write_reg(gc4653->client, 0x519,
653 GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][5]);
654 gc4653_write_reg(gc4653->client, 0x2d9,
655 GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][6]);
656
657
658 gc4653_write_reg(gc4653->client, 0x20e,
659 GC4653_REG_VALUE_08BIT, (tol_dig_gain >> 6));
660 gc4653_write_reg(gc4653->client, 0x20f,
661 GC4653_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f) << 2));
662 return 0;
663 }
664
gc4653_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)665 static int gc4653_g_frame_interval(struct v4l2_subdev *sd,
666 struct v4l2_subdev_frame_interval *fi)
667 {
668 struct gc4653 *gc4653 = to_gc4653(sd);
669 const struct gc4653_mode *mode = gc4653->cur_mode;
670
671 fi->interval = mode->max_fps;
672
673 return 0;
674 }
675
gc4653_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)676 static int gc4653_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
677 struct v4l2_mbus_config *config)
678 {
679 struct gc4653 *gc4653 = to_gc4653(sd);
680 const struct gc4653_mode *mode = gc4653->cur_mode;
681 u32 val = 0;
682
683 if (mode->hdr_mode == NO_HDR)
684 val = 1 << (GC4653_LANES - 1) |
685 V4L2_MBUS_CSI2_CHANNEL_0 |
686 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
687
688 config->type = V4L2_MBUS_CSI2_DPHY;
689 config->flags = val;
690
691 return 0;
692 }
693
gc4653_get_module_inf(struct gc4653 * gc4653,struct rkmodule_inf * inf)694 static void gc4653_get_module_inf(struct gc4653 *gc4653,
695 struct rkmodule_inf *inf)
696 {
697 memset(inf, 0, sizeof(*inf));
698 strscpy(inf->base.sensor, GC4653_NAME, sizeof(inf->base.sensor));
699 strscpy(inf->base.module, gc4653->module_name,
700 sizeof(inf->base.module));
701 strscpy(inf->base.lens, gc4653->len_name, sizeof(inf->base.lens));
702 }
703
gc4653_get_channel_info(struct gc4653 * gc4653,struct rkmodule_channel_info * ch_info)704 static int gc4653_get_channel_info(struct gc4653 *gc4653, struct rkmodule_channel_info *ch_info)
705 {
706 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
707 return -EINVAL;
708 ch_info->vc = gc4653->cur_mode->vc[ch_info->index];
709 ch_info->width = gc4653->cur_mode->width;
710 ch_info->height = gc4653->cur_mode->height;
711 ch_info->bus_fmt = gc4653->cur_mode->bus_fmt;
712 return 0;
713 }
714
gc4653_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)715 static long gc4653_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
716 {
717 struct gc4653 *gc4653 = to_gc4653(sd);
718 struct rkmodule_hdr_cfg *hdr;
719 u32 i, h, w;
720 long ret = 0;
721 u32 stream = 0;
722 struct rkmodule_channel_info *ch_info;
723
724 switch (cmd) {
725 case RKMODULE_GET_MODULE_INFO:
726 gc4653_get_module_inf(gc4653, (struct rkmodule_inf *)arg);
727 break;
728 case RKMODULE_GET_HDR_CFG:
729 hdr = (struct rkmodule_hdr_cfg *)arg;
730 hdr->esp.mode = HDR_NORMAL_VC;
731 hdr->hdr_mode = gc4653->cur_mode->hdr_mode;
732 break;
733 case RKMODULE_SET_HDR_CFG:
734 hdr = (struct rkmodule_hdr_cfg *)arg;
735 w = gc4653->cur_mode->width;
736 h = gc4653->cur_mode->height;
737 for (i = 0; i < gc4653->cfg_num; i++) {
738 if (w == supported_modes[i].width &&
739 h == supported_modes[i].height &&
740 supported_modes[i].hdr_mode == hdr->hdr_mode) {
741 gc4653->cur_mode = &supported_modes[i];
742 break;
743 }
744 }
745 if (i == gc4653->cfg_num) {
746 dev_err(&gc4653->client->dev,
747 "not find hdr mode:%d %dx%d config\n",
748 hdr->hdr_mode, w, h);
749 ret = -EINVAL;
750 } else {
751 w = gc4653->cur_mode->hts_def -
752 gc4653->cur_mode->width;
753 h = gc4653->cur_mode->vts_def -
754 gc4653->cur_mode->height;
755 __v4l2_ctrl_modify_range(gc4653->hblank, w, w, 1, w);
756 __v4l2_ctrl_modify_range(gc4653->vblank, h,
757 GC4653_VTS_MAX -
758 gc4653->cur_mode->height,
759 1, h);
760 gc4653->cur_link_freq = 0;
761 gc4653->cur_pixel_rate = GC4653_PIXEL_RATE_LINEAR;
762
763 __v4l2_ctrl_s_ctrl_int64(gc4653->pixel_rate,
764 gc4653->cur_pixel_rate);
765 __v4l2_ctrl_s_ctrl(gc4653->link_freq,
766 gc4653->cur_link_freq);
767 gc4653->cur_vts = gc4653->cur_mode->vts_def;
768 }
769 break;
770 case PREISP_CMD_SET_HDRAE_EXP:
771 break;
772 case RKMODULE_SET_QUICK_STREAM:
773 stream = *((u32 *)arg);
774 if (stream)
775 ret = gc4653_write_reg(gc4653->client, GC4653_REG_CTRL_MODE,
776 GC4653_REG_VALUE_08BIT, GC4653_MODE_STREAMING);
777 else
778 ret = gc4653_write_reg(gc4653->client, GC4653_REG_CTRL_MODE,
779 GC4653_REG_VALUE_08BIT, GC4653_MODE_SW_STANDBY);
780 break;
781 case RKMODULE_GET_CHANNEL_INFO:
782 ch_info = (struct rkmodule_channel_info *)arg;
783 ret = gc4653_get_channel_info(gc4653, ch_info);
784 break;
785 default:
786 ret = -ENOIOCTLCMD;
787 break;
788 }
789
790 return ret;
791 }
792
793 #ifdef CONFIG_COMPAT
gc4653_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)794 static long gc4653_compat_ioctl32(struct v4l2_subdev *sd,
795 unsigned int cmd, unsigned long arg)
796 {
797 void __user *up = compat_ptr(arg);
798 struct rkmodule_inf *inf;
799 struct rkmodule_awb_cfg *cfg;
800 struct rkmodule_hdr_cfg *hdr;
801 struct preisp_hdrae_exp_s *hdrae;
802 long ret;
803 u32 stream = 0;
804 struct rkmodule_channel_info *ch_info;
805
806 switch (cmd) {
807 case RKMODULE_GET_MODULE_INFO:
808 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
809 if (!inf) {
810 ret = -ENOMEM;
811 return ret;
812 }
813
814 ret = gc4653_ioctl(sd, cmd, inf);
815 if (!ret) {
816 ret = copy_to_user(up, inf, sizeof(*inf));
817 if (ret)
818 ret = -EFAULT;
819 }
820 kfree(inf);
821 break;
822 case RKMODULE_AWB_CFG:
823 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
824 if (!cfg) {
825 ret = -ENOMEM;
826 return ret;
827 }
828
829 ret = copy_from_user(cfg, up, sizeof(*cfg));
830 if (!ret)
831 ret = gc4653_ioctl(sd, cmd, cfg);
832 else
833 ret = -EFAULT;
834 kfree(cfg);
835 break;
836 case RKMODULE_GET_HDR_CFG:
837 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
838 if (!hdr) {
839 ret = -ENOMEM;
840 return ret;
841 }
842
843 ret = gc4653_ioctl(sd, cmd, hdr);
844 if (!ret) {
845 ret = copy_to_user(up, hdr, sizeof(*hdr));
846 if (ret)
847 ret = -EFAULT;
848 }
849 kfree(hdr);
850 break;
851 case RKMODULE_SET_HDR_CFG:
852 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
853 if (!hdr) {
854 ret = -ENOMEM;
855 return ret;
856 }
857
858 ret = copy_from_user(hdr, up, sizeof(*hdr));
859 if (!ret)
860 ret = gc4653_ioctl(sd, cmd, hdr);
861 else
862 ret = -EFAULT;
863 kfree(hdr);
864 break;
865 case PREISP_CMD_SET_HDRAE_EXP:
866 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
867 if (!hdrae) {
868 ret = -ENOMEM;
869 return ret;
870 }
871
872 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
873 if (!ret)
874 ret = gc4653_ioctl(sd, cmd, hdrae);
875 else
876 ret = -EFAULT;
877 kfree(hdrae);
878 break;
879 case RKMODULE_SET_QUICK_STREAM:
880 ret = copy_from_user(&stream, up, sizeof(u32));
881 if (!ret)
882 ret = gc4653_ioctl(sd, cmd, &stream);
883 else
884 ret = -EFAULT;
885 break;
886 case RKMODULE_GET_CHANNEL_INFO:
887 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
888 if (!ch_info) {
889 ret = -ENOMEM;
890 return ret;
891 }
892
893 ret = gc4653_ioctl(sd, cmd, ch_info);
894 if (!ret) {
895 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
896 if (ret)
897 ret = -EFAULT;
898 }
899 kfree(ch_info);
900 break;
901 default:
902 ret = -ENOIOCTLCMD;
903 break;
904 }
905
906 return ret;
907 }
908 #endif
909
__gc4653_start_stream(struct gc4653 * gc4653)910 static int __gc4653_start_stream(struct gc4653 *gc4653)
911 {
912 int ret;
913
914 ret = gc4653_write_array(gc4653->client, gc4653->cur_mode->reg_list);
915 if (ret)
916 return ret;
917
918 /* In case these controls are set before streaming */
919 ret = __v4l2_ctrl_handler_setup(&gc4653->ctrl_handler);
920 if (gc4653->has_init_exp && gc4653->cur_mode->hdr_mode != NO_HDR) {
921 ret = gc4653_ioctl(&gc4653->subdev, PREISP_CMD_SET_HDRAE_EXP,
922 &gc4653->init_hdrae_exp);
923 if (ret) {
924 dev_err(&gc4653->client->dev,
925 "init exp fail in hdr mode\n");
926 return ret;
927 }
928 }
929 if (ret)
930 return ret;
931
932 ret |= gc4653_write_reg(gc4653->client, GC4653_REG_CTRL_MODE,
933 GC4653_REG_VALUE_08BIT, GC4653_MODE_STREAMING);
934 if (gc4653->cur_mode->hdr_mode == NO_HDR)
935 ret |= gc4653_write_array(gc4653->client, gc4653_otp_regs);
936 return ret;
937 }
938
__gc4653_stop_stream(struct gc4653 * gc4653)939 static int __gc4653_stop_stream(struct gc4653 *gc4653)
940 {
941 gc4653->has_init_exp = false;
942 return gc4653_write_reg(gc4653->client, GC4653_REG_CTRL_MODE,
943 GC4653_REG_VALUE_08BIT, GC4653_MODE_SW_STANDBY);
944 }
945
gc4653_s_stream(struct v4l2_subdev * sd,int on)946 static int gc4653_s_stream(struct v4l2_subdev *sd, int on)
947 {
948 struct gc4653 *gc4653 = to_gc4653(sd);
949 struct i2c_client *client = gc4653->client;
950 int ret = 0;
951
952 mutex_lock(&gc4653->mutex);
953 on = !!on;
954 if (on == gc4653->streaming)
955 goto unlock_and_return;
956
957 if (on) {
958 ret = pm_runtime_get_sync(&client->dev);
959 if (ret < 0) {
960 pm_runtime_put_noidle(&client->dev);
961 goto unlock_and_return;
962 }
963
964 ret = __gc4653_start_stream(gc4653);
965 if (ret) {
966 v4l2_err(sd, "start stream failed while write regs\n");
967 pm_runtime_put(&client->dev);
968 goto unlock_and_return;
969 }
970 } else {
971 __gc4653_stop_stream(gc4653);
972 pm_runtime_put(&client->dev);
973 }
974
975 gc4653->streaming = on;
976
977 unlock_and_return:
978 mutex_unlock(&gc4653->mutex);
979
980 return ret;
981 }
982
gc4653_s_power(struct v4l2_subdev * sd,int on)983 static int gc4653_s_power(struct v4l2_subdev *sd, int on)
984 {
985 struct gc4653 *gc4653 = to_gc4653(sd);
986 struct i2c_client *client = gc4653->client;
987 int ret = 0;
988
989 mutex_lock(&gc4653->mutex);
990
991 /* If the power state is not modified - no work to do. */
992 if (gc4653->power_on == !!on)
993 goto unlock_and_return;
994
995 if (on) {
996 ret = pm_runtime_get_sync(&client->dev);
997 if (ret < 0) {
998 pm_runtime_put_noidle(&client->dev);
999 goto unlock_and_return;
1000 }
1001
1002 ret = gc4653_write_array(gc4653->client, gc4653_global_regs);
1003 if (ret) {
1004 v4l2_err(sd, "could not set init registers\n");
1005 pm_runtime_put_noidle(&client->dev);
1006 goto unlock_and_return;
1007 }
1008
1009 gc4653->power_on = true;
1010 } else {
1011 pm_runtime_put(&client->dev);
1012 gc4653->power_on = false;
1013 }
1014
1015 unlock_and_return:
1016 mutex_unlock(&gc4653->mutex);
1017
1018 return ret;
1019 }
1020
1021 /* Calculate the delay in us by clock rate and clock cycles */
gc4653_cal_delay(u32 cycles)1022 static inline u32 gc4653_cal_delay(u32 cycles)
1023 {
1024 return DIV_ROUND_UP(cycles, GC4653_XVCLK_FREQ / 1000 / 1000);
1025 }
1026
__gc4653_power_on(struct gc4653 * gc4653)1027 static int __gc4653_power_on(struct gc4653 *gc4653)
1028 {
1029 int ret;
1030 u32 delay_us;
1031 struct device *dev = &gc4653->client->dev;
1032
1033 if (!IS_ERR_OR_NULL(gc4653->pins_default)) {
1034 ret = pinctrl_select_state(gc4653->pinctrl,
1035 gc4653->pins_default);
1036 if (ret < 0)
1037 dev_err(dev, "could not set pins\n");
1038 }
1039 ret = clk_set_rate(gc4653->xvclk, GC4653_XVCLK_FREQ);
1040 if (ret < 0)
1041 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1042 if (clk_get_rate(gc4653->xvclk) != GC4653_XVCLK_FREQ)
1043 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1044 ret = clk_prepare_enable(gc4653->xvclk);
1045 if (ret < 0) {
1046 dev_err(dev, "Failed to enable xvclk\n");
1047 return ret;
1048 }
1049 if (!IS_ERR(gc4653->reset_gpio))
1050 gpiod_set_value_cansleep(gc4653->reset_gpio, 0);
1051
1052 if (!IS_ERR(gc4653->pwdn_gpio))
1053 gpiod_set_value_cansleep(gc4653->pwdn_gpio, 0);
1054
1055 usleep_range(500, 1000);
1056 ret = regulator_bulk_enable(GC4653_NUM_SUPPLIES, gc4653->supplies);
1057
1058 if (ret < 0) {
1059 dev_err(dev, "Failed to enable regulators\n");
1060 goto disable_clk;
1061 }
1062
1063 if (!IS_ERR(gc4653->pwren_gpio))
1064 gpiod_set_value_cansleep(gc4653->pwren_gpio, 1);
1065
1066 usleep_range(1000, 1100);
1067 if (!IS_ERR(gc4653->pwdn_gpio))
1068 gpiod_set_value_cansleep(gc4653->pwdn_gpio, 1);
1069 usleep_range(100, 150);
1070 if (!IS_ERR(gc4653->reset_gpio))
1071 gpiod_set_value_cansleep(gc4653->reset_gpio, 1);
1072
1073 /* 8192 cycles prior to first SCCB transaction */
1074 delay_us = gc4653_cal_delay(8192);
1075 usleep_range(delay_us, delay_us * 2);
1076
1077 return 0;
1078
1079 disable_clk:
1080 clk_disable_unprepare(gc4653->xvclk);
1081
1082 return ret;
1083 }
1084
__gc4653_power_off(struct gc4653 * gc4653)1085 static void __gc4653_power_off(struct gc4653 *gc4653)
1086 {
1087 int ret;
1088 struct device *dev = &gc4653->client->dev;
1089
1090 if (!IS_ERR(gc4653->pwdn_gpio))
1091 gpiod_set_value_cansleep(gc4653->pwdn_gpio, 0);
1092 clk_disable_unprepare(gc4653->xvclk);
1093 if (!IS_ERR(gc4653->reset_gpio))
1094 gpiod_set_value_cansleep(gc4653->reset_gpio, 0);
1095 if (!IS_ERR_OR_NULL(gc4653->pins_sleep)) {
1096 ret = pinctrl_select_state(gc4653->pinctrl,
1097 gc4653->pins_sleep);
1098 if (ret < 0)
1099 dev_dbg(dev, "could not set pins\n");
1100 }
1101 regulator_bulk_disable(GC4653_NUM_SUPPLIES, gc4653->supplies);
1102 if (!IS_ERR(gc4653->pwren_gpio))
1103 gpiod_set_value_cansleep(gc4653->pwren_gpio, 0);
1104 }
1105
gc4653_runtime_resume(struct device * dev)1106 static int gc4653_runtime_resume(struct device *dev)
1107 {
1108 struct i2c_client *client = to_i2c_client(dev);
1109 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1110 struct gc4653 *gc4653 = to_gc4653(sd);
1111
1112 return __gc4653_power_on(gc4653);
1113 }
1114
gc4653_runtime_suspend(struct device * dev)1115 static int gc4653_runtime_suspend(struct device *dev)
1116 {
1117 struct i2c_client *client = to_i2c_client(dev);
1118 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1119 struct gc4653 *gc4653 = to_gc4653(sd);
1120
1121 __gc4653_power_off(gc4653);
1122
1123 return 0;
1124 }
1125
1126 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc4653_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1127 static int gc4653_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1128 {
1129 struct gc4653 *gc4653 = to_gc4653(sd);
1130 struct v4l2_mbus_framefmt *try_fmt =
1131 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1132 const struct gc4653_mode *def_mode = &supported_modes[0];
1133
1134 mutex_lock(&gc4653->mutex);
1135 /* Initialize try_fmt */
1136 try_fmt->width = def_mode->width;
1137 try_fmt->height = def_mode->height;
1138 try_fmt->code = def_mode->bus_fmt;
1139 try_fmt->field = V4L2_FIELD_NONE;
1140
1141 mutex_unlock(&gc4653->mutex);
1142 /* No crop or compose */
1143
1144 return 0;
1145 }
1146 #endif
1147
gc4653_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1148 static int gc4653_enum_frame_interval(struct v4l2_subdev *sd,
1149 struct v4l2_subdev_pad_config *cfg,
1150 struct v4l2_subdev_frame_interval_enum *fie)
1151 {
1152 struct gc4653 *gc4653 = to_gc4653(sd);
1153
1154 if (fie->index >= gc4653->cfg_num)
1155 return -EINVAL;
1156
1157 fie->code = supported_modes[fie->index].bus_fmt;
1158 fie->width = supported_modes[fie->index].width;
1159 fie->height = supported_modes[fie->index].height;
1160 fie->interval = supported_modes[fie->index].max_fps;
1161 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1162 return 0;
1163 }
1164
1165 static const struct dev_pm_ops gc4653_pm_ops = {
1166 SET_RUNTIME_PM_OPS(gc4653_runtime_suspend,
1167 gc4653_runtime_resume, NULL)
1168 };
1169
1170 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1171 static const struct v4l2_subdev_internal_ops gc4653_internal_ops = {
1172 .open = gc4653_open,
1173 };
1174 #endif
1175
1176 static const struct v4l2_subdev_core_ops gc4653_core_ops = {
1177 .s_power = gc4653_s_power,
1178 .ioctl = gc4653_ioctl,
1179 #ifdef CONFIG_COMPAT
1180 .compat_ioctl32 = gc4653_compat_ioctl32,
1181 #endif
1182 };
1183
1184 static const struct v4l2_subdev_video_ops gc4653_video_ops = {
1185 .s_stream = gc4653_s_stream,
1186 .g_frame_interval = gc4653_g_frame_interval,
1187 };
1188
1189 static const struct v4l2_subdev_pad_ops gc4653_pad_ops = {
1190 .enum_mbus_code = gc4653_enum_mbus_code,
1191 .enum_frame_size = gc4653_enum_frame_sizes,
1192 .enum_frame_interval = gc4653_enum_frame_interval,
1193 .get_fmt = gc4653_get_fmt,
1194 .set_fmt = gc4653_set_fmt,
1195 .get_mbus_config = gc4653_g_mbus_config,
1196 };
1197
1198 static const struct v4l2_subdev_ops gc4653_subdev_ops = {
1199 .core = &gc4653_core_ops,
1200 .video = &gc4653_video_ops,
1201 .pad = &gc4653_pad_ops,
1202 };
1203
gc4653_set_ctrl(struct v4l2_ctrl * ctrl)1204 static int gc4653_set_ctrl(struct v4l2_ctrl *ctrl)
1205 {
1206 struct gc4653 *gc4653 = container_of(ctrl->handler,
1207 struct gc4653, ctrl_handler);
1208 struct i2c_client *client = gc4653->client;
1209 s64 max;
1210 int ret = 0;
1211 int val = 0;
1212
1213 /*Propagate change of current control to all related controls*/
1214 switch (ctrl->id) {
1215 case V4L2_CID_VBLANK:
1216 /*Update max exposure while meeting expected vblanking*/
1217 max = gc4653->cur_mode->height + ctrl->val - 4;
1218 __v4l2_ctrl_modify_range(gc4653->exposure,
1219 gc4653->exposure->minimum,
1220 max,
1221 gc4653->exposure->step,
1222 gc4653->exposure->default_value);
1223 break;
1224 }
1225
1226 if (!pm_runtime_get_if_in_use(&client->dev))
1227 return 0;
1228
1229 switch (ctrl->id) {
1230 case V4L2_CID_EXPOSURE:
1231 /* 4 least significant bits of expsoure are fractional part */
1232 ret = gc4653_write_reg(gc4653->client, GC4653_REG_EXPOSURE_H,
1233 GC4653_REG_VALUE_08BIT,
1234 ctrl->val >> 8);
1235 ret |= gc4653_write_reg(gc4653->client, GC4653_REG_EXPOSURE_L,
1236 GC4653_REG_VALUE_08BIT,
1237 ctrl->val & 0xfe);
1238 break;
1239 case V4L2_CID_ANALOGUE_GAIN:
1240 ret = gc4653_set_gain_reg(gc4653, ctrl->val);
1241 break;
1242 case V4L2_CID_VBLANK:
1243 gc4653->cur_vts = ctrl->val + gc4653->cur_mode->height;
1244 ret = gc4653_write_reg(gc4653->client, GC4653_REG_VTS_H,
1245 GC4653_REG_VALUE_08BIT,
1246 gc4653->cur_vts >> 8);
1247 ret |= gc4653_write_reg(gc4653->client, GC4653_REG_VTS_L,
1248 GC4653_REG_VALUE_08BIT,
1249 gc4653->cur_vts & 0xff);
1250 break;
1251 case V4L2_CID_TEST_PATTERN:
1252 ret = gc4653_enable_test_pattern(gc4653, ctrl->val);
1253 break;
1254 case V4L2_CID_HFLIP:
1255 ret = gc4653_read_reg(gc4653->client, GC4653_FLIP_MIRROR_REG,
1256 GC4653_REG_VALUE_08BIT, &val);
1257 if (ctrl->val)
1258 val |= GC4653_MIRROR_BIT_MASK;
1259 else
1260 val &= ~GC4653_MIRROR_BIT_MASK;
1261 ret |= gc4653_write_reg(gc4653->client, GC4653_FRAME_BUFFER_REG,
1262 GC4653_REG_VALUE_08BIT, GC4653_FRAME_BUFFER_START);
1263 ret |= gc4653_write_reg(gc4653->client, GC4653_FLIP_MIRROR_REG,
1264 GC4653_REG_VALUE_08BIT, val);
1265 ret |= gc4653_write_reg(gc4653->client, GC4653_FRAME_BUFFER_REG,
1266 GC4653_REG_VALUE_08BIT, GC4653_FRAME_BUFFER_END);
1267 break;
1268 case V4L2_CID_VFLIP:
1269 ret = gc4653_read_reg(gc4653->client, GC4653_FLIP_MIRROR_REG,
1270 GC4653_REG_VALUE_08BIT, &val);
1271 if (ctrl->val)
1272 val |= GC4653_FLIP_BIT_MASK;
1273 else
1274 val &= ~GC4653_FLIP_BIT_MASK;
1275 ret |= gc4653_write_reg(gc4653->client, GC4653_FRAME_BUFFER_REG,
1276 GC4653_REG_VALUE_08BIT, GC4653_FRAME_BUFFER_START);
1277 ret |= gc4653_write_reg(gc4653->client, GC4653_FLIP_MIRROR_REG,
1278 GC4653_REG_VALUE_08BIT, val);
1279 ret |= gc4653_write_reg(gc4653->client, GC4653_FRAME_BUFFER_REG,
1280 GC4653_REG_VALUE_08BIT, GC4653_FRAME_BUFFER_END);
1281 break;
1282 default:
1283 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1284 __func__, ctrl->id, ctrl->val);
1285 break;
1286 }
1287
1288 pm_runtime_put(&client->dev);
1289
1290 return ret;
1291 }
1292
1293 static const struct v4l2_ctrl_ops gc4653_ctrl_ops = {
1294 .s_ctrl = gc4653_set_ctrl,
1295 };
1296
gc4653_initialize_controls(struct gc4653 * gc4653)1297 static int gc4653_initialize_controls(struct gc4653 *gc4653)
1298 {
1299 const struct gc4653_mode *mode;
1300 struct v4l2_ctrl_handler *handler;
1301 s64 exposure_max, vblank_def;
1302 u32 h_blank;
1303 int ret;
1304
1305 handler = &gc4653->ctrl_handler;
1306 mode = gc4653->cur_mode;
1307 ret = v4l2_ctrl_handler_init(handler, 9);
1308 if (ret)
1309 return ret;
1310 handler->lock = &gc4653->mutex;
1311
1312 gc4653->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1313 0, 0, link_freq_menu_items);
1314 gc4653->cur_link_freq = 0;
1315 gc4653->cur_pixel_rate = GC4653_PIXEL_RATE_LINEAR;
1316
1317 __v4l2_ctrl_s_ctrl(gc4653->link_freq,
1318 gc4653->cur_link_freq);
1319
1320 gc4653->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1321 0, GC4653_PIXEL_RATE_LINEAR, 1, GC4653_PIXEL_RATE_LINEAR);
1322
1323 h_blank = mode->hts_def - mode->width;
1324 gc4653->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1325 h_blank, h_blank, 1, h_blank);
1326 if (gc4653->hblank)
1327 gc4653->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1328
1329 vblank_def = mode->vts_def - mode->height;
1330 gc4653->cur_vts = mode->vts_def;
1331 gc4653->vblank = v4l2_ctrl_new_std(handler, &gc4653_ctrl_ops,
1332 V4L2_CID_VBLANK, vblank_def,
1333 GC4653_VTS_MAX - mode->height,
1334 1, vblank_def);
1335
1336 exposure_max = mode->vts_def - 4;
1337 gc4653->exposure = v4l2_ctrl_new_std(handler, &gc4653_ctrl_ops,
1338 V4L2_CID_EXPOSURE,
1339 GC4653_EXPOSURE_MIN,
1340 exposure_max,
1341 GC4653_EXPOSURE_STEP,
1342 mode->exp_def);
1343
1344 gc4653->anal_gain = v4l2_ctrl_new_std(handler, &gc4653_ctrl_ops,
1345 V4L2_CID_ANALOGUE_GAIN,
1346 GC4653_GAIN_MIN,
1347 GC4653_GAIN_MAX,
1348 GC4653_GAIN_STEP,
1349 GC4653_GAIN_DEFAULT);
1350
1351 gc4653->test_pattern =
1352 v4l2_ctrl_new_std_menu_items(handler,
1353 &gc4653_ctrl_ops,
1354 V4L2_CID_TEST_PATTERN,
1355 ARRAY_SIZE(gc4653_test_pattern_menu) - 1,
1356 0, 0, gc4653_test_pattern_menu);
1357
1358 gc4653->h_flip = v4l2_ctrl_new_std(handler, &gc4653_ctrl_ops,
1359 V4L2_CID_HFLIP, 0, 1, 1, 0);
1360
1361 gc4653->v_flip = v4l2_ctrl_new_std(handler, &gc4653_ctrl_ops,
1362 V4L2_CID_VFLIP, 0, 1, 1, 0);
1363 if (handler->error) {
1364 ret = handler->error;
1365 dev_err(&gc4653->client->dev,
1366 "Failed to init controls(%d)\n", ret);
1367 goto err_free_handler;
1368 }
1369
1370 gc4653->subdev.ctrl_handler = handler;
1371 gc4653->has_init_exp = false;
1372
1373 return 0;
1374
1375 err_free_handler:
1376 v4l2_ctrl_handler_free(handler);
1377
1378 return ret;
1379 }
1380
gc4653_check_sensor_id(struct gc4653 * gc4653,struct i2c_client * client)1381 static int gc4653_check_sensor_id(struct gc4653 *gc4653,
1382 struct i2c_client *client)
1383 {
1384 struct device *dev = &gc4653->client->dev;
1385 u16 id = 0;
1386 u32 reg_H = 0;
1387 u32 reg_L = 0;
1388 int ret;
1389
1390 ret = gc4653_read_reg(client, GC4653_REG_CHIP_ID_H,
1391 GC4653_REG_VALUE_08BIT, ®_H);
1392 ret |= gc4653_read_reg(client, GC4653_REG_CHIP_ID_L,
1393 GC4653_REG_VALUE_08BIT, ®_L);
1394
1395 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
1396 if (!(reg_H == (CHIP_ID >> 8) || reg_L == (CHIP_ID & 0xff))) {
1397 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1398 return -ENODEV;
1399 }
1400 dev_info(dev, "detected gc%04x sensor\n", id);
1401 return 0;
1402 }
1403
gc4653_configure_regulators(struct gc4653 * gc4653)1404 static int gc4653_configure_regulators(struct gc4653 *gc4653)
1405 {
1406 unsigned int i;
1407
1408 for (i = 0; i < GC4653_NUM_SUPPLIES; i++)
1409 gc4653->supplies[i].supply = gc4653_supply_names[i];
1410
1411 return devm_regulator_bulk_get(&gc4653->client->dev,
1412 GC4653_NUM_SUPPLIES,
1413 gc4653->supplies);
1414 }
1415
gc4653_probe(struct i2c_client * client,const struct i2c_device_id * id)1416 static int gc4653_probe(struct i2c_client *client,
1417 const struct i2c_device_id *id)
1418 {
1419 struct device *dev = &client->dev;
1420 struct device_node *node = dev->of_node;
1421 struct gc4653 *gc4653;
1422 struct v4l2_subdev *sd;
1423 char facing[2];
1424 int ret;
1425 u32 i, hdr_mode = 0;
1426
1427 dev_info(dev, "driver version: %02x.%02x.%02x",
1428 DRIVER_VERSION >> 16,
1429 (DRIVER_VERSION & 0xff00) >> 8,
1430 DRIVER_VERSION & 0x00ff);
1431
1432 gc4653 = devm_kzalloc(dev, sizeof(*gc4653), GFP_KERNEL);
1433 if (!gc4653)
1434 return -ENOMEM;
1435
1436 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1437 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1438 &gc4653->module_index);
1439 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1440 &gc4653->module_facing);
1441 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1442 &gc4653->module_name);
1443 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1444 &gc4653->len_name);
1445 if (ret) {
1446 dev_err(dev, "could not get module information!\n");
1447 return -EINVAL;
1448 }
1449
1450 gc4653->client = client;
1451 gc4653->cfg_num = ARRAY_SIZE(supported_modes);
1452 for (i = 0; i < gc4653->cfg_num; i++) {
1453 if (hdr_mode == supported_modes[i].hdr_mode) {
1454 gc4653->cur_mode = &supported_modes[i];
1455 break;
1456 }
1457 }
1458 if (i == gc4653->cfg_num)
1459 gc4653->cur_mode = &supported_modes[0];
1460
1461 gc4653->xvclk = devm_clk_get(dev, "xvclk");
1462 if (IS_ERR(gc4653->xvclk)) {
1463 dev_err(dev, "Failed to get xvclk\n");
1464 return -EINVAL;
1465 }
1466
1467 gc4653->pwren_gpio = devm_gpiod_get(dev, "pwren", GPIOD_OUT_LOW);
1468 if (IS_ERR(gc4653->pwren_gpio))
1469 dev_warn(dev, "Failed to get pwren-gpios\n");
1470
1471 gc4653->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1472 if (IS_ERR(gc4653->reset_gpio))
1473 dev_warn(dev, "Failed to get reset-gpios\n");
1474
1475 gc4653->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1476 if (IS_ERR(gc4653->pwdn_gpio))
1477 dev_warn(dev, "Failed to get pwdn-gpios\n");
1478
1479 gc4653->pinctrl = devm_pinctrl_get(dev);
1480 if (!IS_ERR(gc4653->pinctrl)) {
1481 gc4653->pins_default =
1482 pinctrl_lookup_state(gc4653->pinctrl,
1483 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1484 if (IS_ERR(gc4653->pins_default))
1485 dev_err(dev, "could not get default pinstate\n");
1486
1487 gc4653->pins_sleep =
1488 pinctrl_lookup_state(gc4653->pinctrl,
1489 OF_CAMERA_PINCTRL_STATE_SLEEP);
1490 if (IS_ERR(gc4653->pins_sleep))
1491 dev_err(dev, "could not get sleep pinstate\n");
1492 } else {
1493 dev_err(dev, "no pinctrl\n");
1494 }
1495
1496 ret = gc4653_configure_regulators(gc4653);
1497 if (ret) {
1498 dev_err(dev, "Failed to get power regulators\n");
1499 return ret;
1500 }
1501
1502 mutex_init(&gc4653->mutex);
1503
1504 sd = &gc4653->subdev;
1505 v4l2_i2c_subdev_init(sd, client, &gc4653_subdev_ops);
1506 ret = gc4653_initialize_controls(gc4653);
1507 if (ret)
1508 goto err_destroy_mutex;
1509
1510 ret = __gc4653_power_on(gc4653);
1511 if (ret)
1512 goto err_free_handler;
1513
1514 usleep_range(3000, 4000);
1515
1516 ret = gc4653_check_sensor_id(gc4653, client);
1517 if (ret)
1518 goto err_power_off;
1519
1520 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1521 sd->internal_ops = &gc4653_internal_ops;
1522 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1523 V4L2_SUBDEV_FL_HAS_EVENTS;
1524 #endif
1525 #if defined(CONFIG_MEDIA_CONTROLLER)
1526 gc4653->pad.flags = MEDIA_PAD_FL_SOURCE;
1527 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1528 ret = media_entity_pads_init(&sd->entity, 1, &gc4653->pad);
1529 if (ret < 0)
1530 goto err_power_off;
1531 #endif
1532
1533 memset(facing, 0, sizeof(facing));
1534 if (strcmp(gc4653->module_facing, "back") == 0)
1535 facing[0] = 'b';
1536 else
1537 facing[0] = 'f';
1538
1539 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1540 gc4653->module_index, facing,
1541 GC4653_NAME, dev_name(sd->dev));
1542 ret = v4l2_async_register_subdev_sensor_common(sd);
1543 if (ret) {
1544 dev_err(dev, "v4l2 async register subdev failed\n");
1545 goto err_clean_entity;
1546 }
1547
1548 pm_runtime_set_active(dev);
1549 pm_runtime_enable(dev);
1550 pm_runtime_idle(dev);
1551
1552 return 0;
1553
1554 err_clean_entity:
1555 #if defined(CONFIG_MEDIA_CONTROLLER)
1556 media_entity_cleanup(&sd->entity);
1557 #endif
1558 err_power_off:
1559 __gc4653_power_off(gc4653);
1560 err_free_handler:
1561 v4l2_ctrl_handler_free(&gc4653->ctrl_handler);
1562 err_destroy_mutex:
1563 mutex_destroy(&gc4653->mutex);
1564
1565 return ret;
1566 }
1567
gc4653_remove(struct i2c_client * client)1568 static int gc4653_remove(struct i2c_client *client)
1569 {
1570 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1571 struct gc4653 *gc4653 = to_gc4653(sd);
1572
1573 v4l2_async_unregister_subdev(sd);
1574 #if defined(CONFIG_MEDIA_CONTROLLER)
1575 media_entity_cleanup(&sd->entity);
1576 #endif
1577 v4l2_ctrl_handler_free(&gc4653->ctrl_handler);
1578 mutex_destroy(&gc4653->mutex);
1579
1580 pm_runtime_disable(&client->dev);
1581 if (!pm_runtime_status_suspended(&client->dev))
1582 __gc4653_power_off(gc4653);
1583 pm_runtime_set_suspended(&client->dev);
1584
1585 return 0;
1586 }
1587
1588 #if IS_ENABLED(CONFIG_OF)
1589 static const struct of_device_id gc4653_of_match[] = {
1590 { .compatible = "galaxycore,gc4653" },
1591 {},
1592 };
1593 MODULE_DEVICE_TABLE(of, gc4653_of_match);
1594 #endif
1595
1596 static const struct i2c_device_id gc4653_match_id[] = {
1597 { "galaxycore,gc4653", 0 },
1598 { },
1599 };
1600
1601 static struct i2c_driver gc4653_i2c_driver = {
1602 .driver = {
1603 .name = GC4653_NAME,
1604 .pm = &gc4653_pm_ops,
1605 .of_match_table = of_match_ptr(gc4653_of_match),
1606 },
1607 .probe = &gc4653_probe,
1608 .remove = &gc4653_remove,
1609 .id_table = gc4653_match_id,
1610 };
1611
sensor_mod_init(void)1612 static int __init sensor_mod_init(void)
1613 {
1614 return i2c_add_driver(&gc4653_i2c_driver);
1615 }
1616
sensor_mod_exit(void)1617 static void __exit sensor_mod_exit(void)
1618 {
1619 i2c_del_driver(&gc4653_i2c_driver);
1620 }
1621
1622 device_initcall_sync(sensor_mod_init);
1623 module_exit(sensor_mod_exit);
1624
1625 MODULE_DESCRIPTION("galaxycore gc4653 sensor driver");
1626 MODULE_LICENSE("GPL");
1627