1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * GC4023 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 init version.
8 * V0.0X02.0X00 update version.
9 * 1, update init registers setting;
10 * 2, update gain table;
11 * 3, update mirror/flip setting;
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/sysfs.h>
23 #include <linux/slab.h>
24 #include <linux/version.h>
25 #include <linux/rk-camera-module.h>
26 #include <linux/rk-preisp.h>
27 #include <media/media-entity.h>
28 #include <media/v4l2-async.h>
29 #include <media/v4l2-ctrls.h>
30 #include <media/v4l2-subdev.h>
31 #include <linux/pinctrl/consumer.h>
32
33 #define DRIVER_VERSION KERNEL_VERSION(0, 0x02, 0x00)
34
35 #ifndef V4L2_CID_DIGITAL_GAIN
36 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
37 #endif
38
39 #define GC4023_LANES 2
40 #define GC4023_BITS_PER_SAMPLE 10
41 #define GC4023_LINK_FREQ_LINEAR 351000000 //2560*1440
42
43 #define GC4023_PIXEL_RATE_LINEAR (GC4023_LINK_FREQ_LINEAR * 2 / 10 * 2)
44
45 #define GC4023_XVCLK_FREQ 27000000
46
47 #define CHIP_ID 0x4023
48 #define GC4023_REG_CHIP_ID_H 0x03f0
49 #define GC4023_REG_CHIP_ID_L 0x03f1
50
51 #define GC4023_REG_CTRL_MODE 0x0100
52 #define GC4023_MODE_SW_STANDBY 0x00
53 #define GC4023_MODE_STREAMING 0x09
54
55 #define GC4023_REG_EXPOSURE_H 0x0202
56 #define GC4023_REG_EXPOSURE_L 0x0203
57 #define GC4023_EXPOSURE_MIN 4
58 #define GC4023_EXPOSURE_STEP 1
59 #define GC4023_VTS_MAX 0x7fff
60
61 #define GC4023_GAIN_MIN 64
62 #define GC4023_GAIN_MAX 0xffff
63 #define GC4023_GAIN_STEP 1
64 #define GC4023_GAIN_DEFAULT 256
65
66 #define GC4023_REG_TEST_PATTERN 0x008c
67 #define GC4023_TEST_PATTERN_ENABLE 0x11
68 #define GC4023_TEST_PATTERN_DISABLE 0x0
69
70 #define GC4023_REG_VTS_H 0x0340
71 #define GC4023_REG_VTS_L 0x0341
72
73 #define GC4023_OTP_MIRROR_FLIP_REG 0x0a73
74 #define GC4023_MIRROR_BIT_MASK BIT(0)
75 #define GC4023_MIRROR_FLIP_REG 0x022c
76 #define GC4023_FLIP_BIT_MASK BIT(1)
77 #define REG_DELAY 0xFFFE
78 #define REG_NULL 0xFFFF
79
80 #define GC4023_REG_VALUE_08BIT 1
81 #define GC4023_REG_VALUE_16BIT 2
82 #define GC4023_REG_VALUE_24BIT 3
83
84 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
85 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
86 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
87 #define GC4023_NAME "gc4023"
88
89 static const char * const gc4023_supply_names[] = {
90 "dovdd", /* Digital I/O power */
91 "dvdd", /* Digital core power */
92 "avdd", /* Analog power */
93 };
94
95 #define GC4023_NUM_SUPPLIES ARRAY_SIZE(gc4023_supply_names)
96
97 struct regval {
98 u16 addr;
99 u8 val;
100 };
101
102 struct gc4023_mode {
103 u32 bus_fmt;
104 u32 width;
105 u32 height;
106 struct v4l2_fract max_fps;
107 u32 hts_def;
108 u32 vts_def;
109 u32 exp_def;
110 const struct regval *reg_list;
111 u32 hdr_mode;
112 u32 vc[PAD_MAX];
113 };
114
115 struct gc4023 {
116 struct i2c_client *client;
117 struct clk *xvclk;
118 struct gpio_desc *reset_gpio;
119 struct gpio_desc *pwdn_gpio;
120 struct gpio_desc *pwren_gpio;
121 struct regulator_bulk_data supplies[GC4023_NUM_SUPPLIES];
122
123 struct pinctrl *pinctrl;
124 struct pinctrl_state *pins_default;
125 struct pinctrl_state *pins_sleep;
126
127 struct v4l2_subdev subdev;
128 struct media_pad pad;
129 struct v4l2_ctrl_handler ctrl_handler;
130 struct v4l2_ctrl *exposure;
131 struct v4l2_ctrl *anal_gain;
132 struct v4l2_ctrl *digi_gain;
133 struct v4l2_ctrl *hblank;
134 struct v4l2_ctrl *vblank;
135 struct v4l2_ctrl *pixel_rate;
136 struct v4l2_ctrl *link_freq;
137 struct v4l2_ctrl *h_flip;
138 struct v4l2_ctrl *v_flip;
139 struct v4l2_ctrl *test_pattern;
140 struct mutex mutex;
141 bool streaming;
142 bool power_on;
143 const struct gc4023_mode *cur_mode;
144 u32 cfg_num;
145 u32 module_index;
146 u32 cur_vts;
147 u32 cur_pixel_rate;
148 u32 cur_link_freq;
149 struct preisp_hdrae_exp_s init_hdrae_exp;
150 const char *module_facing;
151 const char *module_name;
152 const char *len_name;
153 bool has_init_exp;
154 };
155
156 #define to_gc4023(sd) container_of(sd, struct gc4023, subdev)
157
158 /*
159 * Xclk 24Mhz
160 */
161 static const struct regval gc4023_global_regs[] = {
162 {REG_NULL, 0x00},
163 };
164
165 static const u32 reg_val_table_liner[26][7] = {
166 // 614 615 218 1467 1468 b8 b9
167 {0x00, 0x00, 0x00, 0x0D, 0x15, 0x01, 0x00},
168 {0x80, 0x02, 0x00, 0x0D, 0x15, 0x01, 0x0B},
169 {0x01, 0x00, 0x00, 0x0D, 0x15, 0x01, 0x19},
170 {0x81, 0x02, 0x00, 0x0E, 0x16, 0x01, 0x2A},
171 {0x02, 0x00, 0x00, 0x0E, 0x16, 0x02, 0x00},
172 {0x82, 0x02, 0x00, 0x0F, 0x17, 0x02, 0x17},
173 {0x03, 0x00, 0x00, 0x10, 0x18, 0x02, 0x33},
174 {0x83, 0x02, 0x00, 0x11, 0x19, 0x03, 0x14},
175 {0x04, 0x00, 0x00, 0x12, 0x1a, 0x04, 0x00},
176 {0x80, 0x02, 0x20, 0x13, 0x1b, 0x04, 0x2F},
177 {0x01, 0x00, 0x20, 0x14, 0x1c, 0x05, 0x26},
178 {0x81, 0x02, 0x20, 0x15, 0x1d, 0x06, 0x28},
179 {0x02, 0x00, 0x20, 0x16, 0x1e, 0x08, 0x00},
180 {0x82, 0x02, 0x20, 0x16, 0x1e, 0x09, 0x1E},
181 {0x03, 0x00, 0x20, 0x18, 0x20, 0x0B, 0x0C},
182 {0x83, 0x02, 0x20, 0x18, 0x20, 0x0D, 0x11},
183 {0x04, 0x00, 0x20, 0x18, 0x20, 0x10, 0x00},
184 {0x84, 0x02, 0x20, 0x19, 0x21, 0x12, 0x3D},
185 {0x05, 0x00, 0x20, 0x19, 0x21, 0x16, 0x19},
186 {0x85, 0x02, 0x20, 0x1A, 0x22, 0x1A, 0x22},
187 {0xb5, 0x04, 0x20, 0x1B, 0x23, 0x20, 0x00},
188 {0x85, 0x05, 0x20, 0x1B, 0x23, 0x25, 0x3A},
189 {0x05, 0x08, 0x20, 0x1C, 0x24, 0x2C, 0x33},
190 {0x45, 0x09, 0x20, 0x1D, 0x25, 0x35, 0x05},
191 {0x55, 0x0a, 0x20, 0x1F, 0x27, 0x40, 0x00},
192 };
193
194 static const u32 gain_level_table[26] = {
195 64,
196 76,
197 90,
198 106,
199 128,
200 152,
201 179,
202 212,
203 256,
204 303,
205 358,
206 425,
207 512,
208 607,
209 717,
210 849,
211 1024,
212 1213,
213 1434,
214 1699,
215 2048,
216 2427,
217 2867,
218 3398,
219 4096,
220 0xffff,
221 };
222
223 /*
224 * Xclk 27Mhz
225 * max_framerate 30fps
226 * mipi_datarate per lane 864Mbps, 2lane
227 */
228 static const struct regval gc4023_linear10bit_2560x1440_regs[] = {
229 {0x03fe, 0xf0},
230 {0x03fe, 0x00},
231 {0x03fe, 0x10},
232 {0x03fe, 0x00},
233 {0x0a38, 0x00},
234 {0x0a38, 0x01},
235 {0x0a20, 0x07},
236 {0x061c, 0x50},
237 {0x061d, 0x22},
238 {0x061e, 0x78},
239 {0x061f, 0x06},
240 {0x0a21, 0x10},
241 {0x0a34, 0x40},
242 {0x0a35, 0x01},
243 {0x0a36, 0x4e},
244 {0x0a37, 0x06},
245 {0x0314, 0x50},
246 {0x0315, 0x00},
247 {0x031c, 0xce},
248 {0x0219, 0x47},
249 {0x0342, 0x04},
250 {0x0343, 0xb0},
251 {0x0259, 0x05},
252 {0x025a, 0xa0},
253 {0x0340, 0x05},
254 {0x0341, 0xdc},
255 {0x0347, 0x02},
256 {0x0348, 0x0a},
257 {0x0349, 0x08},
258 {0x034a, 0x05},
259 {0x034b, 0xa8},
260 {0x0094, 0x0a},
261 {0x0095, 0x00},
262 {0x0096, 0x05},
263 {0x0097, 0xa0},
264 {0x0099, 0x04},
265 {0x009b, 0x04},
266 {0x060c, 0x01},
267 {0x060e, 0x08},
268 {0x060f, 0x05},
269 {0x070c, 0x01},
270 {0x070e, 0x08},
271 {0x070f, 0x05},
272 {0x0909, 0x03},
273 {0x0902, 0x04},
274 {0x0904, 0x0b},
275 {0x0907, 0x54},
276 {0x0908, 0x06},
277 {0x0903, 0x9d},
278 {0x072a, 0x18},
279 {0x0724, 0x0a},
280 {0x0727, 0x0a},
281 {0x072a, 0x1c},
282 {0x072b, 0x0a},
283 {0x1466, 0x10},
284 {0x1468, 0x0b},
285 {0x1467, 0x13},
286 {0x1469, 0x80},
287 {0x146a, 0xe8},
288 {0x0707, 0x07},
289 {0x0737, 0x0f},
290 {0x0704, 0x01},
291 {0x0706, 0x03},
292 {0x0716, 0x03},
293 {0x0708, 0xc8},
294 {0x0718, 0xc8},
295 {0x061a, 0x00},
296 {0x1430, 0x80},
297 {0x1407, 0x10},
298 {0x1408, 0x16},
299 {0x1409, 0x03},
300 {0x146d, 0x0e},
301 {0x146e, 0x42},
302 {0x146f, 0x43},
303 {0x1470, 0x3c},
304 {0x1471, 0x3d},
305 {0x1472, 0x3a},
306 {0x1473, 0x3a},
307 {0x1474, 0x40},
308 {0x1475, 0x46},
309 {0x1420, 0x14},
310 {0x1464, 0x15},
311 {0x146c, 0x40},
312 {0x146d, 0x40},
313 {0x1423, 0x08},
314 {0x1428, 0x10},
315 {0x1462, 0x18},
316 {0x02ce, 0x04},
317 {0x143a, 0x0f},
318 {0x142b, 0x88},
319 {0x0245, 0xc9},
320 {0x023a, 0x08},
321 {0x02cd, 0x99},
322 {0x0612, 0x02},
323 {0x0613, 0xc7},
324 {0x0243, 0x03},
325 {0x021b, 0x09},
326 {0x0089, 0x03},
327 {0x0040, 0xa3},
328 {0x0075, 0x64},
329 {0x0004, 0x0f},
330 {0x0002, 0xab},
331 {0x0053, 0x0a},
332 {0x0205, 0x0c},
333 {0x0202, 0x06},
334 {0x0203, 0x27},
335 {0x0614, 0x00},
336 {0x0615, 0x00},
337 {0x0181, 0x0c},
338 {0x0182, 0x05},
339 {0x0185, 0x01},
340 {0x0180, 0x46},
341 {0x0100, 0x08},
342 {0x0106, 0x38},
343 {0x010d, 0x80},
344 {0x010e, 0x0c},
345 {0x0113, 0x02},
346 {0x0114, 0x01},
347 {0x0115, 0x10},
348 {0x022c, 0x00},
349 //{0x0100, 0x09},
350 {0x0a67, 0x80},
351 {0x0a54, 0x0e},
352 {0x0a65, 0x10},
353 {0x0a98, 0x10},
354 {0x05be, 0x00},
355 {0x05a9, 0x01},
356 {0x0029, 0x08},
357 {0x002b, 0xa8},
358 {0x0a83, 0xe0},
359 {0x0a72, 0x02},
360 {0x0a73, 0x60},
361 {0x0a75, 0x41},
362 {0x0a70, 0x03},
363 {0x0a5a, 0x80},
364 {REG_DELAY, 0x14},
365 {0x05be, 0x01},
366 {0x0a70, 0x00},
367 {0x0080, 0x02},
368 {0x0a67, 0x00},
369 {REG_NULL, 0x00},
370 };
371
372 static const struct gc4023_mode supported_modes[] = {
373 {
374 .width = 2560,
375 .height = 1440,
376 .max_fps = {
377 .numerator = 10000,
378 .denominator = 300000,
379 },
380 .exp_def = 0x0100,
381 .hts_def = 0x0AA0,
382 .vts_def = 0x05DC,
383 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
384 .reg_list = gc4023_linear10bit_2560x1440_regs,
385 .hdr_mode = NO_HDR,
386 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
387 },
388 };
389
390 static const s64 link_freq_menu_items[] = {
391 GC4023_LINK_FREQ_LINEAR,
392 };
393
394 static const char * const gc4023_test_pattern_menu[] = {
395 "Disabled",
396 "Vertical Color Bar Type 1",
397 "Vertical Color Bar Type 2",
398 "Vertical Color Bar Type 3",
399 "Vertical Color Bar Type 4"
400 };
401
402 /* Write registers up to 4 at a time */
gc4023_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)403 static int gc4023_write_reg(struct i2c_client *client, u16 reg,
404 u32 len, u32 val)
405 {
406 u32 buf_i, val_i;
407 u8 buf[6];
408 u8 *val_p;
409 __be32 val_be;
410
411 if (len > 4)
412 return -EINVAL;
413
414 buf[0] = reg >> 8;
415 buf[1] = reg & 0xff;
416
417 val_be = cpu_to_be32(val);
418 val_p = (u8 *)&val_be;
419 buf_i = 2;
420 val_i = 4 - len;
421
422 while (val_i < 4)
423 buf[buf_i++] = val_p[val_i++];
424
425 if (i2c_master_send(client, buf, len + 2) != len + 2)
426 return -EIO;
427
428 return 0;
429 }
430
gc4023_write_array(struct i2c_client * client,const struct regval * regs)431 static int gc4023_write_array(struct i2c_client *client,
432 const struct regval *regs)
433 {
434 u32 i;
435 int ret = 0;
436
437 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
438 if (regs[i].addr == REG_DELAY)
439 usleep_range(regs[i].val * 1000, regs[i].val * 2 * 1000);
440 else
441 ret = gc4023_write_reg(client, regs[i].addr,
442 GC4023_REG_VALUE_08BIT, regs[i].val);
443 }
444
445 return ret;
446 }
447
448 /* Read registers up to 4 at a time */
gc4023_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)449 static int gc4023_read_reg(struct i2c_client *client, u16 reg,
450 unsigned int len, u32 *val)
451 {
452 struct i2c_msg msgs[2];
453 u8 *data_be_p;
454 __be32 data_be = 0;
455 __be16 reg_addr_be = cpu_to_be16(reg);
456 int ret;
457
458 if (len > 4 || !len)
459 return -EINVAL;
460
461 data_be_p = (u8 *)&data_be;
462 /* Write register address */
463 msgs[0].addr = client->addr;
464 msgs[0].flags = 0;
465 msgs[0].len = 2;
466 msgs[0].buf = (u8 *)®_addr_be;
467
468 /* Read data from register */
469 msgs[1].addr = client->addr;
470 msgs[1].flags = I2C_M_RD;
471 msgs[1].len = len;
472 msgs[1].buf = &data_be_p[4 - len];
473
474 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
475 if (ret != ARRAY_SIZE(msgs))
476 return -EIO;
477
478 *val = be32_to_cpu(data_be);
479
480 return 0;
481 }
482
gc4023_get_reso_dist(const struct gc4023_mode * mode,struct v4l2_mbus_framefmt * framefmt)483 static int gc4023_get_reso_dist(const struct gc4023_mode *mode,
484 struct v4l2_mbus_framefmt *framefmt)
485 {
486 return abs(mode->width - framefmt->width) +
487 abs(mode->height - framefmt->height);
488 }
489
490 static const struct gc4023_mode *
gc4023_find_best_fit(struct gc4023 * gc4023,struct v4l2_subdev_format * fmt)491 gc4023_find_best_fit(struct gc4023 *gc4023, struct v4l2_subdev_format *fmt)
492 {
493 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
494 int dist;
495 int cur_best_fit = 0;
496 int cur_best_fit_dist = -1;
497 unsigned int i;
498
499 for (i = 0; i < gc4023->cfg_num; i++) {
500 dist = gc4023_get_reso_dist(&supported_modes[i], framefmt);
501 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
502 cur_best_fit_dist = dist;
503 cur_best_fit = i;
504 }
505 }
506
507 return &supported_modes[cur_best_fit];
508 }
509
gc4023_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)510 static int gc4023_set_fmt(struct v4l2_subdev *sd,
511 struct v4l2_subdev_pad_config *cfg,
512 struct v4l2_subdev_format *fmt)
513 {
514 struct gc4023 *gc4023 = to_gc4023(sd);
515 const struct gc4023_mode *mode;
516 s64 h_blank, vblank_def;
517
518 mutex_lock(&gc4023->mutex);
519
520 mode = gc4023_find_best_fit(gc4023, fmt);
521 fmt->format.code = mode->bus_fmt;
522 fmt->format.width = mode->width;
523 fmt->format.height = mode->height;
524 fmt->format.field = V4L2_FIELD_NONE;
525 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
526 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
527 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
528 #else
529 mutex_unlock(&gc4023->mutex);
530 return -ENOTTY;
531 #endif
532 } else {
533 gc4023->cur_mode = mode;
534 h_blank = mode->hts_def - mode->width;
535 __v4l2_ctrl_modify_range(gc4023->hblank, h_blank,
536 h_blank, 1, h_blank);
537 vblank_def = mode->vts_def - mode->height;
538 __v4l2_ctrl_modify_range(gc4023->vblank, vblank_def,
539 GC4023_VTS_MAX - mode->height,
540 1, vblank_def);
541
542 gc4023->cur_link_freq = 0;
543 gc4023->cur_pixel_rate = GC4023_PIXEL_RATE_LINEAR;
544
545 __v4l2_ctrl_s_ctrl_int64(gc4023->pixel_rate,
546 gc4023->cur_pixel_rate);
547 __v4l2_ctrl_s_ctrl(gc4023->link_freq,
548 gc4023->cur_link_freq);
549 gc4023->cur_vts = mode->vts_def;
550 }
551 mutex_unlock(&gc4023->mutex);
552
553 return 0;
554 }
555
gc4023_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)556 static int gc4023_get_fmt(struct v4l2_subdev *sd,
557 struct v4l2_subdev_pad_config *cfg,
558 struct v4l2_subdev_format *fmt)
559 {
560 struct gc4023 *gc4023 = to_gc4023(sd);
561 const struct gc4023_mode *mode = gc4023->cur_mode;
562
563 mutex_lock(&gc4023->mutex);
564 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
565 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
566 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
567 #else
568 mutex_unlock(&gc4023->mutex);
569 return -ENOTTY;
570 #endif
571 } else {
572 fmt->format.width = mode->width;
573 fmt->format.height = mode->height;
574 fmt->format.code = mode->bus_fmt;
575 fmt->format.field = V4L2_FIELD_NONE;
576 }
577 mutex_unlock(&gc4023->mutex);
578
579 return 0;
580 }
581
gc4023_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)582 static int gc4023_enum_mbus_code(struct v4l2_subdev *sd,
583 struct v4l2_subdev_pad_config *cfg,
584 struct v4l2_subdev_mbus_code_enum *code)
585 {
586 struct gc4023 *gc4023 = to_gc4023(sd);
587
588 if (code->index != 0)
589 return -EINVAL;
590 code->code = gc4023->cur_mode->bus_fmt;
591
592 return 0;
593 }
594
gc4023_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)595 static int gc4023_enum_frame_sizes(struct v4l2_subdev *sd,
596 struct v4l2_subdev_pad_config *cfg,
597 struct v4l2_subdev_frame_size_enum *fse)
598 {
599 struct gc4023 *gc4023 = to_gc4023(sd);
600
601 if (fse->index >= gc4023->cfg_num)
602 return -EINVAL;
603
604 if (fse->code != supported_modes[0].bus_fmt)
605 return -EINVAL;
606
607 fse->min_width = supported_modes[fse->index].width;
608 fse->max_width = supported_modes[fse->index].width;
609 fse->max_height = supported_modes[fse->index].height;
610 fse->min_height = supported_modes[fse->index].height;
611
612 return 0;
613 }
614
gc4023_enable_test_pattern(struct gc4023 * gc4023,u32 pattern)615 static int gc4023_enable_test_pattern(struct gc4023 *gc4023, u32 pattern)
616 {
617 u32 val;
618
619 if (pattern)
620 val = GC4023_TEST_PATTERN_ENABLE;
621 else
622 val = GC4023_TEST_PATTERN_DISABLE;
623
624 return gc4023_write_reg(gc4023->client, GC4023_REG_TEST_PATTERN,
625 GC4023_REG_VALUE_08BIT, val);
626 }
627
gc4023_set_gain_reg(struct gc4023 * gc4023,u32 gain)628 static int gc4023_set_gain_reg(struct gc4023 *gc4023, u32 gain)
629 {
630 int i;
631 int total;
632 u32 tol_dig_gain = 0;
633
634 if (gain < 64)
635 gain = 64;
636 total = ARRAY_SIZE(gain_level_table) - 1;
637 for (i = 0; i < total; i++) {
638 if (gain_level_table[i] <= gain &&
639 gain < gain_level_table[i + 1])
640 break;
641 }
642 tol_dig_gain = gain * 64 / gain_level_table[i];
643
644 gc4023_write_reg(gc4023->client, 0x614,
645 GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][0]);
646 gc4023_write_reg(gc4023->client, 0x615,
647 GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][1]);
648 gc4023_write_reg(gc4023->client, 0x218,
649 GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][2]);
650 gc4023_write_reg(gc4023->client, 0x1467,
651 GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][3]);
652 gc4023_write_reg(gc4023->client, 0x1468,
653 GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][4]);
654 gc4023_write_reg(gc4023->client, 0xb8,
655 GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][5]);
656 gc4023_write_reg(gc4023->client, 0xb9,
657 GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][6]);
658
659
660 gc4023_write_reg(gc4023->client, 0x64,
661 GC4023_REG_VALUE_08BIT, (tol_dig_gain >> 6));
662 gc4023_write_reg(gc4023->client, 0x65,
663 GC4023_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f) << 2));
664 return 0;
665 }
666
gc4023_set_mirror_flip(struct gc4023 * gc4023,u8 val,u8 otp_val)667 static int gc4023_set_mirror_flip(struct gc4023 *gc4023, u8 val, u8 otp_val)
668 {
669 int ret = 0;
670
671 ret = gc4023_write_reg(gc4023->client, 0x022c,
672 GC4023_REG_VALUE_08BIT, val);
673 ret |= gc4023_write_reg(gc4023->client, 0x0a67,
674 GC4023_REG_VALUE_08BIT, 0x80);
675 ret |= gc4023_write_reg(gc4023->client, 0x0a54,
676 GC4023_REG_VALUE_08BIT, 0x0e);
677 ret |= gc4023_write_reg(gc4023->client, 0x0a65,
678 GC4023_REG_VALUE_08BIT, 0x10);
679 ret |= gc4023_write_reg(gc4023->client, 0x0a98,
680 GC4023_REG_VALUE_08BIT, 0x10);
681 ret |= gc4023_write_reg(gc4023->client, 0x05be,
682 GC4023_REG_VALUE_08BIT, 0x00);
683 ret |= gc4023_write_reg(gc4023->client, 0x05a9,
684 GC4023_REG_VALUE_08BIT, 0x01);
685 ret |= gc4023_write_reg(gc4023->client, 0x0029,
686 GC4023_REG_VALUE_08BIT, 0x08);
687 ret |= gc4023_write_reg(gc4023->client, 0x002b,
688 GC4023_REG_VALUE_08BIT, 0xa8);
689 ret |= gc4023_write_reg(gc4023->client, 0x0a83,
690 GC4023_REG_VALUE_08BIT, 0xe0);
691 ret |= gc4023_write_reg(gc4023->client, 0x0a72,
692 GC4023_REG_VALUE_08BIT, 0x02);
693 ret |= gc4023_write_reg(gc4023->client, 0x0a73,
694 GC4023_REG_VALUE_08BIT, otp_val);
695 ret |= gc4023_write_reg(gc4023->client, 0x0a75,
696 GC4023_REG_VALUE_08BIT, 0x41);
697 ret |= gc4023_write_reg(gc4023->client, 0x0a70,
698 GC4023_REG_VALUE_08BIT, 0x03);
699 ret |= gc4023_write_reg(gc4023->client, 0x0a5a,
700 GC4023_REG_VALUE_08BIT, 0x80);
701
702 usleep_range(20 * 1000, 30 * 1000);
703
704 ret |= gc4023_write_reg(gc4023->client, 0x05be,
705 GC4023_REG_VALUE_08BIT, 0x01);
706 ret |= gc4023_write_reg(gc4023->client, 0x0a70,
707 GC4023_REG_VALUE_08BIT, 0x00);
708 ret |= gc4023_write_reg(gc4023->client, 0x0080,
709 GC4023_REG_VALUE_08BIT, 0x02);
710 ret |= gc4023_write_reg(gc4023->client, 0x0a67,
711 GC4023_REG_VALUE_08BIT, 0x00);
712
713 return ret;
714
715 }
716
gc4023_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)717 static int gc4023_g_frame_interval(struct v4l2_subdev *sd,
718 struct v4l2_subdev_frame_interval *fi)
719 {
720 struct gc4023 *gc4023 = to_gc4023(sd);
721 const struct gc4023_mode *mode = gc4023->cur_mode;
722
723 fi->interval = mode->max_fps;
724
725 return 0;
726 }
727
gc4023_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)728 static int gc4023_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
729 struct v4l2_mbus_config *config)
730 {
731 struct gc4023 *gc4023 = to_gc4023(sd);
732 const struct gc4023_mode *mode = gc4023->cur_mode;
733 u32 val = 0;
734
735 if (mode->hdr_mode == NO_HDR)
736 val = 1 << (GC4023_LANES - 1) |
737 V4L2_MBUS_CSI2_CHANNEL_0 |
738 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
739 if (mode->hdr_mode == HDR_X2)
740 val = 1 << (GC4023_LANES - 1) |
741 V4L2_MBUS_CSI2_CHANNEL_0 |
742 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
743 V4L2_MBUS_CSI2_CHANNEL_1;
744
745 config->type = V4L2_MBUS_CSI2_DPHY;
746 config->flags = val;
747
748 return 0;
749 }
750
gc4023_get_module_inf(struct gc4023 * gc4023,struct rkmodule_inf * inf)751 static void gc4023_get_module_inf(struct gc4023 *gc4023,
752 struct rkmodule_inf *inf)
753 {
754 memset(inf, 0, sizeof(*inf));
755 strscpy(inf->base.sensor, GC4023_NAME, sizeof(inf->base.sensor));
756 strscpy(inf->base.module, gc4023->module_name,
757 sizeof(inf->base.module));
758 strscpy(inf->base.lens, gc4023->len_name, sizeof(inf->base.lens));
759 }
760
gc4023_get_channel_info(struct gc4023 * gc4023,struct rkmodule_channel_info * ch_info)761 static int gc4023_get_channel_info(struct gc4023 *gc4023, struct rkmodule_channel_info *ch_info)
762 {
763 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
764 return -EINVAL;
765 ch_info->vc = gc4023->cur_mode->vc[ch_info->index];
766 ch_info->width = gc4023->cur_mode->width;
767 ch_info->height = gc4023->cur_mode->height;
768 ch_info->bus_fmt = gc4023->cur_mode->bus_fmt;
769 return 0;
770 }
771
gc4023_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)772 static long gc4023_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
773 {
774 struct gc4023 *gc4023 = to_gc4023(sd);
775 struct rkmodule_hdr_cfg *hdr;
776 u32 i, h, w;
777 long ret = 0;
778 u32 stream = 0;
779 struct rkmodule_channel_info *ch_info;
780
781 switch (cmd) {
782 case RKMODULE_GET_MODULE_INFO:
783 gc4023_get_module_inf(gc4023, (struct rkmodule_inf *)arg);
784 break;
785 case RKMODULE_GET_HDR_CFG:
786 hdr = (struct rkmodule_hdr_cfg *)arg;
787 hdr->esp.mode = HDR_NORMAL_VC;
788 hdr->hdr_mode = gc4023->cur_mode->hdr_mode;
789 break;
790 case RKMODULE_SET_HDR_CFG:
791 hdr = (struct rkmodule_hdr_cfg *)arg;
792 w = gc4023->cur_mode->width;
793 h = gc4023->cur_mode->height;
794 for (i = 0; i < gc4023->cfg_num; i++) {
795 if (w == supported_modes[i].width &&
796 h == supported_modes[i].height &&
797 supported_modes[i].hdr_mode == hdr->hdr_mode) {
798 gc4023->cur_mode = &supported_modes[i];
799 break;
800 }
801 }
802 if (i == gc4023->cfg_num) {
803 dev_err(&gc4023->client->dev,
804 "not find hdr mode:%d %dx%d config\n",
805 hdr->hdr_mode, w, h);
806 ret = -EINVAL;
807 } else {
808 w = gc4023->cur_mode->hts_def -
809 gc4023->cur_mode->width;
810 h = gc4023->cur_mode->vts_def -
811 gc4023->cur_mode->height;
812 __v4l2_ctrl_modify_range(gc4023->hblank, w, w, 1, w);
813 __v4l2_ctrl_modify_range(gc4023->vblank, h,
814 GC4023_VTS_MAX -
815 gc4023->cur_mode->height,
816 1, h);
817
818 gc4023->cur_link_freq = 0;
819 gc4023->cur_pixel_rate = GC4023_PIXEL_RATE_LINEAR;
820
821 __v4l2_ctrl_s_ctrl_int64(gc4023->pixel_rate,
822 gc4023->cur_pixel_rate);
823 __v4l2_ctrl_s_ctrl(gc4023->link_freq,
824 gc4023->cur_link_freq);
825 gc4023->cur_vts = gc4023->cur_mode->vts_def;
826 }
827 break;
828 case RKMODULE_SET_QUICK_STREAM:
829 stream = *((u32 *)arg);
830 if (stream)
831 ret = gc4023_write_reg(gc4023->client, GC4023_REG_CTRL_MODE,
832 GC4023_REG_VALUE_08BIT, GC4023_MODE_STREAMING);
833 else
834 ret = gc4023_write_reg(gc4023->client, GC4023_REG_CTRL_MODE,
835 GC4023_REG_VALUE_08BIT, GC4023_MODE_SW_STANDBY);
836 break;
837 case RKMODULE_GET_CHANNEL_INFO:
838 ch_info = (struct rkmodule_channel_info *)arg;
839 ret = gc4023_get_channel_info(gc4023, ch_info);
840 break;
841 default:
842 ret = -ENOIOCTLCMD;
843 break;
844 }
845
846 return ret;
847 }
848
849 #ifdef CONFIG_COMPAT
gc4023_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)850 static long gc4023_compat_ioctl32(struct v4l2_subdev *sd,
851 unsigned int cmd, unsigned long arg)
852 {
853 void __user *up = compat_ptr(arg);
854 struct rkmodule_inf *inf;
855 struct rkmodule_hdr_cfg *hdr;
856 long ret;
857 u32 stream = 0;
858 struct rkmodule_channel_info *ch_info;
859
860 switch (cmd) {
861 case RKMODULE_GET_MODULE_INFO:
862 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
863 if (!inf) {
864 ret = -ENOMEM;
865 return ret;
866 }
867
868 ret = gc4023_ioctl(sd, cmd, inf);
869 if (!ret) {
870 ret = copy_to_user(up, inf, sizeof(*inf));
871 if (ret)
872 ret = -EFAULT;
873 }
874 kfree(inf);
875 break;
876 case RKMODULE_GET_HDR_CFG:
877 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
878 if (!hdr) {
879 ret = -ENOMEM;
880 return ret;
881 }
882
883 ret = gc4023_ioctl(sd, cmd, hdr);
884 if (!ret) {
885 ret = copy_to_user(up, hdr, sizeof(*hdr));
886 if (ret)
887 ret = -EFAULT;
888 }
889 kfree(hdr);
890 break;
891 case RKMODULE_SET_HDR_CFG:
892 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
893 if (!hdr) {
894 ret = -ENOMEM;
895 return ret;
896 }
897
898 ret = copy_from_user(hdr, up, sizeof(*hdr));
899 if (!ret)
900 ret = gc4023_ioctl(sd, cmd, hdr);
901 else
902 ret = -EFAULT;
903 kfree(hdr);
904 break;
905 case RKMODULE_SET_QUICK_STREAM:
906 ret = copy_from_user(&stream, up, sizeof(u32));
907 if (!ret)
908 ret = gc4023_ioctl(sd, cmd, &stream);
909 else
910 ret = -EFAULT;
911 break;
912 case RKMODULE_GET_CHANNEL_INFO:
913 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
914 if (!ch_info) {
915 ret = -ENOMEM;
916 return ret;
917 }
918
919 ret = gc4023_ioctl(sd, cmd, ch_info);
920 if (!ret) {
921 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
922 if (ret)
923 ret = -EFAULT;
924 }
925 kfree(ch_info);
926 break;
927 default:
928 ret = -ENOIOCTLCMD;
929 break;
930 }
931
932 return ret;
933 }
934 #endif
935
__gc4023_start_stream(struct gc4023 * gc4023)936 static int __gc4023_start_stream(struct gc4023 *gc4023)
937 {
938 int ret;
939
940 ret = gc4023_write_array(gc4023->client, gc4023->cur_mode->reg_list);
941 if (ret)
942 return ret;
943
944 /* In case these controls are set before streaming */
945 ret = __v4l2_ctrl_handler_setup(&gc4023->ctrl_handler);
946 if (gc4023->has_init_exp && gc4023->cur_mode->hdr_mode != NO_HDR) {
947 ret = gc4023_ioctl(&gc4023->subdev, PREISP_CMD_SET_HDRAE_EXP,
948 &gc4023->init_hdrae_exp);
949 if (ret) {
950 dev_err(&gc4023->client->dev,
951 "init exp fail in hdr mode\n");
952 return ret;
953 }
954 }
955 if (ret)
956 return ret;
957
958 ret |= gc4023_write_reg(gc4023->client, GC4023_REG_CTRL_MODE,
959 GC4023_REG_VALUE_08BIT, GC4023_MODE_STREAMING);
960
961 return ret;
962 }
963
__gc4023_stop_stream(struct gc4023 * gc4023)964 static int __gc4023_stop_stream(struct gc4023 *gc4023)
965 {
966 gc4023->has_init_exp = false;
967 return gc4023_write_reg(gc4023->client, GC4023_REG_CTRL_MODE,
968 GC4023_REG_VALUE_08BIT, GC4023_MODE_SW_STANDBY);
969 }
970
gc4023_s_stream(struct v4l2_subdev * sd,int on)971 static int gc4023_s_stream(struct v4l2_subdev *sd, int on)
972 {
973 struct gc4023 *gc4023 = to_gc4023(sd);
974 struct i2c_client *client = gc4023->client;
975 int ret = 0;
976
977 mutex_lock(&gc4023->mutex);
978 on = !!on;
979 if (on == gc4023->streaming)
980 goto unlock_and_return;
981
982 if (on) {
983 ret = pm_runtime_get_sync(&client->dev);
984 if (ret < 0) {
985 pm_runtime_put_noidle(&client->dev);
986 goto unlock_and_return;
987 }
988
989 ret = __gc4023_start_stream(gc4023);
990 if (ret) {
991 v4l2_err(sd, "start stream failed while write regs\n");
992 pm_runtime_put(&client->dev);
993 goto unlock_and_return;
994 }
995 } else {
996 __gc4023_stop_stream(gc4023);
997 pm_runtime_put(&client->dev);
998 }
999
1000 gc4023->streaming = on;
1001
1002 unlock_and_return:
1003 mutex_unlock(&gc4023->mutex);
1004
1005 return ret;
1006 }
1007
gc4023_s_power(struct v4l2_subdev * sd,int on)1008 static int gc4023_s_power(struct v4l2_subdev *sd, int on)
1009 {
1010 struct gc4023 *gc4023 = to_gc4023(sd);
1011 struct i2c_client *client = gc4023->client;
1012 int ret = 0;
1013
1014 mutex_lock(&gc4023->mutex);
1015
1016 /* If the power state is not modified - no work to do. */
1017 if (gc4023->power_on == !!on)
1018 goto unlock_and_return;
1019
1020 if (on) {
1021 ret = pm_runtime_get_sync(&client->dev);
1022 if (ret < 0) {
1023 pm_runtime_put_noidle(&client->dev);
1024 goto unlock_and_return;
1025 }
1026
1027 ret = gc4023_write_array(gc4023->client, gc4023_global_regs);
1028 if (ret) {
1029 v4l2_err(sd, "could not set init registers\n");
1030 pm_runtime_put_noidle(&client->dev);
1031 goto unlock_and_return;
1032 }
1033
1034 gc4023->power_on = true;
1035 } else {
1036 pm_runtime_put(&client->dev);
1037 gc4023->power_on = false;
1038 }
1039
1040 unlock_and_return:
1041 mutex_unlock(&gc4023->mutex);
1042
1043 return ret;
1044 }
1045
1046 /* Calculate the delay in us by clock rate and clock cycles */
gc4023_cal_delay(u32 cycles)1047 static inline u32 gc4023_cal_delay(u32 cycles)
1048 {
1049 return DIV_ROUND_UP(cycles, GC4023_XVCLK_FREQ / 1000 / 1000);
1050 }
1051
__gc4023_power_on(struct gc4023 * gc4023)1052 static int __gc4023_power_on(struct gc4023 *gc4023)
1053 {
1054 int ret;
1055 u32 delay_us;
1056 struct device *dev = &gc4023->client->dev;
1057
1058 if (!IS_ERR_OR_NULL(gc4023->pins_default)) {
1059 ret = pinctrl_select_state(gc4023->pinctrl,
1060 gc4023->pins_default);
1061 if (ret < 0)
1062 dev_err(dev, "could not set pins\n");
1063 }
1064 ret = clk_set_rate(gc4023->xvclk, GC4023_XVCLK_FREQ);
1065 if (ret < 0)
1066 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1067 if (clk_get_rate(gc4023->xvclk) != GC4023_XVCLK_FREQ)
1068 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1069 ret = clk_prepare_enable(gc4023->xvclk);
1070 if (ret < 0) {
1071 dev_err(dev, "Failed to enable xvclk\n");
1072 return ret;
1073 }
1074 if (!IS_ERR(gc4023->reset_gpio))
1075 gpiod_set_value_cansleep(gc4023->reset_gpio, 0);
1076
1077 if (!IS_ERR(gc4023->pwdn_gpio))
1078 gpiod_set_value_cansleep(gc4023->pwdn_gpio, 0);
1079
1080 usleep_range(500, 1000);
1081 ret = regulator_bulk_enable(GC4023_NUM_SUPPLIES, gc4023->supplies);
1082
1083 if (ret < 0) {
1084 dev_err(dev, "Failed to enable regulators\n");
1085 goto disable_clk;
1086 }
1087
1088 if (!IS_ERR(gc4023->pwren_gpio))
1089 gpiod_set_value_cansleep(gc4023->pwren_gpio, 1);
1090
1091 usleep_range(1000, 1100);
1092 if (!IS_ERR(gc4023->pwdn_gpio))
1093 gpiod_set_value_cansleep(gc4023->pwdn_gpio, 1);
1094 usleep_range(100, 150);
1095 if (!IS_ERR(gc4023->reset_gpio))
1096 gpiod_set_value_cansleep(gc4023->reset_gpio, 1);
1097
1098 /* 8192 cycles prior to first SCCB transaction */
1099 delay_us = gc4023_cal_delay(8192);
1100 usleep_range(delay_us, delay_us * 2);
1101
1102 return 0;
1103
1104 disable_clk:
1105 clk_disable_unprepare(gc4023->xvclk);
1106
1107 return ret;
1108 }
1109
__gc4023_power_off(struct gc4023 * gc4023)1110 static void __gc4023_power_off(struct gc4023 *gc4023)
1111 {
1112 int ret;
1113 struct device *dev = &gc4023->client->dev;
1114
1115 if (!IS_ERR(gc4023->pwdn_gpio))
1116 gpiod_set_value_cansleep(gc4023->pwdn_gpio, 0);
1117 clk_disable_unprepare(gc4023->xvclk);
1118 if (!IS_ERR(gc4023->reset_gpio))
1119 gpiod_set_value_cansleep(gc4023->reset_gpio, 0);
1120 if (!IS_ERR_OR_NULL(gc4023->pins_sleep)) {
1121 ret = pinctrl_select_state(gc4023->pinctrl,
1122 gc4023->pins_sleep);
1123 if (ret < 0)
1124 dev_dbg(dev, "could not set pins\n");
1125 }
1126 regulator_bulk_disable(GC4023_NUM_SUPPLIES, gc4023->supplies);
1127 if (!IS_ERR(gc4023->pwren_gpio))
1128 gpiod_set_value_cansleep(gc4023->pwren_gpio, 0);
1129 }
1130
gc4023_runtime_resume(struct device * dev)1131 static int gc4023_runtime_resume(struct device *dev)
1132 {
1133 struct i2c_client *client = to_i2c_client(dev);
1134 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1135 struct gc4023 *gc4023 = to_gc4023(sd);
1136
1137 return __gc4023_power_on(gc4023);
1138 }
1139
gc4023_runtime_suspend(struct device * dev)1140 static int gc4023_runtime_suspend(struct device *dev)
1141 {
1142 struct i2c_client *client = to_i2c_client(dev);
1143 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1144 struct gc4023 *gc4023 = to_gc4023(sd);
1145
1146 __gc4023_power_off(gc4023);
1147
1148 return 0;
1149 }
1150
1151 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc4023_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1152 static int gc4023_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1153 {
1154 struct gc4023 *gc4023 = to_gc4023(sd);
1155 struct v4l2_mbus_framefmt *try_fmt =
1156 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1157 const struct gc4023_mode *def_mode = &supported_modes[0];
1158
1159 mutex_lock(&gc4023->mutex);
1160 /* Initialize try_fmt */
1161 try_fmt->width = def_mode->width;
1162 try_fmt->height = def_mode->height;
1163 try_fmt->code = def_mode->bus_fmt;
1164 try_fmt->field = V4L2_FIELD_NONE;
1165
1166 mutex_unlock(&gc4023->mutex);
1167 /* No crop or compose */
1168
1169 return 0;
1170 }
1171 #endif
1172
gc4023_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1173 static int gc4023_enum_frame_interval(struct v4l2_subdev *sd,
1174 struct v4l2_subdev_pad_config *cfg,
1175 struct v4l2_subdev_frame_interval_enum *fie)
1176 {
1177 struct gc4023 *gc4023 = to_gc4023(sd);
1178
1179 if (fie->index >= gc4023->cfg_num)
1180 return -EINVAL;
1181
1182 fie->code = supported_modes[fie->index].bus_fmt;
1183 fie->width = supported_modes[fie->index].width;
1184 fie->height = supported_modes[fie->index].height;
1185 fie->interval = supported_modes[fie->index].max_fps;
1186 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1187 return 0;
1188 }
1189
1190 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1191 #define DST_WIDTH 2560
1192 #define DST_HEIGHT 1440
1193
1194 /*
1195 * The resolution of the driver configuration needs to be exactly
1196 * the same as the current output resolution of the sensor,
1197 * the input width of the isp needs to be 16 aligned,
1198 * the input height of the isp needs to be 8 aligned.
1199 * Can be cropped to standard resolution by this function,
1200 * otherwise it will crop out strange resolution according
1201 * to the alignment rules.
1202 */
1203
gc4023_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1204 static int gc4023_get_selection(struct v4l2_subdev *sd,
1205 struct v4l2_subdev_pad_config *cfg,
1206 struct v4l2_subdev_selection *sel)
1207 {
1208 struct gc4023 *gc4023 = to_gc4023(sd);
1209
1210 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1211 sel->r.left = CROP_START(gc4023->cur_mode->width, DST_WIDTH);
1212 sel->r.width = DST_WIDTH;
1213 sel->r.top = CROP_START(gc4023->cur_mode->height, DST_HEIGHT);
1214 sel->r.height = DST_HEIGHT;
1215 return 0;
1216 }
1217 return -EINVAL;
1218 }
1219
1220 static const struct dev_pm_ops gc4023_pm_ops = {
1221 SET_RUNTIME_PM_OPS(gc4023_runtime_suspend,
1222 gc4023_runtime_resume, NULL)
1223 };
1224
1225 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1226 static const struct v4l2_subdev_internal_ops gc4023_internal_ops = {
1227 .open = gc4023_open,
1228 };
1229 #endif
1230
1231 static const struct v4l2_subdev_core_ops gc4023_core_ops = {
1232 .s_power = gc4023_s_power,
1233 .ioctl = gc4023_ioctl,
1234 #ifdef CONFIG_COMPAT
1235 .compat_ioctl32 = gc4023_compat_ioctl32,
1236 #endif
1237 };
1238
1239 static const struct v4l2_subdev_video_ops gc4023_video_ops = {
1240 .s_stream = gc4023_s_stream,
1241 .g_frame_interval = gc4023_g_frame_interval,
1242 };
1243
1244 static const struct v4l2_subdev_pad_ops gc4023_pad_ops = {
1245 .enum_mbus_code = gc4023_enum_mbus_code,
1246 .enum_frame_size = gc4023_enum_frame_sizes,
1247 .enum_frame_interval = gc4023_enum_frame_interval,
1248 .get_fmt = gc4023_get_fmt,
1249 .set_fmt = gc4023_set_fmt,
1250 .get_selection = gc4023_get_selection,
1251 .get_mbus_config = gc4023_g_mbus_config,
1252 };
1253
1254 static const struct v4l2_subdev_ops gc4023_subdev_ops = {
1255 .core = &gc4023_core_ops,
1256 .video = &gc4023_video_ops,
1257 .pad = &gc4023_pad_ops,
1258 };
1259
gc4023_set_ctrl(struct v4l2_ctrl * ctrl)1260 static int gc4023_set_ctrl(struct v4l2_ctrl *ctrl)
1261 {
1262 struct gc4023 *gc4023 = container_of(ctrl->handler,
1263 struct gc4023, ctrl_handler);
1264 struct i2c_client *client = gc4023->client;
1265 s64 max;
1266 int ret = 0;
1267 int mirror = 0, flip = 0;
1268 int otp_mirror = 0, otp_flip = 0;
1269
1270 /*Propagate change of current control to all related controls*/
1271 switch (ctrl->id) {
1272 case V4L2_CID_VBLANK:
1273 /*Update max exposure while meeting expected vblanking*/
1274 max = gc4023->cur_mode->height + ctrl->val - 4;
1275 __v4l2_ctrl_modify_range(gc4023->exposure,
1276 gc4023->exposure->minimum,
1277 max,
1278 gc4023->exposure->step,
1279 gc4023->exposure->default_value);
1280 break;
1281 }
1282
1283 if (!pm_runtime_get_if_in_use(&client->dev))
1284 return 0;
1285
1286 switch (ctrl->id) {
1287 case V4L2_CID_EXPOSURE:
1288 /* 4 least significant bits of expsoure are fractional part */
1289 ret = gc4023_write_reg(gc4023->client, GC4023_REG_EXPOSURE_H,
1290 GC4023_REG_VALUE_08BIT,
1291 ctrl->val >> 8);
1292 ret |= gc4023_write_reg(gc4023->client, GC4023_REG_EXPOSURE_L,
1293 GC4023_REG_VALUE_08BIT,
1294 ctrl->val & 0xff);
1295 break;
1296 case V4L2_CID_ANALOGUE_GAIN:
1297 ret = gc4023_set_gain_reg(gc4023, ctrl->val);
1298 break;
1299 case V4L2_CID_VBLANK:
1300 gc4023->cur_vts = ctrl->val + gc4023->cur_mode->height;
1301 ret = gc4023_write_reg(gc4023->client, GC4023_REG_VTS_H,
1302 GC4023_REG_VALUE_08BIT,
1303 gc4023->cur_vts >> 8);
1304 ret |= gc4023_write_reg(gc4023->client, GC4023_REG_VTS_L,
1305 GC4023_REG_VALUE_08BIT,
1306 gc4023->cur_vts & 0xff);
1307 break;
1308 case V4L2_CID_TEST_PATTERN:
1309 ret = gc4023_enable_test_pattern(gc4023, ctrl->val);
1310 break;
1311 case V4L2_CID_HFLIP:
1312 ret = gc4023_read_reg(gc4023->client, GC4023_MIRROR_FLIP_REG,
1313 GC4023_REG_VALUE_08BIT, &mirror);
1314 ret |= gc4023_read_reg(gc4023->client, GC4023_OTP_MIRROR_FLIP_REG,
1315 GC4023_REG_VALUE_08BIT, &otp_mirror);
1316 if (ctrl->val) {
1317 mirror |= GC4023_MIRROR_BIT_MASK;
1318 otp_mirror |= GC4023_MIRROR_BIT_MASK;
1319 } else {
1320 mirror &= ~GC4023_MIRROR_BIT_MASK;
1321 otp_mirror &= ~GC4023_MIRROR_BIT_MASK;
1322 }
1323 ret |= gc4023_set_mirror_flip(gc4023, mirror, otp_mirror);
1324 break;
1325 case V4L2_CID_VFLIP:
1326 ret = gc4023_read_reg(gc4023->client, GC4023_MIRROR_FLIP_REG,
1327 GC4023_REG_VALUE_08BIT, &flip);
1328 ret |= gc4023_read_reg(gc4023->client, GC4023_OTP_MIRROR_FLIP_REG,
1329 GC4023_REG_VALUE_08BIT, &otp_flip);
1330 if (ctrl->val) {
1331 flip |= GC4023_FLIP_BIT_MASK;
1332 otp_flip |= GC4023_FLIP_BIT_MASK;
1333 } else {
1334 flip &= ~GC4023_FLIP_BIT_MASK;
1335 otp_flip &= ~GC4023_FLIP_BIT_MASK;
1336 }
1337 ret |= gc4023_set_mirror_flip(gc4023, flip, otp_flip);
1338 break;
1339 default:
1340 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1341 __func__, ctrl->id, ctrl->val);
1342 break;
1343 }
1344
1345 pm_runtime_put(&client->dev);
1346
1347 return ret;
1348 }
1349
1350 static const struct v4l2_ctrl_ops gc4023_ctrl_ops = {
1351 .s_ctrl = gc4023_set_ctrl,
1352 };
1353
gc4023_initialize_controls(struct gc4023 * gc4023)1354 static int gc4023_initialize_controls(struct gc4023 *gc4023)
1355 {
1356 const struct gc4023_mode *mode;
1357 struct v4l2_ctrl_handler *handler;
1358 s64 exposure_max, vblank_def;
1359 u32 h_blank;
1360 int ret;
1361
1362 handler = &gc4023->ctrl_handler;
1363 mode = gc4023->cur_mode;
1364 ret = v4l2_ctrl_handler_init(handler, 9);
1365 if (ret)
1366 return ret;
1367 handler->lock = &gc4023->mutex;
1368
1369 gc4023->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1370 1, 0, link_freq_menu_items);
1371
1372 gc4023->cur_link_freq = 0;
1373 gc4023->cur_pixel_rate = GC4023_PIXEL_RATE_LINEAR;
1374
1375
1376 __v4l2_ctrl_s_ctrl(gc4023->link_freq,
1377 gc4023->cur_link_freq);
1378
1379 gc4023->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1380 0, GC4023_PIXEL_RATE_LINEAR, 1, GC4023_PIXEL_RATE_LINEAR);
1381
1382 h_blank = mode->hts_def - mode->width;
1383 gc4023->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1384 h_blank, h_blank, 1, h_blank);
1385 if (gc4023->hblank)
1386 gc4023->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1387
1388 vblank_def = mode->vts_def - mode->height;
1389 gc4023->cur_vts = mode->vts_def;
1390 gc4023->vblank = v4l2_ctrl_new_std(handler, &gc4023_ctrl_ops,
1391 V4L2_CID_VBLANK, vblank_def,
1392 GC4023_VTS_MAX - mode->height,
1393 1, vblank_def);
1394
1395 exposure_max = mode->vts_def - 4;
1396 gc4023->exposure = v4l2_ctrl_new_std(handler, &gc4023_ctrl_ops,
1397 V4L2_CID_EXPOSURE,
1398 GC4023_EXPOSURE_MIN,
1399 exposure_max,
1400 GC4023_EXPOSURE_STEP,
1401 mode->exp_def);
1402
1403 gc4023->anal_gain = v4l2_ctrl_new_std(handler, &gc4023_ctrl_ops,
1404 V4L2_CID_ANALOGUE_GAIN,
1405 GC4023_GAIN_MIN,
1406 GC4023_GAIN_MAX,
1407 GC4023_GAIN_STEP,
1408 GC4023_GAIN_DEFAULT);
1409
1410 gc4023->test_pattern =
1411 v4l2_ctrl_new_std_menu_items(handler,
1412 &gc4023_ctrl_ops,
1413 V4L2_CID_TEST_PATTERN,
1414 ARRAY_SIZE(gc4023_test_pattern_menu) - 1,
1415 0, 0, gc4023_test_pattern_menu);
1416
1417 gc4023->h_flip = v4l2_ctrl_new_std(handler, &gc4023_ctrl_ops,
1418 V4L2_CID_HFLIP, 0, 1, 1, 0);
1419
1420 gc4023->v_flip = v4l2_ctrl_new_std(handler, &gc4023_ctrl_ops,
1421 V4L2_CID_VFLIP, 0, 1, 1, 0);
1422 if (handler->error) {
1423 ret = handler->error;
1424 dev_err(&gc4023->client->dev,
1425 "Failed to init controls(%d)\n", ret);
1426 goto err_free_handler;
1427 }
1428
1429 gc4023->subdev.ctrl_handler = handler;
1430 gc4023->has_init_exp = false;
1431
1432 return 0;
1433
1434 err_free_handler:
1435 v4l2_ctrl_handler_free(handler);
1436
1437 return ret;
1438 }
1439
gc4023_check_sensor_id(struct gc4023 * gc4023,struct i2c_client * client)1440 static int gc4023_check_sensor_id(struct gc4023 *gc4023,
1441 struct i2c_client *client)
1442 {
1443 struct device *dev = &gc4023->client->dev;
1444 u16 id = 0;
1445 u32 reg_H = 0;
1446 u32 reg_L = 0;
1447 int ret;
1448
1449 ret = gc4023_read_reg(client, GC4023_REG_CHIP_ID_H,
1450 GC4023_REG_VALUE_08BIT, ®_H);
1451 ret |= gc4023_read_reg(client, GC4023_REG_CHIP_ID_L,
1452 GC4023_REG_VALUE_08BIT, ®_L);
1453
1454 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
1455 if (!(reg_H == (CHIP_ID >> 8) || reg_L == (CHIP_ID & 0xff))) {
1456 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1457 return -ENODEV;
1458 }
1459 dev_info(dev, "detected gc%04x sensor\n", id);
1460 return 0;
1461 }
1462
gc4023_configure_regulators(struct gc4023 * gc4023)1463 static int gc4023_configure_regulators(struct gc4023 *gc4023)
1464 {
1465 unsigned int i;
1466
1467 for (i = 0; i < GC4023_NUM_SUPPLIES; i++)
1468 gc4023->supplies[i].supply = gc4023_supply_names[i];
1469
1470 return devm_regulator_bulk_get(&gc4023->client->dev,
1471 GC4023_NUM_SUPPLIES,
1472 gc4023->supplies);
1473 }
1474
gc4023_probe(struct i2c_client * client,const struct i2c_device_id * id)1475 static int gc4023_probe(struct i2c_client *client,
1476 const struct i2c_device_id *id)
1477 {
1478 struct device *dev = &client->dev;
1479 struct device_node *node = dev->of_node;
1480 struct gc4023 *gc4023;
1481 struct v4l2_subdev *sd;
1482 char facing[2];
1483 int ret;
1484 u32 i, hdr_mode = 0;
1485
1486 dev_info(dev, "driver version: %02x.%02x.%02x",
1487 DRIVER_VERSION >> 16,
1488 (DRIVER_VERSION & 0xff00) >> 8,
1489 DRIVER_VERSION & 0x00ff);
1490
1491 gc4023 = devm_kzalloc(dev, sizeof(*gc4023), GFP_KERNEL);
1492 if (!gc4023)
1493 return -ENOMEM;
1494
1495 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1496 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1497 &gc4023->module_index);
1498 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1499 &gc4023->module_facing);
1500 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1501 &gc4023->module_name);
1502 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1503 &gc4023->len_name);
1504 if (ret) {
1505 dev_err(dev, "could not get module information!\n");
1506 return -EINVAL;
1507 }
1508
1509 gc4023->client = client;
1510 gc4023->cfg_num = ARRAY_SIZE(supported_modes);
1511 for (i = 0; i < gc4023->cfg_num; i++) {
1512 if (hdr_mode == supported_modes[i].hdr_mode) {
1513 gc4023->cur_mode = &supported_modes[i];
1514 break;
1515 }
1516 }
1517 if (i == gc4023->cfg_num)
1518 gc4023->cur_mode = &supported_modes[0];
1519
1520 gc4023->xvclk = devm_clk_get(dev, "xvclk");
1521 if (IS_ERR(gc4023->xvclk)) {
1522 dev_err(dev, "Failed to get xvclk\n");
1523 return -EINVAL;
1524 }
1525
1526 gc4023->pwren_gpio = devm_gpiod_get(dev, "pwren", GPIOD_OUT_LOW);
1527 if (IS_ERR(gc4023->pwren_gpio))
1528 dev_warn(dev, "Failed to get pwren-gpios\n");
1529
1530 gc4023->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1531 if (IS_ERR(gc4023->reset_gpio))
1532 dev_warn(dev, "Failed to get reset-gpios\n");
1533
1534 gc4023->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1535 if (IS_ERR(gc4023->pwdn_gpio))
1536 dev_warn(dev, "Failed to get pwdn-gpios\n");
1537
1538 gc4023->pinctrl = devm_pinctrl_get(dev);
1539 if (!IS_ERR(gc4023->pinctrl)) {
1540 gc4023->pins_default =
1541 pinctrl_lookup_state(gc4023->pinctrl,
1542 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1543 if (IS_ERR(gc4023->pins_default))
1544 dev_err(dev, "could not get default pinstate\n");
1545
1546 gc4023->pins_sleep =
1547 pinctrl_lookup_state(gc4023->pinctrl,
1548 OF_CAMERA_PINCTRL_STATE_SLEEP);
1549 if (IS_ERR(gc4023->pins_sleep))
1550 dev_err(dev, "could not get sleep pinstate\n");
1551 } else {
1552 dev_err(dev, "no pinctrl\n");
1553 }
1554
1555 ret = gc4023_configure_regulators(gc4023);
1556 if (ret) {
1557 dev_err(dev, "Failed to get power regulators\n");
1558 return ret;
1559 }
1560
1561 mutex_init(&gc4023->mutex);
1562
1563 sd = &gc4023->subdev;
1564 v4l2_i2c_subdev_init(sd, client, &gc4023_subdev_ops);
1565 ret = gc4023_initialize_controls(gc4023);
1566 if (ret)
1567 goto err_destroy_mutex;
1568
1569 ret = __gc4023_power_on(gc4023);
1570 if (ret)
1571 goto err_free_handler;
1572
1573 usleep_range(3000, 4000);
1574
1575 ret = gc4023_check_sensor_id(gc4023, client);
1576 if (ret)
1577 goto err_power_off;
1578
1579 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1580 sd->internal_ops = &gc4023_internal_ops;
1581 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1582 V4L2_SUBDEV_FL_HAS_EVENTS;
1583 #endif
1584 #if defined(CONFIG_MEDIA_CONTROLLER)
1585 gc4023->pad.flags = MEDIA_PAD_FL_SOURCE;
1586 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1587 ret = media_entity_pads_init(&sd->entity, 1, &gc4023->pad);
1588 if (ret < 0)
1589 goto err_power_off;
1590 #endif
1591
1592 memset(facing, 0, sizeof(facing));
1593 if (strcmp(gc4023->module_facing, "back") == 0)
1594 facing[0] = 'b';
1595 else
1596 facing[0] = 'f';
1597
1598 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1599 gc4023->module_index, facing,
1600 GC4023_NAME, dev_name(sd->dev));
1601 ret = v4l2_async_register_subdev_sensor_common(sd);
1602 if (ret) {
1603 dev_err(dev, "v4l2 async register subdev failed\n");
1604 goto err_clean_entity;
1605 }
1606
1607 pm_runtime_set_active(dev);
1608 pm_runtime_enable(dev);
1609 pm_runtime_idle(dev);
1610
1611 return 0;
1612
1613 err_clean_entity:
1614 #if defined(CONFIG_MEDIA_CONTROLLER)
1615 media_entity_cleanup(&sd->entity);
1616 #endif
1617 err_power_off:
1618 __gc4023_power_off(gc4023);
1619 err_free_handler:
1620 v4l2_ctrl_handler_free(&gc4023->ctrl_handler);
1621 err_destroy_mutex:
1622 mutex_destroy(&gc4023->mutex);
1623
1624 return ret;
1625 }
1626
gc4023_remove(struct i2c_client * client)1627 static int gc4023_remove(struct i2c_client *client)
1628 {
1629 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1630 struct gc4023 *gc4023 = to_gc4023(sd);
1631
1632 v4l2_async_unregister_subdev(sd);
1633 #if defined(CONFIG_MEDIA_CONTROLLER)
1634 media_entity_cleanup(&sd->entity);
1635 #endif
1636 v4l2_ctrl_handler_free(&gc4023->ctrl_handler);
1637 mutex_destroy(&gc4023->mutex);
1638
1639 pm_runtime_disable(&client->dev);
1640 if (!pm_runtime_status_suspended(&client->dev))
1641 __gc4023_power_off(gc4023);
1642 pm_runtime_set_suspended(&client->dev);
1643
1644 return 0;
1645 }
1646
1647 #if IS_ENABLED(CONFIG_OF)
1648 static const struct of_device_id gc4023_of_match[] = {
1649 { .compatible = "galaxycore,gc4023" },
1650 {},
1651 };
1652 MODULE_DEVICE_TABLE(of, gc4023_of_match);
1653 #endif
1654
1655 static const struct i2c_device_id gc4023_match_id[] = {
1656 { "galaxycore,gc4023", 0 },
1657 { },
1658 };
1659
1660 static struct i2c_driver gc4023_i2c_driver = {
1661 .driver = {
1662 .name = GC4023_NAME,
1663 .pm = &gc4023_pm_ops,
1664 .of_match_table = of_match_ptr(gc4023_of_match),
1665 },
1666 .probe = &gc4023_probe,
1667 .remove = &gc4023_remove,
1668 .id_table = gc4023_match_id,
1669 };
1670
sensor_mod_init(void)1671 static int __init sensor_mod_init(void)
1672 {
1673 return i2c_add_driver(&gc4023_i2c_driver);
1674 }
1675
sensor_mod_exit(void)1676 static void __exit sensor_mod_exit(void)
1677 {
1678 i2c_del_driver(&gc4023_i2c_driver);
1679 }
1680
1681 device_initcall_sync(sensor_mod_init);
1682 module_exit(sensor_mod_exit);
1683
1684 MODULE_DESCRIPTION("galaxycore gc4023 sensor driver");
1685 MODULE_LICENSE("GPL");
1686