1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc2385 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 add enum_frame_interval function.
10 * V0.0X01.0X04 add quick stream on/off
11 * V0.0X01.0X05 add function g_mbus_config
12 * V0.0X01.0X06 set max framerate to strictly 30FPS for cts
13 */
14
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/delay.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/sysfs.h>
24 #include <linux/version.h>
25 #include <linux/rk-camera-module.h>
26 #include <media/media-entity.h>
27 #include <media/v4l2-async.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-subdev.h>
30 #include <linux/pinctrl/consumer.h>
31
32 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
33
34 #ifndef V4L2_CID_DIGITAL_GAIN
35 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
36 #endif
37
38 #define GC2385_LANES 1
39 #define GC2385_BITS_PER_SAMPLE 10
40 #define GC2385_LINK_FREQ_MHZ 328000000
41 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
42 #define GC2385_PIXEL_RATE (GC2385_LINK_FREQ_MHZ * 2 * 1 / 10)
43 #define GC2385_XVCLK_FREQ 24000000
44
45 #define CHIP_ID 0x2385
46 #define GC2385_REG_CHIP_ID_H 0xf0
47 #define GC2385_REG_CHIP_ID_L 0xf1
48
49 #define GC2385_REG_SET_PAGE 0xfe
50 #define GC2385_SET_PAGE_ONE 0x00
51
52 #define GC2385_REG_CTRL_MODE 0xed
53 #define GC2385_MODE_SW_STANDBY 0x00
54 #define GC2385_MODE_STREAMING 0x90
55
56 #define GC2385_REG_EXPOSURE_H 0x03
57 #define GC2385_REG_EXPOSURE_L 0x04
58 #define GC2385_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0x3F) /* 6 Bits */
59 #define GC2385_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 8 Bits */
60 #define GC2385_EXPOSURE_MIN 4
61 #define GC2385_EXPOSURE_STEP 1
62 #define GC2385_VTS_MAX 0x1fff
63
64 #define GC2385_REG_AGAIN 0xb6
65 #define GC2385_REG_DGAIN_INT 0xb1
66 #define GC2385_REG_DGAIN_FRAC 0xb2
67 #define GC2385_GAIN_MIN 64
68 #define GC2385_GAIN_MAX 1092
69 #define GC2385_GAIN_STEP 1
70 #define GC2385_GAIN_DEFAULT 64
71
72 #define GC2385_REG_VTS_H 0x07
73 #define GC2385_REG_VTS_L 0x08
74
75 #define REG_NULL 0xFF
76
77 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
78 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
79
80 #define GC2385_NAME "gc2385"
81
82 static const char * const gc2385_supply_names[] = {
83 "avdd", /* Analog power */
84 "dovdd", /* Digital I/O power */
85 "dvdd", /* Digital core power */
86 };
87
88 #define GC2385_NUM_SUPPLIES ARRAY_SIZE(gc2385_supply_names)
89
90 struct regval {
91 u8 addr;
92 u8 val;
93 };
94
95 struct gc2385_mode {
96 u32 width;
97 u32 height;
98 struct v4l2_fract max_fps;
99 u32 hts_def;
100 u32 vts_def;
101 u32 exp_def;
102 const struct regval *reg_list;
103 };
104
105 struct gc2385 {
106 struct i2c_client *client;
107 struct clk *xvclk;
108 struct gpio_desc *reset_gpio;
109 struct gpio_desc *pwdn_gpio;
110 struct regulator_bulk_data supplies[GC2385_NUM_SUPPLIES];
111 struct pinctrl *pinctrl;
112 struct pinctrl_state *pins_default;
113 struct pinctrl_state *pins_sleep;
114 struct v4l2_subdev subdev;
115 struct media_pad pad;
116 struct v4l2_ctrl_handler ctrl_handler;
117 struct v4l2_ctrl *exposure;
118 struct v4l2_ctrl *anal_gain;
119 struct v4l2_ctrl *digi_gain;
120 struct v4l2_ctrl *hblank;
121 struct v4l2_ctrl *vblank;
122 struct mutex mutex;
123 bool streaming;
124 bool power_on;
125 const struct gc2385_mode *cur_mode;
126 u32 module_index;
127 const char *module_facing;
128 const char *module_name;
129 const char *len_name;
130 };
131
132 #define to_gc2385(sd) container_of(sd, struct gc2385, subdev)
133
134 /*
135 * Xclk 24Mhz
136 */
137 static const struct regval gc2385_global_regs[] = {
138 {REG_NULL, 0x00},
139 };
140
141 /*
142 * Xclk 24Mhz
143 * max_framerate 30fps
144 * mipi_datarate per lane 656Mbps
145 */
146 static const struct regval gc2385_1600x1200_regs[] = {
147 {0xfe, 0x00},
148 {0xfe, 0x00},
149 {0xfe, 0x00},
150 {0xf2, 0x02},
151 {0xf4, 0x03},
152 {0xf7, 0x01},
153 {0xf8, 0x28},
154 {0xf9, 0x02},
155 {0xfa, 0x08},
156 {0xfc, 0x8e},
157 {0xe7, 0xcc},
158 {0x88, 0x03},
159 {0x03, 0x04},
160 {0x04, 0x80},
161 {0x05, 0x02},
162 {0x06, 0x86},
163 {0x07, 0x00},
164 {0x08, 0x10},
165 {0x09, 0x00},
166 {0x0a, 0x04},
167 {0x0b, 0x00},
168 {0x0c, 0x02},
169 {0x17, 0xd4},
170 {0x18, 0x02},
171 {0x19, 0x17},
172 {0x1c, 0x18},
173 {0x20, 0x73},
174 {0x21, 0x38},
175 {0x22, 0xa2},
176 {0x29, 0x20},
177 {0x2f, 0x14},
178 {0x3f, 0x40},
179 {0xcd, 0x94},
180 {0xce, 0x45},
181 {0xd1, 0x0c},
182 {0xd7, 0x9b},
183 {0xd8, 0x99},
184 {0xda, 0x3b},
185 {0xd9, 0xb5},
186 {0xdb, 0x75},
187 {0xe3, 0x1b},
188 {0xe4, 0xf8},
189 {0x40, 0x22},
190 {0x43, 0x07},
191 {0x4e, 0x3c},
192 {0x4f, 0x00},
193 {0x68, 0x00},
194 {0xb0, 0x46},
195 {0xb1, 0x01},
196 {0xb2, 0x00},
197 {0xb6, 0x00},
198 {0x90, 0x01},
199 {0x92, 0x03},
200 {0x94, 0x05},
201 {0x95, 0x04},
202 {0x96, 0xb0},
203 {0x97, 0x06},
204 {0x98, 0x40},
205 {0xfe, 0x00},
206 {0xed, 0x00},
207 {0xfe, 0x03},
208 {0x01, 0x03},
209 {0x02, 0x82},
210 {0x03, 0xd0},
211 {0x04, 0x04},
212 {0x05, 0x00},
213 {0x06, 0x80},
214 {0x11, 0x2b},
215 {0x12, 0xd0},
216 {0x13, 0x07},
217 {0x15, 0x00},
218 {0x1b, 0x10},
219 {0x1c, 0x10},
220 {0x21, 0x08},
221 {0x22, 0x05},
222 {0x23, 0x13},
223 {0x24, 0x02},
224 {0x25, 0x13},
225 {0x26, 0x06},
226 {0x29, 0x06},
227 {0x2a, 0x08},
228 {0x2b, 0x06},
229 {0xfe, 0x00},
230 {REG_NULL, 0x00},
231 };
232
233 static const struct gc2385_mode supported_modes[] = {
234 {
235 .width = 1600,
236 .height = 1200,
237 .max_fps = {
238 .numerator = 10000,
239 .denominator = 300000,
240 },
241 .exp_def = 0x0480,
242 .hts_def = 0x10DC,
243 .vts_def = 0x04F0,
244 .reg_list = gc2385_1600x1200_regs,
245 },
246 };
247
248 static const s64 link_freq_menu_items[] = {
249 GC2385_LINK_FREQ_MHZ
250 };
251
252 /* Write registers up to 4 at a time */
gc2385_write_reg(struct i2c_client * client,u8 reg,u8 val)253 static int gc2385_write_reg(struct i2c_client *client, u8 reg, u8 val)
254 {
255 struct i2c_msg msg;
256 u8 buf[2];
257 int ret;
258
259 buf[0] = reg & 0xFF;
260 buf[1] = val;
261
262 msg.addr = client->addr;
263 msg.flags = client->flags;
264 msg.buf = buf;
265 msg.len = sizeof(buf);
266
267 ret = i2c_transfer(client->adapter, &msg, 1);
268 if (ret >= 0)
269 return 0;
270
271 dev_err(&client->dev,
272 "gc2385 write reg(0x%x val:0x%x) failed !\n", reg, val);
273
274 return ret;
275 }
276
gc2385_write_array(struct i2c_client * client,const struct regval * regs)277 static int gc2385_write_array(struct i2c_client *client,
278 const struct regval *regs)
279 {
280 u32 i = 0;
281 int ret = 0;
282
283 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
284 ret = gc2385_write_reg(client, regs[i].addr, regs[i].val);
285
286 return ret;
287 }
288
289 /* Read registers up to 4 at a time */
gc2385_read_reg(struct i2c_client * client,u8 reg,u8 * val)290 static int gc2385_read_reg(struct i2c_client *client, u8 reg, u8 *val)
291 {
292 struct i2c_msg msg[2];
293 u8 buf[1];
294 int ret;
295
296 buf[0] = reg & 0xFF;
297
298 msg[0].addr = client->addr;
299 msg[0].flags = client->flags;
300 msg[0].buf = buf;
301 msg[0].len = sizeof(buf);
302
303 msg[1].addr = client->addr;
304 msg[1].flags = client->flags | I2C_M_RD;
305 msg[1].buf = buf;
306 msg[1].len = 1;
307
308 ret = i2c_transfer(client->adapter, msg, 2);
309 if (ret >= 0) {
310 *val = buf[0];
311 return 0;
312 }
313
314 dev_err(&client->dev,
315 "gc2385 read reg:0x%x failed !\n", reg);
316
317 return ret;
318 }
319
gc2385_get_reso_dist(const struct gc2385_mode * mode,struct v4l2_mbus_framefmt * framefmt)320 static int gc2385_get_reso_dist(const struct gc2385_mode *mode,
321 struct v4l2_mbus_framefmt *framefmt)
322 {
323 return abs(mode->width - framefmt->width) +
324 abs(mode->height - framefmt->height);
325 }
326
327 static const struct gc2385_mode *
gc2385_find_best_fit(struct v4l2_subdev_format * fmt)328 gc2385_find_best_fit(struct v4l2_subdev_format *fmt)
329 {
330 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
331 int dist;
332 int cur_best_fit = 0;
333 int cur_best_fit_dist = -1;
334 unsigned int i;
335
336 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
337 dist = gc2385_get_reso_dist(&supported_modes[i], framefmt);
338 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
339 cur_best_fit_dist = dist;
340 cur_best_fit = i;
341 }
342 }
343
344 return &supported_modes[cur_best_fit];
345 }
346
gc2385_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)347 static int gc2385_set_fmt(struct v4l2_subdev *sd,
348 struct v4l2_subdev_pad_config *cfg,
349 struct v4l2_subdev_format *fmt)
350 {
351 struct gc2385 *gc2385 = to_gc2385(sd);
352 const struct gc2385_mode *mode;
353 s64 h_blank, vblank_def;
354
355 mutex_lock(&gc2385->mutex);
356
357 mode = gc2385_find_best_fit(fmt);
358 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
359 fmt->format.width = mode->width;
360 fmt->format.height = mode->height;
361 fmt->format.field = V4L2_FIELD_NONE;
362 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
363 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
364 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
365 #else
366 mutex_unlock(&gc2385->mutex);
367 return -ENOTTY;
368 #endif
369 } else {
370 gc2385->cur_mode = mode;
371 h_blank = mode->hts_def - mode->width;
372 __v4l2_ctrl_modify_range(gc2385->hblank, h_blank,
373 h_blank, 1, h_blank);
374 vblank_def = mode->vts_def - mode->height;
375 __v4l2_ctrl_modify_range(gc2385->vblank, vblank_def,
376 GC2385_VTS_MAX - mode->height,
377 1, vblank_def);
378 }
379
380 mutex_unlock(&gc2385->mutex);
381
382 return 0;
383 }
384
gc2385_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)385 static int gc2385_get_fmt(struct v4l2_subdev *sd,
386 struct v4l2_subdev_pad_config *cfg,
387 struct v4l2_subdev_format *fmt)
388 {
389 struct gc2385 *gc2385 = to_gc2385(sd);
390 const struct gc2385_mode *mode = gc2385->cur_mode;
391
392 mutex_lock(&gc2385->mutex);
393 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
394 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
395 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
396 #else
397 mutex_unlock(&gc2385->mutex);
398 return -ENOTTY;
399 #endif
400 } else {
401 fmt->format.width = mode->width;
402 fmt->format.height = mode->height;
403 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
404 fmt->format.field = V4L2_FIELD_NONE;
405 }
406 mutex_unlock(&gc2385->mutex);
407
408 return 0;
409 }
410
gc2385_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)411 static int gc2385_enum_mbus_code(struct v4l2_subdev *sd,
412 struct v4l2_subdev_pad_config *cfg,
413 struct v4l2_subdev_mbus_code_enum *code)
414 {
415 if (code->index != 0)
416 return -EINVAL;
417 code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
418
419 return 0;
420 }
421
gc2385_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)422 static int gc2385_enum_frame_sizes(struct v4l2_subdev *sd,
423 struct v4l2_subdev_pad_config *cfg,
424 struct v4l2_subdev_frame_size_enum *fse)
425 {
426 if (fse->index >= ARRAY_SIZE(supported_modes))
427 return -EINVAL;
428
429 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
430 return -EINVAL;
431
432 fse->min_width = supported_modes[fse->index].width;
433 fse->max_width = supported_modes[fse->index].width;
434 fse->max_height = supported_modes[fse->index].height;
435 fse->min_height = supported_modes[fse->index].height;
436
437 return 0;
438 }
439
gc2385_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)440 static int gc2385_g_frame_interval(struct v4l2_subdev *sd,
441 struct v4l2_subdev_frame_interval *fi)
442 {
443 struct gc2385 *gc2385 = to_gc2385(sd);
444 const struct gc2385_mode *mode = gc2385->cur_mode;
445
446 fi->interval = mode->max_fps;
447
448 return 0;
449 }
450
gc2385_get_module_inf(struct gc2385 * gc2385,struct rkmodule_inf * inf)451 static void gc2385_get_module_inf(struct gc2385 *gc2385,
452 struct rkmodule_inf *inf)
453 {
454 memset(inf, 0, sizeof(*inf));
455 strlcpy(inf->base.sensor, GC2385_NAME, sizeof(inf->base.sensor));
456 strlcpy(inf->base.module, gc2385->module_name,
457 sizeof(inf->base.module));
458 strlcpy(inf->base.lens, gc2385->len_name, sizeof(inf->base.lens));
459 }
460
gc2385_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)461 static long gc2385_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
462 {
463 struct gc2385 *gc2385 = to_gc2385(sd);
464 long ret = 0;
465 u32 stream = 0;
466
467 switch (cmd) {
468 case RKMODULE_GET_MODULE_INFO:
469 gc2385_get_module_inf(gc2385, (struct rkmodule_inf *)arg);
470 break;
471 case RKMODULE_SET_QUICK_STREAM:
472
473 stream = *((u32 *)arg);
474
475 if (stream) {
476 ret = gc2385_write_reg(gc2385->client,
477 GC2385_REG_SET_PAGE,
478 GC2385_SET_PAGE_ONE);
479 ret |= gc2385_write_reg(gc2385->client,
480 GC2385_REG_CTRL_MODE,
481 GC2385_MODE_STREAMING);
482 } else {
483 ret = gc2385_write_reg(gc2385->client,
484 GC2385_REG_SET_PAGE, GC2385_SET_PAGE_ONE);
485 ret |= gc2385_write_reg(gc2385->client,
486 GC2385_REG_CTRL_MODE, GC2385_MODE_SW_STANDBY);
487 }
488 break;
489 default:
490 ret = -ENOTTY;
491 break;
492 }
493
494 return ret;
495 }
496
497 #ifdef CONFIG_COMPAT
gc2385_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)498 static long gc2385_compat_ioctl32(struct v4l2_subdev *sd,
499 unsigned int cmd, unsigned long arg)
500 {
501 void __user *up = compat_ptr(arg);
502 struct rkmodule_inf *inf;
503 struct rkmodule_awb_cfg *cfg;
504 long ret;
505 u32 stream = 0;
506
507 switch (cmd) {
508 case RKMODULE_GET_MODULE_INFO:
509 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
510 if (!inf) {
511 ret = -ENOMEM;
512 return ret;
513 }
514
515 ret = gc2385_ioctl(sd, cmd, inf);
516 if (!ret)
517 ret = copy_to_user(up, inf, sizeof(*inf));
518 kfree(inf);
519 break;
520 case RKMODULE_AWB_CFG:
521 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
522 if (!cfg) {
523 ret = -ENOMEM;
524 return ret;
525 }
526
527 ret = copy_from_user(cfg, up, sizeof(*cfg));
528 if (!ret)
529 ret = gc2385_ioctl(sd, cmd, cfg);
530 kfree(cfg);
531 break;
532 case RKMODULE_SET_QUICK_STREAM:
533 ret = copy_from_user(&stream, up, sizeof(u32));
534 if (!ret)
535 ret = gc2385_ioctl(sd, cmd, &stream);
536 break;
537 default:
538 ret = -ENOIOCTLCMD;
539 break;
540 }
541
542 return ret;
543 }
544 #endif
545
__gc2385_start_stream(struct gc2385 * gc2385)546 static int __gc2385_start_stream(struct gc2385 *gc2385)
547 {
548 int ret;
549
550 ret = gc2385_write_array(gc2385->client, gc2385->cur_mode->reg_list);
551 if (ret)
552 return ret;
553
554 /* In case these controls are set before streaming */
555 mutex_unlock(&gc2385->mutex);
556 ret = v4l2_ctrl_handler_setup(&gc2385->ctrl_handler);
557 mutex_lock(&gc2385->mutex);
558 if (ret)
559 return ret;
560 ret = gc2385_write_reg(gc2385->client,
561 GC2385_REG_SET_PAGE,
562 GC2385_SET_PAGE_ONE);
563 ret |= gc2385_write_reg(gc2385->client,
564 GC2385_REG_CTRL_MODE,
565 GC2385_MODE_STREAMING);
566 return ret;
567 }
568
__gc2385_stop_stream(struct gc2385 * gc2385)569 static int __gc2385_stop_stream(struct gc2385 *gc2385)
570 {
571 int ret;
572
573 ret = gc2385_write_reg(gc2385->client,
574 GC2385_REG_SET_PAGE, GC2385_SET_PAGE_ONE);
575 ret |= gc2385_write_reg(gc2385->client,
576 GC2385_REG_CTRL_MODE, GC2385_MODE_SW_STANDBY);
577 return ret;
578 }
579
gc2385_s_stream(struct v4l2_subdev * sd,int on)580 static int gc2385_s_stream(struct v4l2_subdev *sd, int on)
581 {
582 struct gc2385 *gc2385 = to_gc2385(sd);
583 struct i2c_client *client = gc2385->client;
584 int ret = 0;
585
586 mutex_lock(&gc2385->mutex);
587 on = !!on;
588 if (on == gc2385->streaming)
589 goto unlock_and_return;
590
591 if (on) {
592 ret = pm_runtime_get_sync(&client->dev);
593 if (ret < 0) {
594 pm_runtime_put_noidle(&client->dev);
595 goto unlock_and_return;
596 }
597
598 ret = __gc2385_start_stream(gc2385);
599 if (ret) {
600 v4l2_err(sd, "start stream failed while write regs\n");
601 pm_runtime_put(&client->dev);
602 goto unlock_and_return;
603 }
604 } else {
605 __gc2385_stop_stream(gc2385);
606 pm_runtime_put(&client->dev);
607 }
608
609 gc2385->streaming = on;
610
611 unlock_and_return:
612 mutex_unlock(&gc2385->mutex);
613
614 return ret;
615 }
616
gc2385_s_power(struct v4l2_subdev * sd,int on)617 static int gc2385_s_power(struct v4l2_subdev *sd, int on)
618 {
619 struct gc2385 *gc2385 = to_gc2385(sd);
620 struct i2c_client *client = gc2385->client;
621 int ret = 0;
622
623 mutex_lock(&gc2385->mutex);
624
625 /* If the power state is not modified - no work to do. */
626 if (gc2385->power_on == !!on)
627 goto unlock_and_return;
628
629 if (on) {
630 ret = pm_runtime_get_sync(&client->dev);
631 if (ret < 0) {
632 pm_runtime_put_noidle(&client->dev);
633 goto unlock_and_return;
634 }
635
636 ret = gc2385_write_array(gc2385->client, gc2385_global_regs);
637 if (ret) {
638 v4l2_err(sd, "could not set init registers\n");
639 pm_runtime_put_noidle(&client->dev);
640 goto unlock_and_return;
641 }
642
643 gc2385->power_on = true;
644 } else {
645 pm_runtime_put(&client->dev);
646 gc2385->power_on = false;
647 }
648
649 unlock_and_return:
650 mutex_unlock(&gc2385->mutex);
651
652 return ret;
653 }
654
655 /* Calculate the delay in us by clock rate and clock cycles */
gc2385_cal_delay(u32 cycles)656 static inline u32 gc2385_cal_delay(u32 cycles)
657 {
658 return DIV_ROUND_UP(cycles, GC2385_XVCLK_FREQ / 1000 / 1000);
659 }
660
__gc2385_power_on(struct gc2385 * gc2385)661 static int __gc2385_power_on(struct gc2385 *gc2385)
662 {
663 int ret;
664 u32 delay_us;
665 struct device *dev = &gc2385->client->dev;
666
667 if (!IS_ERR_OR_NULL(gc2385->pins_default)) {
668 ret = pinctrl_select_state(gc2385->pinctrl,
669 gc2385->pins_default);
670 if (ret < 0)
671 dev_err(dev, "could not set pins\n");
672 }
673 ret = clk_set_rate(gc2385->xvclk, GC2385_XVCLK_FREQ);
674 if (ret < 0)
675 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
676 if (clk_get_rate(gc2385->xvclk) != GC2385_XVCLK_FREQ)
677 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
678 ret = clk_prepare_enable(gc2385->xvclk);
679 if (ret < 0) {
680 dev_err(dev, "Failed to enable xvclk\n");
681 return ret;
682 }
683 if (!IS_ERR(gc2385->reset_gpio))
684 gpiod_set_value_cansleep(gc2385->reset_gpio, 1);
685
686 ret = regulator_bulk_enable(GC2385_NUM_SUPPLIES, gc2385->supplies);
687 if (ret < 0) {
688 dev_err(dev, "Failed to enable regulators\n");
689 goto disable_clk;
690 }
691
692 usleep_range(1000, 1100);
693 if (!IS_ERR(gc2385->reset_gpio))
694 gpiod_set_value_cansleep(gc2385->reset_gpio, 0);
695
696 usleep_range(500, 1000);
697 if (!IS_ERR(gc2385->pwdn_gpio))
698 gpiod_set_value_cansleep(gc2385->pwdn_gpio, 1);
699
700 /* 8192 cycles prior to first SCCB transaction */
701 delay_us = gc2385_cal_delay(8192);
702 usleep_range(delay_us, delay_us * 2);
703
704 return 0;
705
706 disable_clk:
707 clk_disable_unprepare(gc2385->xvclk);
708
709 return ret;
710 }
711
__gc2385_power_off(struct gc2385 * gc2385)712 static void __gc2385_power_off(struct gc2385 *gc2385)
713 {
714 int ret = 0;
715
716 if (!IS_ERR(gc2385->pwdn_gpio))
717 gpiod_set_value_cansleep(gc2385->pwdn_gpio, 0);
718 clk_disable_unprepare(gc2385->xvclk);
719 if (!IS_ERR(gc2385->reset_gpio))
720 gpiod_set_value_cansleep(gc2385->reset_gpio, 1);
721 if (!IS_ERR_OR_NULL(gc2385->pins_sleep)) {
722 ret = pinctrl_select_state(gc2385->pinctrl,
723 gc2385->pins_sleep);
724 if (ret < 0)
725 dev_dbg(&gc2385->client->dev, "could not set pins\n");
726 }
727 regulator_bulk_disable(GC2385_NUM_SUPPLIES, gc2385->supplies);
728 }
729
gc2385_runtime_resume(struct device * dev)730 static int __maybe_unused gc2385_runtime_resume(struct device *dev)
731 {
732 struct i2c_client *client = to_i2c_client(dev);
733 struct v4l2_subdev *sd = i2c_get_clientdata(client);
734 struct gc2385 *gc2385 = to_gc2385(sd);
735
736 return __gc2385_power_on(gc2385);
737 }
738
gc2385_runtime_suspend(struct device * dev)739 static int __maybe_unused gc2385_runtime_suspend(struct device *dev)
740 {
741 struct i2c_client *client = to_i2c_client(dev);
742 struct v4l2_subdev *sd = i2c_get_clientdata(client);
743 struct gc2385 *gc2385 = to_gc2385(sd);
744
745 __gc2385_power_off(gc2385);
746
747 return 0;
748 }
749
750 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc2385_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)751 static int gc2385_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
752 {
753 struct gc2385 *gc2385 = to_gc2385(sd);
754 struct v4l2_mbus_framefmt *try_fmt =
755 v4l2_subdev_get_try_format(sd, fh->pad, 0);
756 const struct gc2385_mode *def_mode = &supported_modes[0];
757
758 mutex_lock(&gc2385->mutex);
759 /* Initialize try_fmt */
760 try_fmt->width = def_mode->width;
761 try_fmt->height = def_mode->height;
762 try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
763 try_fmt->field = V4L2_FIELD_NONE;
764
765 mutex_unlock(&gc2385->mutex);
766 /* No crop or compose */
767
768 return 0;
769 }
770 #endif
771
gc2385_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)772 static int gc2385_enum_frame_interval(struct v4l2_subdev *sd,
773 struct v4l2_subdev_pad_config *cfg,
774 struct v4l2_subdev_frame_interval_enum *fie)
775 {
776 if (fie->index >= ARRAY_SIZE(supported_modes))
777 return -EINVAL;
778
779 fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
780 fie->width = supported_modes[fie->index].width;
781 fie->height = supported_modes[fie->index].height;
782 fie->interval = supported_modes[fie->index].max_fps;
783 return 0;
784 }
785
gc2385_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)786 static int gc2385_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
787 struct v4l2_mbus_config *config)
788 {
789 u32 val = 0;
790
791 val = 1 << (GC2385_LANES - 1) |
792 V4L2_MBUS_CSI2_CHANNEL_0 |
793 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
794 config->type = V4L2_MBUS_CSI2_DPHY;
795 config->flags = val;
796
797 return 0;
798 }
799
800 static const struct dev_pm_ops gc2385_pm_ops = {
801 SET_RUNTIME_PM_OPS(gc2385_runtime_suspend,
802 gc2385_runtime_resume, NULL)
803 };
804
805 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
806 static const struct v4l2_subdev_internal_ops gc2385_internal_ops = {
807 .open = gc2385_open,
808 };
809 #endif
810
811 static const struct v4l2_subdev_core_ops gc2385_core_ops = {
812 .s_power = gc2385_s_power,
813 .ioctl = gc2385_ioctl,
814 #ifdef CONFIG_COMPAT
815 .compat_ioctl32 = gc2385_compat_ioctl32,
816 #endif
817 };
818
819 static const struct v4l2_subdev_video_ops gc2385_video_ops = {
820 .s_stream = gc2385_s_stream,
821 .g_frame_interval = gc2385_g_frame_interval,
822 };
823
824 static const struct v4l2_subdev_pad_ops gc2385_pad_ops = {
825 .enum_mbus_code = gc2385_enum_mbus_code,
826 .enum_frame_size = gc2385_enum_frame_sizes,
827 .enum_frame_interval = gc2385_enum_frame_interval,
828 .get_fmt = gc2385_get_fmt,
829 .set_fmt = gc2385_set_fmt,
830 .get_mbus_config = gc2385_g_mbus_config,
831 };
832
833 static const struct v4l2_subdev_ops gc2385_subdev_ops = {
834 .core = &gc2385_core_ops,
835 .video = &gc2385_video_ops,
836 .pad = &gc2385_pad_ops,
837 };
838
839 #define GC2385_ANALOG_GAIN_1 64 /*1.00x*/
840 #define GC2385_ANALOG_GAIN_2 92 // 1.43x
841 #define GC2385_ANALOG_GAIN_3 127 // 1.99x
842 #define GC2385_ANALOG_GAIN_4 183 // 2.86x
843 #define GC2385_ANALOG_GAIN_5 257 // 4.01x
844 #define GC2385_ANALOG_GAIN_6 369 // 5.76x
845 #define GC2385_ANALOG_GAIN_7 531 //8.30x
846 #define GC2385_ANALOG_GAIN_8 750 // 11.72x
847 #define GC2385_ANALOG_GAIN_9 1092 // 17.06x
848
gc2385_set_gain_reg(struct gc2385 * gc2385,u32 a_gain)849 static int gc2385_set_gain_reg(struct gc2385 *gc2385, u32 a_gain)
850 {
851 int ret = 0;
852 u32 temp = 0;
853
854 ret = gc2385_write_reg(gc2385->client,
855 GC2385_REG_SET_PAGE, GC2385_SET_PAGE_ONE);
856 if (a_gain >= GC2385_ANALOG_GAIN_1 &&
857 a_gain < GC2385_ANALOG_GAIN_2) {
858 ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
859 ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa2);
860 ret |= gc2385_write_reg(gc2385->client,
861 GC2385_REG_AGAIN, 0x0);
862 temp = 256 * a_gain / GC2385_ANALOG_GAIN_1;
863 ret |= gc2385_write_reg(gc2385->client,
864 GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
865 ret |= gc2385_write_reg(gc2385->client,
866 GC2385_REG_DGAIN_FRAC, temp & 0xff);
867 } else if (a_gain >= GC2385_ANALOG_GAIN_2 &&
868 a_gain < GC2385_ANALOG_GAIN_3) {
869 ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
870 ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa2);
871 ret |= gc2385_write_reg(gc2385->client,
872 GC2385_REG_AGAIN, 0x1);
873 temp = 256 * a_gain / GC2385_ANALOG_GAIN_2;
874 ret |= gc2385_write_reg(gc2385->client,
875 GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
876 ret |= gc2385_write_reg(gc2385->client,
877 GC2385_REG_DGAIN_FRAC, temp & 0xff);
878 } else if (a_gain >= GC2385_ANALOG_GAIN_3 &&
879 a_gain < GC2385_ANALOG_GAIN_4) {
880 ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
881 ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa2);
882 ret |= gc2385_write_reg(gc2385->client,
883 GC2385_REG_AGAIN, 0x2);
884 temp = 256 * a_gain / GC2385_ANALOG_GAIN_3;
885 ret |= gc2385_write_reg(gc2385->client,
886 GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
887 ret |= gc2385_write_reg(gc2385->client,
888 GC2385_REG_DGAIN_FRAC, temp & 0xff);
889 } else if (a_gain >= GC2385_ANALOG_GAIN_4 &&
890 a_gain < GC2385_ANALOG_GAIN_5) {
891 ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
892 ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa2);
893 ret |= gc2385_write_reg(gc2385->client,
894 GC2385_REG_AGAIN, 0x3);
895 temp = 256 * a_gain / GC2385_ANALOG_GAIN_4;
896 ret |= gc2385_write_reg(gc2385->client,
897 GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
898 ret |= gc2385_write_reg(gc2385->client,
899 GC2385_REG_DGAIN_FRAC, temp & 0xff);
900 } else if (a_gain >= GC2385_ANALOG_GAIN_5 &&
901 a_gain < GC2385_ANALOG_GAIN_6) {
902 ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
903 ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa3);
904 ret |= gc2385_write_reg(gc2385->client,
905 GC2385_REG_AGAIN, 0x4);
906 temp = 256 * a_gain / GC2385_ANALOG_GAIN_5;
907 ret |= gc2385_write_reg(gc2385->client,
908 GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
909 ret |= gc2385_write_reg(gc2385->client,
910 GC2385_REG_DGAIN_FRAC, temp & 0xff);
911 } else if (a_gain >= GC2385_ANALOG_GAIN_6 &&
912 a_gain < GC2385_ANALOG_GAIN_7) {
913 ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
914 ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa3);
915 ret |= gc2385_write_reg(gc2385->client,
916 GC2385_REG_AGAIN, 0x5);
917 temp = 256 * a_gain / GC2385_ANALOG_GAIN_6;
918 ret |= gc2385_write_reg(gc2385->client,
919 GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
920 ret |= gc2385_write_reg(gc2385->client,
921 GC2385_REG_DGAIN_FRAC, temp & 0xff);
922 } else if (a_gain >= GC2385_ANALOG_GAIN_7 &&
923 a_gain < GC2385_ANALOG_GAIN_8) {
924 ret |= gc2385_write_reg(gc2385->client, 0x20, 0x74);
925 ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa3);
926 ret |= gc2385_write_reg(gc2385->client,
927 GC2385_REG_AGAIN, 0x6);
928 temp = 256 * a_gain / GC2385_ANALOG_GAIN_7;
929 ret |= gc2385_write_reg(gc2385->client,
930 GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
931 ret |= gc2385_write_reg(gc2385->client,
932 GC2385_REG_DGAIN_FRAC, temp & 0xff);
933 } else if (a_gain >= GC2385_ANALOG_GAIN_8 &&
934 a_gain < GC2385_ANALOG_GAIN_9) {
935 ret |= gc2385_write_reg(gc2385->client, 0x20, 0x74);
936 ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa3);
937 ret |= gc2385_write_reg(gc2385->client,
938 GC2385_REG_AGAIN, 0x7);
939 temp = 256 * a_gain / GC2385_ANALOG_GAIN_8;
940 ret |= gc2385_write_reg(gc2385->client,
941 GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
942 ret |= gc2385_write_reg(gc2385->client,
943 GC2385_REG_DGAIN_FRAC, temp & 0xff);
944 } else {
945 ret |= gc2385_write_reg(gc2385->client, 0x20, 0x75);
946 ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa4);
947 ret |= gc2385_write_reg(gc2385->client,
948 GC2385_REG_AGAIN, 0x8);
949 temp = 256 * a_gain / GC2385_ANALOG_GAIN_9;
950 ret |= gc2385_write_reg(gc2385->client,
951 GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
952 ret |= gc2385_write_reg(gc2385->client,
953 GC2385_REG_DGAIN_FRAC, temp & 0xff);
954 }
955 return ret;
956 }
957
gc2385_set_ctrl(struct v4l2_ctrl * ctrl)958 static int gc2385_set_ctrl(struct v4l2_ctrl *ctrl)
959 {
960 struct gc2385 *gc2385 = container_of(ctrl->handler,
961 struct gc2385, ctrl_handler);
962 struct i2c_client *client = gc2385->client;
963 s64 max;
964 int ret = 0;
965
966 /* Propagate change of current control to all related controls */
967 switch (ctrl->id) {
968 case V4L2_CID_VBLANK:
969 /* Update max exposure while meeting expected vblanking */
970 max = gc2385->cur_mode->height + ctrl->val - 4;
971 __v4l2_ctrl_modify_range(gc2385->exposure,
972 gc2385->exposure->minimum, max,
973 gc2385->exposure->step,
974 gc2385->exposure->default_value);
975 break;
976 }
977
978 if (!pm_runtime_get_if_in_use(&client->dev))
979 return 0;
980
981 switch (ctrl->id) {
982 case V4L2_CID_EXPOSURE:
983 /* 4 least significant bits of expsoure are fractional part */
984 ret = gc2385_write_reg(gc2385->client,
985 GC2385_REG_SET_PAGE,
986 GC2385_SET_PAGE_ONE);
987 ret |= gc2385_write_reg(gc2385->client,
988 GC2385_REG_EXPOSURE_H,
989 GC2385_FETCH_HIGH_BYTE_EXP(ctrl->val));
990 ret |= gc2385_write_reg(gc2385->client,
991 GC2385_REG_EXPOSURE_L,
992 GC2385_FETCH_LOW_BYTE_EXP(ctrl->val));
993 break;
994 case V4L2_CID_ANALOGUE_GAIN:
995 ret = gc2385_set_gain_reg(gc2385, ctrl->val);
996 break;
997 case V4L2_CID_VBLANK:
998 ret = gc2385_write_reg(gc2385->client,
999 GC2385_REG_SET_PAGE,
1000 GC2385_SET_PAGE_ONE);
1001 ret |= gc2385_write_reg(gc2385->client,
1002 GC2385_REG_VTS_H,
1003 ((ctrl->val - 32) >> 8) & 0xff);
1004 ret |= gc2385_write_reg(gc2385->client,
1005 GC2385_REG_VTS_L,
1006 (ctrl->val - 32) & 0xff);
1007 break;
1008 default:
1009 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1010 __func__, ctrl->id, ctrl->val);
1011 break;
1012 }
1013
1014 pm_runtime_put(&client->dev);
1015
1016 return ret;
1017 }
1018
1019 static const struct v4l2_ctrl_ops gc2385_ctrl_ops = {
1020 .s_ctrl = gc2385_set_ctrl,
1021 };
1022
gc2385_initialize_controls(struct gc2385 * gc2385)1023 static int gc2385_initialize_controls(struct gc2385 *gc2385)
1024 {
1025 const struct gc2385_mode *mode;
1026 struct v4l2_ctrl_handler *handler;
1027 struct v4l2_ctrl *ctrl;
1028 s64 exposure_max, vblank_def;
1029 u32 h_blank;
1030 int ret;
1031
1032 handler = &gc2385->ctrl_handler;
1033 mode = gc2385->cur_mode;
1034 ret = v4l2_ctrl_handler_init(handler, 8);
1035 if (ret)
1036 return ret;
1037 handler->lock = &gc2385->mutex;
1038
1039 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1040 0, 0, link_freq_menu_items);
1041 if (ctrl)
1042 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1043
1044 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1045 0, GC2385_PIXEL_RATE, 1, GC2385_PIXEL_RATE);
1046
1047 h_blank = mode->hts_def - mode->width;
1048 gc2385->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1049 h_blank, h_blank, 1, h_blank);
1050 if (gc2385->hblank)
1051 gc2385->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1052
1053 vblank_def = mode->vts_def - mode->height;
1054 gc2385->vblank = v4l2_ctrl_new_std(handler, &gc2385_ctrl_ops,
1055 V4L2_CID_VBLANK, vblank_def,
1056 GC2385_VTS_MAX - mode->height,
1057 1, vblank_def);
1058
1059 exposure_max = mode->vts_def - 4;
1060 gc2385->exposure = v4l2_ctrl_new_std(handler, &gc2385_ctrl_ops,
1061 V4L2_CID_EXPOSURE, GC2385_EXPOSURE_MIN,
1062 exposure_max, GC2385_EXPOSURE_STEP,
1063 mode->exp_def);
1064
1065 gc2385->anal_gain = v4l2_ctrl_new_std(handler, &gc2385_ctrl_ops,
1066 V4L2_CID_ANALOGUE_GAIN, GC2385_GAIN_MIN,
1067 GC2385_GAIN_MAX, GC2385_GAIN_STEP,
1068 GC2385_GAIN_DEFAULT);
1069 if (handler->error) {
1070 ret = handler->error;
1071 dev_err(&gc2385->client->dev,
1072 "Failed to init controls(%d)\n", ret);
1073 goto err_free_handler;
1074 }
1075
1076 gc2385->subdev.ctrl_handler = handler;
1077
1078 return 0;
1079
1080 err_free_handler:
1081 v4l2_ctrl_handler_free(handler);
1082
1083 return ret;
1084 }
1085
gc2385_check_sensor_id(struct gc2385 * gc2385,struct i2c_client * client)1086 static int gc2385_check_sensor_id(struct gc2385 *gc2385,
1087 struct i2c_client *client)
1088 {
1089 struct device *dev = &gc2385->client->dev;
1090 u16 id = 0;
1091 u8 reg_H = 0;
1092 u8 reg_L = 0;
1093 int ret;
1094
1095 ret = gc2385_write_reg(gc2385->client,
1096 GC2385_REG_SET_PAGE,
1097 GC2385_SET_PAGE_ONE);
1098 ret |= gc2385_read_reg(client, GC2385_REG_CHIP_ID_H, ®_H);
1099 ret |= gc2385_read_reg(client, GC2385_REG_CHIP_ID_L, ®_L);
1100 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
1101 if (id != CHIP_ID) {
1102 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1103 return -ENODEV;
1104 }
1105 return ret;
1106 }
1107
gc2385_configure_regulators(struct gc2385 * gc2385)1108 static int gc2385_configure_regulators(struct gc2385 *gc2385)
1109 {
1110 unsigned int i;
1111
1112 for (i = 0; i < GC2385_NUM_SUPPLIES; i++)
1113 gc2385->supplies[i].supply = gc2385_supply_names[i];
1114
1115 return devm_regulator_bulk_get(&gc2385->client->dev,
1116 GC2385_NUM_SUPPLIES,
1117 gc2385->supplies);
1118 }
1119
gc2385_probe(struct i2c_client * client,const struct i2c_device_id * id)1120 static int gc2385_probe(struct i2c_client *client,
1121 const struct i2c_device_id *id)
1122 {
1123 struct device *dev = &client->dev;
1124 struct device_node *node = dev->of_node;
1125 struct gc2385 *gc2385;
1126 struct v4l2_subdev *sd;
1127 char facing[2];
1128 int ret;
1129
1130 dev_info(dev, "driver version: %02x.%02x.%02x",
1131 DRIVER_VERSION >> 16,
1132 (DRIVER_VERSION & 0xff00) >> 8,
1133 DRIVER_VERSION & 0x00ff);
1134
1135 gc2385 = devm_kzalloc(dev, sizeof(*gc2385), GFP_KERNEL);
1136 if (!gc2385)
1137 return -ENOMEM;
1138
1139 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1140 &gc2385->module_index);
1141 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1142 &gc2385->module_facing);
1143 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1144 &gc2385->module_name);
1145 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1146 &gc2385->len_name);
1147 if (ret) {
1148 dev_err(dev, "could not get module information!\n");
1149 return -EINVAL;
1150 }
1151 gc2385->client = client;
1152 gc2385->cur_mode = &supported_modes[0];
1153
1154 gc2385->xvclk = devm_clk_get(dev, "xvclk");
1155 if (IS_ERR(gc2385->xvclk)) {
1156 dev_err(dev, "Failed to get xvclk\n");
1157 return -EINVAL;
1158 }
1159
1160 gc2385->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1161 if (IS_ERR(gc2385->reset_gpio))
1162 dev_warn(dev, "Failed to get reset-gpios\n");
1163
1164 gc2385->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1165 if (IS_ERR(gc2385->pwdn_gpio))
1166 dev_warn(dev, "Failed to get pwdn-gpios\n");
1167
1168 ret = gc2385_configure_regulators(gc2385);
1169 if (ret) {
1170 dev_err(dev, "Failed to get power regulators\n");
1171 return ret;
1172 }
1173
1174 gc2385->pinctrl = devm_pinctrl_get(dev);
1175 if (!IS_ERR(gc2385->pinctrl)) {
1176 gc2385->pins_default =
1177 pinctrl_lookup_state(gc2385->pinctrl,
1178 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1179 if (IS_ERR(gc2385->pins_default))
1180 dev_err(dev, "could not get default pinstate\n");
1181
1182 gc2385->pins_sleep =
1183 pinctrl_lookup_state(gc2385->pinctrl,
1184 OF_CAMERA_PINCTRL_STATE_SLEEP);
1185 if (IS_ERR(gc2385->pins_sleep))
1186 dev_err(dev, "could not get sleep pinstate\n");
1187 }
1188
1189 mutex_init(&gc2385->mutex);
1190
1191 sd = &gc2385->subdev;
1192 v4l2_i2c_subdev_init(sd, client, &gc2385_subdev_ops);
1193 ret = gc2385_initialize_controls(gc2385);
1194 if (ret)
1195 goto err_destroy_mutex;
1196
1197 ret = __gc2385_power_on(gc2385);
1198 if (ret)
1199 goto err_free_handler;
1200
1201 ret = gc2385_check_sensor_id(gc2385, client);
1202 if (ret)
1203 goto err_power_off;
1204
1205 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1206 sd->internal_ops = &gc2385_internal_ops;
1207 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1208 V4L2_SUBDEV_FL_HAS_EVENTS;
1209 #endif
1210 #if defined(CONFIG_MEDIA_CONTROLLER)
1211 gc2385->pad.flags = MEDIA_PAD_FL_SOURCE;
1212 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1213 ret = media_entity_pads_init(&sd->entity, 1, &gc2385->pad);
1214 if (ret < 0)
1215 goto err_power_off;
1216 #endif
1217
1218 memset(facing, 0, sizeof(facing));
1219 if (strcmp(gc2385->module_facing, "back") == 0)
1220 facing[0] = 'b';
1221 else
1222 facing[0] = 'f';
1223
1224 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1225 gc2385->module_index, facing,
1226 GC2385_NAME, dev_name(sd->dev));
1227 ret = v4l2_async_register_subdev_sensor_common(sd);
1228 if (ret) {
1229 dev_err(dev, "v4l2 async register subdev failed\n");
1230 goto err_clean_entity;
1231 }
1232
1233 pm_runtime_set_active(dev);
1234 pm_runtime_enable(dev);
1235 pm_runtime_idle(dev);
1236
1237 return 0;
1238
1239 err_clean_entity:
1240 #if defined(CONFIG_MEDIA_CONTROLLER)
1241 media_entity_cleanup(&sd->entity);
1242 #endif
1243 err_power_off:
1244 __gc2385_power_off(gc2385);
1245 err_free_handler:
1246 v4l2_ctrl_handler_free(&gc2385->ctrl_handler);
1247 err_destroy_mutex:
1248 mutex_destroy(&gc2385->mutex);
1249
1250 return ret;
1251 }
1252
gc2385_remove(struct i2c_client * client)1253 static int gc2385_remove(struct i2c_client *client)
1254 {
1255 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1256 struct gc2385 *gc2385 = to_gc2385(sd);
1257
1258 v4l2_async_unregister_subdev(sd);
1259 #if defined(CONFIG_MEDIA_CONTROLLER)
1260 media_entity_cleanup(&sd->entity);
1261 #endif
1262 v4l2_ctrl_handler_free(&gc2385->ctrl_handler);
1263 mutex_destroy(&gc2385->mutex);
1264
1265 pm_runtime_disable(&client->dev);
1266 if (!pm_runtime_status_suspended(&client->dev))
1267 __gc2385_power_off(gc2385);
1268 pm_runtime_set_suspended(&client->dev);
1269
1270 return 0;
1271 }
1272
1273 #if IS_ENABLED(CONFIG_OF)
1274 static const struct of_device_id gc2385_of_match[] = {
1275 { .compatible = "galaxycore,gc2385" },
1276 {},
1277 };
1278 MODULE_DEVICE_TABLE(of, gc2385_of_match);
1279 #endif
1280
1281 static const struct i2c_device_id gc2385_match_id[] = {
1282 { "galaxycore,gc2385", 0 },
1283 { },
1284 };
1285
1286 static struct i2c_driver gc2385_i2c_driver = {
1287 .driver = {
1288 .name = GC2385_NAME,
1289 .pm = &gc2385_pm_ops,
1290 .of_match_table = of_match_ptr(gc2385_of_match),
1291 },
1292 .probe = &gc2385_probe,
1293 .remove = &gc2385_remove,
1294 .id_table = gc2385_match_id,
1295 };
1296
sensor_mod_init(void)1297 static int __init sensor_mod_init(void)
1298 {
1299 return i2c_add_driver(&gc2385_i2c_driver);
1300 }
1301
sensor_mod_exit(void)1302 static void __exit sensor_mod_exit(void)
1303 {
1304 i2c_del_driver(&gc2385_i2c_driver);
1305 }
1306
1307 device_initcall_sync(sensor_mod_init);
1308 module_exit(sensor_mod_exit);
1309
1310 MODULE_DESCRIPTION("GalaxyCore gc2385 sensor driver");
1311 MODULE_LICENSE("GPL v2");
1312