1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc2375h driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 init driver.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 add enum_frame_interval function.
10 * TODO: add OTP function.
11 * V0.0X01.0X04 add quick stream on/off
12 * V0.0X01.0X05 add function g_mbus_config
13 * V0.0X01.0X06 fix vblank set issue
14 */
15
16 //#define DEBUG 1
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/i2c.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/of.h>
25 #include <linux/of_graph.h>
26 #include <linux/of_gpio.h>
27
28 #include <linux/regulator/consumer.h>
29 #include <linux/sysfs.h>
30 #include <linux/version.h>
31 #include <linux/rk-camera-module.h>
32 #include <media/media-entity.h>
33 #include <media/v4l2-async.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-subdev.h>
36 #include <linux/pinctrl/consumer.h>
37 #include <linux/slab.h>
38
39 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x6)
40
41 #ifndef V4L2_CID_DIGITAL_GAIN
42 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
43 #endif
44
45 #define MIPI_FREQ 338000000
46 /* pixel rate = link frequency * 1 * lanes / BITS_PER_SAMPLE */
47 #define GC2375H_PIXEL_RATE (MIPI_FREQ * 2LL * 1LL / 10)
48 #define GC2375H_XVCLK_FREQ 24000000
49
50 #define CHIP_ID 0x2375
51 #define GC2375H_REG_CHIP_ID_H 0xf0
52 #define GC2375H_REG_CHIP_ID_L 0xf1
53 #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
54
55 #define GC2375H_REG_SET_PAGE 0xfe
56 #define GC2375H_SET_PAGE_ONE 0x00
57
58 #define GC2375H_PAGE_SELECT 0xfe
59 #define GC2375H_MODE_SELECT 0xef
60 #define GC2375H_MODE_SW_STANDBY 0x00
61 #define GC2375H_MODE_STREAMING 0x90
62
63 #define GC2375H_REG_EXPOSURE_H 0x03
64 #define GC2375H_REG_EXPOSURE_L 0x04
65 #define GC2375H_EXPOSURE_MIN 4
66 #define GC2375H_EXPOSURE_STEP 1
67 #define GC2375H_VTS_MAX 0x7fff
68
69 #define GC2375H_ANALOG_GAIN_1 64 /*1.00x*/
70 #define GC2375H_ANALOG_GAIN_2 88 /*1.375x*/
71 #define GC2375H_ANALOG_GAIN_3 122 /*1.90x*/
72 #define GC2375H_ANALOG_GAIN_4 168 /*2.625x*/
73 #define GC2375H_ANALOG_GAIN_5 239 /*3.738x*/
74 #define GC2375H_ANALOG_GAIN_6 330 /*5.163x*/
75 #define GC2375H_ANALOG_GAIN_7 470 /*7.350x*/
76 #define GC2375H_ANALOG_GAIN_8 725 // 11.34x
77 #define GC2375H_ANALOG_GAIN_9 1038 // 16.23x
78
79 #define GC2375H_ANALOG_GAIN_REG 0xb6
80 #define GC2375H_PREGAIN_H_REG 0xb1
81 #define GC2375H_PREGAIN_L_REG 0xb2
82
83 #define GC2375H_GAIN_MIN 0x40
84 #define GC2375H_GAIN_MAX 0x200
85 #define GC2375H_GAIN_STEP 1
86 #define GC2375H_GAIN_DEFAULT 0x80
87
88 #define GC2375H_REG_VTS_H 0x07
89 #define GC2375H_REG_VTS_L 0x08
90
91 #define GC2375_MIRROR_NORMAL
92 //#define GC2375_MIRROR_H
93 //#define GC2375_MIRROR_V
94 //#define GC2375_MIRROR_HV
95
96 #if defined(GC2375_MIRROR_NORMAL)
97 #define MIRROR 0xd4
98 #define BLK_Select1_H 0x00
99 #define BLK_Select1_L 0x3c
100 #define BLK_Select2_H 0x00
101 #define BLK_Select2_L 0x03
102
103 #elif defined(GC2375_MIRROR_H)
104 #define MIRROR 0xd5
105 #define BLK_Select1_H 0x00
106 #define BLK_Select1_L 0x3c
107 #define BLK_Select2_H 0x00
108 #define BLK_Select2_L 0x03
109
110 #elif defined(GC2375_MIRROR_V)
111 #define MIRROR 0xd6
112 #define BLK_Select1_H 0x3c
113 #define BLK_Select1_L 0x00
114 #define BLK_Select2_H 0xc0
115 #define BLK_Select2_L 0x00
116
117 #elif defined(GC2375_MIRROR_HV)
118 #define MIRROR 0xd7
119 #define BLK_Select1_H 0x3c
120 #define BLK_Select1_L 0x00
121 #define BLK_Select2_H 0xc0
122 #define BLK_Select2_L 0x00
123
124 #else
125 #define MIRROR 0xd4
126 #define BLK_Select1_H 0x00
127 #define BLK_Select1_L 0x3c
128 #define BLK_Select2_H 0x00
129 #define BLK_Select2_L 0x03
130
131 #endif
132
133 //#define GC2375_OLD_SETTING
134
135 #define REG_NULL 0xFFFF
136
137 #define GC2375H_LANES 1
138 #define GC2375H_BITS_PER_SAMPLE 10
139
140 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
141 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
142
143 #define GC2375H_NAME "gc2375h"
144
145 static const char * const gc2375h_supply_names[] = {
146 "avdd", /* Analog power */
147 "dovdd", /* Digital I/O power */
148 "dvdd", /* Digital core power */
149 };
150
151 #define GC2375H_NUM_SUPPLIES ARRAY_SIZE(gc2375h_supply_names)
152
153 struct regval {
154 u16 addr;
155 u8 val;
156 };
157
158 struct gc2375h_mode {
159 u32 width;
160 u32 height;
161 struct v4l2_fract max_fps;
162 u32 hts_def;
163 u32 vts_def;
164 u32 exp_def;
165 const struct regval *reg_list;
166 };
167
168 struct gc2375h {
169 struct i2c_client *client;
170 struct clk *xvclk;
171 struct gpio_desc *reset_gpio;
172 struct gpio_desc *pwdn_gpio;
173 struct regulator_bulk_data supplies[GC2375H_NUM_SUPPLIES];
174
175 struct pinctrl *pinctrl;
176 struct pinctrl_state *pins_default;
177 struct pinctrl_state *pins_sleep;
178
179 struct v4l2_subdev subdev;
180 struct media_pad pad;
181 struct v4l2_ctrl_handler ctrl_handler;
182 struct v4l2_ctrl *exposure;
183 struct v4l2_ctrl *anal_gain;
184 struct v4l2_ctrl *digi_gain;
185 struct v4l2_ctrl *hblank;
186 struct v4l2_ctrl *vblank;
187 struct v4l2_ctrl *test_pattern;
188 struct mutex mutex;
189 bool streaming;
190 bool power_on;
191 const struct gc2375h_mode *cur_mode;
192 unsigned int lane_num;
193 unsigned int cfg_num;
194 unsigned int pixel_rate;
195 u32 module_index;
196 const char *module_facing;
197 const char *module_name;
198 const char *len_name;
199 };
200
201 #define to_gc2375h(sd) container_of(sd, struct gc2375h, subdev)
202
203 /*
204 * Xclk 24Mhz
205 */
206 static const struct regval gc2375h_global_regs[] = {
207 #ifdef GC2375_OLD_SETTING
208 {0xfe, 0x00},
209 {0xfe, 0x00},
210 {0xfe, 0x00},
211 {0xf7, 0x01},
212 {0xf8, 0x0c},
213 {0xf9, 0x42},
214 {0xfa, 0x88},
215 {0xfc, 0x8e},
216 {0xfe, 0x00},
217 {0x88, 0x03},
218 {0x03, 0x04},
219 {0x04, 0x65},
220 {0x05, 0x02},
221 {0x06, 0x5a},
222 {0x07, 0x00},
223 {0x08, 0x10},
224 {0x09, 0x00},
225 {0x0a, 0x08},
226 {0x0b, 0x00},
227 {0x0c, 0x18},
228 {0x0d, 0x04},
229 {0x0e, 0xb8},
230 {0x0f, 0x06},
231 {0x10, 0x48},
232 {0x17, 0xd4},
233 {0x1c, 0x10},
234 {0x1d, 0x13},
235 {0x20, 0x0b},
236 {0x21, 0x6d},
237 {0x22, 0x0c},
238 {0x25, 0xc1},
239 {0x26, 0x0e},
240 {0x27, 0x22},
241 {0x29, 0x5f},
242 {0x2b, 0x88},
243 {0x2f, 0x12},
244 {0x38, 0x86},
245 {0x3d, 0x00},
246 {0xcd, 0xa3},
247 {0xce, 0x57},
248 {0xd0, 0x09},
249 {0xd1, 0xca},
250 {0xd2, 0x34},
251 {0xd3, 0xbb},
252 {0xd8, 0x60},
253 {0xe0, 0x08},
254 {0xe1, 0x1f},
255 {0xe4, 0xf8},
256 {0xe5, 0x0c},
257 {0xe6, 0x10},
258 {0xe7, 0xcc},
259 {0xe8, 0x02},
260 {0xe9, 0x01},
261 {0xea, 0x02},
262 {0xeb, 0x01},
263 {0x90, 0x01},
264 {0x92, 0x02},
265 {0x94, 0x00},
266 {0x95, 0x04},
267 {0x96, 0xb0},
268 {0x97, 0x06},
269 {0x98, 0x40},
270 {0x18, 0x02},
271 {0x1a, 0x18},
272 {0x28, 0x00},
273 {0x3f, 0x40},
274 {0x40, 0x26},
275 {0x41, 0x00},
276 {0x43, 0x03},
277 {0x4a, 0x00},
278 {0x4e, 0x3c},
279 {0x4f, 0x00},
280 {0x66, 0xc0},
281 {0x67, 0x00},
282 {0x68, 0x00},
283 {0xb0, 0x58},
284 {0xb1, 0x01},
285 {0xb2, 0x00},
286 {0xb6, 0x00},
287 {0xef, 0x90},
288 {0xfe, 0x03},
289 {0x01, 0x03},
290 {0x02, 0x33},
291 {0x03, 0x90},
292 {0x04, 0x04},
293 {0x05, 0x00},
294 {0x06, 0x80},
295 {0x11, 0x2b},
296 {0x12, 0xd0},
297 {0x13, 0x07},
298 {0x15, 0x00},
299 {0x21, 0x08},
300 {0x22, 0x05},
301 {0x23, 0x13},
302 {0x24, 0x02},
303 {0x25, 0x13},
304 {0x26, 0x08},
305 {0x29, 0x06},
306 {0x2a, 0x08},
307 {0x2b, 0x08},
308 {0xfe, 0x00},
309 {0x20, 0x0b},
310 {0x22, 0x0c},
311 {0x26, 0x0e},
312 {0xb6, 0x00},
313 #else
314 /*System*/
315 {0xfe, 0x00},
316 {0xfe, 0x00},
317 {0xfe, 0x00},
318 {0xf7, 0x01},
319 {0xf8, 0x0c},
320 {0xf9, 0x42},
321 {0xfa, 0x88},
322 {0xfc, 0x8e},
323 {0xfe, 0x00},
324 {0x88, 0x03},
325 /*Analog*/
326 {0xfe, 0x00},
327 {0x03, 0x04},
328 {0x04, 0x65},
329 {0x05, 0x02},
330 {0x06, 0x5a},
331 {0x07, 0x00},
332 {0x08, 0x10},
333 {0x09, 0x00},
334 {0x0a, 0x04},
335 {0x0b, 0x00},
336 {0x0c, 0x14},
337 {0x0d, 0x04},
338 {0x0e, 0xb8},
339 {0x0f, 0x06},
340 {0x10, 0x48},
341 {0x17, MIRROR},
342 {0x1c, 0x10},
343 {0x1d, 0x13},
344 {0x20, 0x0b},
345 {0x21, 0x6d},
346 {0x22, 0x0c},
347 {0x25, 0xc1},
348 {0x26, 0x0e},
349 {0x27, 0x22},
350 {0x29, 0x5f},
351 {0x2b, 0x88},
352 {0x2f, 0x12},
353 {0x38, 0x86},
354 {0x3d, 0x00},
355 {0xcd, 0xa3},
356 {0xce, 0x57},
357 {0xd0, 0x09},
358 {0xd1, 0xca},
359 {0xd2, 0x34},
360 {0xd3, 0xbb},
361 {0xd8, 0x60},
362 {0xe0, 0x08},
363 {0xe1, 0x1f},
364 {0xe4, 0xf8},
365 {0xe5, 0x0c},
366 {0xe6, 0x10},
367 {0xe7, 0xcc},
368 {0xe8, 0x02},
369 {0xe9, 0x01},
370 {0xea, 0x02},
371 {0xeb, 0x01},
372 /*Crop*/
373 {0x90, 0x01},
374 {0x92, 0x04},
375 {0x94, 0x04},
376 {0x95, 0x04},
377 {0x96, 0xb0},
378 {0x97, 0x06},
379 {0x98, 0x40},
380 /*BLK*/
381 {0x18, 0x02},
382 {0x1a, 0x18},
383 {0x28, 0x00},
384 {0x3f, 0x40},
385 {0x40, 0x26},
386 {0x41, 0x00},
387 {0x43, 0x03},
388 {0x4a, 0x00},
389 {0x4e, BLK_Select1_H},
390 {0x4f, BLK_Select1_L},
391 {0x66, BLK_Select2_H},
392 {0x67, BLK_Select2_L},
393 /*Dark sun*/
394 {0x68, 0x00},
395 /*Gain*/
396 {0xb0, 0x58},
397 {0xb1, 0x01},
398 {0xb2, 0x00},
399 {0xb6, 0x00},
400 /*MIPI*/
401 {0xef, 0x00},
402 {0xfe, 0x03},
403 {0x01, 0x03},
404 {0x02, 0x33},
405 {0x03, 0x90},
406 {0x04, 0x04},
407 {0x05, 0x00},
408 {0x06, 0x80},
409 {0x11, 0x2b},
410 {0x12, 0xd0},
411 {0x13, 0x07},
412 {0x15, 0x00},
413 {0x21, 0x08},
414 {0x22, 0x05},
415 {0x23, 0x13},
416 {0x24, 0x02},
417 {0x25, 0x13},
418 {0x26, 0x08},
419 {0x29, 0x06},
420 {0x2a, 0x08},
421 {0x2b, 0x08},
422 {0xfe, 0x00},
423 #endif
424 {REG_NULL, 0x00},
425 };
426
427 /*
428 * Xclk 24Mhz
429 * max_framerate 30fps
430 * mipi_datarate per lane 1008Mbps
431 */
432 static const struct regval gc2375h_1600x1200_regs[] = {
433 {REG_NULL, 0x00},
434 };
435
436 static const struct gc2375h_mode supported_modes_1lane[] = {
437 {
438 .width = 1600,
439 .height = 1200,
440 .max_fps = {
441 .numerator = 10000,
442 .denominator = 300000,
443 },
444 .exp_def = 0x04d0,
445 .hts_def = 0x0820,
446 .vts_def = 0x04d9,
447 .reg_list = gc2375h_1600x1200_regs,
448 },
449 };
450
451 static const struct gc2375h_mode *supported_modes;
452
453 static const s64 link_freq_menu_items[] = {
454 MIPI_FREQ
455 };
456
457 /* sensor register write */
gc2375h_write_reg(struct i2c_client * client,u8 reg,u8 val)458 static int gc2375h_write_reg(struct i2c_client *client, u8 reg, u8 val)
459 {
460 struct i2c_msg msg;
461 u8 buf[2];
462 int ret;
463
464 dev_dbg(&client->dev, "%s(%d) enter!\n", __func__, __LINE__);
465 dev_dbg(&client->dev, "gc2375h write reg(0x%x val:0x%x)!\n", reg, val);
466 buf[0] = reg & 0xFF;
467 buf[1] = val;
468
469 msg.addr = client->addr;
470 msg.flags = client->flags;
471 msg.buf = buf;
472 msg.len = sizeof(buf);
473
474 ret = i2c_transfer(client->adapter, &msg, 1);
475 if (ret >= 0)
476 return 0;
477
478 dev_err(&client->dev,
479 "gc2375h write reg(0x%x val:0x%x) failed !\n", reg, val);
480
481 return ret;
482 }
483
484 /* sensor register read */
gc2375h_read_reg(struct i2c_client * client,u8 reg,u8 * val)485 static int gc2375h_read_reg(struct i2c_client *client, u8 reg, u8 *val)
486 {
487 struct i2c_msg msg[2];
488 u8 buf[1];
489 int ret;
490
491 buf[0] = reg & 0xFF;
492
493 msg[0].addr = client->addr;
494 msg[0].flags = client->flags;
495 msg[0].buf = buf;
496 msg[0].len = sizeof(buf);
497
498 msg[1].addr = client->addr;
499 msg[1].flags = client->flags | I2C_M_RD;
500 msg[1].buf = buf;
501 msg[1].len = 1;
502
503 ret = i2c_transfer(client->adapter, msg, 2);
504 if (ret >= 0) {
505 *val = buf[0];
506 return 0;
507 }
508
509 dev_err(&client->dev,
510 "gc2375h read reg:0x%x failed !\n", reg);
511
512 return ret;
513 }
514
gc2375h_write_array(struct i2c_client * client,const struct regval * regs)515 static int gc2375h_write_array(struct i2c_client *client,
516 const struct regval *regs)
517 {
518 u32 i;
519 int ret = 0;
520
521 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
522 ret = gc2375h_write_reg(client, regs[i].addr, regs[i].val);
523
524 return ret;
525 }
526
gc2375h_get_reso_dist(const struct gc2375h_mode * mode,struct v4l2_mbus_framefmt * framefmt)527 static int gc2375h_get_reso_dist(const struct gc2375h_mode *mode,
528 struct v4l2_mbus_framefmt *framefmt)
529 {
530 return abs(mode->width - framefmt->width) +
531 abs(mode->height - framefmt->height);
532 }
533
534 static const struct gc2375h_mode *
gc2375h_find_best_fit(struct gc2375h * gc2375h,struct v4l2_subdev_format * fmt)535 gc2375h_find_best_fit(struct gc2375h *gc2375h,
536 struct v4l2_subdev_format *fmt)
537 {
538 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
539 int dist;
540 int cur_best_fit = 0;
541 int cur_best_fit_dist = -1;
542 unsigned int i;
543
544 for (i = 0; i < gc2375h->cfg_num; i++) {
545 dist = gc2375h_get_reso_dist(&supported_modes[i], framefmt);
546 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
547 cur_best_fit_dist = dist;
548 cur_best_fit = i;
549 }
550 }
551
552 return &supported_modes[cur_best_fit];
553 }
554
gc2375h_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)555 static int gc2375h_set_fmt(struct v4l2_subdev *sd,
556 struct v4l2_subdev_pad_config *cfg,
557 struct v4l2_subdev_format *fmt)
558 {
559 struct gc2375h *gc2375h = to_gc2375h(sd);
560 const struct gc2375h_mode *mode;
561 s64 h_blank, vblank_def;
562
563 mutex_lock(&gc2375h->mutex);
564
565 mode = gc2375h_find_best_fit(gc2375h, fmt);
566 fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
567 fmt->format.width = mode->width;
568 fmt->format.height = mode->height;
569 fmt->format.field = V4L2_FIELD_NONE;
570 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
571 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
572 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
573 #else
574 mutex_unlock(&gc2375h->mutex);
575 return -ENOTTY;
576 #endif
577 } else {
578 gc2375h->cur_mode = mode;
579 h_blank = mode->hts_def - mode->width;
580 __v4l2_ctrl_modify_range(gc2375h->hblank, h_blank,
581 h_blank, 1, h_blank);
582 vblank_def = mode->vts_def - mode->height;
583 __v4l2_ctrl_modify_range(gc2375h->vblank, vblank_def,
584 GC2375H_VTS_MAX - mode->height,
585 1, vblank_def);
586 }
587
588 mutex_unlock(&gc2375h->mutex);
589
590 return 0;
591 }
592
gc2375h_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)593 static int gc2375h_get_fmt(struct v4l2_subdev *sd,
594 struct v4l2_subdev_pad_config *cfg,
595 struct v4l2_subdev_format *fmt)
596 {
597 struct gc2375h *gc2375h = to_gc2375h(sd);
598 const struct gc2375h_mode *mode = gc2375h->cur_mode;
599
600 mutex_lock(&gc2375h->mutex);
601 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
602 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
603 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
604 #else
605 mutex_unlock(&gc2375h->mutex);
606 return -ENOTTY;
607 #endif
608 } else {
609 fmt->format.width = mode->width;
610 fmt->format.height = mode->height;
611 fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
612 fmt->format.field = V4L2_FIELD_NONE;
613 }
614 mutex_unlock(&gc2375h->mutex);
615
616 return 0;
617 }
618
gc2375h_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)619 static int gc2375h_enum_mbus_code(struct v4l2_subdev *sd,
620 struct v4l2_subdev_pad_config *cfg,
621 struct v4l2_subdev_mbus_code_enum *code)
622 {
623 if (code->index != 0)
624 return -EINVAL;
625 code->code = MEDIA_BUS_FMT_SRGGB10_1X10;
626
627 return 0;
628 }
629
gc2375h_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)630 static int gc2375h_enum_frame_sizes(struct v4l2_subdev *sd,
631 struct v4l2_subdev_pad_config *cfg,
632 struct v4l2_subdev_frame_size_enum *fse)
633 {
634 struct gc2375h *gc2375h = to_gc2375h(sd);
635
636 if (fse->index >= gc2375h->cfg_num)
637 return -EINVAL;
638
639 if (fse->code != MEDIA_BUS_FMT_SRGGB10_1X10)
640 return -EINVAL;
641
642 fse->min_width = supported_modes[fse->index].width;
643 fse->max_width = supported_modes[fse->index].width;
644 fse->max_height = supported_modes[fse->index].height;
645 fse->min_height = supported_modes[fse->index].height;
646
647 return 0;
648 }
649
gc2375h_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)650 static int gc2375h_g_frame_interval(struct v4l2_subdev *sd,
651 struct v4l2_subdev_frame_interval *fi)
652 {
653 struct gc2375h *gc2375h = to_gc2375h(sd);
654 const struct gc2375h_mode *mode = gc2375h->cur_mode;
655
656 fi->interval = mode->max_fps;
657
658 return 0;
659 }
660
gc2375h_get_module_inf(struct gc2375h * gc2375h,struct rkmodule_inf * inf)661 static void gc2375h_get_module_inf(struct gc2375h *gc2375h,
662 struct rkmodule_inf *inf)
663 {
664 memset(inf, 0, sizeof(*inf));
665 strlcpy(inf->base.sensor, GC2375H_NAME, sizeof(inf->base.sensor));
666 strlcpy(inf->base.module, gc2375h->module_name,
667 sizeof(inf->base.module));
668 strlcpy(inf->base.lens, gc2375h->len_name, sizeof(inf->base.lens));
669 }
670
gc2375h_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)671 static long gc2375h_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
672 {
673 struct gc2375h *gc2375h = to_gc2375h(sd);
674 long ret = 0;
675 u32 stream = 0;
676
677 switch (cmd) {
678 case RKMODULE_GET_MODULE_INFO:
679 gc2375h_get_module_inf(gc2375h, (struct rkmodule_inf *)arg);
680 break;
681 case RKMODULE_SET_QUICK_STREAM:
682
683 stream = *((u32 *)arg);
684
685 if (stream) {
686 ret = gc2375h_write_reg(gc2375h->client, GC2375H_PAGE_SELECT, 0x00);
687 ret |= gc2375h_write_reg(gc2375h->client, GC2375H_MODE_SELECT,
688 GC2375H_MODE_STREAMING);
689 ret |= gc2375h_write_reg(gc2375h->client, GC2375H_PAGE_SELECT, 0x00);
690 } else {
691 ret = gc2375h_write_reg(gc2375h->client, GC2375H_PAGE_SELECT, 0x00);
692 ret |= gc2375h_write_reg(gc2375h->client, GC2375H_MODE_SELECT,
693 GC2375H_MODE_SW_STANDBY);
694 ret |= gc2375h_write_reg(gc2375h->client, GC2375H_PAGE_SELECT, 0x00);
695 }
696 break;
697 default:
698 ret = -ENOIOCTLCMD;
699 break;
700 }
701
702 return ret;
703 }
704
705 #ifdef CONFIG_COMPAT
gc2375h_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)706 static long gc2375h_compat_ioctl32(struct v4l2_subdev *sd,
707 unsigned int cmd, unsigned long arg)
708 {
709 void __user *up = compat_ptr(arg);
710 struct rkmodule_inf *inf;
711 struct rkmodule_awb_cfg *cfg;
712 long ret;
713 u32 stream = 0;
714
715 switch (cmd) {
716 case RKMODULE_GET_MODULE_INFO:
717 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
718 if (!inf) {
719 ret = -ENOMEM;
720 return ret;
721 }
722
723 ret = gc2375h_ioctl(sd, cmd, inf);
724 if (!ret) {
725 ret = copy_to_user(up, inf, sizeof(*inf));
726 if (ret)
727 ret = -EFAULT;
728 }
729 kfree(inf);
730 break;
731 case RKMODULE_AWB_CFG:
732 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
733 if (!cfg) {
734 ret = -ENOMEM;
735 return ret;
736 }
737
738 ret = copy_from_user(cfg, up, sizeof(*cfg));
739 if (!ret)
740 ret = gc2375h_ioctl(sd, cmd, cfg);
741 else
742 ret = -EFAULT;
743 kfree(cfg);
744 break;
745 case RKMODULE_SET_QUICK_STREAM:
746 ret = copy_from_user(&stream, up, sizeof(u32));
747 if (!ret)
748 ret = gc2375h_ioctl(sd, cmd, &stream);
749 else
750 ret = -EFAULT;
751 break;
752 default:
753 ret = -ENOIOCTLCMD;
754 break;
755 }
756
757 return ret;
758 }
759 #endif
760
__gc2375h_start_stream(struct gc2375h * gc2375h)761 static int __gc2375h_start_stream(struct gc2375h *gc2375h)
762 {
763 int ret;
764
765 ret = gc2375h_write_array(gc2375h->client, gc2375h->cur_mode->reg_list);
766 if (ret)
767 return ret;
768
769 /* In case these controls are set before streaming */
770 mutex_unlock(&gc2375h->mutex);
771 ret = v4l2_ctrl_handler_setup(&gc2375h->ctrl_handler);
772 mutex_lock(&gc2375h->mutex);
773 if (ret)
774 return ret;
775 //add mark
776 ret = gc2375h_write_reg(gc2375h->client, GC2375H_PAGE_SELECT, 0x00);
777 ret |= gc2375h_write_reg(gc2375h->client, GC2375H_MODE_SELECT,
778 GC2375H_MODE_STREAMING);
779 ret |= gc2375h_write_reg(gc2375h->client, GC2375H_PAGE_SELECT, 0x00);
780
781 return ret;
782 }
783
__gc2375h_stop_stream(struct gc2375h * gc2375h)784 static int __gc2375h_stop_stream(struct gc2375h *gc2375h)
785 {
786 int ret;
787
788 ret = gc2375h_write_reg(gc2375h->client, GC2375H_PAGE_SELECT, 0x00);
789 ret |= gc2375h_write_reg(gc2375h->client, GC2375H_MODE_SELECT,
790 GC2375H_MODE_SW_STANDBY);
791 ret |= gc2375h_write_reg(gc2375h->client, GC2375H_PAGE_SELECT, 0x00);
792
793 return ret;
794 // return 0;
795 }
796
gc2375h_s_stream(struct v4l2_subdev * sd,int on)797 static int gc2375h_s_stream(struct v4l2_subdev *sd, int on)
798 {
799 struct gc2375h *gc2375h = to_gc2375h(sd);
800 struct i2c_client *client = gc2375h->client;
801 int ret = 0;
802
803 mutex_lock(&gc2375h->mutex);
804 on = !!on;
805 if (on == gc2375h->streaming)
806 goto unlock_and_return;
807
808 if (on) {
809 ret = pm_runtime_get_sync(&client->dev);
810 if (ret < 0) {
811 pm_runtime_put_noidle(&client->dev);
812 goto unlock_and_return;
813 }
814
815 ret = __gc2375h_start_stream(gc2375h);
816 if (ret) {
817 v4l2_err(sd, "start stream failed while write regs\n");
818 pm_runtime_put(&client->dev);
819 goto unlock_and_return;
820 }
821 } else {
822 __gc2375h_stop_stream(gc2375h);
823 pm_runtime_put(&client->dev);
824 }
825
826 gc2375h->streaming = on;
827
828 unlock_and_return:
829 mutex_unlock(&gc2375h->mutex);
830
831 return ret;
832 }
833
gc2375h_s_power(struct v4l2_subdev * sd,int on)834 static int gc2375h_s_power(struct v4l2_subdev *sd, int on)
835 {
836 struct gc2375h *gc2375h = to_gc2375h(sd);
837 struct i2c_client *client = gc2375h->client;
838 int ret = 0;
839
840 mutex_lock(&gc2375h->mutex);
841
842 /* If the power state is not modified - no work to do. */
843 if (gc2375h->power_on == !!on)
844 goto unlock_and_return;
845
846 if (on) {
847 ret = pm_runtime_get_sync(&client->dev);
848 if (ret < 0) {
849 pm_runtime_put_noidle(&client->dev);
850 goto unlock_and_return;
851 }
852
853 ret = gc2375h_write_array(gc2375h->client, gc2375h_global_regs);
854 if (ret) {
855 v4l2_err(sd, "could not set init registers\n");
856 pm_runtime_put_noidle(&client->dev);
857 goto unlock_and_return;
858 }
859
860 gc2375h->power_on = true;
861 } else {
862 pm_runtime_put(&client->dev);
863 gc2375h->power_on = false;
864 }
865
866 unlock_and_return:
867 mutex_unlock(&gc2375h->mutex);
868
869 return ret;
870 }
871
872 /* Calculate the delay in us by clock rate and clock cycles */
gc2375h_cal_delay(u32 cycles)873 static inline u32 gc2375h_cal_delay(u32 cycles)
874 {
875 return DIV_ROUND_UP(cycles, GC2375H_XVCLK_FREQ / 1000 / 1000);
876 }
877
__gc2375h_power_on(struct gc2375h * gc2375h)878 static int __gc2375h_power_on(struct gc2375h *gc2375h)
879 {
880 int ret;
881 u32 delay_us;
882 struct device *dev = &gc2375h->client->dev;
883
884 if (!IS_ERR_OR_NULL(gc2375h->pins_default)) {
885 ret = pinctrl_select_state(gc2375h->pinctrl,
886 gc2375h->pins_default);
887 if (ret < 0)
888 dev_err(dev, "could not set pins\n");
889 }
890 ret = clk_set_rate(gc2375h->xvclk, GC2375H_XVCLK_FREQ);
891 if (ret < 0)
892 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
893 if (clk_get_rate(gc2375h->xvclk) != GC2375H_XVCLK_FREQ)
894 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
895 ret = clk_prepare_enable(gc2375h->xvclk);
896 if (ret < 0) {
897 dev_err(dev, "Failed to enable xvclk\n");
898 return ret;
899 }
900
901 if (!IS_ERR(gc2375h->pwdn_gpio))
902 gpiod_set_value_cansleep(gc2375h->pwdn_gpio, 0);
903
904 if (!IS_ERR(gc2375h->reset_gpio))
905 gpiod_set_value_cansleep(gc2375h->reset_gpio, 0);
906
907 usleep_range(500, 1000);
908
909 ret = regulator_bulk_enable(GC2375H_NUM_SUPPLIES, gc2375h->supplies);
910 if (ret < 0) {
911 dev_err(dev, "Failed to enable regulators\n");
912 goto disable_clk;
913 }
914
915 if (!IS_ERR(gc2375h->reset_gpio))
916 gpiod_set_value_cansleep(gc2375h->reset_gpio, 1);
917
918 /* 8192 cycles prior to first SCCB transaction */
919 delay_us = gc2375h_cal_delay(8192);
920 usleep_range(delay_us, delay_us * 2);
921 gc2375h->power_on = true;
922 return 0;
923
924 disable_clk:
925 clk_disable_unprepare(gc2375h->xvclk);
926
927 return ret;
928 }
929
__gc2375h_power_off(struct gc2375h * gc2375h)930 static void __gc2375h_power_off(struct gc2375h *gc2375h)
931 {
932 int ret;
933 struct device *dev = &gc2375h->client->dev;
934
935 if (!IS_ERR(gc2375h->pwdn_gpio))
936 gpiod_set_value_cansleep(gc2375h->pwdn_gpio, 1);
937 clk_disable_unprepare(gc2375h->xvclk);
938 if (!IS_ERR(gc2375h->reset_gpio))
939 gpiod_set_value_cansleep(gc2375h->reset_gpio, 0);
940 if (!IS_ERR_OR_NULL(gc2375h->pins_sleep)) {
941 ret = pinctrl_select_state(gc2375h->pinctrl,
942 gc2375h->pins_sleep);
943 if (ret < 0)
944 dev_dbg(dev, "could not set pins\n");
945 }
946 regulator_bulk_disable(GC2375H_NUM_SUPPLIES, gc2375h->supplies);
947 gc2375h->power_on = false;
948 }
949
gc2375h_runtime_resume(struct device * dev)950 static int gc2375h_runtime_resume(struct device *dev)
951 {
952 struct i2c_client *client = to_i2c_client(dev);
953 struct v4l2_subdev *sd = i2c_get_clientdata(client);
954 struct gc2375h *gc2375h = to_gc2375h(sd);
955
956 return __gc2375h_power_on(gc2375h);
957 }
958
gc2375h_runtime_suspend(struct device * dev)959 static int gc2375h_runtime_suspend(struct device *dev)
960 {
961 struct i2c_client *client = to_i2c_client(dev);
962 struct v4l2_subdev *sd = i2c_get_clientdata(client);
963 struct gc2375h *gc2375h = to_gc2375h(sd);
964
965 __gc2375h_power_off(gc2375h);
966
967 return 0;
968 }
969
970 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc2375h_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)971 static int gc2375h_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
972 {
973 struct gc2375h *gc2375h = to_gc2375h(sd);
974 struct v4l2_mbus_framefmt *try_fmt =
975 v4l2_subdev_get_try_format(sd, fh->pad, 0);
976 const struct gc2375h_mode *def_mode = &supported_modes[0];
977
978 mutex_lock(&gc2375h->mutex);
979 /* Initialize try_fmt */
980 try_fmt->width = def_mode->width;
981 try_fmt->height = def_mode->height;
982 try_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
983 try_fmt->field = V4L2_FIELD_NONE;
984
985 mutex_unlock(&gc2375h->mutex);
986 /* No crop or compose */
987
988 return 0;
989 }
990 #endif
991
gc2375h_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)992 static int gc2375h_enum_frame_interval(struct v4l2_subdev *sd,
993 struct v4l2_subdev_pad_config *cfg,
994 struct v4l2_subdev_frame_interval_enum *fie)
995 {
996 struct gc2375h *gc2375h = to_gc2375h(sd);
997
998 if (fie->index >= gc2375h->cfg_num)
999 return -EINVAL;
1000
1001 fie->code = MEDIA_BUS_FMT_SRGGB10_1X10;
1002 fie->width = supported_modes[fie->index].width;
1003 fie->height = supported_modes[fie->index].height;
1004 fie->interval = supported_modes[fie->index].max_fps;
1005 return 0;
1006 }
1007
gc2375h_g_mbus_config(struct v4l2_subdev * sd,struct v4l2_mbus_config * config)1008 static int gc2375h_g_mbus_config(struct v4l2_subdev *sd,
1009 struct v4l2_mbus_config *config)
1010 {
1011 u32 val = 0;
1012
1013 val = 1 << (GC2375H_LANES - 1) |
1014 V4L2_MBUS_CSI2_CHANNEL_0 |
1015 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1016 config->type = V4L2_MBUS_CSI2;
1017 config->flags = val;
1018
1019 return 0;
1020 }
1021
1022 static const struct dev_pm_ops gc2375h_pm_ops = {
1023 SET_RUNTIME_PM_OPS(gc2375h_runtime_suspend,
1024 gc2375h_runtime_resume, NULL)
1025 };
1026
1027 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1028 static const struct v4l2_subdev_internal_ops gc2375h_internal_ops = {
1029 .open = gc2375h_open,
1030 };
1031 #endif
1032
1033 static const struct v4l2_subdev_core_ops gc2375h_core_ops = {
1034 .s_power = gc2375h_s_power,
1035 .ioctl = gc2375h_ioctl,
1036 #ifdef CONFIG_COMPAT
1037 .compat_ioctl32 = gc2375h_compat_ioctl32,
1038 #endif
1039 };
1040
1041 static const struct v4l2_subdev_video_ops gc2375h_video_ops = {
1042 .s_stream = gc2375h_s_stream,
1043 .g_frame_interval = gc2375h_g_frame_interval,
1044 .g_mbus_config = gc2375h_g_mbus_config,
1045 };
1046
1047 static const struct v4l2_subdev_pad_ops gc2375h_pad_ops = {
1048 .enum_mbus_code = gc2375h_enum_mbus_code,
1049 .enum_frame_size = gc2375h_enum_frame_sizes,
1050 .enum_frame_interval = gc2375h_enum_frame_interval,
1051 .get_fmt = gc2375h_get_fmt,
1052 .set_fmt = gc2375h_set_fmt,
1053 };
1054
1055 static const struct v4l2_subdev_ops gc2375h_subdev_ops = {
1056 .core = &gc2375h_core_ops,
1057 .video = &gc2375h_video_ops,
1058 .pad = &gc2375h_pad_ops,
1059 };
1060
gc2375h_set_gain_reg(struct gc2375h * gc2375h,u32 a_gain)1061 static int gc2375h_set_gain_reg(struct gc2375h *gc2375h, u32 a_gain)
1062 {
1063 int ret = 0;
1064 u32 temp = 0;
1065
1066 ret = gc2375h_write_reg(gc2375h->client,
1067 GC2375H_PAGE_SELECT,
1068 0x00);
1069 if (a_gain >= GC2375H_ANALOG_GAIN_1 &&
1070 a_gain < GC2375H_ANALOG_GAIN_2) {
1071 ret |= gc2375h_write_reg(gc2375h->client, 0x20, 0x0b);
1072 ret |= gc2375h_write_reg(gc2375h->client, 0x22, 0x0c);
1073 ret |= gc2375h_write_reg(gc2375h->client, 0x26, 0x0e);
1074
1075 ret |= gc2375h_write_reg(gc2375h->client,
1076 GC2375H_ANALOG_GAIN_REG,
1077 0x00);
1078 temp = a_gain;
1079 ret |= gc2375h_write_reg(gc2375h->client,
1080 GC2375H_PREGAIN_H_REG,
1081 temp >> 6);
1082 ret |= gc2375h_write_reg(gc2375h->client,
1083 GC2375H_PREGAIN_L_REG,
1084 (temp << 2) & 0xfc);
1085 } else if (a_gain >= GC2375H_ANALOG_GAIN_2 &&
1086 a_gain < GC2375H_ANALOG_GAIN_3) {
1087 ret |= gc2375h_write_reg(gc2375h->client, 0x20, 0x0c);
1088 ret |= gc2375h_write_reg(gc2375h->client, 0x22, 0x0e);
1089 ret |= gc2375h_write_reg(gc2375h->client, 0x26, 0x0e);
1090
1091 ret |= gc2375h_write_reg(gc2375h->client,
1092 GC2375H_ANALOG_GAIN_REG,
1093 0x01);
1094 temp = 64 * a_gain / GC2375H_ANALOG_GAIN_2;
1095 ret |= gc2375h_write_reg(gc2375h->client,
1096 GC2375H_PREGAIN_H_REG,
1097 temp >> 6);
1098 ret |= gc2375h_write_reg(gc2375h->client,
1099 GC2375H_PREGAIN_L_REG,
1100 (temp << 2) & 0xfc);
1101 } else if (a_gain >= GC2375H_ANALOG_GAIN_3 &&
1102 a_gain < GC2375H_ANALOG_GAIN_4) {
1103 ret |= gc2375h_write_reg(gc2375h->client, 0x20, 0x0c);
1104 ret |= gc2375h_write_reg(gc2375h->client, 0x22, 0x0e);
1105 ret |= gc2375h_write_reg(gc2375h->client, 0x26, 0x0e);
1106
1107 ret |= gc2375h_write_reg(gc2375h->client,
1108 GC2375H_ANALOG_GAIN_REG,
1109 0x02);
1110 temp = 64 * a_gain / GC2375H_ANALOG_GAIN_3;
1111 ret |= gc2375h_write_reg(gc2375h->client,
1112 GC2375H_PREGAIN_H_REG,
1113 temp >> 6);
1114 ret |= gc2375h_write_reg(gc2375h->client,
1115 GC2375H_PREGAIN_L_REG,
1116 (temp << 2) & 0xfc);
1117 } else if (a_gain >= GC2375H_ANALOG_GAIN_4 &&
1118 a_gain < GC2375H_ANALOG_GAIN_5) {
1119 ret |= gc2375h_write_reg(gc2375h->client, 0x20, 0x0c);
1120 ret |= gc2375h_write_reg(gc2375h->client, 0x22, 0x0e);
1121 ret |= gc2375h_write_reg(gc2375h->client, 0x26, 0x0e);
1122 ret |= gc2375h_write_reg(gc2375h->client,
1123 GC2375H_ANALOG_GAIN_REG,
1124 0x03);
1125 temp = 64 * a_gain / GC2375H_ANALOG_GAIN_4;
1126 ret |= gc2375h_write_reg(gc2375h->client,
1127 GC2375H_PREGAIN_H_REG,
1128 temp >> 6);
1129 ret |= gc2375h_write_reg(gc2375h->client,
1130 GC2375H_PREGAIN_L_REG,
1131 (temp << 2) & 0xfc);
1132 } else if (a_gain >= GC2375H_ANALOG_GAIN_5 &&
1133 a_gain < GC2375H_ANALOG_GAIN_6) {
1134 ret |= gc2375h_write_reg(gc2375h->client, 0x20, 0x0c);
1135 ret |= gc2375h_write_reg(gc2375h->client, 0x22, 0x0e);
1136 ret |= gc2375h_write_reg(gc2375h->client, 0x26, 0x0e);
1137 ret |= gc2375h_write_reg(gc2375h->client,
1138 GC2375H_ANALOG_GAIN_REG,
1139 0x04);
1140 temp = 64 * a_gain / GC2375H_ANALOG_GAIN_5;
1141 ret |= gc2375h_write_reg(gc2375h->client,
1142 GC2375H_PREGAIN_H_REG,
1143 temp >> 6);
1144 ret |= gc2375h_write_reg(gc2375h->client,
1145 GC2375H_PREGAIN_L_REG,
1146 (temp << 2) & 0xfc);
1147 } else if (a_gain >= GC2375H_ANALOG_GAIN_6 &&
1148 a_gain < GC2375H_ANALOG_GAIN_7) {
1149 ret |= gc2375h_write_reg(gc2375h->client, 0x20, 0x0e);
1150 ret |= gc2375h_write_reg(gc2375h->client, 0x22, 0x0e);
1151 ret |= gc2375h_write_reg(gc2375h->client, 0x26, 0x0e);
1152 ret |= gc2375h_write_reg(gc2375h->client,
1153 GC2375H_ANALOG_GAIN_REG,
1154 0x05);
1155 temp = 64 * a_gain / GC2375H_ANALOG_GAIN_6;
1156 ret |= gc2375h_write_reg(gc2375h->client,
1157 GC2375H_PREGAIN_H_REG,
1158 temp >> 6);
1159 ret |= gc2375h_write_reg(gc2375h->client,
1160 GC2375H_PREGAIN_L_REG,
1161 (temp << 2) & 0xfc);
1162 } else if (a_gain >= GC2375H_ANALOG_GAIN_7 &&
1163 a_gain < GC2375H_ANALOG_GAIN_8) {
1164 ret |= gc2375h_write_reg(gc2375h->client, 0x20, 0x0c);
1165 ret |= gc2375h_write_reg(gc2375h->client, 0x22, 0x0c);
1166 ret |= gc2375h_write_reg(gc2375h->client, 0x26, 0x0e);
1167 ret |= gc2375h_write_reg(gc2375h->client,
1168 GC2375H_ANALOG_GAIN_REG,
1169 0x06);
1170 temp = 64 * a_gain / GC2375H_ANALOG_GAIN_7;
1171 ret |= gc2375h_write_reg(gc2375h->client,
1172 GC2375H_PREGAIN_H_REG,
1173 temp >> 6);
1174 ret |= gc2375h_write_reg(gc2375h->client,
1175 GC2375H_PREGAIN_L_REG,
1176 (temp << 2) & 0xfc);
1177 } else if (a_gain >= GC2375H_ANALOG_GAIN_8 &&
1178 a_gain < GC2375H_ANALOG_GAIN_9) {
1179 ret |= gc2375h_write_reg(gc2375h->client, 0x20, 0x0e);
1180 ret |= gc2375h_write_reg(gc2375h->client, 0x22, 0x0e);
1181 ret |= gc2375h_write_reg(gc2375h->client, 0x26, 0x0e);
1182 ret |= gc2375h_write_reg(gc2375h->client,
1183 GC2375H_ANALOG_GAIN_REG,
1184 0x07);
1185 temp = 64 * a_gain / GC2375H_ANALOG_GAIN_8;
1186 ret |= gc2375h_write_reg(gc2375h->client,
1187 GC2375H_PREGAIN_H_REG,
1188 temp >> 6);
1189 ret |= gc2375h_write_reg(gc2375h->client,
1190 GC2375H_PREGAIN_L_REG,
1191 (temp << 2) & 0xfc);
1192 } else {
1193 ret |= gc2375h_write_reg(gc2375h->client, 0x20, 0x0c);
1194 ret |= gc2375h_write_reg(gc2375h->client, 0x22, 0x0e);
1195 ret |= gc2375h_write_reg(gc2375h->client, 0x26, 0x0e);
1196 ret |= gc2375h_write_reg(gc2375h->client,
1197 GC2375H_ANALOG_GAIN_REG,
1198 0x08);
1199 temp = 64 * a_gain / GC2375H_ANALOG_GAIN_9;
1200 ret |= gc2375h_write_reg(gc2375h->client,
1201 GC2375H_PREGAIN_H_REG,
1202 temp >> 6);
1203 ret |= gc2375h_write_reg(gc2375h->client,
1204 GC2375H_PREGAIN_L_REG,
1205 (temp << 2) & 0xfc);
1206 }
1207 return ret;
1208 }
1209
gc2375h_set_ctrl(struct v4l2_ctrl * ctrl)1210 static int gc2375h_set_ctrl(struct v4l2_ctrl *ctrl)
1211 {
1212 struct gc2375h *gc2375h = container_of(ctrl->handler,
1213 struct gc2375h, ctrl_handler);
1214 struct i2c_client *client = gc2375h->client;
1215 s64 max;
1216 int ret = 0;
1217
1218 /* Propagate change of current control to all related controls */
1219 switch (ctrl->id) {
1220 case V4L2_CID_VBLANK:
1221 /* Update max exposure while meeting expected vblanking */
1222 max = gc2375h->cur_mode->height + ctrl->val - 4;
1223 __v4l2_ctrl_modify_range(gc2375h->exposure,
1224 gc2375h->exposure->minimum, max,
1225 gc2375h->exposure->step,
1226 gc2375h->exposure->default_value);
1227 break;
1228 }
1229
1230 if (!pm_runtime_get_if_in_use(&client->dev))
1231 return 0;
1232
1233 switch (ctrl->id) {
1234 case V4L2_CID_EXPOSURE:
1235 /* 4 least significant bits of expsoure are fractional part */
1236 ret |= gc2375h_write_reg(gc2375h->client,
1237 GC2375H_PAGE_SELECT,
1238 0x00);
1239 ret |= gc2375h_write_reg(gc2375h->client,
1240 GC2375H_REG_EXPOSURE_H,
1241 (ctrl->val >> 8) & 0x3f);
1242 ret |= gc2375h_write_reg(gc2375h->client,
1243 GC2375H_REG_EXPOSURE_L,
1244 ctrl->val & 0xff);
1245 break;
1246 case V4L2_CID_ANALOGUE_GAIN:
1247 ret = gc2375h_set_gain_reg(gc2375h, ctrl->val);
1248 break;
1249 case V4L2_CID_VBLANK:
1250 ret |= gc2375h_write_reg(gc2375h->client,
1251 GC2375H_PAGE_SELECT,
1252 0x00);
1253 ret |= gc2375h_write_reg(gc2375h->client,
1254 GC2375H_REG_VTS_H,
1255 ((ctrl->val) >> 8) & 0x1f);
1256 ret |= gc2375h_write_reg(gc2375h->client,
1257 GC2375H_REG_VTS_L,
1258 (ctrl->val & 0xff));
1259 break;
1260
1261 default:
1262 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1263 __func__, ctrl->id, ctrl->val);
1264 break;
1265 }
1266
1267 pm_runtime_put(&client->dev);
1268
1269 return ret;
1270 }
1271
1272 static const struct v4l2_ctrl_ops gc2375h_ctrl_ops = {
1273 .s_ctrl = gc2375h_set_ctrl,
1274 };
1275
gc2375h_initialize_controls(struct gc2375h * gc2375h)1276 static int gc2375h_initialize_controls(struct gc2375h *gc2375h)
1277 {
1278 const struct gc2375h_mode *mode;
1279 struct v4l2_ctrl_handler *handler;
1280 struct v4l2_ctrl *ctrl;
1281 s64 exposure_max, vblank_def;
1282 u32 h_blank;
1283 int ret;
1284 struct device *dev = &gc2375h->client->dev;
1285
1286 dev_info(dev, "Enter %s(%d) !\n", __func__, __LINE__);
1287 handler = &gc2375h->ctrl_handler;
1288 mode = gc2375h->cur_mode;
1289 ret = v4l2_ctrl_handler_init(handler, 8);
1290 if (ret)
1291 return ret;
1292 handler->lock = &gc2375h->mutex;
1293
1294 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1295 0, 0, link_freq_menu_items);
1296 if (ctrl)
1297 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1298
1299 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1300 0, GC2375H_PIXEL_RATE, 1, GC2375H_PIXEL_RATE);
1301
1302 h_blank = mode->hts_def - mode->width;
1303 gc2375h->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1304 h_blank, h_blank, 1, h_blank);
1305 if (gc2375h->hblank)
1306 gc2375h->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1307
1308 vblank_def = mode->vts_def - mode->height;
1309 gc2375h->vblank = v4l2_ctrl_new_std(handler, &gc2375h_ctrl_ops,
1310 V4L2_CID_VBLANK, vblank_def,
1311 GC2375H_VTS_MAX - mode->height,
1312 1, vblank_def);
1313
1314 exposure_max = mode->vts_def - 4;
1315 gc2375h->exposure = v4l2_ctrl_new_std(handler, &gc2375h_ctrl_ops,
1316 V4L2_CID_EXPOSURE, GC2375H_EXPOSURE_MIN,
1317 exposure_max, GC2375H_EXPOSURE_STEP,
1318 mode->exp_def);
1319
1320 gc2375h->anal_gain = v4l2_ctrl_new_std(handler, &gc2375h_ctrl_ops,
1321 V4L2_CID_ANALOGUE_GAIN, GC2375H_GAIN_MIN,
1322 GC2375H_GAIN_MAX, GC2375H_GAIN_STEP,
1323 GC2375H_GAIN_DEFAULT);
1324
1325 if (handler->error) {
1326 ret = handler->error;
1327 dev_err(&gc2375h->client->dev,
1328 "Failed to init controls(%d)\n", ret);
1329 goto err_free_handler;
1330 }
1331
1332 gc2375h->subdev.ctrl_handler = handler;
1333
1334 return 0;
1335
1336 err_free_handler:
1337 v4l2_ctrl_handler_free(handler);
1338
1339 return ret;
1340 }
1341
gc2375h_check_sensor_id(struct gc2375h * gc2375h,struct i2c_client * client)1342 static int gc2375h_check_sensor_id(struct gc2375h *gc2375h,
1343 struct i2c_client *client)
1344 {
1345 struct device *dev = &gc2375h->client->dev;
1346 u8 pid, ver = 0x00;
1347 int ret;
1348 unsigned short id;
1349
1350 ret = gc2375h_read_reg(client, GC2375H_REG_CHIP_ID_H, &pid);
1351 if (ret) {
1352 dev_err(dev, "Read chip ID H register error\n");
1353 return ret;
1354 }
1355
1356 ret = gc2375h_read_reg(client, GC2375H_REG_CHIP_ID_L, &ver);
1357 if (ret) {
1358 dev_err(dev, "Read chip ID L register error\n");
1359 return ret;
1360 }
1361
1362 id = SENSOR_ID(pid, ver);
1363 if (id != CHIP_ID) {
1364 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1365 return ret;
1366 }
1367
1368 dev_info(dev, "detected gc%04x sensor\n", id);
1369
1370 return 0;
1371 }
1372
gc2375h_configure_regulators(struct gc2375h * gc2375h)1373 static int gc2375h_configure_regulators(struct gc2375h *gc2375h)
1374 {
1375 unsigned int i;
1376
1377 for (i = 0; i < GC2375H_NUM_SUPPLIES; i++)
1378 gc2375h->supplies[i].supply = gc2375h_supply_names[i];
1379
1380 return devm_regulator_bulk_get(&gc2375h->client->dev,
1381 GC2375H_NUM_SUPPLIES,
1382 gc2375h->supplies);
1383 }
1384
gc2375h_parse_of(struct gc2375h * gc2375h)1385 static int gc2375h_parse_of(struct gc2375h *gc2375h)
1386 {
1387 struct device *dev = &gc2375h->client->dev;
1388 struct device_node *endpoint;
1389 struct fwnode_handle *fwnode;
1390 int rval;
1391
1392 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1393 if (!endpoint) {
1394 dev_err(dev, "Failed to get endpoint\n");
1395 return -EINVAL;
1396 }
1397 fwnode = of_fwnode_handle(endpoint);
1398 rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
1399 of_node_put(endpoint);
1400 if (rval <= 0) {
1401 dev_warn(dev, " Get mipi lane num failed!\n");
1402 return -1;
1403 }
1404
1405 gc2375h->lane_num = rval;
1406 if (1 == gc2375h->lane_num) {
1407 gc2375h->cur_mode = &supported_modes_1lane[0];
1408 supported_modes = supported_modes_1lane;
1409 gc2375h->cfg_num = ARRAY_SIZE(supported_modes_1lane);
1410
1411 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1412 gc2375h->pixel_rate = MIPI_FREQ * 2U * gc2375h->lane_num / 10U;
1413 dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
1414 gc2375h->lane_num, gc2375h->pixel_rate);
1415 } else {
1416 dev_err(dev, "unsupported lane_num(%d)\n", gc2375h->lane_num);
1417 return -1;
1418 }
1419 return 0;
1420 }
1421
gc2375h_probe(struct i2c_client * client,const struct i2c_device_id * id)1422 static int gc2375h_probe(struct i2c_client *client,
1423 const struct i2c_device_id *id)
1424 {
1425 struct device *dev = &client->dev;
1426 struct device_node *node = dev->of_node;
1427 struct gc2375h *gc2375h;
1428 struct v4l2_subdev *sd;
1429 char facing[2];
1430 int ret;
1431
1432 dev_info(dev, "driver version: %02x.%02x.%02x",
1433 DRIVER_VERSION >> 16,
1434 (DRIVER_VERSION & 0xff00) >> 8,
1435 DRIVER_VERSION & 0x00ff);
1436
1437 gc2375h = devm_kzalloc(dev, sizeof(*gc2375h), GFP_KERNEL);
1438 if (!gc2375h)
1439 return -ENOMEM;
1440
1441 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1442 &gc2375h->module_index);
1443 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1444 &gc2375h->module_facing);
1445 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1446 &gc2375h->module_name);
1447 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1448 &gc2375h->len_name);
1449 if (ret) {
1450 dev_err(dev, "could not get module information!\n");
1451 return -EINVAL;
1452 }
1453
1454 gc2375h->client = client;
1455 gc2375h->cur_mode = &supported_modes[0];
1456
1457 gc2375h->xvclk = devm_clk_get(dev, "xvclk");
1458 if (IS_ERR(gc2375h->xvclk)) {
1459 dev_err(dev, "Failed to get xvclk\n");
1460 return -EINVAL;
1461 }
1462
1463 gc2375h->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1464 if (IS_ERR(gc2375h->reset_gpio))
1465 dev_warn(dev, "Failed to get reset-gpios\n");
1466
1467 gc2375h->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_HIGH);
1468 if (IS_ERR(gc2375h->pwdn_gpio))
1469 dev_warn(dev, "Failed to get pwdn-gpios\n");
1470
1471 ret = gc2375h_parse_of(gc2375h);
1472 if (ret != 0)
1473 return -EINVAL;
1474
1475 gc2375h->pinctrl = devm_pinctrl_get(dev);
1476 if (!IS_ERR(gc2375h->pinctrl)) {
1477 gc2375h->pins_default =
1478 pinctrl_lookup_state(gc2375h->pinctrl,
1479 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1480 if (IS_ERR(gc2375h->pins_default))
1481 dev_err(dev, "could not get default pinstate\n");
1482
1483 gc2375h->pins_sleep =
1484 pinctrl_lookup_state(gc2375h->pinctrl,
1485 OF_CAMERA_PINCTRL_STATE_SLEEP);
1486 if (IS_ERR(gc2375h->pins_sleep))
1487 dev_err(dev, "could not get sleep pinstate\n");
1488 } else {
1489 dev_err(dev, "no pinctrl\n");
1490 }
1491
1492 ret = gc2375h_configure_regulators(gc2375h);
1493 if (ret) {
1494 dev_err(dev, "Failed to get power regulators\n");
1495 return ret;
1496 }
1497
1498 mutex_init(&gc2375h->mutex);
1499
1500 sd = &gc2375h->subdev;
1501 v4l2_i2c_subdev_init(sd, client, &gc2375h_subdev_ops);
1502 ret = gc2375h_initialize_controls(gc2375h);
1503 if (ret)
1504 goto err_destroy_mutex;
1505
1506 ret = __gc2375h_power_on(gc2375h);
1507 if (ret)
1508 goto err_free_handler;
1509
1510 ret = gc2375h_check_sensor_id(gc2375h, client);
1511 if (ret)
1512 goto err_power_off;
1513
1514 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1515 sd->internal_ops = &gc2375h_internal_ops;
1516 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1517 #endif
1518 #if defined(CONFIG_MEDIA_CONTROLLER)
1519 gc2375h->pad.flags = MEDIA_PAD_FL_SOURCE;
1520 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1521 ret = media_entity_pads_init(&sd->entity, 1, &gc2375h->pad);
1522 if (ret < 0)
1523 goto err_power_off;
1524 #endif
1525
1526 memset(facing, 0, sizeof(facing));
1527 if (strcmp(gc2375h->module_facing, "back") == 0)
1528 facing[0] = 'b';
1529 else
1530 facing[0] = 'f';
1531
1532 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1533 gc2375h->module_index, facing,
1534 GC2375H_NAME, dev_name(sd->dev));
1535 ret = v4l2_async_register_subdev_sensor_common(sd);
1536 if (ret) {
1537 dev_err(dev, "v4l2 async register subdev failed\n");
1538 goto err_clean_entity;
1539 }
1540
1541 pm_runtime_set_active(dev);
1542 pm_runtime_enable(dev);
1543 pm_runtime_idle(dev);
1544
1545 return 0;
1546
1547 err_clean_entity:
1548 #if defined(CONFIG_MEDIA_CONTROLLER)
1549 media_entity_cleanup(&sd->entity);
1550 #endif
1551 err_power_off:
1552 __gc2375h_power_off(gc2375h);
1553 err_free_handler:
1554 v4l2_ctrl_handler_free(&gc2375h->ctrl_handler);
1555 err_destroy_mutex:
1556 mutex_destroy(&gc2375h->mutex);
1557
1558 return ret;
1559 }
1560
gc2375h_remove(struct i2c_client * client)1561 static int gc2375h_remove(struct i2c_client *client)
1562 {
1563 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1564 struct gc2375h *gc2375h = to_gc2375h(sd);
1565
1566 v4l2_async_unregister_subdev(sd);
1567 #if defined(CONFIG_MEDIA_CONTROLLER)
1568 media_entity_cleanup(&sd->entity);
1569 #endif
1570 v4l2_ctrl_handler_free(&gc2375h->ctrl_handler);
1571 mutex_destroy(&gc2375h->mutex);
1572
1573 pm_runtime_disable(&client->dev);
1574 if (!pm_runtime_status_suspended(&client->dev))
1575 __gc2375h_power_off(gc2375h);
1576 pm_runtime_set_suspended(&client->dev);
1577
1578 return 0;
1579 }
1580
1581 #if IS_ENABLED(CONFIG_OF)
1582 static const struct of_device_id gc2375h_of_match[] = {
1583 { .compatible = "galaxycore,gc2375h" },
1584 {},
1585 };
1586 MODULE_DEVICE_TABLE(of, gc2375h_of_match);
1587 #endif
1588
1589 static const struct i2c_device_id gc2375h_match_id[] = {
1590 { "galaxycore,gc2375h", 0 },
1591 { },
1592 };
1593
1594 static struct i2c_driver gc2375h_i2c_driver = {
1595 .driver = {
1596 .name = GC2375H_NAME,
1597 .pm = &gc2375h_pm_ops,
1598 .of_match_table = of_match_ptr(gc2375h_of_match),
1599 },
1600 .probe = &gc2375h_probe,
1601 .remove = &gc2375h_remove,
1602 .id_table = gc2375h_match_id,
1603 };
1604
sensor_mod_init(void)1605 static int __init sensor_mod_init(void)
1606 {
1607 return i2c_add_driver(&gc2375h_i2c_driver);
1608 }
1609
sensor_mod_exit(void)1610 static void __exit sensor_mod_exit(void)
1611 {
1612 i2c_del_driver(&gc2375h_i2c_driver);
1613 }
1614
1615 device_initcall_sync(sensor_mod_init);
1616 module_exit(sensor_mod_exit);
1617
1618 MODULE_DESCRIPTION("GC2375H CMOS Image Sensor driver");
1619 MODULE_LICENSE("GPL v2");
1620