1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc2093 sensor driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01 Add HDR support.
9 * V0.0X01.0X02 update sensor driver
10 * 1. fix linear mode ae flicker issue.
11 * 2. add hdr mode exposure limit issue.
12 * 3. fix hdr mode highlighting pink issue.
13 * 4. add some debug info.
14 */
15 //#define DEBUG
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/of_graph.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/version.h>
26 #include <linux/rk-camera-module.h>
27 #include <linux/rk-preisp.h>
28
29 #include <media/v4l2-async.h>
30 #include <media/media-entity.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-fwnode.h>
34 #include <media/v4l2-subdev.h>
35 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
36
37 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
38 #define GC2093_NAME "gc2093"
39 #define GC2093_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
40
41 #define MIPI_FREQ_297M 297000000
42 #define MIPI_FREQ_396M 396000000
43
44 #define GC2093_XVCLK_FREQ 27000000
45
46 #define GC2093_REG_CHIP_ID_H 0x03F0
47 #define GC2093_REG_CHIP_ID_L 0x03F1
48
49 #define GC2093_REG_EXP_SHORT_H 0x0001
50 #define GC2093_REG_EXP_SHORT_L 0x0002
51 #define GC2093_REG_EXP_LONG_H 0x0003
52 #define GC2093_REG_EXP_LONG_L 0x0004
53
54 #define GC2093_REG_VB_H 0x0007
55 #define GC2093_REG_VB_L 0x0008
56
57 #define GC2093_REG_VTS_H 0x0041
58 #define GC2093_REG_VTS_L 0x0042
59
60 #define GC2093_MIRROR_FLIP_REG 0x0017
61 #define MIRROR_MASK BIT(0)
62 #define FLIP_MASK BIT(1)
63
64 #define GC2093_REG_CTRL_MODE 0x003E
65 #define GC2093_MODE_SW_STANDBY 0x11
66 #define GC2093_MODE_STREAMING 0x91
67
68 #define GC2093_CHIP_ID 0x2093
69
70 #define GC2093_VTS_MAX 0x3FFF
71 #define GC2093_HTS_MAX 0xFFF
72
73 #define GC2093_EXPOSURE_MAX 0x3FFF
74 #define GC2093_EXPOSURE_MIN 1
75 #define GC2093_EXPOSURE_STEP 1
76
77 #define GC2093_GAIN_MIN 0x40
78 #define GC2093_GAIN_MAX 0x2000
79 #define GC2093_GAIN_STEP 1
80 #define GC2093_GAIN_DEFAULT 64
81 #define REG_NULL 0xFFFF
82
83 #define GC2093_LANES 2
84
85 static const char * const gc2093_supply_names[] = {
86 "dovdd", /* Digital I/O power */
87 "avdd", /* Analog power */
88 "dvdd", /* Digital power */
89 };
90
91 #define GC2093_NUM_SUPPLIES ARRAY_SIZE(gc2093_supply_names)
92
93 #define to_gc2093(sd) container_of(sd, struct gc2093, subdev)
94
95 enum {
96 LINK_FREQ_297M_INDEX,
97 LINK_FREQ_396M_INDEX,
98 };
99
100 struct gain_reg_config {
101 u32 value;
102 u16 analog_gain;
103 u16 col_gain;
104 u16 analog_sw;
105 u16 ram_width;
106 };
107
108 struct gc2093_mode {
109 u32 width;
110 u32 height;
111 struct v4l2_fract max_fps;
112 u32 hts_def;
113 u32 vts_def;
114 u32 exp_def;
115 u32 link_freq_index;
116 const struct reg_sequence *reg_list;
117 u32 reg_num;
118 u32 hdr_mode;
119 u32 vc[PAD_MAX];
120 };
121
122 struct gc2093 {
123 struct device *dev;
124 struct clk *xvclk;
125 struct regmap *regmap;
126 struct gpio_desc *reset_gpio;
127 struct gpio_desc *pwdn_gpio;
128 struct regulator_bulk_data supplies[GC2093_NUM_SUPPLIES];
129
130 struct v4l2_subdev subdev;
131 struct media_pad pad;
132 struct v4l2_ctrl_handler ctrl_handler;
133 struct v4l2_ctrl *exposure;
134 struct v4l2_ctrl *anal_gain;
135 struct v4l2_ctrl *hblank;
136 struct v4l2_ctrl *vblank;
137 struct v4l2_ctrl *h_flip;
138 struct v4l2_ctrl *v_flip;
139 struct v4l2_ctrl *link_freq;
140 struct v4l2_ctrl *pixel_rate;
141
142 struct mutex lock;
143 bool streaming;
144 bool power_on;
145 unsigned int cfg_num;
146 const struct gc2093_mode *cur_mode;
147
148 u32 module_index;
149 const char *module_facing;
150 const char *module_name;
151 const char *len_name;
152
153 struct v4l2_fract cur_fps;
154 u32 cur_vts;
155
156 bool has_init_exp;
157 bool is_thunderboot;
158 bool is_first_streamoff;
159 struct preisp_hdrae_exp_s init_hdrae_exp;
160 };
161
162 static const struct regmap_config gc2093_regmap_config = {
163 .reg_bits = 16,
164 .val_bits = 8,
165 .max_register = 0x04f0,
166 };
167
168 static const s64 link_freq_menu_items[] = {
169 MIPI_FREQ_297M,
170 MIPI_FREQ_396M,
171 };
172
173 /*
174 * window size=1920*1080 mipi@2lane
175 * mclk=27M mipi_clk=594Mbps
176 * pixel_line_total=2200 line_frame_total=1125
177 * row_time=29.62us frame_rate=30fps
178 */
179 static const struct reg_sequence gc2093_1080p_liner_settings[] = {
180 /* System */
181 {0x03fe, 0x80},
182 {0x03fe, 0x80},
183 {0x03fe, 0x80},
184 {0x03fe, 0x00},
185 {0x03f2, 0x00},
186 {0x03f3, 0x00},
187 {0x03f4, 0x36},
188 {0x03f5, 0xc0},
189 {0x03f6, 0x0a},
190 {0x03f7, 0x01},
191 {0x03f8, 0x2c},
192 {0x03f9, 0x10},
193 {0x03fc, 0x8e},
194 /* Cisctl & Analog */
195 {0x0087, 0x18},
196 {0x00ee, 0x30},
197 {0x00d0, 0xb7},
198 {0x01a0, 0x00},
199 {0x01a4, 0x40},
200 {0x01a5, 0x40},
201 {0x01a6, 0x40},
202 {0x01af, 0x09},
203 {0x0001, 0x00},
204 {0x0002, 0x02},
205 {0x0003, 0x00},
206 {0x0004, 0x02},
207 {0x0005, 0x04},
208 {0x0006, 0x4c},
209 {0x0007, 0x00},
210 {0x0008, 0x11},
211 {0x0009, 0x00},
212 {0x000a, 0x02},
213 {0x000b, 0x00},
214 {0x000c, 0x04},
215 {0x000d, 0x04},
216 {0x000e, 0x40},
217 {0x000f, 0x07},
218 {0x0010, 0x8c},
219 {0x0013, 0x15},
220 {0x0019, 0x0c},
221 {0x0041, 0x04},
222 {0x0042, 0x65},
223 {0x0053, 0x60},
224 {0x008d, 0x92},
225 {0x0090, 0x00},
226 {0x00c7, 0xe1},
227 {0x001b, 0x73},
228 {0x0028, 0x0d},
229 {0x0029, 0x24},
230 {0x002b, 0x04},
231 {0x002e, 0x23},
232 {0x0037, 0x03},
233 {0x0043, 0x04},
234 {0x0044, 0x38},
235 {0x004a, 0x01},
236 {0x004b, 0x28},
237 {0x0055, 0x38},
238 {0x006b, 0x44},
239 {0x0077, 0x00},
240 {0x0078, 0x20},
241 {0x007c, 0xa1},
242 {0x00d3, 0xd4},
243 {0x00e6, 0x50},
244 /* Gain */
245 {0x00b6, 0xc0},
246 {0x00b0, 0x60},
247 /* Isp */
248 {0x0102, 0x89},
249 {0x0104, 0x01},
250 {0x010f, 0x00},
251 {0x0158, 0x00},
252 {0x0123, 0x08},
253 {0x0123, 0x00},
254 {0x0120, 0x01},
255 {0x0121, 0x00},
256 {0x0122, 0x10},
257 {0x0124, 0x03},
258 {0x0125, 0xff},
259 {0x0126, 0x3c},
260 {0x001a, 0x8c},
261 {0x00c6, 0xe0},
262 /* Blk */
263 {0x0026, 0x30},
264 {0x0142, 0x00},
265 {0x0149, 0x1e},
266 {0x014a, 0x07},
267 {0x014b, 0x80},
268 {0x0155, 0x00},
269 {0x0414, 0x78},
270 {0x0415, 0x78},
271 {0x0416, 0x78},
272 {0x0417, 0x78},
273 /* Window */
274 {0x0192, 0x02},
275 {0x0194, 0x03},
276 {0x0195, 0x04},
277 {0x0196, 0x38},
278 {0x0197, 0x07},
279 {0x0198, 0x80},
280 /* MIPI */
281 {0x019a, 0x06},
282 {0x007b, 0x2a},
283 {0x0023, 0x2d},
284 {0x0201, 0x27},
285 {0x0202, 0x56},
286 {0x0203, 0xce},
287 {0x0212, 0x80},
288 {0x0213, 0x07},
289 {0x003e, 0x91},
290 };
291
292 /*
293 * window size=1920*1080 mipi@2lane
294 * mclk=27M mipi_clk=792Mbps
295 * pixel_line_total=2640 line_frame_total=1250
296 * row_time=13.33us frame_rate=60fps
297 */
298 static const struct reg_sequence gc2093_1080p_hdr_settings[] = {
299 /* System */
300 {0x03fe, 0x80},
301 {0x03fe, 0x80},
302 {0x03fe, 0x80},
303 {0x03fe, 0x00},
304 {0x03f2, 0x00},
305 {0x03f3, 0x00},
306 {0x03f4, 0x36},
307 {0x03f5, 0xc0},
308 {0x03f6, 0x0B},
309 {0x03f7, 0x01},
310 {0x03f8, 0x58},
311 {0x03f9, 0x40},
312 {0x03fc, 0x8e},
313 /* Cisctl & Analog */
314 {0x0087, 0x18},
315 {0x00ee, 0x30},
316 {0x00d0, 0xbf},
317 {0x01a0, 0x00},
318 {0x01a4, 0x40},
319 {0x01a5, 0x40},
320 {0x01a6, 0x40},
321 {0x01af, 0x09},
322 {0x0001, 0x00},
323 {0x0002, 0x02},
324 {0x0003, 0x04},
325 {0x0004, 0x02},
326 {0x0005, 0x02},
327 {0x0006, 0x94},
328 {0x0007, 0x00},
329 {0x0008, 0x11},
330 {0x0009, 0x00},
331 {0x000a, 0x02},
332 {0x000b, 0x00},
333 {0x000c, 0x04},
334 {0x000d, 0x04},
335 {0x000e, 0x40},
336 {0x000f, 0x07},
337 {0x0010, 0x8c},
338 {0x0013, 0x15},
339 {0x0019, 0x0c},
340 {0x0041, 0x04},
341 {0x0042, 0xe2},
342 {0x0053, 0x60},
343 {0x008d, 0x92},
344 {0x0090, 0x00},
345 {0x00c7, 0xe1},
346 {0x001b, 0x73},
347 {0x0028, 0x0d},
348 {0x0029, 0x24},
349 {0x002b, 0x04},
350 {0x002e, 0x23},
351 {0x0037, 0x03},
352 {0x0043, 0x04},
353 {0x0044, 0x20},
354 {0x004a, 0x01},
355 {0x004b, 0x20},
356 {0x0055, 0x30},
357 {0x006b, 0x44},
358 {0x0077, 0x00},
359 {0x0078, 0x20},
360 {0x007c, 0xa1},
361 {0x00d3, 0xd4},
362 {0x00e6, 0x50},
363 /* Gain */
364 {0x00b6, 0xc0},
365 {0x00b0, 0x60},
366 /* Isp */
367 {0x0102, 0x89},
368 {0x0104, 0x01},
369 {0x010e, 0x01},
370 {0x0158, 0x00},
371 {0x0183, 0x01},
372 {0x0187, 0x50},
373 /* Dark sun*/
374 {0x0123, 0x08},
375 {0x0123, 0x00},
376 {0x0120, 0x01},
377 {0x0121, 0x00},
378 {0x0122, 0x10},
379 {0x0124, 0x03},
380 {0x0125, 0xff},
381 {0x0126, 0x3c},
382 {0x001a, 0x8c},
383 {0x00c6, 0xe0},
384 /* Blk */
385 {0x0026, 0x30},
386 {0x0142, 0x00},
387 {0x0149, 0x1e},
388 {0x014a, 0x0f},
389 {0x014b, 0x00},
390 {0x0155, 0x00},
391 {0x0414, 0x78},
392 {0x0415, 0x78},
393 {0x0416, 0x78},
394 {0x0417, 0x78},
395 {0x0454, 0x78},
396 {0x0455, 0x78},
397 {0x0456, 0x78},
398 {0x0457, 0x78},
399 {0x04e0, 0x18},
400 /* Window */
401 {0x0192, 0x02},
402 {0x0194, 0x03},
403 {0x0195, 0x04},
404 {0x0196, 0x38},
405 {0x0197, 0x07},
406 {0x0198, 0x80},
407 /* MIPI */
408 {0x019a, 0x06},
409 {0x007b, 0x2a},
410 {0x0023, 0x2d},
411 {0x0201, 0x27},
412 {0x0202, 0x56},
413 {0x0203, 0xb6},
414 {0x0212, 0x80},
415 {0x0213, 0x07},
416 {0x0215, 0x12},
417 {0x003e, 0x91},
418 /* HDR En */
419 {0x0027, 0x71},
420 {0x0215, 0x92},
421 {0x024d, 0x01},
422 };
423
424 static const struct gc2093_mode supported_modes[] = {
425 {
426 .width = 1920,
427 .height = 1080,
428 .max_fps = {
429 .numerator = 10000,
430 .denominator = 300000,
431 },
432 .exp_def = 0x460,
433 .hts_def = 0x898,
434 .vts_def = 0x465,
435 .link_freq_index = LINK_FREQ_297M_INDEX,
436 .reg_list = gc2093_1080p_liner_settings,
437 .reg_num = ARRAY_SIZE(gc2093_1080p_liner_settings),
438 .hdr_mode = NO_HDR,
439 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
440 },
441 {
442 .width = 1920,
443 .height = 1080,
444 .max_fps = {
445 .numerator = 10000,
446 .denominator = 300000,
447 },
448 .exp_def = 0x460,
449 .hts_def = 0xa50,
450 .vts_def = 0x4e2,
451 .link_freq_index = LINK_FREQ_396M_INDEX,
452 .reg_list = gc2093_1080p_hdr_settings,
453 .reg_num = ARRAY_SIZE(gc2093_1080p_hdr_settings),
454 .hdr_mode = HDR_X2,
455 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
456 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
457 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
458 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
459 },
460 };
461
462 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
463 /* * 2, to match suitable isp freq */
to_pixel_rate(u32 index)464 static u64 to_pixel_rate(u32 index)
465 {
466 u64 pixel_rate = link_freq_menu_items[index] * 2 * GC2093_LANES * 2;
467
468 do_div(pixel_rate, 10);
469
470 return pixel_rate;
471 }
472
gc2093_read_reg(struct gc2093 * gc2093,u16 addr,u8 * value)473 static inline int gc2093_read_reg(struct gc2093 *gc2093, u16 addr, u8 *value)
474 {
475 unsigned int val;
476 int ret;
477
478 ret = regmap_read(gc2093->regmap, addr, &val);
479 if (ret) {
480 dev_err(gc2093->dev, "i2c read failed at addr: %x\n", addr);
481 return ret;
482 }
483
484 *value = val & 0xff;
485
486 return 0;
487 }
488
gc2093_write_reg(struct gc2093 * gc2093,u16 addr,u8 value)489 static inline int gc2093_write_reg(struct gc2093 *gc2093, u16 addr, u8 value)
490 {
491 int ret;
492
493 ret = regmap_write(gc2093->regmap, addr, value);
494 if (ret) {
495 dev_err(gc2093->dev, "i2c write failed at addr: %x\n", addr);
496 return ret;
497 }
498
499 return ret;
500 }
501
502 static const struct gain_reg_config gain_reg_configs[] = {
503 { 64, 0x0000, 0x0100, 0x6807, 0x00f8},
504 { 75, 0x0010, 0x010c, 0x6807, 0x00f8},
505 { 90, 0x0020, 0x011b, 0x6c08, 0x00f9},
506 { 105, 0x0030, 0x012c, 0x6c0a, 0x00fa},
507 { 122, 0x0040, 0x013f, 0x7c0b, 0x00fb},
508 { 142, 0x0050, 0x0216, 0x7c0d, 0x00fe},
509 { 167, 0x0060, 0x0235, 0x7c0e, 0x00ff},
510 { 193, 0x0070, 0x0316, 0x7c10, 0x0801},
511 { 223, 0x0080, 0x0402, 0x7c12, 0x0802},
512 { 257, 0x0090, 0x0431, 0x7c13, 0x0803},
513 { 299, 0x00a0, 0x0532, 0x7c15, 0x0805},
514 { 346, 0x00b0, 0x0635, 0x7c17, 0x0807},
515 { 397, 0x00c0, 0x0804, 0x7c18, 0x0808},
516 { 444, 0x005a, 0x0919, 0x7c17, 0x0807},
517 { 523, 0x0083, 0x0b0f, 0x7c17, 0x0807},
518 { 607, 0x0093, 0x0d12, 0x7c19, 0x0809},
519 { 700, 0x0084, 0x1000, 0x7c1b, 0x080c},
520 { 817, 0x0094, 0x123a, 0x7c1e, 0x080f},
521 {1131, 0x005d, 0x1a02, 0x7c23, 0x0814},
522 {1142, 0x009b, 0x1b20, 0x7c25, 0x0816},
523 {1334, 0x008c, 0x200f, 0x7c27, 0x0818},
524 {1568, 0x009c, 0x2607, 0x7c2a, 0x081b},
525 {2195, 0x00b6, 0x3621, 0x7c32, 0x0823},
526 {2637, 0x00ad, 0x373a, 0x7c36, 0x0827},
527 {3121, 0x00bd, 0x3d02, 0x7c3a, 0x082b},
528 };
529
gc2093_set_gain(struct gc2093 * gc2093,u32 gain)530 static int gc2093_set_gain(struct gc2093 *gc2093, u32 gain)
531 {
532 int ret, i = 0;
533 u16 pre_gain = 0;
534
535 for (i = 0; i < ARRAY_SIZE(gain_reg_configs) - 1; i++)
536 if ((gain_reg_configs[i].value <= gain) && (gain < gain_reg_configs[i+1].value))
537 break;
538
539 ret = gc2093_write_reg(gc2093, 0x00b4, gain_reg_configs[i].analog_gain >> 8);
540 ret |= gc2093_write_reg(gc2093, 0x00b3, gain_reg_configs[i].analog_gain & 0xff);
541 ret |= gc2093_write_reg(gc2093, 0x00b8, gain_reg_configs[i].col_gain >> 8);
542 ret |= gc2093_write_reg(gc2093, 0x00b9, gain_reg_configs[i].col_gain & 0xff);
543 ret |= gc2093_write_reg(gc2093, 0x00ce, gain_reg_configs[i].analog_sw >> 8);
544 ret |= gc2093_write_reg(gc2093, 0x00c2, gain_reg_configs[i].analog_sw & 0xff);
545 ret |= gc2093_write_reg(gc2093, 0x00cf, gain_reg_configs[i].ram_width >> 8);
546 ret |= gc2093_write_reg(gc2093, 0x00d9, gain_reg_configs[i].ram_width & 0xff);
547
548 pre_gain = 64 * gain / gain_reg_configs[i].value;
549
550 ret |= gc2093_write_reg(gc2093, 0x00b1, (pre_gain >> 6));
551 ret |= gc2093_write_reg(gc2093, 0x00b2, ((pre_gain & 0x3f) << 2));
552
553 return ret;
554 }
555
gc2093_modify_fps_info(struct gc2093 * gc2093)556 static void gc2093_modify_fps_info(struct gc2093 *gc2093)
557 {
558 const struct gc2093_mode *mode = gc2093->cur_mode;
559
560 gc2093->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
561 gc2093->cur_vts;
562 }
563
gc2093_set_ctrl(struct v4l2_ctrl * ctrl)564 static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl)
565 {
566 struct gc2093 *gc2093 = container_of(ctrl->handler,
567 struct gc2093, ctrl_handler);
568 s64 max;
569 int ret = 0;
570 u32 vts = 0;
571
572 /* Propagate change of current control to all related controls */
573 switch (ctrl->id) {
574 case V4L2_CID_VBLANK:
575 /* Update max exposure while meeting expected vblanking */
576 max = gc2093->cur_mode->height + ctrl->val - 4;
577 __v4l2_ctrl_modify_range(gc2093->exposure,
578 gc2093->exposure->minimum, max,
579 gc2093->exposure->step,
580 gc2093->exposure->default_value);
581 break;
582 }
583 if (!pm_runtime_get_if_in_use(gc2093->dev))
584 return 0;
585
586 switch (ctrl->id) {
587 case V4L2_CID_EXPOSURE:
588 if (gc2093->cur_mode->hdr_mode != NO_HDR)
589 goto ctrl_end;
590 dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
591 ret = gc2093_write_reg(gc2093, GC2093_REG_EXP_LONG_H,
592 (ctrl->val >> 8) & 0x3f);
593 ret |= gc2093_write_reg(gc2093, GC2093_REG_EXP_LONG_L,
594 ctrl->val & 0xff);
595 break;
596 case V4L2_CID_ANALOGUE_GAIN:
597 if (gc2093->cur_mode->hdr_mode != NO_HDR)
598 goto ctrl_end;
599 dev_dbg(gc2093->dev, "set gain value 0x%x\n", ctrl->val);
600 gc2093_set_gain(gc2093, ctrl->val);
601 break;
602 case V4L2_CID_VBLANK:
603 vts = gc2093->cur_mode->height + ctrl->val;
604 gc2093->cur_vts = vts;
605 ret = gc2093_write_reg(gc2093, GC2093_REG_VTS_H,
606 (vts >> 8) & 0x3f);
607 ret |= gc2093_write_reg(gc2093, GC2093_REG_VTS_L,
608 vts & 0xff);
609 gc2093_modify_fps_info(gc2093);
610 dev_dbg(gc2093->dev, " set blank value 0x%x\n", ctrl->val);
611 break;
612 case V4L2_CID_HFLIP:
613 regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
614 MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
615 break;
616 case V4L2_CID_VFLIP:
617 regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
618 FLIP_MASK, ctrl->val ? FLIP_MASK : 0);
619 break;
620 default:
621 dev_warn(gc2093->dev, "%s Unhandled id:0x%x, val:0x%x\n",
622 __func__, ctrl->id, ctrl->val);
623 break;
624 }
625
626 ctrl_end:
627 pm_runtime_put(gc2093->dev);
628 return ret;
629 }
630
631 static const struct v4l2_ctrl_ops gc2093_ctrl_ops = {
632 .s_ctrl = gc2093_set_ctrl,
633 };
634
gc2093_get_regulators(struct gc2093 * gc2093)635 static int gc2093_get_regulators(struct gc2093 *gc2093)
636 {
637 unsigned int i;
638
639 for (i = 0; i < GC2093_NUM_SUPPLIES; i++)
640 gc2093->supplies[i].supply = gc2093_supply_names[i];
641
642 return devm_regulator_bulk_get(gc2093->dev,
643 GC2093_NUM_SUPPLIES,
644 gc2093->supplies);
645 }
646
gc2093_initialize_controls(struct gc2093 * gc2093)647 static int gc2093_initialize_controls(struct gc2093 *gc2093)
648 {
649 const struct gc2093_mode *mode;
650 struct v4l2_ctrl_handler *handler;
651 s64 exposure_max, vblank_def;
652 u32 h_blank;
653 int ret;
654
655 handler = &gc2093->ctrl_handler;
656 mode = gc2093->cur_mode;
657 ret = v4l2_ctrl_handler_init(handler, 8);
658 if (ret)
659 return ret;
660 handler->lock = &gc2093->lock;
661
662 gc2093->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
663 ARRAY_SIZE(link_freq_menu_items) - 1, 0,
664 link_freq_menu_items);
665
666 gc2093->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
667 0, to_pixel_rate(LINK_FREQ_396M_INDEX),
668 1, to_pixel_rate(LINK_FREQ_297M_INDEX));
669
670 h_blank = mode->hts_def - mode->width;
671 gc2093->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
672 h_blank, h_blank, 1, h_blank);
673 if (gc2093->hblank)
674 gc2093->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
675
676 vblank_def = mode->vts_def - mode->height;
677 gc2093->cur_vts = mode->vts_def;
678 gc2093->vblank = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops,
679 V4L2_CID_VBLANK, vblank_def,
680 GC2093_VTS_MAX - mode->height,
681 1, vblank_def);
682
683 exposure_max = mode->vts_def - 4;
684 gc2093->exposure = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops,
685 V4L2_CID_EXPOSURE, GC2093_EXPOSURE_MIN,
686 exposure_max, GC2093_EXPOSURE_STEP,
687 mode->exp_def);
688
689 gc2093->anal_gain = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops,
690 V4L2_CID_ANALOGUE_GAIN, GC2093_GAIN_MIN,
691 GC2093_GAIN_MAX, GC2093_GAIN_STEP,
692 GC2093_GAIN_DEFAULT);
693
694 gc2093->h_flip = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops,
695 V4L2_CID_HFLIP, 0, 1, 1, 0);
696
697 gc2093->v_flip = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops,
698 V4L2_CID_VFLIP, 0, 1, 1, 0);
699
700 if (handler->error) {
701 ret = handler->error;
702 dev_err(gc2093->dev, "Failed to init controls(%d)\n", ret);
703 goto err_free_handler;
704 }
705
706 gc2093->subdev.ctrl_handler = handler;
707 gc2093->has_init_exp = false;
708 gc2093->cur_vts = mode->vts_def;
709 gc2093->cur_fps = mode->max_fps;
710
711 return 0;
712
713 err_free_handler:
714 v4l2_ctrl_handler_free(handler);
715 return ret;
716 }
717
__gc2093_power_on(struct gc2093 * gc2093)718 static int __gc2093_power_on(struct gc2093 *gc2093)
719 {
720 int ret;
721 struct device *dev = gc2093->dev;
722
723 ret = clk_set_rate(gc2093->xvclk, GC2093_XVCLK_FREQ);
724 if (ret < 0)
725 dev_warn(dev, "Failed to set xvclk rate\n");
726
727 if (clk_get_rate(gc2093->xvclk) != GC2093_XVCLK_FREQ)
728 dev_warn(dev, "xvclk mismatched, modes are based on 27MHz\n");
729
730 ret = clk_prepare_enable(gc2093->xvclk);
731 if (ret < 0) {
732 dev_err(dev, "Failed to enable xvclk\n");
733 return ret;
734 }
735
736 if (gc2093->is_thunderboot)
737 return 0;
738
739 ret = regulator_bulk_enable(GC2093_NUM_SUPPLIES, gc2093->supplies);
740 if (ret < 0) {
741 dev_err(dev, "Failed to enable regulators\n");
742 goto disable_clk;
743 }
744
745 if (!IS_ERR(gc2093->reset_gpio))
746 gpiod_direction_output(gc2093->reset_gpio, 1);
747
748 usleep_range(1000, 2000);
749
750 if (!IS_ERR(gc2093->pwdn_gpio))
751 gpiod_direction_output(gc2093->pwdn_gpio, 1);
752 if (!IS_ERR(gc2093->reset_gpio))
753 gpiod_direction_output(gc2093->reset_gpio, 0);
754
755 usleep_range(10000, 20000);
756
757 return 0;
758
759 disable_clk:
760 clk_disable_unprepare(gc2093->xvclk);
761 return ret;
762 }
763
__gc2093_power_off(struct gc2093 * gc2093)764 static void __gc2093_power_off(struct gc2093 *gc2093)
765 {
766 clk_disable_unprepare(gc2093->xvclk);
767 if (gc2093->is_thunderboot) {
768 if (gc2093->is_first_streamoff) {
769 gc2093->is_thunderboot = false;
770 gc2093->is_first_streamoff = false;
771 } else {
772 return;
773 }
774 }
775
776 if (!IS_ERR(gc2093->reset_gpio))
777 gpiod_direction_output(gc2093->reset_gpio, 1);
778 if (!IS_ERR(gc2093->pwdn_gpio))
779 gpiod_direction_output(gc2093->pwdn_gpio, 0);
780
781 regulator_bulk_disable(GC2093_NUM_SUPPLIES, gc2093->supplies);
782 }
783
gc2093_check_sensor_id(struct gc2093 * gc2093)784 static int gc2093_check_sensor_id(struct gc2093 *gc2093)
785 {
786 struct device *dev = gc2093->dev;
787 u8 id_h = 0, id_l = 0;
788 u16 id = 0;
789 int ret = 0;
790
791 if (gc2093->is_thunderboot) {
792 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
793 return 0;
794 }
795
796 ret = gc2093_read_reg(gc2093, GC2093_REG_CHIP_ID_H, &id_h);
797 ret |= gc2093_read_reg(gc2093, GC2093_REG_CHIP_ID_L, &id_l);
798 if (ret) {
799 dev_err(gc2093->dev, "Failed to read sensor id, (%d)\n", ret);
800 return ret;
801 }
802
803 id = id_h << 8 | id_l;
804 if (id != GC2093_CHIP_ID) {
805 dev_err(gc2093->dev, "sensor id: %04X mismatched\n", id);
806 return -ENODEV;
807 }
808
809 dev_info(gc2093->dev, "Detected GC2093 sensor\n");
810 return 0;
811 }
812
gc2093_get_module_inf(struct gc2093 * gc2093,struct rkmodule_inf * inf)813 static void gc2093_get_module_inf(struct gc2093 *gc2093,
814 struct rkmodule_inf *inf)
815 {
816 memset(inf, 0, sizeof(*inf));
817 strlcpy(inf->base.lens, gc2093->len_name, sizeof(inf->base.lens));
818 strlcpy(inf->base.sensor, GC2093_NAME, sizeof(inf->base.sensor));
819 strlcpy(inf->base.module, gc2093->module_name, sizeof(inf->base.module));
820 }
821
gc2093_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)822 static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
823 {
824 struct gc2093 *gc2093 = to_gc2093(sd);
825 struct preisp_hdrae_exp_s *hdrae_exp = arg;
826 struct rkmodule_hdr_cfg *hdr_cfg;
827 long ret = 0;
828 u32 i, h, w;
829 u32 stream = 0;
830 u8 vb_h = 0, vb_l = 0;
831 u16 vb = 0, cur_vts = 0, short_exp = 0, middle_exp = 0;
832 u64 delay_us = 0;
833 u32 fps = 0;
834
835 switch (cmd) {
836 case PREISP_CMD_SET_HDRAE_EXP:
837 if (!gc2093->has_init_exp && !gc2093->streaming) {
838 gc2093->init_hdrae_exp = *hdrae_exp;
839 gc2093->has_init_exp = true;
840 dev_info(gc2093->dev, "don't streaming, record hdrae\n");
841 break;
842 }
843
844 ret = gc2093_set_gain(gc2093, hdrae_exp->short_gain_reg);
845 if (ret) {
846 dev_err(gc2093->dev, "Failed to set gain!)\n");
847 return ret;
848 }
849
850 dev_dbg(gc2093->dev, "%s exp_reg middle: 0x%x, short: 0x%x, gain 0x%x\n",
851 __func__, hdrae_exp->middle_exp_reg,
852 hdrae_exp->short_exp_reg, hdrae_exp->short_gain_reg);
853 // Optimize blooming effect
854 if (hdrae_exp->middle_exp_reg < 0x30 || hdrae_exp->short_exp_reg < 4)
855 gc2093_write_reg(gc2093, 0x0032, 0xfd);
856 else
857 gc2093_write_reg(gc2093, 0x0032, 0xf8);
858
859 /* hdr exp limit
860 * 1. max short_exp_reg < VB
861 * 2. short_exp_reg + middle_exp_reg < framelength
862 */
863 /* 30FPS sample */
864 // if (hdrae_exp->middle_exp_reg > 1100)
865 // hdrae_exp->middle_exp_reg = 1100;
866 //
867 // if (hdrae_exp->short_exp_reg > 68)
868 // hdrae_exp->short_exp_reg = 68;
869
870 ret = gc2093_read_reg(gc2093, GC2093_REG_VB_H, &vb_h);
871 ret |= gc2093_read_reg(gc2093, GC2093_REG_VB_L, &vb_l);
872 if (ret) {
873 dev_err(gc2093->dev, "Failed to read vb data)\n");
874 return ret;
875 }
876 vb = vb_h << 8 | vb_l;
877
878 /* max short exposure limit to 3 ms */
879 if (hdrae_exp->short_exp_reg <= (vb - 8)) {
880 short_exp = hdrae_exp->short_exp_reg;
881 } else {
882 short_exp = vb - 8;
883 dev_err(gc2093->dev, "short exposure should be less than %d\n",
884 vb - 8);
885 }
886 cur_vts = gc2093->cur_vts;
887 dev_dbg(gc2093->dev, "%s cur_vts: 0x%x\n", __func__, cur_vts);
888
889 if (short_exp + hdrae_exp->middle_exp_reg > cur_vts) {
890 middle_exp = cur_vts - short_exp;
891 dev_err(gc2093->dev, "total exposure should be less than %d\n",
892 cur_vts);
893 } else {
894 middle_exp = hdrae_exp->middle_exp_reg;
895 }
896 dev_dbg(gc2093->dev, "%s cal exp_reg middle: 0x%x, short: 0x%x\n",
897 __func__, middle_exp, short_exp);
898 ret |= gc2093_write_reg(gc2093, GC2093_REG_EXP_LONG_H,
899 (middle_exp >> 8) & 0x3f);
900 ret |= gc2093_write_reg(gc2093, GC2093_REG_EXP_LONG_L,
901 middle_exp & 0xff);
902 ret |= gc2093_write_reg(gc2093, GC2093_REG_EXP_SHORT_H,
903 (short_exp >> 8) & 0x3f);
904 ret |= gc2093_write_reg(gc2093, GC2093_REG_EXP_SHORT_L,
905 short_exp & 0xff);
906 break;
907 case RKMODULE_GET_HDR_CFG:
908 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
909 hdr_cfg->esp.mode = HDR_NORMAL_VC;
910 hdr_cfg->hdr_mode = gc2093->cur_mode->hdr_mode;
911 break;
912 case RKMODULE_SET_HDR_CFG:
913 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
914 w = gc2093->cur_mode->width;
915 h = gc2093->cur_mode->height;
916 for (i = 0; i < gc2093->cfg_num; i++) {
917 if (w == supported_modes[i].width &&
918 h == supported_modes[i].height &&
919 supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
920 gc2093->cur_mode = &supported_modes[i];
921 break;
922 }
923 }
924 if (i == gc2093->cfg_num) {
925 dev_err(gc2093->dev, "not find hdr mode:%d %dx%d config\n",
926 hdr_cfg->hdr_mode, w, h);
927 ret = -EINVAL;
928 } else {
929 w = gc2093->cur_mode->hts_def - gc2093->cur_mode->width;
930 h = gc2093->cur_mode->vts_def - gc2093->cur_mode->height;
931 __v4l2_ctrl_modify_range(gc2093->hblank, w, w, 1, w);
932 __v4l2_ctrl_modify_range(gc2093->vblank, h,
933 GC2093_VTS_MAX - gc2093->cur_mode->height,
934 1, h);
935 gc2093->cur_vts = gc2093->cur_mode->vts_def;
936 gc2093->cur_fps = gc2093->cur_mode->max_fps;
937 dev_info(gc2093->dev, "sensor mode: %d\n",
938 gc2093->cur_mode->hdr_mode);
939 }
940 break;
941 case RKMODULE_GET_MODULE_INFO:
942 gc2093_get_module_inf(gc2093, (struct rkmodule_inf *)arg);
943 break;
944 case RKMODULE_SET_QUICK_STREAM:
945
946 stream = *((u32 *)arg);
947
948 if (stream) {
949 ret = gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
950 GC2093_MODE_STREAMING);
951 } else {
952 ret = gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
953 GC2093_MODE_SW_STANDBY);
954 fps = gc2093->cur_mode->max_fps.denominator /
955 gc2093->cur_mode->max_fps.numerator;
956 delay_us = 1000000 / (gc2093->cur_mode->vts_def * fps / gc2093->cur_vts);
957 usleep_range(delay_us, delay_us + 2000);
958 }
959 break;
960 default:
961 ret = -ENOIOCTLCMD;
962 break;
963 }
964 return ret;
965 }
966
__gc2093_start_stream(struct gc2093 * gc2093)967 static int __gc2093_start_stream(struct gc2093 *gc2093)
968 {
969 int ret;
970
971 if (!gc2093->is_thunderboot) {
972 ret = regmap_multi_reg_write(gc2093->regmap,
973 gc2093->cur_mode->reg_list,
974 gc2093->cur_mode->reg_num);
975 if (ret)
976 return ret;
977
978 /* Apply customized control from user */
979 mutex_unlock(&gc2093->lock);
980 v4l2_ctrl_handler_setup(&gc2093->ctrl_handler);
981 mutex_lock(&gc2093->lock);
982
983 if (gc2093->has_init_exp && gc2093->cur_mode->hdr_mode != NO_HDR) {
984 ret = gc2093_ioctl(&gc2093->subdev, PREISP_CMD_SET_HDRAE_EXP,
985 &gc2093->init_hdrae_exp);
986 if (ret) {
987 dev_err(gc2093->dev, "init exp fail in hdr mode\n");
988 return ret;
989 }
990 }
991 }
992 return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
993 GC2093_MODE_STREAMING);
994 }
995
__gc2093_stop_stream(struct gc2093 * gc2093)996 static int __gc2093_stop_stream(struct gc2093 *gc2093)
997 {
998 gc2093->has_init_exp = false;
999 if (gc2093->is_thunderboot) {
1000 gc2093->is_first_streamoff = true;
1001 pm_runtime_put(gc2093->dev);
1002 }
1003 return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
1004 GC2093_MODE_SW_STANDBY);
1005 }
1006
1007 #ifdef CONFIG_COMPAT
gc2093_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1008 static long gc2093_compat_ioctl32(struct v4l2_subdev *sd,
1009 unsigned int cmd, unsigned long arg)
1010 {
1011 void __user *up = compat_ptr(arg);
1012 struct rkmodule_inf *inf;
1013 struct rkmodule_hdr_cfg *hdr;
1014 struct preisp_hdrae_exp_s *hdrae;
1015 long ret = 0;
1016 u32 stream = 0;
1017
1018 switch (cmd) {
1019 case RKMODULE_GET_MODULE_INFO:
1020 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1021 if (!inf) {
1022 ret = -ENOMEM;
1023 return ret;
1024 }
1025
1026 ret = gc2093_ioctl(sd, cmd, inf);
1027 if (!ret) {
1028 ret = copy_to_user(up, inf, sizeof(*inf));
1029 if (ret)
1030 ret = -EFAULT;
1031 }
1032 kfree(inf);
1033 break;
1034 case RKMODULE_GET_HDR_CFG:
1035 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1036 if (!hdr) {
1037 ret = -ENOMEM;
1038 return ret;
1039 }
1040
1041 ret = gc2093_ioctl(sd, cmd, hdr);
1042 if (!ret) {
1043 ret = copy_to_user(up, hdr, sizeof(*hdr));
1044 if (ret)
1045 ret = -EFAULT;
1046 }
1047 kfree(hdr);
1048 break;
1049 case RKMODULE_SET_HDR_CFG:
1050 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1051 if (!hdr) {
1052 ret = -ENOMEM;
1053 return ret;
1054 }
1055
1056 ret = copy_from_user(hdr, up, sizeof(*hdr));
1057 if (!ret)
1058 ret = gc2093_ioctl(sd, cmd, hdr);
1059 else
1060 ret = -EFAULT;
1061 kfree(hdr);
1062 break;
1063 case PREISP_CMD_SET_HDRAE_EXP:
1064 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1065 if (!hdrae) {
1066 ret = -ENOMEM;
1067 return ret;
1068 }
1069
1070 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1071 if (!ret)
1072 ret = gc2093_ioctl(sd, cmd, hdrae);
1073 else
1074 ret = -EFAULT;
1075 kfree(hdrae);
1076 break;
1077 case RKMODULE_SET_QUICK_STREAM:
1078 ret = copy_from_user(&stream, up, sizeof(u32));
1079 if (!ret)
1080 ret = gc2093_ioctl(sd, cmd, &stream);
1081 else
1082 ret = -EFAULT;
1083 break;
1084 default:
1085 ret = -ENOIOCTLCMD;
1086 break;
1087 }
1088 return ret;
1089 }
1090 #endif
1091
gc2093_s_stream(struct v4l2_subdev * sd,int on)1092 static int gc2093_s_stream(struct v4l2_subdev *sd, int on)
1093 {
1094 struct gc2093 *gc2093 = to_gc2093(sd);
1095 int ret = 0;
1096 unsigned int fps;
1097 unsigned int delay_us;
1098
1099 fps = DIV_ROUND_CLOSEST(gc2093->cur_mode->max_fps.denominator,
1100 gc2093->cur_mode->max_fps.numerator);
1101
1102 dev_info(gc2093->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1103 gc2093->cur_mode->width,
1104 gc2093->cur_mode->height,
1105 fps);
1106
1107 mutex_lock(&gc2093->lock);
1108 on = !!on;
1109 if (on == gc2093->streaming)
1110 goto unlock_and_return;
1111
1112 if (on) {
1113 if (gc2093->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1114 gc2093->is_thunderboot = false;
1115 __gc2093_power_on(gc2093);
1116 }
1117 ret = pm_runtime_get_sync(gc2093->dev);
1118 if (ret < 0) {
1119 pm_runtime_put_noidle(gc2093->dev);
1120 goto unlock_and_return;
1121 }
1122
1123 ret = __gc2093_start_stream(gc2093);
1124 if (ret) {
1125 dev_err(gc2093->dev, "Failed to start gc2093 stream\n");
1126 pm_runtime_put(gc2093->dev);
1127 goto unlock_and_return;
1128 }
1129 } else {
1130 __gc2093_stop_stream(gc2093);
1131 /* delay to enable oneframe complete */
1132 delay_us = 1000 * 1000 / fps;
1133 usleep_range(delay_us, delay_us+10);
1134 dev_info(gc2093->dev, "%s: on: %d, sleep(%dus)\n",
1135 __func__, on, delay_us);
1136
1137 pm_runtime_put(gc2093->dev);
1138 }
1139
1140 gc2093->streaming = on;
1141
1142 unlock_and_return:
1143 mutex_unlock(&gc2093->lock);
1144 return 0;
1145 }
1146
gc2093_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1147 static int gc2093_g_frame_interval(struct v4l2_subdev *sd,
1148 struct v4l2_subdev_frame_interval *fi)
1149 {
1150 struct gc2093 *gc2093 = to_gc2093(sd);
1151 const struct gc2093_mode *mode = gc2093->cur_mode;
1152
1153 fi->interval = mode->max_fps;
1154
1155 return 0;
1156 }
1157
gc2093_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1158 static int gc2093_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1159 struct v4l2_mbus_config *config)
1160 {
1161 struct gc2093 *gc2093 = to_gc2093(sd);
1162 u32 val = 1 << (GC2093_LANES - 1) | V4L2_MBUS_CSI2_CHANNEL_0 |
1163 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1164
1165 config->type = V4L2_MBUS_CSI2_DPHY;
1166 config->flags = (gc2093->cur_mode->hdr_mode == NO_HDR) ?
1167 val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
1168
1169 return 0;
1170 }
1171
gc2093_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1172 static int gc2093_enum_mbus_code(struct v4l2_subdev *sd,
1173 struct v4l2_subdev_pad_config *cfg,
1174 struct v4l2_subdev_mbus_code_enum *code)
1175 {
1176 if (code->index != 0)
1177 return -EINVAL;
1178 code->code = GC2093_MEDIA_BUS_FMT;
1179 return 0;
1180 }
1181
gc2093_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1182 static int gc2093_enum_frame_sizes(struct v4l2_subdev *sd,
1183 struct v4l2_subdev_pad_config *cfg,
1184 struct v4l2_subdev_frame_size_enum *fse)
1185 {
1186 struct gc2093 *gc2093 = to_gc2093(sd);
1187
1188 if (fse->index >= gc2093->cfg_num)
1189 return -EINVAL;
1190
1191 if (fse->code != GC2093_MEDIA_BUS_FMT)
1192 return -EINVAL;
1193
1194 fse->min_width = supported_modes[fse->index].width;
1195 fse->max_width = supported_modes[fse->index].width;
1196 fse->max_height = supported_modes[fse->index].height;
1197 fse->min_height = supported_modes[fse->index].height;
1198 return 0;
1199 }
1200
gc2093_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1201 static int gc2093_enum_frame_interval(struct v4l2_subdev *sd,
1202 struct v4l2_subdev_pad_config *cfg,
1203 struct v4l2_subdev_frame_interval_enum *fie)
1204 {
1205 struct gc2093 *gc2093 = to_gc2093(sd);
1206
1207 if (fie->index >= gc2093->cfg_num)
1208 return -EINVAL;
1209
1210 fie->code = GC2093_MEDIA_BUS_FMT;
1211 fie->width = supported_modes[fie->index].width;
1212 fie->height = supported_modes[fie->index].height;
1213 fie->interval = supported_modes[fie->index].max_fps;
1214 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1215 return 0;
1216 }
1217
gc2093_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1218 static int gc2093_set_fmt(struct v4l2_subdev *sd,
1219 struct v4l2_subdev_pad_config *cfg,
1220 struct v4l2_subdev_format *fmt)
1221 {
1222 struct gc2093 *gc2093 = to_gc2093(sd);
1223 const struct gc2093_mode *mode;
1224 s64 h_blank, vblank_def;
1225
1226 mutex_lock(&gc2093->lock);
1227
1228 mode = v4l2_find_nearest_size(supported_modes,
1229 ARRAY_SIZE(supported_modes),
1230 width, height,
1231 fmt->format.width, fmt->format.height);
1232
1233 fmt->format.code = GC2093_MEDIA_BUS_FMT;
1234 fmt->format.width = mode->width;
1235 fmt->format.height = mode->height;
1236 fmt->format.field = V4L2_FIELD_NONE;
1237 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1238 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1239 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1240 #else
1241 mutex_unlock(&gc2093->lock);
1242 return -ENOTTY;
1243 #endif
1244 } else {
1245 gc2093->cur_mode = mode;
1246 __v4l2_ctrl_s_ctrl(gc2093->link_freq, mode->link_freq_index);
1247 __v4l2_ctrl_s_ctrl_int64(gc2093->pixel_rate,
1248 to_pixel_rate(mode->link_freq_index));
1249 h_blank = mode->hts_def - mode->width;
1250 __v4l2_ctrl_modify_range(gc2093->hblank, h_blank,
1251 h_blank, 1, h_blank);
1252 vblank_def = mode->vts_def - mode->height;
1253 __v4l2_ctrl_modify_range(gc2093->vblank, vblank_def,
1254 GC2093_VTS_MAX - mode->height,
1255 1, vblank_def);
1256 gc2093->cur_vts = mode->vts_def;
1257 gc2093->cur_fps = mode->max_fps;
1258 }
1259
1260 mutex_unlock(&gc2093->lock);
1261 return 0;
1262 }
1263
gc2093_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1264 static int gc2093_get_fmt(struct v4l2_subdev *sd,
1265 struct v4l2_subdev_pad_config *cfg,
1266 struct v4l2_subdev_format *fmt)
1267 {
1268 struct gc2093 *gc2093 = to_gc2093(sd);
1269 const struct gc2093_mode *mode = gc2093->cur_mode;
1270
1271 mutex_lock(&gc2093->lock);
1272 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1273 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1274 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1275 #else
1276 mutex_unlock(&gc2093->lock);
1277 return -ENOTTY;
1278 #endif
1279 } else {
1280 fmt->format.width = mode->width;
1281 fmt->format.height = mode->height;
1282 fmt->format.code = GC2093_MEDIA_BUS_FMT;
1283 fmt->format.field = V4L2_FIELD_NONE;
1284
1285 /* format info: width/height/data type/virctual channel */
1286 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
1287 fmt->reserved[0] = mode->vc[fmt->pad];
1288 else
1289 fmt->reserved[0] = mode->vc[PAD0];
1290
1291 }
1292 mutex_unlock(&gc2093->lock);
1293 return 0;
1294 }
1295
1296 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc2093_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1297 static int gc2093_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1298 {
1299 struct gc2093 *gc2093 = to_gc2093(sd);
1300 struct v4l2_mbus_framefmt *try_fmt =
1301 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1302 const struct gc2093_mode *def_mode = &supported_modes[0];
1303
1304 mutex_lock(&gc2093->lock);
1305 /* Initialize try_fmt */
1306 try_fmt->width = def_mode->width;
1307 try_fmt->height = def_mode->height;
1308 try_fmt->code = GC2093_MEDIA_BUS_FMT;
1309 try_fmt->field = V4L2_FIELD_NONE;
1310 mutex_unlock(&gc2093->lock);
1311
1312 return 0;
1313 }
1314 #endif
1315
1316 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1317 static const struct v4l2_subdev_internal_ops gc2093_internal_ops = {
1318 .open = gc2093_open,
1319 };
1320 #endif
1321
gc2093_s_power(struct v4l2_subdev * sd,int on)1322 static int gc2093_s_power(struct v4l2_subdev *sd, int on)
1323 {
1324 struct gc2093 *gc2093 = to_gc2093(sd);
1325 int ret = 0;
1326
1327 mutex_lock(&gc2093->lock);
1328
1329 if (gc2093->power_on == !!on)
1330 goto unlock_and_return;
1331
1332 if (on) {
1333 ret = pm_runtime_get_sync(gc2093->dev);
1334 if (ret < 0) {
1335 pm_runtime_put_noidle(gc2093->dev);
1336 goto unlock_and_return;
1337 }
1338 gc2093->power_on = true;
1339 } else {
1340 pm_runtime_put(gc2093->dev);
1341 gc2093->power_on = false;
1342 }
1343
1344 unlock_and_return:
1345 mutex_unlock(&gc2093->lock);
1346
1347 return ret;
1348 }
1349
1350 static const struct v4l2_subdev_core_ops gc2093_core_ops = {
1351 .s_power = gc2093_s_power,
1352 .ioctl = gc2093_ioctl,
1353 #ifdef CONFIG_COMPAT
1354 .compat_ioctl32 = gc2093_compat_ioctl32,
1355 #endif
1356 };
1357
1358 static const struct v4l2_subdev_video_ops gc2093_video_ops = {
1359 .s_stream = gc2093_s_stream,
1360 .g_frame_interval = gc2093_g_frame_interval,
1361 };
1362
1363 static const struct v4l2_subdev_pad_ops gc2093_pad_ops = {
1364 .enum_mbus_code = gc2093_enum_mbus_code,
1365 .enum_frame_size = gc2093_enum_frame_sizes,
1366 .enum_frame_interval = gc2093_enum_frame_interval,
1367 .get_fmt = gc2093_get_fmt,
1368 .set_fmt = gc2093_set_fmt,
1369 .get_mbus_config = gc2093_g_mbus_config,
1370 };
1371
1372 static const struct v4l2_subdev_ops gc2093_subdev_ops = {
1373 .core = &gc2093_core_ops,
1374 .video = &gc2093_video_ops,
1375 .pad = &gc2093_pad_ops,
1376 };
1377
gc2093_runtime_resume(struct device * dev)1378 static int __maybe_unused gc2093_runtime_resume(struct device *dev)
1379 {
1380 struct i2c_client *client = to_i2c_client(dev);
1381 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1382 struct gc2093 *gc2093 = to_gc2093(sd);
1383
1384 __gc2093_power_on(gc2093);
1385 return 0;
1386 }
1387
gc2093_runtime_suspend(struct device * dev)1388 static int __maybe_unused gc2093_runtime_suspend(struct device *dev)
1389 {
1390 struct i2c_client *client = to_i2c_client(dev);
1391 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1392 struct gc2093 *gc2093 = to_gc2093(sd);
1393
1394 __gc2093_power_off(gc2093);
1395 return 0;
1396 }
1397
1398 static const struct dev_pm_ops gc2093_pm_ops = {
1399 SET_RUNTIME_PM_OPS(gc2093_runtime_suspend,
1400 gc2093_runtime_resume, NULL)
1401 };
1402
gc2093_probe(struct i2c_client * client,const struct i2c_device_id * id)1403 static int gc2093_probe(struct i2c_client *client,
1404 const struct i2c_device_id *id)
1405 {
1406 struct device *dev = &client->dev;
1407 struct device_node *node = dev->of_node;
1408 struct gc2093 *gc2093;
1409 struct v4l2_subdev *sd;
1410 char facing[2];
1411 int ret;
1412
1413 dev_info(dev, "driver version: %02x.%02x.%02x",
1414 DRIVER_VERSION >> 16,
1415 (DRIVER_VERSION & 0xff00) >> 8,
1416 DRIVER_VERSION & 0x00ff);
1417
1418 gc2093 = devm_kzalloc(dev, sizeof(*gc2093), GFP_KERNEL);
1419 if (!gc2093)
1420 return -ENOMEM;
1421
1422 gc2093->dev = dev;
1423 gc2093->regmap = devm_regmap_init_i2c(client, &gc2093_regmap_config);
1424 if (IS_ERR(gc2093->regmap)) {
1425 dev_err(dev, "Failed to initialize I2C\n");
1426 return -ENODEV;
1427 }
1428
1429 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1430 &gc2093->module_index);
1431 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1432 &gc2093->module_facing);
1433 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1434 &gc2093->module_name);
1435 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1436 &gc2093->len_name);
1437 if (ret) {
1438 dev_err(dev, "Failed to get module information\n");
1439 return -EINVAL;
1440 }
1441
1442 gc2093->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
1443
1444 gc2093->xvclk = devm_clk_get(gc2093->dev, "xvclk");
1445 if (IS_ERR(gc2093->xvclk)) {
1446 dev_err(gc2093->dev, "Failed to get xvclk\n");
1447 return -EINVAL;
1448 }
1449
1450 gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1451 if (IS_ERR(gc2093->reset_gpio))
1452 dev_warn(dev, "Failed to get reset-gpios\n");
1453
1454 gc2093->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1455 if (IS_ERR(gc2093->pwdn_gpio))
1456 dev_warn(dev, "Failed to get pwdn-gpios\n");
1457
1458 ret = gc2093_get_regulators(gc2093);
1459 if (ret) {
1460 dev_err(dev, "Failed to get regulators\n");
1461 return ret;
1462 }
1463
1464 mutex_init(&gc2093->lock);
1465
1466 /* set default mode */
1467 gc2093->cur_mode = &supported_modes[0];
1468 gc2093->cfg_num = ARRAY_SIZE(supported_modes);
1469 gc2093->cur_vts = gc2093->cur_mode->vts_def;
1470
1471 sd = &gc2093->subdev;
1472 v4l2_i2c_subdev_init(sd, client, &gc2093_subdev_ops);
1473 ret = gc2093_initialize_controls(gc2093);
1474 if (ret)
1475 goto err_destroy_mutex;
1476
1477 ret = __gc2093_power_on(gc2093);
1478 if (ret)
1479 goto err_free_handler;
1480
1481 ret = gc2093_check_sensor_id(gc2093);
1482 if (ret)
1483 goto err_power_off;
1484
1485 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1486 sd->internal_ops = &gc2093_internal_ops;
1487 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1488 #endif
1489
1490 #ifdef CONFIG_MEDIA_CONTROLLER
1491 gc2093->pad.flags = MEDIA_PAD_FL_SOURCE;
1492 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1493 ret = media_entity_pads_init(&sd->entity, 1, &gc2093->pad);
1494 if (ret < 0)
1495 goto err_power_off;
1496 #endif
1497
1498 memset(facing, 0, sizeof(facing));
1499 if (strcmp(gc2093->module_facing, "back") == 0)
1500 facing[0] = 'b';
1501 else
1502 facing[0] = 'f';
1503
1504 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1505 gc2093->module_index, facing,
1506 GC2093_NAME, dev_name(sd->dev));
1507
1508 ret = v4l2_async_register_subdev_sensor_common(sd);
1509 if (ret) {
1510 dev_err(dev, "Failed to register v4l2 async subdev\n");
1511 goto err_clean_entity;
1512 }
1513
1514 pm_runtime_set_active(dev);
1515 pm_runtime_enable(dev);
1516 if (gc2093->is_thunderboot)
1517 pm_runtime_get_sync(dev);
1518 else
1519 pm_runtime_idle(dev);
1520
1521 return 0;
1522
1523 err_clean_entity:
1524 #ifdef CONFIG_MEDIA_CONTROLLER
1525 media_entity_cleanup(&sd->entity);
1526 #endif
1527 err_power_off:
1528 __gc2093_power_off(gc2093);
1529 err_free_handler:
1530 v4l2_ctrl_handler_free(&gc2093->ctrl_handler);
1531 err_destroy_mutex:
1532 mutex_destroy(&gc2093->lock);
1533
1534 return ret;
1535 }
1536
gc2093_remove(struct i2c_client * client)1537 static int gc2093_remove(struct i2c_client *client)
1538 {
1539 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1540 struct gc2093 *gc2093 = to_gc2093(sd);
1541
1542 v4l2_async_unregister_subdev(sd);
1543 #ifdef CONFIG_MEDIA_CONTROLLER
1544 media_entity_cleanup(&sd->entity);
1545 #endif
1546 v4l2_ctrl_handler_free(&gc2093->ctrl_handler);
1547 mutex_destroy(&gc2093->lock);
1548
1549 pm_runtime_disable(&client->dev);
1550 if (!pm_runtime_status_suspended(&client->dev))
1551 __gc2093_power_off(gc2093);
1552 pm_runtime_set_suspended(&client->dev);
1553 return 0;
1554 }
1555
1556 static const struct i2c_device_id gc2093_match_id[] = {
1557 { "gc2093", 0 },
1558 { },
1559 };
1560
1561 static const struct of_device_id gc2093_of_match[] = {
1562 { .compatible = "galaxycore,gc2093" },
1563 {},
1564 };
1565 MODULE_DEVICE_TABLE(of, gc2093_of_match);
1566
1567 static struct i2c_driver gc2093_i2c_driver = {
1568 .driver = {
1569 .name = GC2093_NAME,
1570 .pm = &gc2093_pm_ops,
1571 .of_match_table = of_match_ptr(gc2093_of_match),
1572 },
1573 .probe = &gc2093_probe,
1574 .remove = &gc2093_remove,
1575 .id_table = gc2093_match_id,
1576 };
1577
sensor_mod_init(void)1578 static int __init sensor_mod_init(void)
1579 {
1580 return i2c_add_driver(&gc2093_i2c_driver);
1581 }
sensor_mod_exit(void)1582 static void __exit sensor_mod_exit(void)
1583 {
1584 i2c_del_driver(&gc2093_i2c_driver);
1585 }
1586
1587 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1588 subsys_initcall(sensor_mod_init);
1589 #else
1590 device_initcall_sync(sensor_mod_init);
1591 #endif
1592 module_exit(sensor_mod_exit);
1593
1594 MODULE_DESCRIPTION("Galaxycore GC2093 Image Sensor driver");
1595 MODULE_LICENSE("GPL v2");
1596