1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc1084 sensor driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01 Add HDR support.
9 * V0.0X01.0X02 update sensor driver
10 * 1. fix linear mode ae flicker issue.
11 * 2. add hdr mode exposure limit issue.
12 * 3. fix hdr mode highlighting pink issue.
13 * 4. add some debug info.
14 */
15 //#define DEBUG
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/of_graph.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/version.h>
26 #include <linux/rk-camera-module.h>
27 #include <linux/rk-preisp.h>
28
29 #include <media/v4l2-async.h>
30 #include <media/media-entity.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-fwnode.h>
34 #include <media/v4l2-subdev.h>
35
36 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
37 #define GC1084_NAME "gc1084"
38 #define GC1084_MEDIA_BUS_FMT MEDIA_BUS_FMT_SGRBG10_1X10
39
40 #define MIPI_FREQ_400M 400000000
41
42 #define GC1084_XVCLK_FREQ 27000000
43
44 #define GC1084_REG_CHIP_ID_H 0x03F0
45 #define GC1084_REG_CHIP_ID_L 0x03F1
46
47 #define GC1084_REG_EXP_H 0x0d03
48 #define GC1084_REG_EXP_L 0x0d04
49
50 #define GC1084_REG_VTS_H 0x0000
51 #define GC1084_REG_VTS_L 0x0001
52
53 #define GC1084_REG_CTRL_MODE 0x003E
54 #define GC1084_MODE_SW_STANDBY 0x11
55 #define GC1084_MODE_STREAMING 0x91
56
57 #define GC1084_CHIP_ID 0x1084
58
59 #define GC1084_VTS_MAX 0x3FFF
60 #define GC1084_HTS_MAX 0xFFF
61
62 #define GC1084_EXPOSURE_MAX 0x3FFF
63 #define GC1084_EXPOSURE_MIN 1
64 #define GC1084_EXPOSURE_STEP 1
65
66 #define GC1084_GAIN_MIN 0x40
67 #define GC1084_GAIN_MAX 0x2000
68 #define GC1084_GAIN_STEP 1
69 #define GC1084_GAIN_DEFAULT 64
70 #define REG_NULL 0xFFFF
71
72 #define GC1084_LANES 1
73
74 static const char * const gc1084_supply_names[] = {
75 "dovdd", /* Digital I/O power */
76 "avdd", /* Analog power */
77 "dvdd", /* Digital power */
78 };
79
80 #define GC1084_NUM_SUPPLIES ARRAY_SIZE(gc1084_supply_names)
81
82 #define to_gc1084(sd) container_of(sd, struct gc1084, subdev)
83
84 enum {
85 LINK_FREQ_400M_INDEX,
86 };
87
88 struct gain_reg_config {
89 u32 value;
90 u16 analog_gain;
91 u16 col_gain;
92 u16 reserved;
93 };
94
95 struct gc1084_mode {
96 u32 width;
97 u32 height;
98 struct v4l2_fract max_fps;
99 u32 hts_def;
100 u32 vts_def;
101 u32 exp_def;
102 u32 link_freq_index;
103 const struct reg_sequence *reg_list;
104 u32 reg_num;
105 u32 hdr_mode;
106 u32 vc[PAD_MAX];
107 };
108
109 struct gc1084 {
110 struct device *dev;
111 struct clk *xvclk;
112 struct regmap *regmap;
113 struct gpio_desc *reset_gpio;
114 struct gpio_desc *pwdn_gpio;
115 struct regulator_bulk_data supplies[GC1084_NUM_SUPPLIES];
116
117 struct v4l2_subdev subdev;
118 struct media_pad pad;
119 struct v4l2_ctrl_handler ctrl_handler;
120 struct v4l2_ctrl *exposure;
121 struct v4l2_ctrl *anal_gain;
122 struct v4l2_ctrl *hblank;
123 struct v4l2_ctrl *vblank;
124 struct v4l2_ctrl *h_flip;
125 struct v4l2_ctrl *v_flip;
126 struct v4l2_ctrl *link_freq;
127 struct v4l2_ctrl *pixel_rate;
128
129 struct mutex lock;
130 bool streaming;
131 bool power_on;
132 unsigned int cfg_num;
133 const struct gc1084_mode *cur_mode;
134
135 u32 module_index;
136 const char *module_facing;
137 const char *module_name;
138 const char *len_name;
139 enum rkmodule_sync_mode sync_mode;
140 u32 cur_vts;
141
142 bool has_init_exp;
143 struct preisp_hdrae_exp_s init_hdrae_exp;
144 };
145
146 static const struct regmap_config gc1084_regmap_config = {
147 .reg_bits = 16,
148 .val_bits = 8,
149 .max_register = 0x1000,
150 };
151
152 static const s64 link_freq_menu_items[] = {
153 MIPI_FREQ_400M,
154 };
155
156 static const struct reg_sequence gc1084_master_mode_regs[] = {
157 {0x0068, 0x85},
158 {0x0d6a, 0x80},
159 {0x0069, 0x00},
160 {0x006a, 0x02},
161 {0x0d69, 0x04},
162 };
163
164 static const struct reg_sequence gc1084_slave_mode_regs[] = {
165 {0x0d67, 0x00},
166 {0x0d69, 0x03},
167 {0x0d6a, 0x08},
168 {0x0d6b, 0x50},
169 {0x0d6c, 0x00},
170 {0x0d6d, 0x53},
171 {0x0d6e, 0x00},
172 {0x0d6f, 0x10},
173 {0x0d70, 0x00},
174 {0x0d71, 0x12},
175 };
176
177 /*
178 * window size=1280*720 mipi@1lane
179 * mclk=27M mipi_clk=400Mbps
180 * pixel_line_total=2200 line_frame_total=1125
181 * row_time=44.4444us frame_rate=30fps
182 */
183 static const struct reg_sequence gc1084_1280x720_liner_settings[] = {
184 {0x03fe, 0xf0},
185 {0x03fe, 0xf0},
186 {0x03fe, 0xf0},
187 {0x03fe, 0x00},
188 {0x03f2, 0x00},
189 {0x03f3, 0x00},
190 {0x03f4, 0x36},
191 {0x03f5, 0xc0},
192 {0x03f6, 0x13},
193 {0x03f7, 0x01},
194 {0x03f8, 0x32},
195 {0x03f9, 0x21},
196 {0x03fc, 0xae},
197 {0x0d05, 0x08},
198 {0x0d06, 0xae},
199 {0x0d08, 0x10},
200 {0x0d0a, 0x02},
201 {0x000c, 0x03},
202 {0x0d0d, 0x02},
203 {0x0d0e, 0xd4},
204 {0x000f, 0x05},
205 {0x0010, 0x08},
206 {0x0017, 0x08},
207 {0x0d73, 0x92},
208 {0x0076, 0x00},
209 {0x0d76, 0x00},
210 {0x0d41, 0x02},
211 {0x0d42, 0xee},
212 {0x0d7a, 0x0a},
213 {0x006b, 0x18},
214 {0x0db0, 0x9d},
215 {0x0db1, 0x00},
216 {0x0db2, 0xac},
217 {0x0db3, 0xd5},
218 {0x0db4, 0x00},
219 {0x0db5, 0x97},
220 {0x0db6, 0x09},
221 {0x00d2, 0xfc},
222 {0x0d19, 0x31},
223 {0x0d20, 0x40},
224 {0x0d25, 0xcb},
225 {0x0d27, 0x03},
226 {0x0d29, 0x40},
227 {0x0d43, 0x20},
228 {0x0058, 0x60},
229 {0x00d6, 0x66},
230 {0x00d7, 0x19},
231 {0x0093, 0x02},
232 {0x00d9, 0x14},
233 {0x00da, 0xc1},
234 {0x0d2a, 0x00},
235 {0x0d28, 0x04},
236 {0x0dc2, 0x84},
237 {0x0050, 0x30},
238 {0x0080, 0x07},
239 {0x008c, 0x05},
240 {0x008d, 0xa8},
241 {0x0077, 0x01},
242 {0x0078, 0xee},
243 {0x0079, 0x02},
244 {0x0067, 0xc0},
245 {0x0054, 0xff},
246 {0x0055, 0x02},
247 {0x0056, 0x00},
248 {0x0057, 0x04},
249 {0x005a, 0xff},
250 {0x005b, 0x07},
251 {0x00d5, 0x03},
252 {0x0102, 0xa9},
253 {0x0d03, 0x02},
254 {0x0d04, 0xd0},
255 {0x007a, 0x60},
256 {0x04e0, 0xff},
257 {0x0414, 0x75},
258 {0x0415, 0x75},
259 {0x0416, 0x75},
260 {0x0417, 0x75},
261 {0x0122, 0x00},
262 {0x0121, 0x80},
263 {0x0428, 0x10},
264 {0x0429, 0x10},
265 {0x042a, 0x10},
266 {0x042b, 0x10},
267 {0x042c, 0x14},
268 {0x042d, 0x14},
269 {0x042e, 0x18},
270 {0x042f, 0x18},
271 {0x0430, 0x05},
272 {0x0431, 0x05},
273 {0x0432, 0x05},
274 {0x0433, 0x05},
275 {0x0434, 0x05},
276 {0x0435, 0x05},
277 {0x0436, 0x05},
278 {0x0437, 0x05},
279 {0x0153, 0x00},
280 {0x0190, 0x01},
281 {0x0192, 0x02},
282 {0x0194, 0x04},
283 {0x0195, 0x02},
284 {0x0196, 0xd0},
285 {0x0197, 0x05},
286 {0x0198, 0x00},
287 {0x0201, 0x23},
288 {0x0202, 0x53},
289 {0x0203, 0xce},
290 {0x0208, 0x39},
291 {0x0212, 0x06},
292 {0x0213, 0x40},
293 {0x0215, 0x12},
294 {0x0229, 0x05},
295 {0x023e, 0x98},
296 {0x031e, 0x3e},
297 };
298
299 static const struct gc1084_mode supported_modes[] = {
300 {
301 .width = 1280,
302 .height = 720,
303 .max_fps = {
304 .numerator = 10000,
305 .denominator = 300000,
306 },
307 .exp_def = 0x460,
308 .hts_def = 0x898,
309 .vts_def = 0x465,
310 .link_freq_index = LINK_FREQ_400M_INDEX,
311 .reg_list = gc1084_1280x720_liner_settings,
312 .reg_num = ARRAY_SIZE(gc1084_1280x720_liner_settings),
313 .hdr_mode = NO_HDR,
314 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
315 },
316 };
317
318 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
319 /* * 2, to match suitable isp freq */
to_pixel_rate(u32 index)320 static u64 to_pixel_rate(u32 index)
321 {
322 u64 pixel_rate = link_freq_menu_items[index] * 2 * GC1084_LANES * 2;
323
324 do_div(pixel_rate, 10);
325
326 return pixel_rate;
327 }
328
gc1084_read_reg(struct gc1084 * gc1084,u16 addr,u8 * value)329 static inline int gc1084_read_reg(struct gc1084 *gc1084, u16 addr, u8 *value)
330 {
331 unsigned int val;
332 int ret;
333
334 ret = regmap_read(gc1084->regmap, addr, &val);
335 if (ret) {
336 dev_err(gc1084->dev, "i2c read failed at addr: %x\n", addr);
337 return ret;
338 }
339
340 *value = val & 0xff;
341
342 return 0;
343 }
344
gc1084_write_reg(struct gc1084 * gc1084,u16 addr,u8 value)345 static inline int gc1084_write_reg(struct gc1084 *gc1084, u16 addr, u8 value)
346 {
347 int ret;
348
349 ret = regmap_write(gc1084->regmap, addr, value);
350 if (ret) {
351 dev_err(gc1084->dev, "i2c write failed at addr: %x\n", addr);
352 return ret;
353 }
354
355 return ret;
356 }
357
358 static const struct gain_reg_config gain_reg_configs[] = {
359 { 64, 0x0000, 0x0100, 0x0080},
360 { 76, 0x0a00, 0x010b, 0x0080},
361 { 90, 0x0001, 0x0119, 0x0080},
362 { 106, 0x0a01, 0x012a, 0x0080},
363 { 128, 0x0002, 0x0200, 0x0080},
364 { 152, 0x0a02, 0x0217, 0x0080},
365 { 179, 0x0003, 0x0233, 0x0080},
366 { 212, 0x0a03, 0x0314, 0x0080},
367 { 256, 0x0004, 0x0400, 0x0090},
368 { 303, 0x0a04, 0x042f, 0x0090},
369 { 358, 0x0005, 0x0526, 0x0090},
370 { 425, 0x0a05, 0x0628, 0x0090},
371 { 512, 0x0006, 0x0800, 0x00a0},
372 { 607, 0x0a06, 0x091e, 0x00a0},
373 { 716, 0x1246, 0x0b0c, 0x00a0},
374 { 848, 0x1966, 0x0d10, 0x00a0},
375 {1024, 0x4004, 0x1000, 0x00a0},
376 {1214, 0x4a04, 0x123d, 0x00a0},
377 {1434, 0x4005, 0x1619, 0x00b0},
378 {1699, 0x4a05, 0x1a23, 0x00c0},
379 {2048, 0x4006, 0x2000, 0x00c0},
380 {2427, 0x4a06, 0x253b, 0x00c0},
381 {2865, 0x5246, 0x2c30, 0x00c0},
382 {3393, 0x5946, 0x3501, 0x00d0},
383 {4096, 0x6006, 0x3f3f, 0x00e0},
384 };
385
gc1084_set_gain(struct gc1084 * gc1084,u32 gain)386 static int gc1084_set_gain(struct gc1084 *gc1084, u32 gain)
387 {
388 int ret, i = 0;
389 u16 pre_gain = 0;
390
391 for (i = 0; i < ARRAY_SIZE(gain_reg_configs) - 1; i++)
392 if ((gain_reg_configs[i].value <= gain) && (gain < gain_reg_configs[i+1].value))
393 break;
394
395 ret = gc1084_write_reg(gc1084, 0x00d1, (gain_reg_configs[i].analog_gain >> 8) & 0x3f);
396 ret |= gc1084_write_reg(gc1084, 0x00d0, gain_reg_configs[i].analog_gain & 0xff);
397
398 ret |= gc1084_write_reg(gc1084, 0x031d, 0x2e);
399
400 ret |= gc1084_write_reg(gc1084, 0x0dc1, (gain_reg_configs[i].analog_gain >> 14) & 1);
401
402 ret |= gc1084_write_reg(gc1084, 0x031d, 0x28);
403
404 ret |= gc1084_write_reg(gc1084, 0x0155, gain_reg_configs[i].reserved & 0xff);
405
406 ret |= gc1084_write_reg(gc1084, 0x00b8, gain_reg_configs[i].col_gain >> 8);
407 ret |= gc1084_write_reg(gc1084, 0x00b9, gain_reg_configs[i].col_gain & 0xff);
408
409 pre_gain = 64 * gain / gain_reg_configs[i].value;
410
411 ret |= gc1084_write_reg(gc1084, 0x00b1, (pre_gain >> 6));
412 ret |= gc1084_write_reg(gc1084, 0x00b2, ((pre_gain & 0x3f) << 2));
413
414 return ret;
415 }
416
gc1084_set_ctrl(struct v4l2_ctrl * ctrl)417 static int gc1084_set_ctrl(struct v4l2_ctrl *ctrl)
418 {
419 struct gc1084 *gc1084 = container_of(ctrl->handler,
420 struct gc1084, ctrl_handler);
421 s64 max;
422 int ret = 0;
423 u32 vts = 0;
424
425 /* Propagate change of current control to all related controls */
426 switch (ctrl->id) {
427 case V4L2_CID_VBLANK:
428 /* Update max exposure while meeting expected vblanking */
429 max = gc1084->cur_mode->height + ctrl->val - 4;
430 __v4l2_ctrl_modify_range(gc1084->exposure,
431 gc1084->exposure->minimum, max,
432 gc1084->exposure->step,
433 gc1084->exposure->default_value);
434 break;
435 }
436 if (!pm_runtime_get_if_in_use(gc1084->dev))
437 return 0;
438
439 switch (ctrl->id) {
440 case V4L2_CID_EXPOSURE:
441 if (gc1084->cur_mode->hdr_mode != NO_HDR)
442 goto ctrl_end;
443 dev_dbg(gc1084->dev, "set exposure value 0x%x\n", ctrl->val);
444 ret = gc1084_write_reg(gc1084, GC1084_REG_EXP_H,
445 (ctrl->val >> 8) & 0x3f);
446 ret |= gc1084_write_reg(gc1084, GC1084_REG_EXP_L,
447 ctrl->val & 0xff);
448 break;
449 case V4L2_CID_ANALOGUE_GAIN:
450 if (gc1084->cur_mode->hdr_mode != NO_HDR)
451 goto ctrl_end;
452 dev_dbg(gc1084->dev, "set gain value 0x%x\n", ctrl->val);
453 gc1084_set_gain(gc1084, ctrl->val);
454 break;
455 case V4L2_CID_VBLANK:
456 vts = gc1084->cur_mode->height + ctrl->val;
457 gc1084->cur_vts = vts;
458 ret = gc1084_write_reg(gc1084, GC1084_REG_VTS_H,
459 (vts >> 8) & 0x3f);
460 ret |= gc1084_write_reg(gc1084, GC1084_REG_VTS_L,
461 vts & 0xff);
462 dev_dbg(gc1084->dev, " set blank value 0x%x\n", ctrl->val);
463 break;
464 default:
465 dev_warn(gc1084->dev, "%s Unhandled id:0x%x, val:0x%x\n",
466 __func__, ctrl->id, ctrl->val);
467 break;
468 }
469
470 ctrl_end:
471 pm_runtime_put(gc1084->dev);
472 return ret;
473 }
474
475 static const struct v4l2_ctrl_ops gc1084_ctrl_ops = {
476 .s_ctrl = gc1084_set_ctrl,
477 };
478
gc1084_get_regulators(struct gc1084 * gc1084)479 static int gc1084_get_regulators(struct gc1084 *gc1084)
480 {
481 unsigned int i;
482
483 for (i = 0; i < GC1084_NUM_SUPPLIES; i++)
484 gc1084->supplies[i].supply = gc1084_supply_names[i];
485
486 return devm_regulator_bulk_get(gc1084->dev,
487 GC1084_NUM_SUPPLIES,
488 gc1084->supplies);
489 }
490
gc1084_initialize_controls(struct gc1084 * gc1084)491 static int gc1084_initialize_controls(struct gc1084 *gc1084)
492 {
493 const struct gc1084_mode *mode;
494 struct v4l2_ctrl_handler *handler;
495 s64 exposure_max, vblank_def;
496 u32 h_blank;
497 int ret;
498
499 handler = &gc1084->ctrl_handler;
500 mode = gc1084->cur_mode;
501 ret = v4l2_ctrl_handler_init(handler, 8);
502 if (ret)
503 return ret;
504 handler->lock = &gc1084->lock;
505
506 gc1084->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
507 ARRAY_SIZE(link_freq_menu_items) - 1, 0,
508 link_freq_menu_items);
509
510 gc1084->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
511 0, to_pixel_rate(LINK_FREQ_400M_INDEX),
512 1, to_pixel_rate(LINK_FREQ_400M_INDEX));
513
514 h_blank = mode->hts_def - mode->width;
515 gc1084->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
516 h_blank, h_blank, 1, h_blank);
517 if (gc1084->hblank)
518 gc1084->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
519
520 vblank_def = mode->vts_def - mode->height;
521 gc1084->cur_vts = mode->vts_def;
522 gc1084->vblank = v4l2_ctrl_new_std(handler, &gc1084_ctrl_ops,
523 V4L2_CID_VBLANK, vblank_def,
524 GC1084_VTS_MAX - mode->height,
525 1, vblank_def);
526
527 exposure_max = mode->vts_def - 4;
528 gc1084->exposure = v4l2_ctrl_new_std(handler, &gc1084_ctrl_ops,
529 V4L2_CID_EXPOSURE, GC1084_EXPOSURE_MIN,
530 exposure_max, GC1084_EXPOSURE_STEP,
531 mode->exp_def);
532
533 gc1084->anal_gain = v4l2_ctrl_new_std(handler, &gc1084_ctrl_ops,
534 V4L2_CID_ANALOGUE_GAIN, GC1084_GAIN_MIN,
535 GC1084_GAIN_MAX, GC1084_GAIN_STEP,
536 GC1084_GAIN_DEFAULT);
537
538 gc1084->h_flip = v4l2_ctrl_new_std(handler, &gc1084_ctrl_ops,
539 V4L2_CID_HFLIP, 0, 1, 1, 0);
540
541 gc1084->v_flip = v4l2_ctrl_new_std(handler, &gc1084_ctrl_ops,
542 V4L2_CID_VFLIP, 0, 1, 1, 0);
543
544 if (handler->error) {
545 ret = handler->error;
546 dev_err(gc1084->dev, "Failed to init controls(%d)\n", ret);
547 goto err_free_handler;
548 }
549
550 gc1084->subdev.ctrl_handler = handler;
551 gc1084->has_init_exp = false;
552
553 return 0;
554
555 err_free_handler:
556 v4l2_ctrl_handler_free(handler);
557 return ret;
558 }
559
__gc1084_power_on(struct gc1084 * gc1084)560 static int __gc1084_power_on(struct gc1084 *gc1084)
561 {
562 int ret;
563 struct device *dev = gc1084->dev;
564
565 ret = clk_set_rate(gc1084->xvclk, GC1084_XVCLK_FREQ);
566 if (ret < 0)
567 dev_warn(dev, "Failed to set xvclk rate\n");
568
569 if (clk_get_rate(gc1084->xvclk) != GC1084_XVCLK_FREQ)
570 dev_warn(dev, "xvclk mismatched, modes are based on 27MHz\n");
571
572 ret = clk_prepare_enable(gc1084->xvclk);
573 if (ret < 0) {
574 dev_err(dev, "Failed to enable xvclk\n");
575 return ret;
576 }
577
578 ret = regulator_bulk_enable(GC1084_NUM_SUPPLIES, gc1084->supplies);
579 if (ret < 0) {
580 dev_err(dev, "Failed to enable regulators\n");
581 goto disable_clk;
582 }
583
584 if (!IS_ERR(gc1084->reset_gpio))
585 gpiod_set_value_cansleep(gc1084->reset_gpio, 1);
586
587 usleep_range(1000, 2000);
588
589 if (!IS_ERR(gc1084->pwdn_gpio))
590 gpiod_set_value_cansleep(gc1084->pwdn_gpio, 1);
591 if (!IS_ERR(gc1084->reset_gpio))
592 gpiod_set_value_cansleep(gc1084->reset_gpio, 0);
593
594 usleep_range(10000, 20000);
595
596 return 0;
597
598 disable_clk:
599 clk_disable_unprepare(gc1084->xvclk);
600 return ret;
601 }
602
__gc1084_power_off(struct gc1084 * gc1084)603 static void __gc1084_power_off(struct gc1084 *gc1084)
604 {
605 if (!IS_ERR(gc1084->reset_gpio))
606 gpiod_set_value_cansleep(gc1084->reset_gpio, 1);
607 if (!IS_ERR(gc1084->pwdn_gpio))
608 gpiod_set_value_cansleep(gc1084->pwdn_gpio, 0);
609
610 regulator_bulk_disable(GC1084_NUM_SUPPLIES, gc1084->supplies);
611 clk_disable_unprepare(gc1084->xvclk);
612 }
613
gc1084_check_sensor_id(struct gc1084 * gc1084)614 static int gc1084_check_sensor_id(struct gc1084 *gc1084)
615 {
616 u8 id_h = 0, id_l = 0;
617 u16 id = 0;
618 int ret = 0;
619
620 ret = gc1084_read_reg(gc1084, GC1084_REG_CHIP_ID_H, &id_h);
621 ret |= gc1084_read_reg(gc1084, GC1084_REG_CHIP_ID_L, &id_l);
622 if (ret) {
623 dev_err(gc1084->dev, "Failed to read sensor id, (%d)\n", ret);
624 return ret;
625 }
626
627 id = id_h << 8 | id_l;
628 if (id != GC1084_CHIP_ID) {
629 dev_err(gc1084->dev, "sensor id: %04X mismatched\n", id);
630 return -ENODEV;
631 }
632
633 dev_info(gc1084->dev, "Detected GC1084 sensor\n");
634 return 0;
635 }
636
gc1084_get_module_inf(struct gc1084 * gc1084,struct rkmodule_inf * inf)637 static void gc1084_get_module_inf(struct gc1084 *gc1084,
638 struct rkmodule_inf *inf)
639 {
640 memset(inf, 0, sizeof(*inf));
641 strlcpy(inf->base.lens, gc1084->len_name, sizeof(inf->base.lens));
642 strlcpy(inf->base.sensor, GC1084_NAME, sizeof(inf->base.sensor));
643 strlcpy(inf->base.module, gc1084->module_name, sizeof(inf->base.module));
644 }
645
gc1084_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)646 static long gc1084_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
647 {
648 struct gc1084 *gc1084 = to_gc1084(sd);
649 struct rkmodule_hdr_cfg *hdr_cfg;
650 long ret = 0;
651 u32 stream = 0;
652 u64 delay_us = 0;
653 u32 fps = 0;
654 u32 *sync_mode = NULL;
655
656 switch (cmd) {
657 case RKMODULE_GET_HDR_CFG:
658 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
659 hdr_cfg->esp.mode = HDR_NORMAL_VC;
660 hdr_cfg->hdr_mode = gc1084->cur_mode->hdr_mode;
661 break;
662 case RKMODULE_GET_MODULE_INFO:
663 gc1084_get_module_inf(gc1084, (struct rkmodule_inf *)arg);
664 break;
665 case RKMODULE_SET_QUICK_STREAM:
666
667 stream = *((u32 *)arg);
668
669 if (stream) {
670 ret = gc1084_write_reg(gc1084, GC1084_REG_CTRL_MODE,
671 GC1084_MODE_STREAMING);
672 } else {
673 ret = gc1084_write_reg(gc1084, GC1084_REG_CTRL_MODE,
674 GC1084_MODE_SW_STANDBY);
675 fps = gc1084->cur_mode->max_fps.denominator /
676 gc1084->cur_mode->max_fps.numerator;
677 delay_us = 1000000 / (gc1084->cur_mode->vts_def * fps / gc1084->cur_vts);
678 usleep_range(delay_us, delay_us + 2000);
679 }
680 break;
681 case RKMODULE_GET_SYNC_MODE:
682 sync_mode = (u32 *)arg;
683 *sync_mode = gc1084->sync_mode;
684 break;
685 case RKMODULE_SET_SYNC_MODE:
686 sync_mode = (u32 *)arg;
687 gc1084->sync_mode = *sync_mode;
688 break;
689 default:
690 ret = -ENOIOCTLCMD;
691 break;
692 }
693 return ret;
694 }
695
__gc1084_start_stream(struct gc1084 * gc1084)696 static int __gc1084_start_stream(struct gc1084 *gc1084)
697 {
698 int ret;
699
700 ret = regmap_multi_reg_write(gc1084->regmap,
701 gc1084->cur_mode->reg_list,
702 gc1084->cur_mode->reg_num);
703 if (ret)
704 return ret;
705
706 /* Apply customized control from user */
707 mutex_unlock(&gc1084->lock);
708 v4l2_ctrl_handler_setup(&gc1084->ctrl_handler);
709 mutex_lock(&gc1084->lock);
710
711 if (gc1084->has_init_exp && gc1084->cur_mode->hdr_mode != NO_HDR) {
712 ret = gc1084_ioctl(&gc1084->subdev, PREISP_CMD_SET_HDRAE_EXP,
713 &gc1084->init_hdrae_exp);
714 if (ret) {
715 dev_err(gc1084->dev, "init exp fail in hdr mode\n");
716 return ret;
717 }
718 }
719
720 if (gc1084->sync_mode == INTERNAL_MASTER_MODE) {
721 ret = regmap_multi_reg_write(gc1084->regmap, gc1084_master_mode_regs,
722 ARRAY_SIZE(gc1084_master_mode_regs));
723 if (ret)
724 dev_err(gc1084->dev,
725 "write internal master mode reg failed %d\n", ret);
726 } else if (gc1084->sync_mode == EXTERNAL_MASTER_MODE) {
727 ret = regmap_multi_reg_write(gc1084->regmap, gc1084_slave_mode_regs,
728 ARRAY_SIZE(gc1084_slave_mode_regs));
729 if (ret)
730 dev_err(gc1084->dev,
731 "write external master mode reg failed %d\n", ret);
732 } else if (gc1084->sync_mode == SLAVE_MODE) {
733 ret = regmap_multi_reg_write(gc1084->regmap, gc1084_slave_mode_regs,
734 ARRAY_SIZE(gc1084_slave_mode_regs));
735 if (ret)
736 dev_err(gc1084->dev, "write slave mode reg failed %d\n", ret);
737 }
738
739 return gc1084_write_reg(gc1084, GC1084_REG_CTRL_MODE,
740 GC1084_MODE_STREAMING);
741 }
742
__gc1084_stop_stream(struct gc1084 * gc1084)743 static int __gc1084_stop_stream(struct gc1084 *gc1084)
744 {
745 gc1084->has_init_exp = false;
746 return gc1084_write_reg(gc1084, GC1084_REG_CTRL_MODE,
747 GC1084_MODE_SW_STANDBY);
748 }
749
750 #ifdef CONFIG_COMPAT
gc1084_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)751 static long gc1084_compat_ioctl32(struct v4l2_subdev *sd,
752 unsigned int cmd, unsigned long arg)
753 {
754 void __user *up = compat_ptr(arg);
755 struct rkmodule_inf *inf;
756 struct rkmodule_hdr_cfg *hdr;
757 struct preisp_hdrae_exp_s *hdrae;
758 long ret = 0;
759 u32 stream = 0;
760 u32 sync_mode;
761
762 switch (cmd) {
763 case RKMODULE_GET_MODULE_INFO:
764 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
765 if (!inf) {
766 ret = -ENOMEM;
767 return ret;
768 }
769
770 ret = gc1084_ioctl(sd, cmd, inf);
771 if (!ret) {
772 ret = copy_to_user(up, inf, sizeof(*inf));
773 if (ret)
774 ret = -EFAULT;
775 }
776 kfree(inf);
777 break;
778 case RKMODULE_GET_HDR_CFG:
779 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
780 if (!hdr) {
781 ret = -ENOMEM;
782 return ret;
783 }
784
785 ret = gc1084_ioctl(sd, cmd, hdr);
786 if (!ret) {
787 ret = copy_to_user(up, hdr, sizeof(*hdr));
788 if (ret)
789 ret = -EFAULT;
790 }
791 kfree(hdr);
792 break;
793 case RKMODULE_SET_HDR_CFG:
794 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
795 if (!hdr) {
796 ret = -ENOMEM;
797 return ret;
798 }
799
800 ret = copy_from_user(hdr, up, sizeof(*hdr));
801 if (!ret)
802 ret = gc1084_ioctl(sd, cmd, hdr);
803 else
804 ret = -EFAULT;
805 kfree(hdr);
806 break;
807 case PREISP_CMD_SET_HDRAE_EXP:
808 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
809 if (!hdrae) {
810 ret = -ENOMEM;
811 return ret;
812 }
813
814 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
815 if (!ret)
816 ret = gc1084_ioctl(sd, cmd, hdrae);
817 else
818 ret = -EFAULT;
819 kfree(hdrae);
820 break;
821 case RKMODULE_SET_QUICK_STREAM:
822 ret = copy_from_user(&stream, up, sizeof(u32));
823 if (!ret)
824 ret = gc1084_ioctl(sd, cmd, &stream);
825 else
826 ret = -EFAULT;
827 break;
828 case RKMODULE_GET_SYNC_MODE:
829 ret = gc1084_ioctl(sd, cmd, &sync_mode);
830 if (!ret) {
831 ret = copy_to_user(up, &sync_mode, sizeof(u32));
832 if (ret)
833 ret = -EFAULT;
834 }
835 break;
836 case RKMODULE_SET_SYNC_MODE:
837 ret = copy_from_user(&sync_mode, up, sizeof(u32));
838 if (!ret)
839 ret = gc1084_ioctl(sd, cmd, &sync_mode);
840 else
841 ret = -EFAULT;
842 break;
843 default:
844 ret = -ENOIOCTLCMD;
845 break;
846 }
847 return ret;
848 }
849 #endif
850
gc1084_s_stream(struct v4l2_subdev * sd,int on)851 static int gc1084_s_stream(struct v4l2_subdev *sd, int on)
852 {
853 struct gc1084 *gc1084 = to_gc1084(sd);
854 int ret = 0;
855 unsigned int fps;
856 unsigned int delay_us;
857
858 fps = DIV_ROUND_CLOSEST(gc1084->cur_mode->max_fps.denominator,
859 gc1084->cur_mode->max_fps.numerator);
860
861 dev_info(gc1084->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
862 gc1084->cur_mode->width,
863 gc1084->cur_mode->height,
864 fps);
865
866 mutex_lock(&gc1084->lock);
867 on = !!on;
868 if (on == gc1084->streaming)
869 goto unlock_and_return;
870
871 if (on) {
872 ret = pm_runtime_get_sync(gc1084->dev);
873 if (ret < 0) {
874 pm_runtime_put_noidle(gc1084->dev);
875 goto unlock_and_return;
876 }
877
878 ret = __gc1084_start_stream(gc1084);
879 if (ret) {
880 dev_err(gc1084->dev, "Failed to start gc1084 stream\n");
881 pm_runtime_put(gc1084->dev);
882 goto unlock_and_return;
883 }
884 } else {
885 __gc1084_stop_stream(gc1084);
886 /* delay to enable oneframe complete */
887 delay_us = 1000 * 1000 / fps;
888 usleep_range(delay_us, delay_us+10);
889 dev_info(gc1084->dev, "%s: on: %d, sleep(%dus)\n",
890 __func__, on, delay_us);
891
892 pm_runtime_put(gc1084->dev);
893 }
894
895 gc1084->streaming = on;
896
897 unlock_and_return:
898 mutex_unlock(&gc1084->lock);
899 return 0;
900 }
901
gc1084_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)902 static int gc1084_g_frame_interval(struct v4l2_subdev *sd,
903 struct v4l2_subdev_frame_interval *fi)
904 {
905 struct gc1084 *gc1084 = to_gc1084(sd);
906 const struct gc1084_mode *mode = gc1084->cur_mode;
907
908 fi->interval = mode->max_fps;
909
910 return 0;
911 }
912
gc1084_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)913 static int gc1084_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
914 struct v4l2_mbus_config *config)
915 {
916 struct gc1084 *gc1084 = to_gc1084(sd);
917 u32 val = 1 << (GC1084_LANES - 1) | V4L2_MBUS_CSI2_CHANNEL_0 |
918 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
919
920 config->type = V4L2_MBUS_CSI2_DPHY;
921 config->flags = (gc1084->cur_mode->hdr_mode == NO_HDR) ?
922 val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
923
924 return 0;
925 }
926
gc1084_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)927 static int gc1084_enum_mbus_code(struct v4l2_subdev *sd,
928 struct v4l2_subdev_pad_config *cfg,
929 struct v4l2_subdev_mbus_code_enum *code)
930 {
931 if (code->index != 0)
932 return -EINVAL;
933 code->code = GC1084_MEDIA_BUS_FMT;
934 return 0;
935 }
936
gc1084_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)937 static int gc1084_enum_frame_sizes(struct v4l2_subdev *sd,
938 struct v4l2_subdev_pad_config *cfg,
939 struct v4l2_subdev_frame_size_enum *fse)
940 {
941 struct gc1084 *gc1084 = to_gc1084(sd);
942
943 if (fse->index >= gc1084->cfg_num)
944 return -EINVAL;
945
946 if (fse->code != GC1084_MEDIA_BUS_FMT)
947 return -EINVAL;
948
949 fse->min_width = supported_modes[fse->index].width;
950 fse->max_width = supported_modes[fse->index].width;
951 fse->max_height = supported_modes[fse->index].height;
952 fse->min_height = supported_modes[fse->index].height;
953 return 0;
954 }
955
gc1084_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)956 static int gc1084_enum_frame_interval(struct v4l2_subdev *sd,
957 struct v4l2_subdev_pad_config *cfg,
958 struct v4l2_subdev_frame_interval_enum *fie)
959 {
960 struct gc1084 *gc1084 = to_gc1084(sd);
961
962 if (fie->index >= gc1084->cfg_num)
963 return -EINVAL;
964
965 fie->code = GC1084_MEDIA_BUS_FMT;
966 fie->width = supported_modes[fie->index].width;
967 fie->height = supported_modes[fie->index].height;
968 fie->interval = supported_modes[fie->index].max_fps;
969 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
970 return 0;
971 }
972
gc1084_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)973 static int gc1084_set_fmt(struct v4l2_subdev *sd,
974 struct v4l2_subdev_pad_config *cfg,
975 struct v4l2_subdev_format *fmt)
976 {
977 struct gc1084 *gc1084 = to_gc1084(sd);
978 const struct gc1084_mode *mode;
979 s64 h_blank, vblank_def;
980
981 mutex_lock(&gc1084->lock);
982
983 mode = v4l2_find_nearest_size(supported_modes,
984 ARRAY_SIZE(supported_modes),
985 width, height,
986 fmt->format.width, fmt->format.height);
987
988 fmt->format.code = GC1084_MEDIA_BUS_FMT;
989 fmt->format.width = mode->width;
990 fmt->format.height = mode->height;
991 fmt->format.field = V4L2_FIELD_NONE;
992 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
993 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
994 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
995 #else
996 mutex_unlock(&gc1084->lock);
997 return -ENOTTY;
998 #endif
999 } else {
1000 gc1084->cur_mode = mode;
1001 __v4l2_ctrl_s_ctrl(gc1084->link_freq, mode->link_freq_index);
1002 __v4l2_ctrl_s_ctrl_int64(gc1084->pixel_rate,
1003 to_pixel_rate(mode->link_freq_index));
1004 h_blank = mode->hts_def - mode->width;
1005 __v4l2_ctrl_modify_range(gc1084->hblank, h_blank,
1006 h_blank, 1, h_blank);
1007 vblank_def = mode->vts_def - mode->height;
1008 __v4l2_ctrl_modify_range(gc1084->vblank, vblank_def,
1009 GC1084_VTS_MAX - mode->height,
1010 1, vblank_def);
1011 }
1012
1013 mutex_unlock(&gc1084->lock);
1014 return 0;
1015 }
1016
gc1084_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1017 static int gc1084_get_fmt(struct v4l2_subdev *sd,
1018 struct v4l2_subdev_pad_config *cfg,
1019 struct v4l2_subdev_format *fmt)
1020 {
1021 struct gc1084 *gc1084 = to_gc1084(sd);
1022 const struct gc1084_mode *mode = gc1084->cur_mode;
1023
1024 mutex_lock(&gc1084->lock);
1025 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1026 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1027 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1028 #else
1029 mutex_unlock(&gc1084->lock);
1030 return -ENOTTY;
1031 #endif
1032 } else {
1033 fmt->format.width = mode->width;
1034 fmt->format.height = mode->height;
1035 fmt->format.code = GC1084_MEDIA_BUS_FMT;
1036 fmt->format.field = V4L2_FIELD_NONE;
1037
1038 /* format info: width/height/data type/virctual channel */
1039 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
1040 fmt->reserved[0] = mode->vc[fmt->pad];
1041 else
1042 fmt->reserved[0] = mode->vc[PAD0];
1043
1044 }
1045 mutex_unlock(&gc1084->lock);
1046 return 0;
1047 }
1048
1049 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc1084_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1050 static int gc1084_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1051 {
1052 struct gc1084 *gc1084 = to_gc1084(sd);
1053 struct v4l2_mbus_framefmt *try_fmt =
1054 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1055 const struct gc1084_mode *def_mode = &supported_modes[0];
1056
1057 mutex_lock(&gc1084->lock);
1058 /* Initialize try_fmt */
1059 try_fmt->width = def_mode->width;
1060 try_fmt->height = def_mode->height;
1061 try_fmt->code = GC1084_MEDIA_BUS_FMT;
1062 try_fmt->field = V4L2_FIELD_NONE;
1063 mutex_unlock(&gc1084->lock);
1064
1065 return 0;
1066 }
1067 #endif
1068
1069 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1070 static const struct v4l2_subdev_internal_ops gc1084_internal_ops = {
1071 .open = gc1084_open,
1072 };
1073 #endif
1074
gc1084_s_power(struct v4l2_subdev * sd,int on)1075 static int gc1084_s_power(struct v4l2_subdev *sd, int on)
1076 {
1077 struct gc1084 *gc1084 = to_gc1084(sd);
1078 int ret = 0;
1079
1080 mutex_lock(&gc1084->lock);
1081
1082 if (gc1084->power_on == !!on)
1083 goto unlock_and_return;
1084
1085 if (on) {
1086 ret = pm_runtime_get_sync(gc1084->dev);
1087 if (ret < 0) {
1088 pm_runtime_put_noidle(gc1084->dev);
1089 goto unlock_and_return;
1090 }
1091 gc1084->power_on = true;
1092 } else {
1093 pm_runtime_put(gc1084->dev);
1094 gc1084->power_on = false;
1095 }
1096
1097 unlock_and_return:
1098 mutex_unlock(&gc1084->lock);
1099
1100 return ret;
1101 }
1102
1103 static const struct v4l2_subdev_core_ops gc1084_core_ops = {
1104 .s_power = gc1084_s_power,
1105 .ioctl = gc1084_ioctl,
1106 #ifdef CONFIG_COMPAT
1107 .compat_ioctl32 = gc1084_compat_ioctl32,
1108 #endif
1109 };
1110
1111 static const struct v4l2_subdev_video_ops gc1084_video_ops = {
1112 .s_stream = gc1084_s_stream,
1113 .g_frame_interval = gc1084_g_frame_interval,
1114 };
1115
1116 static const struct v4l2_subdev_pad_ops gc1084_pad_ops = {
1117 .enum_mbus_code = gc1084_enum_mbus_code,
1118 .enum_frame_size = gc1084_enum_frame_sizes,
1119 .enum_frame_interval = gc1084_enum_frame_interval,
1120 .get_fmt = gc1084_get_fmt,
1121 .set_fmt = gc1084_set_fmt,
1122 .get_mbus_config = gc1084_g_mbus_config,
1123 };
1124
1125 static const struct v4l2_subdev_ops gc1084_subdev_ops = {
1126 .core = &gc1084_core_ops,
1127 .video = &gc1084_video_ops,
1128 .pad = &gc1084_pad_ops,
1129 };
1130
gc1084_runtime_resume(struct device * dev)1131 static int gc1084_runtime_resume(struct device *dev)
1132 {
1133 struct i2c_client *client = to_i2c_client(dev);
1134 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1135 struct gc1084 *gc1084 = to_gc1084(sd);
1136
1137 __gc1084_power_on(gc1084);
1138 return 0;
1139 }
1140
gc1084_runtime_suspend(struct device * dev)1141 static int gc1084_runtime_suspend(struct device *dev)
1142 {
1143 struct i2c_client *client = to_i2c_client(dev);
1144 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1145 struct gc1084 *gc1084 = to_gc1084(sd);
1146
1147 __gc1084_power_off(gc1084);
1148 return 0;
1149 }
1150
1151 static const struct dev_pm_ops gc1084_pm_ops = {
1152 SET_RUNTIME_PM_OPS(gc1084_runtime_suspend,
1153 gc1084_runtime_resume, NULL)
1154 };
1155
gc1084_probe(struct i2c_client * client,const struct i2c_device_id * id)1156 static int gc1084_probe(struct i2c_client *client,
1157 const struct i2c_device_id *id)
1158 {
1159 struct device *dev = &client->dev;
1160 struct device_node *node = dev->of_node;
1161 struct gc1084 *gc1084;
1162 struct v4l2_subdev *sd;
1163 char facing[2];
1164 int ret;
1165 const char *sync_mode_name = NULL;
1166
1167 dev_info(dev, "driver version: %02x.%02x.%02x",
1168 DRIVER_VERSION >> 16,
1169 (DRIVER_VERSION & 0xff00) >> 8,
1170 DRIVER_VERSION & 0x00ff);
1171
1172 gc1084 = devm_kzalloc(dev, sizeof(*gc1084), GFP_KERNEL);
1173 if (!gc1084)
1174 return -ENOMEM;
1175
1176 gc1084->dev = dev;
1177 gc1084->regmap = devm_regmap_init_i2c(client, &gc1084_regmap_config);
1178 if (IS_ERR(gc1084->regmap)) {
1179 dev_err(dev, "Failed to initialize I2C\n");
1180 return -ENODEV;
1181 }
1182
1183 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1184 &gc1084->module_index);
1185 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1186 &gc1084->module_facing);
1187 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1188 &gc1084->module_name);
1189 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1190 &gc1084->len_name);
1191 if (ret) {
1192 dev_err(dev, "Failed to get module information\n");
1193 return -EINVAL;
1194 }
1195
1196 ret = of_property_read_string(node, RKMODULE_CAMERA_SYNC_MODE,
1197 &sync_mode_name);
1198 if (ret) {
1199 gc1084->sync_mode = NO_SYNC_MODE;
1200 dev_err(dev, "could not get sync mode!\n");
1201 } else {
1202 if (strcmp(sync_mode_name, RKMODULE_EXTERNAL_MASTER_MODE) == 0)
1203 gc1084->sync_mode = EXTERNAL_MASTER_MODE;
1204 else if (strcmp(sync_mode_name, RKMODULE_INTERNAL_MASTER_MODE) == 0)
1205 gc1084->sync_mode = INTERNAL_MASTER_MODE;
1206 else if (strcmp(sync_mode_name, RKMODULE_SLAVE_MODE) == 0)
1207 gc1084->sync_mode = SLAVE_MODE;
1208 }
1209
1210 gc1084->xvclk = devm_clk_get(gc1084->dev, "xvclk");
1211 if (IS_ERR(gc1084->xvclk)) {
1212 dev_err(gc1084->dev, "Failed to get xvclk\n");
1213 return -EINVAL;
1214 }
1215
1216 gc1084->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1217 if (IS_ERR(gc1084->reset_gpio))
1218 dev_warn(dev, "Failed to get reset-gpios\n");
1219
1220 gc1084->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_HIGH);
1221 if (IS_ERR(gc1084->pwdn_gpio))
1222 dev_warn(dev, "Failed to get pwdn-gpios\n");
1223
1224 ret = gc1084_get_regulators(gc1084);
1225 if (ret) {
1226 dev_err(dev, "Failed to get regulators\n");
1227 return ret;
1228 }
1229
1230 mutex_init(&gc1084->lock);
1231
1232 /* set default mode */
1233 gc1084->cur_mode = &supported_modes[0];
1234 gc1084->cfg_num = ARRAY_SIZE(supported_modes);
1235 gc1084->cur_vts = gc1084->cur_mode->vts_def;
1236
1237 sd = &gc1084->subdev;
1238 v4l2_i2c_subdev_init(sd, client, &gc1084_subdev_ops);
1239 ret = gc1084_initialize_controls(gc1084);
1240 if (ret)
1241 goto err_destroy_mutex;
1242
1243 ret = __gc1084_power_on(gc1084);
1244 if (ret)
1245 goto err_free_handler;
1246
1247 ret = gc1084_check_sensor_id(gc1084);
1248 if (ret)
1249 goto err_power_off;
1250
1251 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1252 sd->internal_ops = &gc1084_internal_ops;
1253 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1254 #endif
1255
1256 #ifdef CONFIG_MEDIA_CONTROLLER
1257 gc1084->pad.flags = MEDIA_PAD_FL_SOURCE;
1258 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1259 ret = media_entity_pads_init(&sd->entity, 1, &gc1084->pad);
1260 if (ret < 0)
1261 goto err_power_off;
1262 #endif
1263
1264 memset(facing, 0, sizeof(facing));
1265 if (strcmp(gc1084->module_facing, "back") == 0)
1266 facing[0] = 'b';
1267 else
1268 facing[0] = 'f';
1269
1270 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1271 gc1084->module_index, facing,
1272 GC1084_NAME, dev_name(sd->dev));
1273
1274 ret = v4l2_async_register_subdev_sensor_common(sd);
1275 if (ret) {
1276 dev_err(dev, "Failed to register v4l2 async subdev\n");
1277 goto err_clean_entity;
1278 }
1279
1280 pm_runtime_set_active(dev);
1281 pm_runtime_enable(dev);
1282 pm_runtime_idle(dev);
1283
1284 return 0;
1285
1286 err_clean_entity:
1287 #ifdef CONFIG_MEDIA_CONTROLLER
1288 media_entity_cleanup(&sd->entity);
1289 #endif
1290 err_power_off:
1291 __gc1084_power_off(gc1084);
1292 err_free_handler:
1293 v4l2_ctrl_handler_free(&gc1084->ctrl_handler);
1294 err_destroy_mutex:
1295 mutex_destroy(&gc1084->lock);
1296
1297 return ret;
1298 }
1299
gc1084_remove(struct i2c_client * client)1300 static int gc1084_remove(struct i2c_client *client)
1301 {
1302 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1303 struct gc1084 *gc1084 = to_gc1084(sd);
1304
1305 v4l2_async_unregister_subdev(sd);
1306 #ifdef CONFIG_MEDIA_CONTROLLER
1307 media_entity_cleanup(&sd->entity);
1308 #endif
1309 v4l2_ctrl_handler_free(&gc1084->ctrl_handler);
1310 mutex_destroy(&gc1084->lock);
1311
1312 pm_runtime_disable(&client->dev);
1313 if (!pm_runtime_status_suspended(&client->dev))
1314 __gc1084_power_off(gc1084);
1315 pm_runtime_set_suspended(&client->dev);
1316 return 0;
1317 }
1318
1319 static const struct i2c_device_id gc1084_match_id[] = {
1320 { "gc1084", 0 },
1321 { },
1322 };
1323
1324 static const struct of_device_id gc1084_of_match[] = {
1325 { .compatible = "galaxycore,gc1084" },
1326 {},
1327 };
1328 MODULE_DEVICE_TABLE(of, gc1084_of_match);
1329
1330 static struct i2c_driver gc1084_i2c_driver = {
1331 .driver = {
1332 .name = GC1084_NAME,
1333 .pm = &gc1084_pm_ops,
1334 .of_match_table = of_match_ptr(gc1084_of_match),
1335 },
1336 .probe = &gc1084_probe,
1337 .remove = &gc1084_remove,
1338 .id_table = gc1084_match_id,
1339 };
1340
sensor_mod_init(void)1341 static int __init sensor_mod_init(void)
1342 {
1343 return i2c_add_driver(&gc1084_i2c_driver);
1344 }
sensor_mod_exit(void)1345 static void __exit sensor_mod_exit(void)
1346 {
1347 i2c_del_driver(&gc1084_i2c_driver);
1348 }
1349
1350 device_initcall_sync(sensor_mod_init);
1351 module_exit(sensor_mod_exit);
1352
1353 MODULE_DESCRIPTION("Galaxycore GC1084 Image Sensor driver");
1354 MODULE_LICENSE("GPL v2");
1355