1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc02m2 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 init version.
8 * V0.0X01.0X02
9 * 1.add hflip/vflip function.
10 * 2.modify set_gain_reg function.
11 */
12
13 //#define DEBUG 1
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/of.h>
22 #include <linux/of_graph.h>
23 #include <linux/of_gpio.h>
24
25 #include <linux/regulator/consumer.h>
26 #include <linux/sysfs.h>
27 #include <linux/version.h>
28 #include <linux/rk-camera-module.h>
29 #include <media/media-entity.h>
30 #include <media/v4l2-async.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-subdev.h>
33 #include <linux/pinctrl/consumer.h>
34 #include <linux/slab.h>
35
36 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
37
38 #ifndef V4L2_CID_DIGITAL_GAIN
39 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
40 #endif
41
42 #define GC02M2_MIPI_LINK_FREQ 336000000
43
44 /* pixel rate = link frequency * 1 * lanes / BITS_PER_SAMPLE */
45 #define GC02M2_PIXEL_RATE (GC02M2_MIPI_LINK_FREQ * 2LL * 1LL / 10)
46 #define GC02M2_XVCLK_FREQ 24000000
47
48 #define CHIP_ID 0x02f0
49 #define GC02M2_REG_CHIP_ID_H 0xf0
50 #define GC02M2_REG_CHIP_ID_L 0xf1
51 #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
52
53 #define GC02M2_PAGE_SELECT 0xfe
54 #define GC02M2_MODE_SELECT 0x3e
55 #define GC02M2_MODE_SW_STANDBY 0x00
56 #define GC02M2_MODE_STREAMING 0x90
57
58 #define GC02M2_REG_EXPOSURE_H 0x03
59 #define GC02M2_REG_EXPOSURE_L 0x04
60 #define GC02M2_EXPOSURE_MIN 4
61 #define GC02M2_EXPOSURE_STEP 1
62 #define GC02M2_VTS_MAX 0x7fff
63
64 #define GC02M2_ANALOG_GAIN_REG 0xb6
65 #define GC02M2_PREGAIN_H_REG 0xb1
66 #define GC02M2_PREGAIN_L_REG 0xb2
67 #define GC02M2_GAIN_MIN 0x40
68 #define GC02M2_GAIN_MAX 0x286
69 #define GC02M2_GAIN_STEP 1
70 #define GC02M2_GAIN_DEFAULT 0x80
71
72 #define GC02M2_REG_VTS_H 0x41
73 #define GC02M2_REG_VTS_L 0x42
74
75 #define GC02M2_MIRROR_FLIP_REG 0x17
76 #define SC200AI_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x01 : VAL & 0xfe)
77 #define SC200AI_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x02 : VAL & 0xfd)
78
79 #define GC02M2_LANES 1
80 #define GC02M2_BITS_PER_SAMPLE 10
81 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
82 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
83 #define GC02M2_NAME "gc02m2"
84 #define REG_NULL 0xFF
85
86 static const char * const gc02m2_supply_names[] = {
87 "dovdd", /* Digital I/O power */
88 "avdd", /* Analog power */
89 "dvdd", /* Digital core power */
90 };
91
92 #define GC02M2_NUM_SUPPLIES ARRAY_SIZE(gc02m2_supply_names)
93
94 #define to_gc02m2(sd) container_of(sd, struct gc02m2, subdev)
95
96 struct regval {
97 u8 addr;
98 u8 val;
99 };
100
101 struct gc02m2_mode {
102 u32 bus_fmt;
103 u32 width;
104 u32 height;
105 struct v4l2_fract max_fps;
106 u32 hts_def;
107 u32 vts_def;
108 u32 exp_def;
109 const struct regval *reg_list;
110 u32 hdr_mode;
111 u32 vc[PAD_MAX];
112 };
113
114 struct gc02m2 {
115 struct i2c_client *client;
116 struct clk *xvclk;
117 struct gpio_desc *reset_gpio;
118 struct gpio_desc *pwdn_gpio;
119 struct regulator_bulk_data supplies[GC02M2_NUM_SUPPLIES];
120 struct pinctrl *pinctrl;
121 struct pinctrl_state *pins_default;
122 struct pinctrl_state *pins_sleep;
123 struct v4l2_subdev subdev;
124 struct media_pad pad;
125 struct v4l2_ctrl_handler ctrl_handler;
126 struct v4l2_ctrl *exposure;
127 struct v4l2_ctrl *anal_gain;
128 struct v4l2_ctrl *digi_gain;
129 struct v4l2_ctrl *hblank;
130 struct v4l2_ctrl *vblank;
131 struct v4l2_ctrl *test_pattern;
132 struct mutex mutex;
133 bool streaming;
134 bool power_on;
135 const struct gc02m2_mode *cur_mode;
136 unsigned int lane_num;
137 unsigned int pixel_rate;
138 u32 module_index;
139 const char *module_facing;
140 const char *module_name;
141 const char *len_name;
142 };
143
144 /*
145 * Xclk 24Mhz
146 */
147 static const struct regval gc02m2_global_regs[] = {
148 /*system*/
149 {0xfc, 0x01},
150 {0xf4, 0x41},
151 {0xf5, 0xc0},
152 {0xf6, 0x44},
153 {0xf8, 0x38},
154 {0xf9, 0x82},
155 {0xfa, 0x00},
156 {0xfd, 0x80},
157 {0xfc, 0x81},
158 {0xfe, 0x03},
159 {0x01, 0x0b},
160 {0xf7, 0x01},
161 {0xfc, 0x80},
162 {0xfc, 0x80},
163 {0xfc, 0x80},
164 {0xfc, 0x8e},
165 /*CISCTL*/
166 {0xfe, 0x00},
167 {0x87, 0x09},
168 {0xee, 0x72},
169 {0xfe, 0x01},
170 {0x8c, 0x90},
171 {0xfe, 0x00},
172 {0x90, 0x00},
173 {0x03, 0x04},
174 {0x04, 0x7d},
175 {0x41, 0x04},
176 {0x42, 0xf4},
177 {0x05, 0x04},
178 {0x06, 0x48},
179 {0x07, 0x00},
180 {0x08, 0x18},
181 {0x9d, 0x18},
182 {0x09, 0x00},
183 {0x0a, 0x02},
184 {0x0d, 0x04},
185 {0x0e, 0xbc},
186 {0x17, 0x80},
187 {0x19, 0x04},
188 {0x24, 0x00},
189 {0x56, 0x20},
190 {0x5b, 0x00},
191 {0x5e, 0x01},
192 /*analog Register width*/
193 {0x21, 0x3c},
194 {0x44, 0x20},
195 {0xcc, 0x01},
196 /*analog mode*/
197 {0x1a, 0x04},
198 {0x1f, 0x11},
199 {0x27, 0x30},
200 {0x2b, 0x00},
201 {0x33, 0x00},
202 {0x53, 0x90},
203 {0xe6, 0x50},
204 /*analog voltage*/
205 {0x39, 0x07},
206 {0x43, 0x04},
207 {0x46, 0x2a},
208 {0x7c, 0xa0},
209 {0xd0, 0xbe},
210 {0xd1, 0x40},
211 {0xd2, 0x40},
212 {0xd3, 0xb3},
213 {0xde, 0x1c},
214 /*analog current*/
215 {0xcd, 0x06},
216 {0xce, 0x6f},
217 /*CISCTL RESET*/
218 {0xfc, 0x88},
219 {0xfe, 0x10},
220 {0xfe, 0x00},
221 {0xfc, 0x8e},
222 {0xfe, 0x00},
223 {0xfe, 0x00},
224 {0xfe, 0x00},
225 {0xfe, 0x00},
226 {0xfc, 0x88},
227 {0xfe, 0x10},
228 {0xfe, 0x00},
229 {0xfc, 0x8e},
230 {0xfe, 0x04},
231 {0xe0, 0x01},
232 {0xfe, 0x00},
233 /*ISP*/
234 {0xfe, 0x01},
235 {0x53, 0x54},
236 {0x87, 0x53},
237 {0x89, 0x03},
238 /*Gain*/
239 {0xfe, 0x00},
240 {0xb0, 0x74},
241 {0xb1, 0x04},
242 {0xb2, 0x00},
243 {0xb6, 0x00},
244 {0xfe, 0x04},
245 {0xd8, 0x00},
246 {0xc0, 0x40},
247 {0xc0, 0x00},
248 {0xc0, 0x00},
249 {0xc0, 0x00},
250 {0xc0, 0x60},
251 {0xc0, 0x00},
252 {0xc0, 0xc0},
253 {0xc0, 0x2a},
254 {0xc0, 0x80},
255 {0xc0, 0x00},
256 {0xc0, 0x00},
257 {0xc0, 0x40},
258 {0xc0, 0xa0},
259 {0xc0, 0x00},
260 {0xc0, 0x90},
261 {0xc0, 0x19},
262 {0xc0, 0xc0},
263 {0xc0, 0x00},
264 {0xc0, 0xD0},
265 {0xc0, 0x2F},
266 {0xc0, 0xe0},
267 {0xc0, 0x00},
268 {0xc0, 0x90},
269 {0xc0, 0x39},
270 {0xc0, 0x00},
271 {0xc0, 0x01},
272 {0xc0, 0x20},
273 {0xc0, 0x04},
274 {0xc0, 0x20},
275 {0xc0, 0x01},
276 {0xc0, 0xe0},
277 {0xc0, 0x0f},
278 {0xc0, 0x40},
279 {0xc0, 0x01},
280 {0xc0, 0xe0},
281 {0xc0, 0x1a},
282 {0xc0, 0x60},
283 {0xc0, 0x01},
284 {0xc0, 0x20},
285 {0xc0, 0x25},
286 {0xc0, 0x80},
287 {0xc0, 0x01},
288 {0xc0, 0xa0},
289 {0xc0, 0x2c},
290 {0xc0, 0xa0},
291 {0xc0, 0x01},
292 {0xc0, 0xe0},
293 {0xc0, 0x32},
294 {0xc0, 0xc0},
295 {0xc0, 0x01},
296 {0xc0, 0x20},
297 {0xc0, 0x38},
298 {0xc0, 0xe0},
299 {0xc0, 0x01},
300 {0xc0, 0x60},
301 {0xc0, 0x3c},
302 {0xc0, 0x00},
303 {0xc0, 0x02},
304 {0xc0, 0xa0},
305 {0xc0, 0x40},
306 {0xc0, 0x80},
307 {0xc0, 0x02},
308 {0xc0, 0x18},
309 {0xc0, 0x5c},
310 {0xfe, 0x00},
311 {0x9f, 0x10},
312 /*BLK*/
313 {0xfe, 0x00},
314 {0x26, 0x20},
315 {0xfe, 0x01},
316 {0x40, 0x22},
317 {0x46, 0x7f},
318 {0x49, 0x0f},
319 {0x4a, 0xf0},
320 {0xfe, 0x04},
321 {0x14, 0x80},
322 {0x15, 0x80},
323 {0x16, 0x80},
324 {0x17, 0x80},
325 /*anti_blooming*/
326 {0xfe, 0x01},
327 {0x41, 0x20},
328 {0x4c, 0x00},
329 {0x4d, 0x0c},
330 {0x44, 0x08},
331 {0x48, 0x03},
332 /*Window 1600X1200*/
333 {0xfe, 0x01},
334 {0x90, 0x01},
335 {0x91, 0x00},
336 {0x92, 0x06},
337 {0x93, 0x00},
338 {0x94, 0x06},
339 {0x95, 0x04},
340 {0x96, 0xb0},
341 {0x97, 0x06},
342 {0x98, 0x40},
343 /*mipi*/
344 {0xfe, 0x03},
345 {0x01, 0x23},
346 {0x03, 0xce},
347 {0x04, 0x48},
348 {0x15, 0x01},
349 {0x21, 0x10},
350 {0x22, 0x05},
351 {0x23, 0x20},
352 {0x25, 0x20},
353 {0x26, 0x08},
354 {0x29, 0x06},
355 {0x2a, 0x0a},
356 {0x2b, 0x08},
357 /*out*/
358 {0xfe, 0x01},
359 {0x8c, 0x10},
360 {REG_NULL, 0x00},
361 };
362
363 static const struct gc02m2_mode supported_modes[] = {
364 {
365 .width = 1600,
366 .height = 1200,
367 .max_fps = {
368 .numerator = 10000,
369 .denominator = 300000,
370 },
371 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
372 .exp_def = 0x0475,
373 .hts_def = 0x0448 * 2,
374 .vts_def = 0x04f4,
375 .reg_list = gc02m2_global_regs,
376 .hdr_mode = NO_HDR,
377 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
378 },
379 };
380
381 static const s64 link_freq_menu_items[] = {
382 GC02M2_MIPI_LINK_FREQ
383 };
384
gc02m2_write_reg(struct i2c_client * client,u8 reg,u8 val)385 static int gc02m2_write_reg(struct i2c_client *client, u8 reg, u8 val)
386 {
387 struct i2c_msg msg;
388 u8 buf[2];
389 int ret;
390
391 buf[0] = reg & 0xFF;
392 buf[1] = val;
393
394 msg.addr = client->addr;
395 msg.flags = client->flags;
396 msg.buf = buf;
397 msg.len = sizeof(buf);
398
399 ret = i2c_transfer(client->adapter, &msg, 1);
400 if (ret >= 0)
401 return 0;
402
403 dev_err(&client->dev,
404 "gc02m2 write reg(0x%x val:0x%x) failed !\n", reg, val);
405
406 return ret;
407 }
408
gc02m2_write_array(struct i2c_client * client,const struct regval * regs)409 static int gc02m2_write_array(struct i2c_client *client,
410 const struct regval *regs)
411 {
412 u32 i;
413 int ret = 0;
414
415 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
416 ret = gc02m2_write_reg(client, regs[i].addr, regs[i].val);
417 }
418 return ret;
419 }
420
gc02m2_read_reg(struct i2c_client * client,u8 reg,u8 * val)421 static int gc02m2_read_reg(struct i2c_client *client, u8 reg, u8 *val)
422 {
423 struct i2c_msg msg[2];
424 u8 buf[1];
425 int ret;
426
427 buf[0] = reg & 0xFF;
428
429 msg[0].addr = client->addr;
430 msg[0].flags = client->flags;
431 msg[0].buf = buf;
432 msg[0].len = sizeof(buf);
433
434 msg[1].addr = client->addr;
435 msg[1].flags = client->flags | I2C_M_RD;
436 msg[1].buf = buf;
437 msg[1].len = 1;
438
439 ret = i2c_transfer(client->adapter, msg, 2);
440 if (ret >= 0) {
441 *val = buf[0];
442 return 0;
443 }
444
445 dev_err(&client->dev,
446 "gc02m2 read reg:0x%x failed !\n", reg);
447
448 return ret;
449 }
450
gc02m2_get_reso_dist(const struct gc02m2_mode * mode,struct v4l2_mbus_framefmt * framefmt)451 static int gc02m2_get_reso_dist(const struct gc02m2_mode *mode,
452 struct v4l2_mbus_framefmt *framefmt)
453 {
454 return abs(mode->width - framefmt->width) +
455 abs(mode->height - framefmt->height);
456 }
457
458 static const struct gc02m2_mode *
gc02m2_find_best_fit(struct v4l2_subdev_format * fmt)459 gc02m2_find_best_fit(struct v4l2_subdev_format *fmt)
460 {
461 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
462 int dist;
463 int cur_best_fit = 0;
464 int cur_best_fit_dist = -1;
465 unsigned int i;
466
467 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
468 dist = gc02m2_get_reso_dist(&supported_modes[i], framefmt);
469 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
470 cur_best_fit_dist = dist;
471 cur_best_fit = i;
472 }
473 }
474
475 return &supported_modes[cur_best_fit];
476 }
477
478 static u32 GC02M2_AGC_Param[17][2] = {
479 { 64 , 0 },
480 { 96 , 1 },
481 { 127 , 2 },
482 { 157 , 3 },
483 { 198 , 4 },
484 { 227 , 5 },
485 { 259 , 6 },
486 { 287 , 7 },
487 { 318 , 8 },
488 { 356 , 9 },
489 { 392 , 10 },
490 { 420 , 11 },
491 { 451 , 12 },
492 { 480 , 13 },
493 { 513 , 14 },
494 { 646 , 15 },
495 { 0xffff , 16 },
496 };
497
gc02m2_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)498 static int gc02m2_set_fmt(struct v4l2_subdev *sd,
499 struct v4l2_subdev_pad_config *cfg,
500 struct v4l2_subdev_format *fmt)
501 {
502 struct gc02m2 *gc02m2 = to_gc02m2(sd);
503 const struct gc02m2_mode *mode;
504 s64 h_blank, vblank_def;
505
506 mutex_lock(&gc02m2->mutex);
507
508 mode = gc02m2_find_best_fit(fmt);
509 fmt->format.code = mode->bus_fmt;
510 fmt->format.width = mode->width;
511 fmt->format.height = mode->height;
512 fmt->format.field = V4L2_FIELD_NONE;
513 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
514 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
515 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
516 #else
517 mutex_unlock(&gc02m2->mutex);
518 return -ENOTTY;
519 #endif
520 } else {
521 gc02m2->cur_mode = mode;
522 h_blank = mode->hts_def - mode->width;
523 __v4l2_ctrl_modify_range(gc02m2->hblank, h_blank,
524 h_blank, 1, h_blank);
525 vblank_def = mode->vts_def - mode->height;
526 __v4l2_ctrl_modify_range(gc02m2->vblank, vblank_def,
527 GC02M2_VTS_MAX - mode->height,
528 1, vblank_def);
529 }
530
531 mutex_unlock(&gc02m2->mutex);
532
533 return 0;
534 }
535
gc02m2_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)536 static int gc02m2_get_fmt(struct v4l2_subdev *sd,
537 struct v4l2_subdev_pad_config *cfg,
538 struct v4l2_subdev_format *fmt)
539 {
540 struct gc02m2 *gc02m2 = to_gc02m2(sd);
541 const struct gc02m2_mode *mode = gc02m2->cur_mode;
542
543 mutex_lock(&gc02m2->mutex);
544 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
545 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
546 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
547 #else
548 mutex_unlock(&gc02m2->mutex);
549 return -ENOTTY;
550 #endif
551 } else {
552 fmt->format.width = mode->width;
553 fmt->format.height = mode->height;
554 fmt->format.code = mode->bus_fmt;
555 fmt->format.field = V4L2_FIELD_NONE;
556 /* format info: width/height/data type/virctual channel */
557 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
558 fmt->reserved[0] = mode->vc[fmt->pad];
559 else
560 fmt->reserved[0] = mode->vc[PAD0];
561 }
562 mutex_unlock(&gc02m2->mutex);
563
564 return 0;
565 }
566
gc02m2_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)567 static int gc02m2_enum_mbus_code(struct v4l2_subdev *sd,
568 struct v4l2_subdev_pad_config *cfg,
569 struct v4l2_subdev_mbus_code_enum *code)
570 {
571 struct gc02m2 *gc02m2 = to_gc02m2(sd);
572 if (code->index != 0)
573 return -EINVAL;
574
575 code->code = gc02m2->cur_mode->bus_fmt;;
576
577 return 0;
578 }
579
gc02m2_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)580 static int gc02m2_enum_frame_sizes(struct v4l2_subdev *sd,
581 struct v4l2_subdev_pad_config *cfg,
582 struct v4l2_subdev_frame_size_enum *fse)
583 {
584 if (fse->index >= ARRAY_SIZE(supported_modes))
585 return -EINVAL;
586
587 if (fse->code != supported_modes[0].bus_fmt)
588 return -EINVAL;
589
590 fse->min_width = supported_modes[fse->index].width;
591 fse->max_width = supported_modes[fse->index].width;
592 fse->max_height = supported_modes[fse->index].height;
593 fse->min_height = supported_modes[fse->index].height;
594
595 return 0;
596 }
597
gc02m2_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)598 static int gc02m2_g_frame_interval(struct v4l2_subdev *sd,
599 struct v4l2_subdev_frame_interval *fi)
600 {
601 struct gc02m2 *gc02m2 = to_gc02m2(sd);
602 const struct gc02m2_mode *mode = gc02m2->cur_mode;
603
604 fi->interval = mode->max_fps;
605
606 return 0;
607 }
608
gc02m2_get_module_inf(struct gc02m2 * gc02m2,struct rkmodule_inf * inf)609 static void gc02m2_get_module_inf(struct gc02m2 *gc02m2,
610 struct rkmodule_inf *inf)
611 {
612 memset(inf, 0, sizeof(*inf));
613 strlcpy(inf->base.sensor, GC02M2_NAME, sizeof(inf->base.sensor));
614 strlcpy(inf->base.module, gc02m2->module_name,
615 sizeof(inf->base.module));
616 strlcpy(inf->base.lens, gc02m2->len_name, sizeof(inf->base.lens));
617 }
618
gc02m2_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)619 static long gc02m2_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
620 {
621 struct gc02m2 *gc02m2 = to_gc02m2(sd);
622 struct rkmodule_hdr_cfg *hdr_cfg;
623 long ret = 0;
624 int i, w, h;
625 u32 stream = 0;
626
627 switch (cmd) {
628 case RKMODULE_GET_MODULE_INFO:
629 gc02m2_get_module_inf(gc02m2, (struct rkmodule_inf *)arg);
630 break;
631 case RKMODULE_SET_QUICK_STREAM:
632 stream = *((u32 *)arg);
633 if (stream) {
634 ret = gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
635 ret |= gc02m2_write_reg(gc02m2->client, GC02M2_MODE_SELECT,
636 GC02M2_MODE_STREAMING);
637 ret |= gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
638 } else {
639 ret = gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
640 ret |= gc02m2_write_reg(gc02m2->client, GC02M2_MODE_SELECT,
641 GC02M2_MODE_SW_STANDBY);
642 ret |= gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
643 }
644 break;
645
646 case RKMODULE_GET_HDR_CFG:
647 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
648 hdr_cfg->esp.mode = HDR_NORMAL_VC;
649 hdr_cfg->hdr_mode = gc02m2->cur_mode->hdr_mode;
650 break;
651 case RKMODULE_SET_HDR_CFG:
652 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
653 w = gc02m2->cur_mode->width;
654 h = gc02m2->cur_mode->height;
655 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
656 if (w == supported_modes[i].width &&
657 h == supported_modes[i].height &&
658 supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
659 gc02m2->cur_mode = &supported_modes[i];
660 break;
661 }
662 }
663 if (i == ARRAY_SIZE(supported_modes)) {
664 dev_err(&gc02m2->client->dev,
665 "not find hdr mode:%d %dx%d config\n",
666 hdr_cfg->hdr_mode, w, h);
667 ret = -EINVAL;
668 } else {
669 w = gc02m2->cur_mode->hts_def - gc02m2->cur_mode->width;
670 h = gc02m2->cur_mode->vts_def - gc02m2->cur_mode->height;
671 __v4l2_ctrl_modify_range(gc02m2->hblank, w, w, 1, w);
672 __v4l2_ctrl_modify_range(gc02m2->vblank, h,
673 GC02M2_VTS_MAX - gc02m2->cur_mode->height, 1, h);
674 }
675 break;
676 default:
677 ret = -ENOIOCTLCMD;
678 break;
679 }
680
681 return ret;
682 }
683
684 #ifdef CONFIG_COMPAT
gc02m2_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)685 static long gc02m2_compat_ioctl32(struct v4l2_subdev *sd,
686 unsigned int cmd, unsigned long arg)
687 {
688 void __user *up = compat_ptr(arg);
689 struct rkmodule_inf *inf;
690 struct rkmodule_hdr_cfg *hdr;
691 long ret;
692 u32 stream = 0;
693
694 switch (cmd) {
695 case RKMODULE_GET_MODULE_INFO:
696 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
697 if (!inf) {
698 ret = -ENOMEM;
699 return ret;
700 }
701
702 ret = gc02m2_ioctl(sd, cmd, inf);
703 if (!ret)
704 ret = copy_to_user(up, inf, sizeof(*inf));
705 kfree(inf);
706 break;
707 case RKMODULE_GET_HDR_CFG:
708 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
709 if (!hdr) {
710 ret = -ENOMEM;
711 return ret;
712 }
713
714 ret = gc02m2_ioctl(sd, cmd, hdr);
715 if (!ret)
716 ret = copy_to_user(up, hdr, sizeof(*hdr));
717 kfree(hdr);
718 break;
719 case RKMODULE_SET_HDR_CFG:
720 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
721 if (!hdr) {
722 ret = -ENOMEM;
723 return ret;
724 }
725
726 ret = copy_from_user(hdr, up, sizeof(*hdr));
727 if (!ret)
728 ret = gc02m2_ioctl(sd, cmd, hdr);
729 kfree(hdr);
730 break;
731 case RKMODULE_SET_QUICK_STREAM:
732 ret = copy_from_user(&stream, up, sizeof(u32));
733 if (!ret)
734 ret = gc02m2_ioctl(sd, cmd, &stream);
735 break;
736 default:
737 ret = -ENOIOCTLCMD;
738 break;
739 }
740
741 return ret;
742 }
743 #endif
744
745 /* Calculate the delay in us by clock rate and clock cycles */
gc02m2_cal_delay(u32 cycles)746 static inline u32 gc02m2_cal_delay(u32 cycles)
747 {
748 return DIV_ROUND_UP(cycles, GC02M2_XVCLK_FREQ / 1000 / 1000);
749 }
750
__gc02m2_power_on(struct gc02m2 * gc02m2)751 static int __gc02m2_power_on(struct gc02m2 *gc02m2)
752 {
753 int ret;
754 u32 delay_us;
755 struct device *dev = &gc02m2->client->dev;
756
757 if (!IS_ERR_OR_NULL(gc02m2->pins_default)) {
758 ret = pinctrl_select_state(gc02m2->pinctrl,
759 gc02m2->pins_default);
760 if (ret < 0)
761 dev_err(dev, "could not set pins\n");
762 }
763 ret = clk_set_rate(gc02m2->xvclk, GC02M2_XVCLK_FREQ);
764 if (ret < 0)
765 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
766 if (clk_get_rate(gc02m2->xvclk) != GC02M2_XVCLK_FREQ)
767 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
768 ret = clk_prepare_enable(gc02m2->xvclk);
769 if (ret < 0) {
770 dev_err(dev, "Failed to enable xvclk\n");
771 return ret;
772 }
773
774 ret = regulator_bulk_enable(GC02M2_NUM_SUPPLIES, gc02m2->supplies);
775 if (ret < 0) {
776 dev_err(dev, "Failed to enable regulators\n");
777 goto disable_clk;
778 }
779
780 if (!IS_ERR(gc02m2->reset_gpio))
781 gpiod_set_value_cansleep(gc02m2->reset_gpio, 1);
782 if (!IS_ERR(gc02m2->pwdn_gpio))
783 gpiod_set_value_cansleep(gc02m2->pwdn_gpio, 0);
784
785 if (!IS_ERR(gc02m2->reset_gpio))
786 gpiod_set_value_cansleep(gc02m2->reset_gpio, 0);
787 usleep_range(500, 1000);
788
789 /* 8192 cycles prior to first SCCB transaction */
790 delay_us = gc02m2_cal_delay(8192);
791 usleep_range(delay_us, delay_us * 2);
792 gc02m2->power_on = true;
793 return 0;
794
795 disable_clk:
796 clk_disable_unprepare(gc02m2->xvclk);
797
798 return ret;
799 }
800
__gc02m2_power_off(struct gc02m2 * gc02m2)801 static void __gc02m2_power_off(struct gc02m2 *gc02m2)
802 {
803
804 int ret;
805 struct device *dev = &gc02m2->client->dev;
806
807 if (!IS_ERR(gc02m2->pwdn_gpio))
808 gpiod_set_value_cansleep(gc02m2->pwdn_gpio, 1);
809 clk_disable_unprepare(gc02m2->xvclk);
810 if (!IS_ERR(gc02m2->reset_gpio))
811 gpiod_set_value_cansleep(gc02m2->reset_gpio, 1);
812 if (!IS_ERR_OR_NULL(gc02m2->pins_sleep)) {
813 ret = pinctrl_select_state(gc02m2->pinctrl,
814 gc02m2->pins_sleep);
815 if (ret < 0)
816 dev_dbg(dev, "could not set pins\n");
817 }
818 regulator_bulk_disable(GC02M2_NUM_SUPPLIES, gc02m2->supplies);
819 gc02m2->power_on = false;
820 }
821
__gc02m2_start_stream(struct gc02m2 * gc02m2)822 static int __gc02m2_start_stream(struct gc02m2 *gc02m2)
823 {
824 int ret;
825
826 /* In case these controls are set before streaming */
827 mutex_unlock(&gc02m2->mutex);
828 ret = v4l2_ctrl_handler_setup(&gc02m2->ctrl_handler);
829 mutex_lock(&gc02m2->mutex);
830 if (ret)
831 return ret;
832
833 ret = gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
834 ret |= gc02m2_write_reg(gc02m2->client, GC02M2_MODE_SELECT,
835 GC02M2_MODE_STREAMING);
836 ret |= gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
837
838 return ret;
839 }
840
__gc02m2_stop_stream(struct gc02m2 * gc02m2)841 static int __gc02m2_stop_stream(struct gc02m2 *gc02m2)
842 {
843 int ret;
844
845 ret = gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
846 ret |= gc02m2_write_reg(gc02m2->client, GC02M2_MODE_SELECT,
847 GC02M2_MODE_SW_STANDBY);
848 ret |= gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
849
850 return ret;
851 }
852
gc02m2_s_stream(struct v4l2_subdev * sd,int on)853 static int gc02m2_s_stream(struct v4l2_subdev *sd, int on)
854 {
855 struct gc02m2 *gc02m2 = to_gc02m2(sd);
856 struct i2c_client *client = gc02m2->client;
857 int ret = 0;
858
859 mutex_lock(&gc02m2->mutex);
860 on = !!on;
861 if (on == gc02m2->streaming)
862 goto unlock_and_return;
863
864 if (on) {
865 ret = pm_runtime_get_sync(&client->dev);
866 if (ret < 0) {
867 pm_runtime_put_noidle(&client->dev);
868 goto unlock_and_return;
869 }
870
871 ret = __gc02m2_start_stream(gc02m2);
872 if (ret) {
873 v4l2_err(sd, "start stream failed while write regs\n");
874 pm_runtime_put(&client->dev);
875 goto unlock_and_return;
876 }
877 } else {
878 __gc02m2_stop_stream(gc02m2);
879 pm_runtime_put(&client->dev);
880 }
881
882 gc02m2->streaming = on;
883
884 unlock_and_return:
885 mutex_unlock(&gc02m2->mutex);
886
887 return ret;
888 }
889
gc02m2_s_power(struct v4l2_subdev * sd,int on)890 static int gc02m2_s_power(struct v4l2_subdev *sd, int on)
891 {
892 struct gc02m2 *gc02m2 = to_gc02m2(sd);
893 struct i2c_client *client = gc02m2->client;
894 int ret = 0;
895
896 mutex_lock(&gc02m2->mutex);
897
898 /* If the power state is not modified - no work to do. */
899 if (gc02m2->power_on == !!on)
900 goto unlock_and_return;
901
902 if (on) {
903 ret = pm_runtime_get_sync(&client->dev);
904 if (ret < 0) {
905 pm_runtime_put_noidle(&client->dev);
906 goto unlock_and_return;
907 }
908
909 ret = gc02m2_write_array(gc02m2->client, gc02m2->cur_mode->reg_list);
910 if (ret) {
911 v4l2_err(sd, "could not set init registers\n");
912 pm_runtime_put_noidle(&client->dev);
913 goto unlock_and_return;
914 }
915
916 gc02m2->power_on = true;
917 } else {
918 pm_runtime_put(&client->dev);
919 gc02m2->power_on = false;
920 }
921
922 unlock_and_return:
923 mutex_unlock(&gc02m2->mutex);
924
925 return ret;
926 }
927
928
gc02m2_runtime_resume(struct device * dev)929 static int gc02m2_runtime_resume(struct device *dev)
930 {
931 struct i2c_client *client = to_i2c_client(dev);
932 struct v4l2_subdev *sd = i2c_get_clientdata(client);
933 struct gc02m2 *gc02m2 = to_gc02m2(sd);
934
935 return __gc02m2_power_on(gc02m2);
936 }
937
gc02m2_runtime_suspend(struct device * dev)938 static int gc02m2_runtime_suspend(struct device *dev)
939 {
940 struct i2c_client *client = to_i2c_client(dev);
941 struct v4l2_subdev *sd = i2c_get_clientdata(client);
942 struct gc02m2 *gc02m2 = to_gc02m2(sd);
943
944 __gc02m2_power_off(gc02m2);
945
946 return 0;
947 }
948
949 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc02m2_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)950 static int gc02m2_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
951 {
952 struct gc02m2 *gc02m2 = to_gc02m2(sd);
953 struct v4l2_mbus_framefmt *try_fmt =
954 v4l2_subdev_get_try_format(sd, fh->pad, 0);
955 const struct gc02m2_mode *def_mode = &supported_modes[0];
956
957 mutex_lock(&gc02m2->mutex);
958 /* Initialize try_fmt */
959 try_fmt->width = def_mode->width;
960 try_fmt->height = def_mode->height;
961 try_fmt->code = def_mode->bus_fmt;
962 try_fmt->field = V4L2_FIELD_NONE;
963
964 mutex_unlock(&gc02m2->mutex);
965 /* No crop or compose */
966
967 return 0;
968 }
969 #endif
970
gc02m2_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)971 static int gc02m2_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
972 struct v4l2_mbus_config *config)
973 {
974 struct gc02m2 *gc02m2 = to_gc02m2(sd);
975 const struct gc02m2_mode *mode = gc02m2->cur_mode;
976 u32 val = 0;
977
978 if (mode->hdr_mode == NO_HDR)
979 val = 1 << (GC02M2_LANES - 1) |
980 V4L2_MBUS_CSI2_CHANNEL_0 |
981 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
982
983 config->type = V4L2_MBUS_CSI2_DPHY;
984 config->flags = val;
985 return 0;
986 }
987
gc02m2_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)988 static int gc02m2_enum_frame_interval(struct v4l2_subdev *sd,
989 struct v4l2_subdev_pad_config *cfg,
990 struct v4l2_subdev_frame_interval_enum *fie)
991 {
992 if (fie->index >= ARRAY_SIZE(supported_modes))
993 return -EINVAL;
994
995 fie->code = supported_modes[fie->index].bus_fmt;
996 fie->width = supported_modes[fie->index].width;
997 fie->height = supported_modes[fie->index].height;
998 fie->interval = supported_modes[fie->index].max_fps;
999 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1000 return 0;
1001 }
1002
1003 static const struct dev_pm_ops gc02m2_pm_ops = {
1004 SET_RUNTIME_PM_OPS(gc02m2_runtime_suspend,
1005 gc02m2_runtime_resume, NULL)
1006 };
1007
1008 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1009 static const struct v4l2_subdev_internal_ops gc02m2_internal_ops = {
1010 .open = gc02m2_open,
1011 };
1012 #endif
1013
1014 static const struct v4l2_subdev_core_ops gc02m2_core_ops = {
1015 .s_power = gc02m2_s_power,
1016 .ioctl = gc02m2_ioctl,
1017 #ifdef CONFIG_COMPAT
1018 .compat_ioctl32 = gc02m2_compat_ioctl32,
1019 #endif
1020 };
1021
1022 static const struct v4l2_subdev_video_ops gc02m2_video_ops = {
1023 .s_stream = gc02m2_s_stream,
1024 .g_frame_interval = gc02m2_g_frame_interval,
1025 };
1026
1027 static const struct v4l2_subdev_pad_ops gc02m2_pad_ops = {
1028 .enum_mbus_code = gc02m2_enum_mbus_code,
1029 .enum_frame_size = gc02m2_enum_frame_sizes,
1030 .enum_frame_interval = gc02m2_enum_frame_interval,
1031 .get_fmt = gc02m2_get_fmt,
1032 .set_fmt = gc02m2_set_fmt,
1033 .get_mbus_config = gc02m2_g_mbus_config,
1034 };
1035
1036 static const struct v4l2_subdev_ops gc02m2_subdev_ops = {
1037 .core = &gc02m2_core_ops,
1038 .video = &gc02m2_video_ops,
1039 .pad = &gc02m2_pad_ops,
1040 };
1041
1042 #define DIGITAL_GAIN_BASE 1024
gc02m2_set_gain_reg(struct gc02m2 * gc02m2,u32 total_gain)1043 static int gc02m2_set_gain_reg(struct gc02m2 *gc02m2, u32 total_gain)
1044 {
1045 struct device *dev = &gc02m2->client->dev;
1046 int ret = 0, i = 0;
1047 u32 dgain = 0;
1048
1049 dev_dbg(dev, "total_gain = 0x%04x!\n", total_gain);
1050 if (total_gain < 0x40)
1051 total_gain = 0x40;
1052
1053 for (i = 15; i >= 0; i--) {
1054 if (total_gain >= GC02M2_AGC_Param[i][0] &&
1055 total_gain < GC02M2_AGC_Param[i + 1][0])
1056 break;
1057 }
1058 ret = gc02m2_write_reg(gc02m2->client,
1059 GC02M2_PAGE_SELECT, 0x00);
1060 ret |= gc02m2_write_reg(gc02m2->client,
1061 GC02M2_ANALOG_GAIN_REG, GC02M2_AGC_Param[i][1]);
1062 dgain = total_gain * DIGITAL_GAIN_BASE / GC02M2_AGC_Param[i][0];
1063
1064 dev_dbg(dev, "AGC_Param[%d][0] = %d dgain = 0x%04x!\n",
1065 i, GC02M2_AGC_Param[i][0], dgain);
1066 ret |= gc02m2_write_reg(gc02m2->client,
1067 GC02M2_PREGAIN_H_REG,
1068 dgain >> 8);
1069 ret |= gc02m2_write_reg(gc02m2->client,
1070 GC02M2_PREGAIN_L_REG,
1071 dgain & 0xff);
1072 return ret;
1073 }
1074
gc02m2_set_ctrl(struct v4l2_ctrl * ctrl)1075 static int gc02m2_set_ctrl(struct v4l2_ctrl *ctrl)
1076 {
1077 struct gc02m2 *gc02m2 = container_of(ctrl->handler,
1078 struct gc02m2, ctrl_handler);
1079 struct i2c_client *client = gc02m2->client;
1080 s64 max;
1081 int ret = 0;
1082 u32 vts = 0;
1083 u8 val = 0;
1084
1085 /* Propagate change of current control to all related controls */
1086 switch (ctrl->id) {
1087 case V4L2_CID_VBLANK:
1088 /* Update max exposure while meeting expected vblanking */
1089 max = gc02m2->cur_mode->height + ctrl->val - 16;
1090 __v4l2_ctrl_modify_range(gc02m2->exposure,
1091 gc02m2->exposure->minimum, max,
1092 gc02m2->exposure->step,
1093 gc02m2->exposure->default_value);
1094 break;
1095 }
1096
1097 if (!pm_runtime_get_if_in_use(&client->dev))
1098 return 0;
1099
1100 switch (ctrl->id) {
1101 case V4L2_CID_EXPOSURE:
1102 /* 4 least significant bits of expsoure are fractional part */
1103 ret = gc02m2_write_reg(gc02m2->client,
1104 GC02M2_PAGE_SELECT, 0x00);
1105 ret |= gc02m2_write_reg(gc02m2->client,
1106 GC02M2_REG_EXPOSURE_H,
1107 (ctrl->val >> 8) & 0x3f);
1108 ret |= gc02m2_write_reg(gc02m2->client,
1109 GC02M2_REG_EXPOSURE_L,
1110 ctrl->val & 0xff);
1111
1112 break;
1113 case V4L2_CID_ANALOGUE_GAIN:
1114 ret = gc02m2_set_gain_reg(gc02m2, ctrl->val);
1115 break;
1116 case V4L2_CID_VBLANK:
1117 vts = ctrl->val + gc02m2->cur_mode->height;
1118 ret = gc02m2_write_reg(gc02m2->client,
1119 GC02M2_PAGE_SELECT, 0x00);
1120 ret |= gc02m2_write_reg(gc02m2->client, GC02M2_REG_VTS_H,
1121 (vts >> 8) & 0x3f);
1122 ret |= gc02m2_write_reg(gc02m2->client, GC02M2_REG_VTS_L,
1123 vts & 0xff);
1124 break;
1125 case V4L2_CID_HFLIP:
1126 ret = gc02m2_write_reg(gc02m2->client,
1127 GC02M2_PAGE_SELECT, 0x00);
1128 ret |= gc02m2_read_reg(gc02m2->client, GC02M2_MIRROR_FLIP_REG, &val);
1129 ret |= gc02m2_write_reg(client, GC02M2_MIRROR_FLIP_REG,
1130 SC200AI_FETCH_MIRROR(val, ctrl->val));
1131 break;
1132 case V4L2_CID_VFLIP:
1133 ret = gc02m2_write_reg(gc02m2->client,
1134 GC02M2_PAGE_SELECT, 0x00);
1135 ret |= gc02m2_read_reg(gc02m2->client, GC02M2_MIRROR_FLIP_REG, &val);
1136 ret |= gc02m2_write_reg(client, GC02M2_MIRROR_FLIP_REG,
1137 SC200AI_FETCH_FLIP(val, ctrl->val));
1138 break;
1139 default:
1140 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1141 __func__, ctrl->id, ctrl->val);
1142 break;
1143 }
1144
1145 pm_runtime_put(&client->dev);
1146
1147 return ret;
1148 }
1149
1150 static const struct v4l2_ctrl_ops gc02m2_ctrl_ops = {
1151 .s_ctrl = gc02m2_set_ctrl,
1152 };
1153
gc02m2_check_sensor_id(struct gc02m2 * gc02m2,struct i2c_client * client)1154 static int gc02m2_check_sensor_id(struct gc02m2 *gc02m2,
1155 struct i2c_client *client)
1156 {
1157 struct device *dev = &gc02m2->client->dev;
1158 u8 pid, ver = 0x00;
1159 int ret;
1160 unsigned short id;
1161
1162 ret = gc02m2_read_reg(client, GC02M2_REG_CHIP_ID_H, &pid);
1163 if (ret) {
1164 dev_err(dev, "Read chip ID H register error\n");
1165 return ret;
1166 }
1167
1168 ret = gc02m2_read_reg(client, GC02M2_REG_CHIP_ID_L, &ver);
1169 if (ret) {
1170 dev_err(dev, "Read chip ID L register error\n");
1171 return ret;
1172 }
1173
1174 id = SENSOR_ID(pid, ver);
1175 if (id != CHIP_ID) {
1176 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1177 return ret;
1178 }
1179
1180 dev_info(dev, "detected gc%04x sensor\n", id);
1181
1182 return 0;
1183 }
1184
gc02m2_configure_regulators(struct gc02m2 * gc02m2)1185 static int gc02m2_configure_regulators(struct gc02m2 *gc02m2)
1186 {
1187 unsigned int i;
1188
1189 for (i = 0; i < GC02M2_NUM_SUPPLIES; i++)
1190 gc02m2->supplies[i].supply = gc02m2_supply_names[i];
1191
1192 return devm_regulator_bulk_get(&gc02m2->client->dev,
1193 GC02M2_NUM_SUPPLIES,
1194 gc02m2->supplies);
1195 }
1196
gc02m2_parse_of(struct gc02m2 * gc02m2)1197 static int gc02m2_parse_of(struct gc02m2 *gc02m2)
1198 {
1199 struct device *dev = &gc02m2->client->dev;
1200 struct device_node *endpoint;
1201 struct fwnode_handle *fwnode;
1202 int rval;
1203
1204 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1205 if (!endpoint) {
1206 dev_err(dev, "Failed to get endpoint\n");
1207 return -EINVAL;
1208 }
1209 fwnode = of_fwnode_handle(endpoint);
1210 rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
1211 of_node_put(endpoint);
1212 if (rval <= 0) {
1213 dev_warn(dev, " Get mipi lane num failed!\n");
1214 return -1;
1215 }
1216
1217 gc02m2->lane_num = rval;
1218 if (1 == gc02m2->lane_num) {
1219 gc02m2->cur_mode = &supported_modes[0];
1220 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1221 gc02m2->pixel_rate = GC02M2_MIPI_LINK_FREQ * 2U * gc02m2->lane_num / 10U;
1222 dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
1223 gc02m2->lane_num, gc02m2->pixel_rate);
1224 } else {
1225 dev_err(dev, "unsupported lane_num(%d)\n", gc02m2->lane_num);
1226 return -1;
1227 }
1228 return 0;
1229 }
1230
gc02m2_initialize_controls(struct gc02m2 * gc02m2)1231 static int gc02m2_initialize_controls(struct gc02m2 *gc02m2)
1232 {
1233 const struct gc02m2_mode *mode;
1234 struct v4l2_ctrl_handler *handler;
1235 struct v4l2_ctrl *ctrl;
1236 s64 exposure_max, vblank_def;
1237 u32 h_blank;
1238 int ret;
1239 struct device *dev = &gc02m2->client->dev;
1240
1241 dev_info(dev, "Enter %s(%d) !\n", __func__, __LINE__);
1242 handler = &gc02m2->ctrl_handler;
1243 mode = gc02m2->cur_mode;
1244 ret = v4l2_ctrl_handler_init(handler, 8);
1245 if (ret)
1246 return ret;
1247 handler->lock = &gc02m2->mutex;
1248
1249 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1250 0, 0, link_freq_menu_items);
1251 if (ctrl)
1252 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1253
1254 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1255 0, GC02M2_PIXEL_RATE, 1, GC02M2_PIXEL_RATE);
1256
1257 h_blank = mode->hts_def - mode->width;
1258 gc02m2->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1259 h_blank, h_blank, 1, h_blank);
1260 if (gc02m2->hblank)
1261 gc02m2->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1262
1263 vblank_def = mode->vts_def - mode->height;
1264 gc02m2->vblank = v4l2_ctrl_new_std(handler, &gc02m2_ctrl_ops,
1265 V4L2_CID_VBLANK, vblank_def,
1266 GC02M2_VTS_MAX - mode->height,
1267 1, vblank_def);
1268
1269 exposure_max = mode->vts_def - 16;
1270 gc02m2->exposure = v4l2_ctrl_new_std(handler, &gc02m2_ctrl_ops,
1271 V4L2_CID_EXPOSURE, GC02M2_EXPOSURE_MIN,
1272 exposure_max, GC02M2_EXPOSURE_STEP,
1273 mode->exp_def);
1274
1275 gc02m2->anal_gain = v4l2_ctrl_new_std(handler, &gc02m2_ctrl_ops,
1276 V4L2_CID_ANALOGUE_GAIN, GC02M2_GAIN_MIN,
1277 GC02M2_GAIN_MAX, GC02M2_GAIN_STEP,
1278 GC02M2_GAIN_DEFAULT);
1279
1280 v4l2_ctrl_new_std(handler, &gc02m2_ctrl_ops,
1281 V4L2_CID_HFLIP, 0, 1, 1, 0);
1282
1283 v4l2_ctrl_new_std(handler, &gc02m2_ctrl_ops,
1284 V4L2_CID_VFLIP, 0, 1, 1, 0);
1285
1286 if (handler->error) {
1287 ret = handler->error;
1288 dev_err(&gc02m2->client->dev,
1289 "Failed to init controls(%d)\n", ret);
1290 goto err_free_handler;
1291 }
1292
1293 gc02m2->subdev.ctrl_handler = handler;
1294
1295 return 0;
1296
1297 err_free_handler:
1298 v4l2_ctrl_handler_free(handler);
1299
1300 return ret;
1301 }
1302
gc02m2_probe(struct i2c_client * client,const struct i2c_device_id * id)1303 static int gc02m2_probe(struct i2c_client *client,
1304 const struct i2c_device_id *id)
1305 {
1306 struct device *dev = &client->dev;
1307 struct device_node *node = dev->of_node;
1308 struct gc02m2 *gc02m2;
1309 struct v4l2_subdev *sd;
1310 char facing[2];
1311 int ret;
1312
1313 dev_info(dev, "driver version: %02x.%02x.%02x",
1314 DRIVER_VERSION >> 16,
1315 (DRIVER_VERSION & 0xff00) >> 8,
1316 DRIVER_VERSION & 0x00ff);
1317
1318 gc02m2 = devm_kzalloc(dev, sizeof(*gc02m2), GFP_KERNEL);
1319 if (!gc02m2)
1320 return -ENOMEM;
1321
1322 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1323 &gc02m2->module_index);
1324 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1325 &gc02m2->module_facing);
1326 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1327 &gc02m2->module_name);
1328 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1329 &gc02m2->len_name);
1330 if (ret) {
1331 dev_err(dev, "could not get module information!\n");
1332 return -EINVAL;
1333 }
1334
1335 gc02m2->client = client;
1336 gc02m2->cur_mode = &supported_modes[0];
1337
1338 gc02m2->xvclk = devm_clk_get(dev, "xvclk");
1339 if (IS_ERR(gc02m2->xvclk)) {
1340 dev_err(dev, "Failed to get xvclk\n");
1341 return -EINVAL;
1342 }
1343
1344 gc02m2->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1345 if (IS_ERR(gc02m2->reset_gpio))
1346 dev_warn(dev, "Failed to get reset-gpios\n");
1347
1348 gc02m2->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_HIGH);
1349 if (IS_ERR(gc02m2->pwdn_gpio))
1350 dev_warn(dev, "Failed to get pwdn-gpios\n");
1351
1352 ret = gc02m2_parse_of(gc02m2);
1353 if (ret != 0)
1354 return -EINVAL;
1355
1356 gc02m2->pinctrl = devm_pinctrl_get(dev);
1357 if (!IS_ERR(gc02m2->pinctrl)) {
1358 gc02m2->pins_default =
1359 pinctrl_lookup_state(gc02m2->pinctrl,
1360 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1361 if (IS_ERR(gc02m2->pins_default))
1362 dev_err(dev, "could not get default pinstate\n");
1363
1364 gc02m2->pins_sleep =
1365 pinctrl_lookup_state(gc02m2->pinctrl,
1366 OF_CAMERA_PINCTRL_STATE_SLEEP);
1367 if (IS_ERR(gc02m2->pins_sleep))
1368 dev_err(dev, "could not get sleep pinstate\n");
1369 } else {
1370 dev_err(dev, "no pinctrl\n");
1371 }
1372
1373 ret = gc02m2_configure_regulators(gc02m2);
1374 if (ret) {
1375 dev_err(dev, "Failed to get power regulators\n");
1376 return ret;
1377 }
1378
1379 mutex_init(&gc02m2->mutex);
1380
1381 sd = &gc02m2->subdev;
1382 v4l2_i2c_subdev_init(sd, client, &gc02m2_subdev_ops);
1383 ret = gc02m2_initialize_controls(gc02m2);
1384 if (ret)
1385 goto err_destroy_mutex;
1386
1387 ret = __gc02m2_power_on(gc02m2);
1388 if (ret)
1389 goto err_free_handler;
1390
1391 ret = gc02m2_check_sensor_id(gc02m2, client);
1392 if (ret)
1393 goto err_power_off;
1394
1395 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1396 sd->internal_ops = &gc02m2_internal_ops;
1397 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1398 #endif
1399 #if defined(CONFIG_MEDIA_CONTROLLER)
1400 gc02m2->pad.flags = MEDIA_PAD_FL_SOURCE;
1401 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1402 ret = media_entity_pads_init(&sd->entity, 1, &gc02m2->pad);
1403 if (ret < 0)
1404 goto err_power_off;
1405 #endif
1406
1407 memset(facing, 0, sizeof(facing));
1408 if (strcmp(gc02m2->module_facing, "back") == 0)
1409 facing[0] = 'b';
1410 else
1411 facing[0] = 'f';
1412
1413 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1414 gc02m2->module_index, facing,
1415 GC02M2_NAME, dev_name(sd->dev));
1416 ret = v4l2_async_register_subdev_sensor_common(sd);
1417 if (ret) {
1418 dev_err(dev, "v4l2 async register subdev failed\n");
1419 goto err_clean_entity;
1420 }
1421
1422 pm_runtime_set_active(dev);
1423 pm_runtime_enable(dev);
1424 pm_runtime_idle(dev);
1425
1426 return 0;
1427
1428 err_clean_entity:
1429 #if defined(CONFIG_MEDIA_CONTROLLER)
1430 media_entity_cleanup(&sd->entity);
1431 #endif
1432 err_power_off:
1433 __gc02m2_power_off(gc02m2);
1434 err_free_handler:
1435 v4l2_ctrl_handler_free(&gc02m2->ctrl_handler);
1436 err_destroy_mutex:
1437 mutex_destroy(&gc02m2->mutex);
1438
1439 return ret;
1440 }
1441
gc02m2_remove(struct i2c_client * client)1442 static int gc02m2_remove(struct i2c_client *client)
1443 {
1444 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1445 struct gc02m2 *gc02m2 = to_gc02m2(sd);
1446
1447 v4l2_async_unregister_subdev(sd);
1448 #if defined(CONFIG_MEDIA_CONTROLLER)
1449 media_entity_cleanup(&sd->entity);
1450 #endif
1451 v4l2_ctrl_handler_free(&gc02m2->ctrl_handler);
1452 mutex_destroy(&gc02m2->mutex);
1453
1454 pm_runtime_disable(&client->dev);
1455 if (!pm_runtime_status_suspended(&client->dev))
1456 __gc02m2_power_off(gc02m2);
1457 pm_runtime_set_suspended(&client->dev);
1458
1459 return 0;
1460 }
1461
1462 #if IS_ENABLED(CONFIG_OF)
1463 static const struct of_device_id gc02m2_of_match[] = {
1464 { .compatible = "galaxycore,gc02m2" },
1465 {},
1466 };
1467 MODULE_DEVICE_TABLE(of, gc02m2_of_match);
1468 #endif
1469
1470 static const struct i2c_device_id gc02m2_match_id[] = {
1471 { "galaxycore,gc02m2", 0 },
1472 { },
1473 };
1474
1475 static struct i2c_driver gc02m2_i2c_driver = {
1476 .driver = {
1477 .name = GC02M2_NAME,
1478 .pm = &gc02m2_pm_ops,
1479 .of_match_table = of_match_ptr(gc02m2_of_match),
1480 },
1481 .probe = &gc02m2_probe,
1482 .remove = &gc02m2_remove,
1483 .id_table = gc02m2_match_id,
1484 };
1485
sensor_mod_init(void)1486 static int __init sensor_mod_init(void)
1487 {
1488 return i2c_add_driver(&gc02m2_i2c_driver);
1489 }
1490
sensor_mod_exit(void)1491 static void __exit sensor_mod_exit(void)
1492 {
1493 i2c_del_driver(&gc02m2_i2c_driver);
1494 }
1495
1496 device_initcall_sync(sensor_mod_init);
1497 module_exit(sensor_mod_exit);
1498
1499 MODULE_DESCRIPTION("GalaxyCore gc02m2 sensor driver");
1500 MODULE_LICENSE("GPL v2");
1501