1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * BF3925 CMOS Image Sensor driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun * V0.0X01.0X01 add enum_frame_interval function.
7*4882a593Smuzhiyun * V0.0X01.0X02 add quick stream on/off
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/media.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/of.h>
22*4882a593Smuzhiyun #include <linux/of_graph.h>
23*4882a593Smuzhiyun #include <linux/of_gpio.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
26*4882a593Smuzhiyun #include <linux/slab.h>
27*4882a593Smuzhiyun #include <linux/uaccess.h>
28*4882a593Smuzhiyun #include <linux/videodev2.h>
29*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
30*4882a593Smuzhiyun #include <linux/version.h>
31*4882a593Smuzhiyun #include <media/media-entity.h>
32*4882a593Smuzhiyun #include <media/v4l2-common.h>
33*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
34*4882a593Smuzhiyun #include <media/v4l2-device.h>
35*4882a593Smuzhiyun #include <media/v4l2-event.h>
36*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
37*4882a593Smuzhiyun #include <media/v4l2-image-sizes.h>
38*4882a593Smuzhiyun #include <media/v4l2-mediabus.h>
39*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x2)
42*4882a593Smuzhiyun #define DRIVER_NAME "bf3925"
43*4882a593Smuzhiyun #define BF3925_PIXEL_RATE (120 * 1000 * 1000)
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun * BF3925 register definitions
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun #define REG_SOFTWARE_STANDBY 0xf2
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define REG_SC_CHIP_ID_H 0xfc
51*4882a593Smuzhiyun #define REG_SC_CHIP_ID_L 0xfd
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define REG_NULL 0xFFFF /* Array end token */
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
56*4882a593Smuzhiyun #define BF3925_ID 0x3925
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun struct sensor_register {
59*4882a593Smuzhiyun u16 addr;
60*4882a593Smuzhiyun u8 value;
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun struct bf3925_framesize {
64*4882a593Smuzhiyun u16 width;
65*4882a593Smuzhiyun u16 height;
66*4882a593Smuzhiyun struct v4l2_fract max_fps;
67*4882a593Smuzhiyun u16 max_exp_lines;
68*4882a593Smuzhiyun const struct sensor_register *regs;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun struct bf3925_pll_ctrl {
72*4882a593Smuzhiyun u8 ctrl1;
73*4882a593Smuzhiyun u8 ctrl2;
74*4882a593Smuzhiyun u8 ctrl3;
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct bf3925_pixfmt {
78*4882a593Smuzhiyun u32 code;
79*4882a593Smuzhiyun /* Output format Register Value (REG_FORMAT_CTRL00) */
80*4882a593Smuzhiyun struct sensor_register *format_ctrl_regs;
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun struct pll_ctrl_reg {
84*4882a593Smuzhiyun unsigned int div;
85*4882a593Smuzhiyun unsigned char reg;
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static const char * const bf3925_supply_names[] = {
89*4882a593Smuzhiyun "dovdd", /* Digital I/O power */
90*4882a593Smuzhiyun "avdd", /* Analog power */
91*4882a593Smuzhiyun "dvdd", /* Digital core power */
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #define BF3925_NUM_SUPPLIES ARRAY_SIZE(bf3925_supply_names)
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun struct bf3925 {
97*4882a593Smuzhiyun struct v4l2_subdev sd;
98*4882a593Smuzhiyun struct media_pad pad;
99*4882a593Smuzhiyun struct v4l2_mbus_framefmt format;
100*4882a593Smuzhiyun unsigned int fps;
101*4882a593Smuzhiyun unsigned int xvclk_frequency;
102*4882a593Smuzhiyun struct clk *xvclk;
103*4882a593Smuzhiyun struct gpio_desc *power_gpio;
104*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
105*4882a593Smuzhiyun struct gpio_desc *pwdn_gpio;
106*4882a593Smuzhiyun struct gpio_desc *pwdn2_gpio;
107*4882a593Smuzhiyun struct regulator_bulk_data supplies[BF3925_NUM_SUPPLIES];
108*4882a593Smuzhiyun struct mutex lock;
109*4882a593Smuzhiyun struct i2c_client *client;
110*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrls;
111*4882a593Smuzhiyun struct v4l2_ctrl *link_frequency;
112*4882a593Smuzhiyun const struct bf3925_framesize *frame_size;
113*4882a593Smuzhiyun int streaming;
114*4882a593Smuzhiyun u32 module_index;
115*4882a593Smuzhiyun const char *module_facing;
116*4882a593Smuzhiyun const char *module_name;
117*4882a593Smuzhiyun const char *len_name;
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static const struct sensor_register bf3925_init_regs[] = {
121*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
122*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
123*4882a593Smuzhiyun {0x50, 0x00}, //bit[4]: digital subsample Data format selection
124*4882a593Smuzhiyun {0x51, 0x02}, //YUV Sequence
125*4882a593Smuzhiyun {0xe0, 0x00},
126*4882a593Smuzhiyun {0xe2, 0x64},
127*4882a593Smuzhiyun {0xe3, 0x48},
128*4882a593Smuzhiyun {0xe4, 0x83}, //Drive capability //0x81 ljx
129*4882a593Smuzhiyun {0xe7, 0x9b},
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun //clock, dummy
132*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
133*4882a593Smuzhiyun {0xe9, 0x2a}, //08 PLL setting
134*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
135*4882a593Smuzhiyun {0x01, 0x00},
136*4882a593Smuzhiyun {0x02, 0x90}, //Dummy Pixel Insert LSB
137*4882a593Smuzhiyun {0x03, 0x00}, ///02 //yang
138*4882a593Smuzhiyun {0x04, 0x00}, //Dummy line Insert LSB
139*4882a593Smuzhiyun {0xff, 0x01},
140*4882a593Smuzhiyun {0xe5, 0x32},
141*4882a593Smuzhiyun //init black
142*4882a593Smuzhiyun {0xff, 0x00},
143*4882a593Smuzhiyun {0x3d, 0x00},
144*4882a593Smuzhiyun {0x30, 0x61},
145*4882a593Smuzhiyun {0x31, 0x63},
146*4882a593Smuzhiyun {0x32, 0x60},
147*4882a593Smuzhiyun {0x33, 0x63},
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun //resolution
150*4882a593Smuzhiyun {0xff, 0x00},
151*4882a593Smuzhiyun {0x05, 0xa2}, ///a0
152*4882a593Smuzhiyun {0x09, 0x90}, ///00
153*4882a593Smuzhiyun {0x0a, 0x48},
154*4882a593Smuzhiyun {0x0b, 0x60},
155*4882a593Smuzhiyun {0x0c, 0x00},
156*4882a593Smuzhiyun {0x0d, 0xb8},
157*4882a593Smuzhiyun {0x0e, 0x40},
158*4882a593Smuzhiyun {0xff, 0x01},
159*4882a593Smuzhiyun {0x52, 0x01}, //Bit[1]: VSYNC option Bit[0]: HSYNC option
160*4882a593Smuzhiyun {0x5d, 0x02},
161*4882a593Smuzhiyun {0x5a, 0x00},
162*4882a593Smuzhiyun {0x5b, 0x00},
163*4882a593Smuzhiyun {0x5c, 0x00},
164*4882a593Smuzhiyun {0xff, 0x01},
165*4882a593Smuzhiyun {0x53, 0x30}, ///60
166*4882a593Smuzhiyun {0x54, 0x20}, ///40
167*4882a593Smuzhiyun {0x55, 0x00},
168*4882a593Smuzhiyun {0x56, 0x20}, ///40
169*4882a593Smuzhiyun {0x57, 0x00},
170*4882a593Smuzhiyun {0x58, 0x58}, ///b0
171*4882a593Smuzhiyun {0xff, 0x01},
172*4882a593Smuzhiyun {0x50, 0x00}, //bit[4]: digital subsample Data format selection
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun //initial AWB and AE
175*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
176*4882a593Smuzhiyun {0xb2, 0x81}, //Manual AWB & AE
177*4882a593Smuzhiyun {0xb0, 0x16},
178*4882a593Smuzhiyun {0xb1, 0x1d},
179*4882a593Smuzhiyun {0xb2, 0x89},
180*4882a593Smuzhiyun {0xff, 0x01},
181*4882a593Smuzhiyun {0x00, 0x00},
182*4882a593Smuzhiyun {0x0e, 0x0a},
183*4882a593Smuzhiyun {0x0f, 0x64},
184*4882a593Smuzhiyun {0x10, 0x28},
185*4882a593Smuzhiyun {0x00, 0x05},
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun //black control
188*4882a593Smuzhiyun {0xff, 0x00},
189*4882a593Smuzhiyun {0x3c, 0x97},
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun //black sun
192*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
193*4882a593Smuzhiyun {0xe1, 0xf8}, //28 bit[7:4]: Pixel bias current
194*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
195*4882a593Smuzhiyun {0x00, 0x47}, //bit[6]: black sun control bit[5:4]: mirror/flip
196*4882a593Smuzhiyun {0x18, 0x0c}, //PRST indoor
197*4882a593Smuzhiyun {0x19, 0x1a}, //PRST outdoor
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun //lens shading
200*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
201*4882a593Smuzhiyun {0x52, 0x13},
202*4882a593Smuzhiyun {0x53, 0x5c},
203*4882a593Smuzhiyun {0x54, 0x24},
204*4882a593Smuzhiyun {0x55, 0x13},
205*4882a593Smuzhiyun {0x56, 0x5c},
206*4882a593Smuzhiyun {0x57, 0x24},
207*4882a593Smuzhiyun {0x58, 0xd3},
208*4882a593Smuzhiyun {0x59, 0x5c},
209*4882a593Smuzhiyun {0x5a, 0x24},
210*4882a593Smuzhiyun {0x5b, 0x44}, ///46 lens shading gain of R
211*4882a593Smuzhiyun {0x5c, 0x3C}, ///43 lens shading gain of G1
212*4882a593Smuzhiyun {0x5d, 0x40}, //lens shading gain of B
213*4882a593Smuzhiyun {0x5e, 0x3C}, /// 43lens shading gain of G0
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun #if 0
216*4882a593Smuzhiyun /*gamma default */
217*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
218*4882a593Smuzhiyun {0x60, 0x30},
219*4882a593Smuzhiyun {0x61, 0x2a},
220*4882a593Smuzhiyun {0x62, 0x24},
221*4882a593Smuzhiyun {0x63, 0x1b},
222*4882a593Smuzhiyun {0x64, 0x18},
223*4882a593Smuzhiyun {0x65, 0x16},
224*4882a593Smuzhiyun {0x66, 0x14},
225*4882a593Smuzhiyun {0x67, 0x12},
226*4882a593Smuzhiyun {0x68, 0x10},
227*4882a593Smuzhiyun {0x69, 0x0e},
228*4882a593Smuzhiyun {0x6a, 0x0d},
229*4882a593Smuzhiyun {0x6b, 0x0c},
230*4882a593Smuzhiyun {0x6c, 0x0a},
231*4882a593Smuzhiyun {0x6d, 0x09},
232*4882a593Smuzhiyun {0x6e, 0x09},
233*4882a593Smuzhiyun #endif
234*4882a593Smuzhiyun {0x6f, 0xf0},
235*4882a593Smuzhiyun {0x70, 0x20},
236*4882a593Smuzhiyun {0x71, 0x60},
237*4882a593Smuzhiyun {0x72, 0x24},///10
238*4882a593Smuzhiyun {0x73, 0x24},///10
239*4882a593Smuzhiyun #if 1
240*4882a593Smuzhiyun //gamma hi-lit,nice over-ex.
241*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
242*4882a593Smuzhiyun {0x60, 0x33},
243*4882a593Smuzhiyun {0x61, 0x2b},
244*4882a593Smuzhiyun {0x62, 0x27},
245*4882a593Smuzhiyun {0x63, 0x22},
246*4882a593Smuzhiyun {0x64, 0x1b},
247*4882a593Smuzhiyun {0x65, 0x17},
248*4882a593Smuzhiyun {0x66, 0x14},
249*4882a593Smuzhiyun {0x67, 0x11},
250*4882a593Smuzhiyun {0x68, 0x0e},
251*4882a593Smuzhiyun {0x69, 0x0c},
252*4882a593Smuzhiyun {0x6a, 0x0b},
253*4882a593Smuzhiyun {0x6b, 0x0a},
254*4882a593Smuzhiyun {0x6c, 0x09},
255*4882a593Smuzhiyun {0x6d, 0x08},
256*4882a593Smuzhiyun {0x6e, 0x07},
257*4882a593Smuzhiyun #else
258*4882a593Smuzhiyun //gamma nice color
259*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
260*4882a593Smuzhiyun {0x60, 0x28},
261*4882a593Smuzhiyun {0x61, 0x28},
262*4882a593Smuzhiyun {0x62, 0x26},
263*4882a593Smuzhiyun {0x63, 0x22},
264*4882a593Smuzhiyun {0x64, 0x1f},
265*4882a593Smuzhiyun {0x65, 0x1c},
266*4882a593Smuzhiyun {0x66, 0x18},
267*4882a593Smuzhiyun {0x67, 0x13},
268*4882a593Smuzhiyun {0x68, 0x10},
269*4882a593Smuzhiyun {0x69, 0x0d},
270*4882a593Smuzhiyun {0x6a, 0x0c},
271*4882a593Smuzhiyun {0x6b, 0x0a},
272*4882a593Smuzhiyun {0x6c, 0x08},
273*4882a593Smuzhiyun {0x6d, 0x07},
274*4882a593Smuzhiyun {0x6e, 0x06},
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun ///gamma low denoise
277*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
278*4882a593Smuzhiyun {0x60, 0x24},
279*4882a593Smuzhiyun {0x61, 0x30},
280*4882a593Smuzhiyun {0x62, 0x20},
281*4882a593Smuzhiyun {0x63, 0x1a},
282*4882a593Smuzhiyun {0x64, 0x16},
283*4882a593Smuzhiyun {0x65, 0x13},
284*4882a593Smuzhiyun {0x66, 0x11},
285*4882a593Smuzhiyun {0x67, 0x0e},
286*4882a593Smuzhiyun {0x68, 0x0d},
287*4882a593Smuzhiyun {0x69, 0x0c},
288*4882a593Smuzhiyun {0x6a, 0x0b},
289*4882a593Smuzhiyun {0x6b, 0x09},
290*4882a593Smuzhiyun {0x6c, 0x09},
291*4882a593Smuzhiyun {0x6d, 0x08},
292*4882a593Smuzhiyun {0x6e, 0x07},
293*4882a593Smuzhiyun #endif
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun #if 1
296*4882a593Smuzhiyun //clearer
297*4882a593Smuzhiyun //denoise and edge enhancement
298*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
299*4882a593Smuzhiyun {0x80, 0x0f},
300*4882a593Smuzhiyun {0x81, 0x1e},
301*4882a593Smuzhiyun {0x83, 0x37}, //0x83[7:4]: de_noise threshhole; 0x83[3:0]: de_noise
302*4882a593Smuzhiyun {0x84, 0xe6},
303*4882a593Smuzhiyun {0x85, 0x00},
304*4882a593Smuzhiyun {0x86, 0xfc},
305*4882a593Smuzhiyun {0x87, 0x00},
306*4882a593Smuzhiyun {0x88, 0xa2}, //bit[7:6] 0 is low noise;
307*4882a593Smuzhiyun {0x89, 0xca},
308*4882a593Smuzhiyun {0x8a, 0x44},
309*4882a593Smuzhiyun {0x8b, 0x12},
310*4882a593Smuzhiyun {0x91, 0x48},
311*4882a593Smuzhiyun {0x92, 0x11},
312*4882a593Smuzhiyun {0x93, 0x0c},
313*4882a593Smuzhiyun #else
314*4882a593Smuzhiyun //denoise and edge enhancement
315*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
316*4882a593Smuzhiyun {0x80, 0x0f},
317*4882a593Smuzhiyun {0x81, 0x0c},
318*4882a593Smuzhiyun {0x83, 0x27}, //0x83[7:4]: de_noise threshhole; 0x83[3:0]: de_noise
319*4882a593Smuzhiyun {0x84, 0xe6},
320*4882a593Smuzhiyun {0x85, 0x88},
321*4882a593Smuzhiyun {0x86, 0xfa},
322*4882a593Smuzhiyun {0x87, 0x1a},
323*4882a593Smuzhiyun {0x88, 0xa2}, //bit[7:6] 0 is low noise;
324*4882a593Smuzhiyun {0x89, 0xca},
325*4882a593Smuzhiyun {0x8b, 0x11}, //12 Bright/Dark edge enhancement
326*4882a593Smuzhiyun {0x91, 0x48}, //45 0x91:40
327*4882a593Smuzhiyun #endif
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun //AWB
330*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
331*4882a593Smuzhiyun {0xa2, 0x06}, //the low limit of blue gain for indoor scene
332*4882a593Smuzhiyun {0xa3, 0x28}, //the upper limit of blue gain for indoor scene
333*4882a593Smuzhiyun {0xa4, 0x0a}, //the low limit of red gain for indoor scene
334*4882a593Smuzhiyun {0xa5, 0x2c}, //the upper limit of red gain for indoor scene
335*4882a593Smuzhiyun {0xa7, 0x1b}, //Base B gain
336*4882a593Smuzhiyun {0xa8, 0x14}, //Base R gain
337*4882a593Smuzhiyun {0xa9, 0x15},
338*4882a593Smuzhiyun {0xaa, 0x18},
339*4882a593Smuzhiyun {0xab, 0x26},
340*4882a593Smuzhiyun {0xac, 0x5c},
341*4882a593Smuzhiyun {0xae, 0x47},
342*4882a593Smuzhiyun {0xb2, 0x89},
343*4882a593Smuzhiyun {0xb3, 0x66}, // green gain
344*4882a593Smuzhiyun {0xb4, 0x03}, //the offset of F light
345*4882a593Smuzhiyun {0xb5, 0x00}, //the offset of non-F light
346*4882a593Smuzhiyun {0xb6, 0xd9}, //bit[7]: outdoor control
347*4882a593Smuzhiyun {0xb8, 0xca},
348*4882a593Smuzhiyun {0xbb, 0x0d},
349*4882a593Smuzhiyun {0xbc, 0x15},
350*4882a593Smuzhiyun {0xbd, 0x09},
351*4882a593Smuzhiyun {0xbe, 0x24},
352*4882a593Smuzhiyun {0xbf, 0x66},
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun #if 1
355*4882a593Smuzhiyun // color default
356*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
357*4882a593Smuzhiyun {0xc0, 0x8a},
358*4882a593Smuzhiyun {0xc1, 0x05},
359*4882a593Smuzhiyun {0xc2, 0x84},
360*4882a593Smuzhiyun {0xc3, 0x86},
361*4882a593Smuzhiyun {0xc4, 0x03},
362*4882a593Smuzhiyun {0xc5, 0x93},
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun #else
365*4882a593Smuzhiyun //color Gorgeous
366*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
367*4882a593Smuzhiyun {0xc0, 0x83},
368*4882a593Smuzhiyun {0xc1, 0x86},
369*4882a593Smuzhiyun {0xc2, 0x82},
370*4882a593Smuzhiyun {0xc3, 0x8a},
371*4882a593Smuzhiyun {0xc4, 0x07},
372*4882a593Smuzhiyun {0xc5, 0x9f},
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun //color light
375*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
376*4882a593Smuzhiyun {0xc0, 0x83},
377*4882a593Smuzhiyun {0xc1, 0x02},
378*4882a593Smuzhiyun {0xc2, 0x84},
379*4882a593Smuzhiyun {0xc3, 0x84},
380*4882a593Smuzhiyun {0xc4, 0x03},
381*4882a593Smuzhiyun {0xc5, 0x8d},
382*4882a593Smuzhiyun #endif
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun // A color
385*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
386*4882a593Smuzhiyun {0xc6, 0x8a},
387*4882a593Smuzhiyun {0xc7, 0x82},
388*4882a593Smuzhiyun {0xc8, 0x8b},
389*4882a593Smuzhiyun {0xc9, 0x87},
390*4882a593Smuzhiyun {0xca, 0x83},
391*4882a593Smuzhiyun {0xcb, 0x91},
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun //Outdoor color
394*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
395*4882a593Smuzhiyun {0xd0, 0x90},
396*4882a593Smuzhiyun {0xd1, 0x05},
397*4882a593Smuzhiyun {0xd2, 0x82},
398*4882a593Smuzhiyun {0xd3, 0x88},
399*4882a593Smuzhiyun {0xd4, 0x03},
400*4882a593Smuzhiyun {0xd5, 0x93},
401*4882a593Smuzhiyun {0xcd, 0x30},
402*4882a593Smuzhiyun {0xd6, 0x61},
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun //AE
405*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
406*4882a593Smuzhiyun {0x00, 0x05},
407*4882a593Smuzhiyun {0x01, 0x8a}, // AE window and weight
408*4882a593Smuzhiyun {0x04, 0x48}, //4f AE Target//40
409*4882a593Smuzhiyun {0x05, 0x48}, //4f Y target value1//48
410*4882a593Smuzhiyun {0x07, 0x92}, //Bit[3:2]: the bigger, Y_AVER_MODIFY is smaller
411*4882a593Smuzhiyun {0x09, 0x8a}, //92 Bit[5:0]: INT_MAX//8c
412*4882a593Smuzhiyun {0x0a, 0xa5},
413*4882a593Smuzhiyun {0x0b, 0x82}, //Bit[5:0]: INT_MIN
414*4882a593Smuzhiyun {0x0c, 0xb4}, //78 50hz banding
415*4882a593Smuzhiyun {0x0d, 0x96}, //64 60hz banding
416*4882a593Smuzhiyun {0x15, 0x02}, //AEC
417*4882a593Smuzhiyun {0x16, 0x8c},
418*4882a593Smuzhiyun {0x17, 0xb5},
419*4882a593Smuzhiyun {0x18, 0x50}, ///30
420*4882a593Smuzhiyun {0x1b, 0x30}, ///33 minimum global gain
421*4882a593Smuzhiyun {0x1c, 0x58}, ///66
422*4882a593Smuzhiyun {0x1d, 0x38}, ///55
423*4882a593Smuzhiyun {0x1e, 0x58}, ///80
424*4882a593Smuzhiyun {0x1f, 0x60}, /// c0 maximum gain//a0
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun // saturation
427*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
428*4882a593Smuzhiyun {0x30, 0xff}, ///e0
429*4882a593Smuzhiyun {0x31, 0x48},
430*4882a593Smuzhiyun {0x32, 0x60}, ///f0
431*4882a593Smuzhiyun {0x34, 0xd8}, ///da Cb Saturation Coefficient low 8 bit for NF light
432*4882a593Smuzhiyun {0x35, 0xc8}, ///ca Cr Saturation Coefficient low 8 bit for NF light
433*4882a593Smuzhiyun {0x36, 0xff}, //Cb Saturation Coefficient low 8 bit for F light
434*4882a593Smuzhiyun {0x37, 0xd0}, //Cr Saturation Coefficient low 8 bit for F light
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun //skin
437*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
438*4882a593Smuzhiyun {0x3b, 0x08},
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun // auto contrast
441*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
442*4882a593Smuzhiyun {0x3e, 0x02}, //
443*4882a593Smuzhiyun {0x3e, 0x82}, //do not change
444*4882a593Smuzhiyun {0x38, 0x40},
445*4882a593Smuzhiyun //yang add start switch to 1600*1200 UXGA
446*4882a593Smuzhiyun //1600*1200
447*4882a593Smuzhiyun //window
448*4882a593Smuzhiyun //yang add end switch to 1600*1200 UXGA
449*4882a593Smuzhiyun {REG_NULL, 0x00},
450*4882a593Smuzhiyun };
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun /* Senor full resolution setting */
453*4882a593Smuzhiyun static const struct sensor_register bf3925_full_regs[] = {
454*4882a593Smuzhiyun //1600*1200
455*4882a593Smuzhiyun //window
456*4882a593Smuzhiyun {0xff, 0x00},
457*4882a593Smuzhiyun {0x05, 0xa0},
458*4882a593Smuzhiyun {0x09, 0x00},
459*4882a593Smuzhiyun {0x0a, 0x48},
460*4882a593Smuzhiyun {0x0b, 0x60},
461*4882a593Smuzhiyun {0x0c, 0x00},
462*4882a593Smuzhiyun {0x0d, 0xb8},
463*4882a593Smuzhiyun {0x0e, 0x40},
464*4882a593Smuzhiyun {0xff, 0x01},
465*4882a593Smuzhiyun {0x52, 0x01}, //Bit[1]: VSYNC option Bit[0]: HSYNC option
466*4882a593Smuzhiyun {0x5d, 0x02},
467*4882a593Smuzhiyun {0x5a, 0x00},
468*4882a593Smuzhiyun {0x5b, 0x00},
469*4882a593Smuzhiyun {0x5c, 0x00},
470*4882a593Smuzhiyun {0xff, 0x01},
471*4882a593Smuzhiyun {0x53, 0x60},
472*4882a593Smuzhiyun {0x54, 0x40},
473*4882a593Smuzhiyun {0x55, 0x00},
474*4882a593Smuzhiyun {0x56, 0x40},
475*4882a593Smuzhiyun {0x57, 0x00},
476*4882a593Smuzhiyun {0x58, 0xb0},
477*4882a593Smuzhiyun {0xff, 0x01},
478*4882a593Smuzhiyun {0x50, 0x00},
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun //clock, dummy
481*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
482*4882a593Smuzhiyun {0x09, 0x86},
483*4882a593Smuzhiyun {0xe9, 0x2a}, //08 PLL setting
484*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
485*4882a593Smuzhiyun {0x01, 0x00},
486*4882a593Smuzhiyun {0x02, 0x00}, //Dummy Pixel Insert LSB
487*4882a593Smuzhiyun {0x03, 0x00}, ///02 //yang
488*4882a593Smuzhiyun {0x04, 0x00}, //Dummy line Insert LSB
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun {REG_NULL, 0x00},
491*4882a593Smuzhiyun };
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun /* Preview resolution setting*/
494*4882a593Smuzhiyun static const struct sensor_register bf3925_svga_regs_15fps[] = {
495*4882a593Smuzhiyun //800*600
496*4882a593Smuzhiyun //window
497*4882a593Smuzhiyun {0xff, 0x00},
498*4882a593Smuzhiyun {0x05, 0xa0},
499*4882a593Smuzhiyun {0x09, 0x00},
500*4882a593Smuzhiyun {0x0a, 0x48},
501*4882a593Smuzhiyun {0x0b, 0x60},
502*4882a593Smuzhiyun {0x0c, 0x00},
503*4882a593Smuzhiyun {0x0d, 0xb8},
504*4882a593Smuzhiyun {0x0e, 0x40},
505*4882a593Smuzhiyun {0xff, 0x01},
506*4882a593Smuzhiyun {0x52, 0x01}, //Bit[1]: VSYNC option Bit[0]: HSYNC option
507*4882a593Smuzhiyun {0x5d, 0x02},
508*4882a593Smuzhiyun {0x5a, 0x00},
509*4882a593Smuzhiyun {0x5b, 0x00},
510*4882a593Smuzhiyun {0x5c, 0x00},
511*4882a593Smuzhiyun {0xff, 0x01},
512*4882a593Smuzhiyun {0x53, 0x30},
513*4882a593Smuzhiyun {0x54, 0x20},
514*4882a593Smuzhiyun {0x55, 0x02},
515*4882a593Smuzhiyun {0x56, 0x22},
516*4882a593Smuzhiyun {0x57, 0x01},
517*4882a593Smuzhiyun {0x58, 0x59},
518*4882a593Smuzhiyun {0xff, 0x01},
519*4882a593Smuzhiyun {0x50, 0x00},
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun //clock, dummy
522*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
523*4882a593Smuzhiyun {0x09, 0x86},
524*4882a593Smuzhiyun {0xe9, 0x2a}, //08 PLL setting
525*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
526*4882a593Smuzhiyun {0x01, 0x00},
527*4882a593Smuzhiyun {0x02, 0x00}, //Dummy Pixel Insert LSB
528*4882a593Smuzhiyun {0x03, 0x00}, ///02 //yang
529*4882a593Smuzhiyun {0x04, 0x00}, //Dummy line Insert LSB
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun {REG_NULL, 0x00},
532*4882a593Smuzhiyun };
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /* Preview resolution setting*/
535*4882a593Smuzhiyun static const struct sensor_register bf3925_svga_regs_30fps[] = {
536*4882a593Smuzhiyun //800*600
537*4882a593Smuzhiyun {0xff, 0x00},
538*4882a593Smuzhiyun {0x05, 0xa2},
539*4882a593Smuzhiyun {0x09, 0x04},
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun {0x0a, 0x4c},
542*4882a593Smuzhiyun {0x0b, 0x60},
543*4882a593Smuzhiyun {0x0c, 0x04},
544*4882a593Smuzhiyun {0x0d, 0xbc},
545*4882a593Smuzhiyun {0x0e, 0x40},
546*4882a593Smuzhiyun {0xff, 0x01},
547*4882a593Smuzhiyun {0x52, 0x01},
548*4882a593Smuzhiyun {0x5d, 0x02},
549*4882a593Smuzhiyun {0x5a, 0x00},
550*4882a593Smuzhiyun {0x5b, 0x00},
551*4882a593Smuzhiyun {0x5c, 0x00},
552*4882a593Smuzhiyun {0xff, 0x01},
553*4882a593Smuzhiyun {0x09, 0x83},
554*4882a593Smuzhiyun {0x53, 0x30},
555*4882a593Smuzhiyun {0x54, 0x20},
556*4882a593Smuzhiyun {0x55, 0x02},
557*4882a593Smuzhiyun {0x56, 0x22},
558*4882a593Smuzhiyun {0x57, 0x01},
559*4882a593Smuzhiyun {0x58, 0x59},
560*4882a593Smuzhiyun {0xff, 0x01},
561*4882a593Smuzhiyun {0x50, 0x00},
562*4882a593Smuzhiyun {0xe9, 0x2a},
563*4882a593Smuzhiyun //clock, dummy
564*4882a593Smuzhiyun {0xff, 0x01}, //Bit[0]: select reg page
565*4882a593Smuzhiyun {0x09, 0x83},
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun /* 08 PLL setting 0x09: 1 times
568*4882a593Smuzhiyun * 0x1b: multiply 5/4 0x2b: 3/2 multiply
569*4882a593Smuzhiyun * 0x08:double 0x1a: 5/2 multiply
570*4882a593Smuzhiyun * 0x2a: triple 0x2a ljx 2017-6
571*4882a593Smuzhiyun */
572*4882a593Smuzhiyun {0xe9, 0x08},
573*4882a593Smuzhiyun {0xff, 0x00}, //Bit[0]: select reg page
574*4882a593Smuzhiyun {0x01, 0x00},
575*4882a593Smuzhiyun {0x02, 0xea}, //Dummy Pixel Insert LSB
576*4882a593Smuzhiyun {0x03, 0x00}, ///02 //yang
577*4882a593Smuzhiyun {0x04, 0x00}, //Dummy line Insert LSB
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun {REG_NULL, 0x00},
580*4882a593Smuzhiyun };
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun static const struct bf3925_framesize bf3925_framesizes[] = {
583*4882a593Smuzhiyun { /* SVGA */
584*4882a593Smuzhiyun .width = 800,
585*4882a593Smuzhiyun .height = 600,
586*4882a593Smuzhiyun .max_fps = {
587*4882a593Smuzhiyun .numerator = 10000,
588*4882a593Smuzhiyun .denominator = 150000,
589*4882a593Smuzhiyun },
590*4882a593Smuzhiyun .regs = bf3925_svga_regs_15fps,
591*4882a593Smuzhiyun }, { /* SVGA */
592*4882a593Smuzhiyun .width = 800,
593*4882a593Smuzhiyun .height = 600,
594*4882a593Smuzhiyun .max_fps = {
595*4882a593Smuzhiyun .numerator = 10000,
596*4882a593Smuzhiyun .denominator = 300000,
597*4882a593Smuzhiyun },
598*4882a593Smuzhiyun .regs = bf3925_svga_regs_30fps,
599*4882a593Smuzhiyun }, { /* FULL */
600*4882a593Smuzhiyun .width = 1600,
601*4882a593Smuzhiyun .height = 1200,
602*4882a593Smuzhiyun .max_fps = {
603*4882a593Smuzhiyun .numerator = 10000,
604*4882a593Smuzhiyun .denominator = 150000,
605*4882a593Smuzhiyun },
606*4882a593Smuzhiyun .regs = bf3925_full_regs,
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun };
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun static const struct bf3925_pixfmt bf3925_formats[] = {
611*4882a593Smuzhiyun {
612*4882a593Smuzhiyun .code = MEDIA_BUS_FMT_UYVY8_2X8,
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun };
615*4882a593Smuzhiyun
to_bf3925(struct v4l2_subdev * sd)616*4882a593Smuzhiyun static inline struct bf3925 *to_bf3925(struct v4l2_subdev *sd)
617*4882a593Smuzhiyun {
618*4882a593Smuzhiyun return container_of(sd, struct bf3925, sd);
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun /* sensor register write */
bf3925_write(struct i2c_client * client,u8 reg,u8 val)622*4882a593Smuzhiyun static int bf3925_write(struct i2c_client *client, u8 reg, u8 val)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun struct i2c_msg msg;
625*4882a593Smuzhiyun u8 buf[2];
626*4882a593Smuzhiyun int ret;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
629*4882a593Smuzhiyun buf[0] = reg & 0xFF;
630*4882a593Smuzhiyun buf[1] = val;
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun msg.addr = client->addr;
633*4882a593Smuzhiyun msg.flags = client->flags;
634*4882a593Smuzhiyun msg.buf = buf;
635*4882a593Smuzhiyun msg.len = sizeof(buf);
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
638*4882a593Smuzhiyun if (ret >= 0)
639*4882a593Smuzhiyun return 0;
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun dev_err(&client->dev,
642*4882a593Smuzhiyun "bf3925 write reg(0x%x val:0x%x) failed !\n", reg, val);
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun return ret;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /* sensor register read */
bf3925_read(struct i2c_client * client,u8 reg,u8 * val)648*4882a593Smuzhiyun static int bf3925_read(struct i2c_client *client, u8 reg, u8 *val)
649*4882a593Smuzhiyun {
650*4882a593Smuzhiyun struct i2c_msg msg[2];
651*4882a593Smuzhiyun u8 buf[1];
652*4882a593Smuzhiyun int ret;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun buf[0] = reg & 0xFF;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun msg[0].addr = client->addr;
657*4882a593Smuzhiyun msg[0].flags = client->flags;
658*4882a593Smuzhiyun msg[0].buf = buf;
659*4882a593Smuzhiyun msg[0].len = sizeof(buf);
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun msg[1].addr = client->addr;
662*4882a593Smuzhiyun msg[1].flags = client->flags | I2C_M_RD;
663*4882a593Smuzhiyun msg[1].buf = buf;
664*4882a593Smuzhiyun msg[1].len = 1;
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msg, 2);
667*4882a593Smuzhiyun if (ret >= 0) {
668*4882a593Smuzhiyun *val = buf[0];
669*4882a593Smuzhiyun return 0;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun dev_err(&client->dev,
673*4882a593Smuzhiyun "bf3925 read reg:0x%x failed !\n", reg);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun return ret;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun
bf3925_write_array(struct i2c_client * client,const struct sensor_register * regs)678*4882a593Smuzhiyun static int bf3925_write_array(struct i2c_client *client,
679*4882a593Smuzhiyun const struct sensor_register *regs)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun int i, ret = 0;
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun i = 0;
684*4882a593Smuzhiyun while (regs[i].addr != REG_NULL) {
685*4882a593Smuzhiyun ret = bf3925_write(client, regs[i].addr, regs[i].value);
686*4882a593Smuzhiyun if (ret) {
687*4882a593Smuzhiyun dev_err(&client->dev, "%s failed !\n", __func__);
688*4882a593Smuzhiyun break;
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun i++;
692*4882a593Smuzhiyun }
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun return ret;
695*4882a593Smuzhiyun }
696*4882a593Smuzhiyun
bf3925_get_default_format(struct v4l2_mbus_framefmt * format)697*4882a593Smuzhiyun static void bf3925_get_default_format(struct v4l2_mbus_framefmt *format)
698*4882a593Smuzhiyun {
699*4882a593Smuzhiyun format->width = bf3925_framesizes[0].width;
700*4882a593Smuzhiyun format->height = bf3925_framesizes[0].height;
701*4882a593Smuzhiyun format->colorspace = V4L2_COLORSPACE_SRGB;
702*4882a593Smuzhiyun format->code = bf3925_formats[0].code;
703*4882a593Smuzhiyun format->field = V4L2_FIELD_NONE;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun
bf3925_set_streaming(struct bf3925 * bf3925,int on)706*4882a593Smuzhiyun static void bf3925_set_streaming(struct bf3925 *bf3925, int on)
707*4882a593Smuzhiyun {
708*4882a593Smuzhiyun struct i2c_client *client = bf3925->client;
709*4882a593Smuzhiyun int ret;
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun ret = bf3925_write(client, REG_SOFTWARE_STANDBY, on);
714*4882a593Smuzhiyun if (ret)
715*4882a593Smuzhiyun dev_err(&client->dev, "bf3925 soft standby failed\n");
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun /*
719*4882a593Smuzhiyun * V4L2 subdev video and pad level operations
720*4882a593Smuzhiyun */
721*4882a593Smuzhiyun
bf3925_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)722*4882a593Smuzhiyun static int bf3925_enum_mbus_code(struct v4l2_subdev *sd,
723*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
724*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
725*4882a593Smuzhiyun {
726*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun dev_dbg(&client->dev, "%s:\n", __func__);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun if (code->index >= ARRAY_SIZE(bf3925_formats))
731*4882a593Smuzhiyun return -EINVAL;
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun code->code = bf3925_formats[code->index].code;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun return 0;
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun
bf3925_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)738*4882a593Smuzhiyun static int bf3925_enum_frame_sizes(struct v4l2_subdev *sd,
739*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
740*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
741*4882a593Smuzhiyun {
742*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
743*4882a593Smuzhiyun int i = ARRAY_SIZE(bf3925_formats);
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun dev_dbg(&client->dev, "%s:\n", __func__);
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun if (fse->index >= ARRAY_SIZE(bf3925_framesizes))
748*4882a593Smuzhiyun return -EINVAL;
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun while (--i)
751*4882a593Smuzhiyun if (fse->code == bf3925_formats[i].code)
752*4882a593Smuzhiyun break;
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun fse->code = bf3925_formats[i].code;
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun fse->min_width = bf3925_framesizes[fse->index].width;
757*4882a593Smuzhiyun fse->max_width = fse->min_width;
758*4882a593Smuzhiyun fse->max_height = bf3925_framesizes[fse->index].height;
759*4882a593Smuzhiyun fse->min_height = fse->max_height;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun return 0;
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun
bf3925_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)764*4882a593Smuzhiyun static int bf3925_get_fmt(struct v4l2_subdev *sd,
765*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
766*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
767*4882a593Smuzhiyun {
768*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
769*4882a593Smuzhiyun struct bf3925 *bf3925 = to_bf3925(sd);
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun dev_dbg(&client->dev, "%s enter\n", __func__);
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
774*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
775*4882a593Smuzhiyun struct v4l2_mbus_framefmt *mf;
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun mf = v4l2_subdev_get_try_format(sd, cfg, 0);
778*4882a593Smuzhiyun mutex_lock(&bf3925->lock);
779*4882a593Smuzhiyun fmt->format = *mf;
780*4882a593Smuzhiyun mutex_unlock(&bf3925->lock);
781*4882a593Smuzhiyun return 0;
782*4882a593Smuzhiyun #else
783*4882a593Smuzhiyun return -ENOTTY;
784*4882a593Smuzhiyun #endif
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun mutex_lock(&bf3925->lock);
788*4882a593Smuzhiyun fmt->format = bf3925->format;
789*4882a593Smuzhiyun mutex_unlock(&bf3925->lock);
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun dev_dbg(&client->dev, "%s: %x %dx%d\n", __func__,
792*4882a593Smuzhiyun bf3925->format.code, bf3925->format.width,
793*4882a593Smuzhiyun bf3925->format.height);
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun return 0;
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun
__bf3925_try_frame_size_fps(struct v4l2_mbus_framefmt * mf,const struct bf3925_framesize ** size,unsigned int fps)798*4882a593Smuzhiyun static void __bf3925_try_frame_size_fps(struct v4l2_mbus_framefmt *mf,
799*4882a593Smuzhiyun const struct bf3925_framesize **size,
800*4882a593Smuzhiyun unsigned int fps)
801*4882a593Smuzhiyun {
802*4882a593Smuzhiyun const struct bf3925_framesize *fsize = &bf3925_framesizes[0];
803*4882a593Smuzhiyun const struct bf3925_framesize *match = NULL;
804*4882a593Smuzhiyun unsigned int i = ARRAY_SIZE(bf3925_framesizes);
805*4882a593Smuzhiyun unsigned int min_err = UINT_MAX;
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun while (i--) {
808*4882a593Smuzhiyun unsigned int err = abs(fsize->width - mf->width)
809*4882a593Smuzhiyun + abs(fsize->height - mf->height);
810*4882a593Smuzhiyun if (err < min_err && fsize->regs[0].addr) {
811*4882a593Smuzhiyun min_err = err;
812*4882a593Smuzhiyun match = fsize;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun fsize++;
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun if (!match) {
818*4882a593Smuzhiyun match = &bf3925_framesizes[0];
819*4882a593Smuzhiyun } else {
820*4882a593Smuzhiyun fsize = &bf3925_framesizes[0];
821*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(bf3925_framesizes); i++) {
822*4882a593Smuzhiyun if (fsize->width == match->width &&
823*4882a593Smuzhiyun fsize->height == match->height &&
824*4882a593Smuzhiyun fps >= DIV_ROUND_CLOSEST(fsize->max_fps.denominator,
825*4882a593Smuzhiyun fsize->max_fps.numerator))
826*4882a593Smuzhiyun match = fsize;
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun fsize++;
829*4882a593Smuzhiyun }
830*4882a593Smuzhiyun }
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun mf->width = match->width;
833*4882a593Smuzhiyun mf->height = match->height;
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun if (size)
836*4882a593Smuzhiyun *size = match;
837*4882a593Smuzhiyun }
838*4882a593Smuzhiyun
bf3925_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)839*4882a593Smuzhiyun static int bf3925_set_fmt(struct v4l2_subdev *sd,
840*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
841*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
842*4882a593Smuzhiyun {
843*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
844*4882a593Smuzhiyun int index = ARRAY_SIZE(bf3925_formats);
845*4882a593Smuzhiyun struct v4l2_mbus_framefmt *mf = &fmt->format;
846*4882a593Smuzhiyun const struct bf3925_framesize *size = NULL;
847*4882a593Smuzhiyun struct bf3925 *bf3925 = to_bf3925(sd);
848*4882a593Smuzhiyun int ret = 0;
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun dev_dbg(&client->dev, "%s enter\n", __func__);
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun __bf3925_try_frame_size_fps(mf, &size, bf3925->fps);
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun while (--index >= 0)
855*4882a593Smuzhiyun if (bf3925_formats[index].code == mf->code)
856*4882a593Smuzhiyun break;
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun if (index < 0)
859*4882a593Smuzhiyun return -EINVAL;
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun mf->colorspace = V4L2_COLORSPACE_SRGB;
862*4882a593Smuzhiyun mf->code = bf3925_formats[index].code;
863*4882a593Smuzhiyun mf->field = V4L2_FIELD_NONE;
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun mutex_lock(&bf3925->lock);
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
868*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
869*4882a593Smuzhiyun mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
870*4882a593Smuzhiyun *mf = fmt->format;
871*4882a593Smuzhiyun #else
872*4882a593Smuzhiyun return -ENOTTY;
873*4882a593Smuzhiyun #endif
874*4882a593Smuzhiyun } else {
875*4882a593Smuzhiyun if (bf3925->streaming) {
876*4882a593Smuzhiyun mutex_unlock(&bf3925->lock);
877*4882a593Smuzhiyun return -EBUSY;
878*4882a593Smuzhiyun }
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun bf3925->frame_size = size;
881*4882a593Smuzhiyun bf3925->format = fmt->format;
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun mutex_unlock(&bf3925->lock);
885*4882a593Smuzhiyun return ret;
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun
bf3925_s_stream(struct v4l2_subdev * sd,int on)888*4882a593Smuzhiyun static int bf3925_s_stream(struct v4l2_subdev *sd, int on)
889*4882a593Smuzhiyun {
890*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
891*4882a593Smuzhiyun struct bf3925 *bf3925 = to_bf3925(sd);
892*4882a593Smuzhiyun int ret = 0;
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun dev_info(&client->dev, "%s: on: %d, %dx%d\n", __func__, on,
895*4882a593Smuzhiyun bf3925->frame_size->width,
896*4882a593Smuzhiyun bf3925->frame_size->height);
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun mutex_lock(&bf3925->lock);
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun on = !!on;
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun if (bf3925->streaming == on)
903*4882a593Smuzhiyun goto unlock;
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun if (!on) {
906*4882a593Smuzhiyun /* Stop Streaming Sequence */
907*4882a593Smuzhiyun bf3925_set_streaming(bf3925, 0x02);
908*4882a593Smuzhiyun bf3925->streaming = on;
909*4882a593Smuzhiyun goto unlock;
910*4882a593Smuzhiyun }
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun ret = bf3925_write_array(client, bf3925->frame_size->regs);
913*4882a593Smuzhiyun if (ret)
914*4882a593Smuzhiyun goto unlock;
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun bf3925_set_streaming(bf3925, 0x00);
917*4882a593Smuzhiyun bf3925->streaming = on;
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun unlock:
920*4882a593Smuzhiyun mutex_unlock(&bf3925->lock);
921*4882a593Smuzhiyun return ret;
922*4882a593Smuzhiyun }
923*4882a593Smuzhiyun
bf3925_set_test_pattern(struct bf3925 * bf3925,int value)924*4882a593Smuzhiyun static int bf3925_set_test_pattern(struct bf3925 *bf3925, int value)
925*4882a593Smuzhiyun {
926*4882a593Smuzhiyun return 0;
927*4882a593Smuzhiyun }
928*4882a593Smuzhiyun
bf3925_s_ctrl(struct v4l2_ctrl * ctrl)929*4882a593Smuzhiyun static int bf3925_s_ctrl(struct v4l2_ctrl *ctrl)
930*4882a593Smuzhiyun {
931*4882a593Smuzhiyun struct bf3925 *bf3925 =
932*4882a593Smuzhiyun container_of(ctrl->handler, struct bf3925, ctrls);
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun switch (ctrl->id) {
935*4882a593Smuzhiyun case V4L2_CID_TEST_PATTERN:
936*4882a593Smuzhiyun return bf3925_set_test_pattern(bf3925, ctrl->val);
937*4882a593Smuzhiyun }
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun return 0;
940*4882a593Smuzhiyun }
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun static const struct v4l2_ctrl_ops bf3925_ctrl_ops = {
943*4882a593Smuzhiyun .s_ctrl = bf3925_s_ctrl,
944*4882a593Smuzhiyun };
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun static const char * const bf3925_test_pattern_menu[] = {
947*4882a593Smuzhiyun "Disabled",
948*4882a593Smuzhiyun "Vertical Color Bars",
949*4882a593Smuzhiyun };
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
952*4882a593Smuzhiyun * V4L2 subdev internal operations
953*4882a593Smuzhiyun */
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
bf3925_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)956*4882a593Smuzhiyun static int bf3925_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
957*4882a593Smuzhiyun {
958*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
959*4882a593Smuzhiyun struct v4l2_mbus_framefmt *format =
960*4882a593Smuzhiyun v4l2_subdev_get_try_format(sd, fh->pad, 0);
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun dev_dbg(&client->dev, "%s:\n", __func__);
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun bf3925_get_default_format(format);
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun return 0;
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun #endif
969*4882a593Smuzhiyun
bf3925_g_mbus_config(struct v4l2_subdev * sd,struct v4l2_mbus_config * config)970*4882a593Smuzhiyun static int bf3925_g_mbus_config(struct v4l2_subdev *sd,
971*4882a593Smuzhiyun struct v4l2_mbus_config *config)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun config->type = V4L2_MBUS_PARALLEL;
974*4882a593Smuzhiyun config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
975*4882a593Smuzhiyun V4L2_MBUS_VSYNC_ACTIVE_LOW |
976*4882a593Smuzhiyun V4L2_MBUS_PCLK_SAMPLE_RISING;
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun return 0;
979*4882a593Smuzhiyun }
980*4882a593Smuzhiyun
bf3925_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)981*4882a593Smuzhiyun static int bf3925_g_frame_interval(struct v4l2_subdev *sd,
982*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *fi)
983*4882a593Smuzhiyun {
984*4882a593Smuzhiyun struct bf3925 *bf3925 = to_bf3925(sd);
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun mutex_lock(&bf3925->lock);
987*4882a593Smuzhiyun fi->interval = bf3925->frame_size->max_fps;
988*4882a593Smuzhiyun mutex_unlock(&bf3925->lock);
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun return 0;
991*4882a593Smuzhiyun }
992*4882a593Smuzhiyun
bf3925_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)993*4882a593Smuzhiyun static int bf3925_s_frame_interval(struct v4l2_subdev *sd,
994*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *fi)
995*4882a593Smuzhiyun {
996*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
997*4882a593Smuzhiyun struct bf3925 *bf3925 = to_bf3925(sd);
998*4882a593Smuzhiyun const struct bf3925_framesize *size = NULL;
999*4882a593Smuzhiyun struct v4l2_mbus_framefmt mf;
1000*4882a593Smuzhiyun unsigned int fps;
1001*4882a593Smuzhiyun int ret = 0;
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun dev_dbg(&client->dev, "Setting %d/%d frame interval\n",
1004*4882a593Smuzhiyun fi->interval.numerator, fi->interval.denominator);
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun mutex_lock(&bf3925->lock);
1007*4882a593Smuzhiyun if (bf3925->format.width == 1600)
1008*4882a593Smuzhiyun goto unlock;
1009*4882a593Smuzhiyun fps = DIV_ROUND_CLOSEST(fi->interval.denominator,
1010*4882a593Smuzhiyun fi->interval.numerator);
1011*4882a593Smuzhiyun mf = bf3925->format;
1012*4882a593Smuzhiyun __bf3925_try_frame_size_fps(&mf, &size, fps);
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun if (bf3925->frame_size != size) {
1015*4882a593Smuzhiyun dev_info(&client->dev, "%s match wxh@FPS is %dx%d@%d\n",
1016*4882a593Smuzhiyun __func__, size->width, size->height,
1017*4882a593Smuzhiyun DIV_ROUND_CLOSEST(size->max_fps.denominator,
1018*4882a593Smuzhiyun size->max_fps.numerator));
1019*4882a593Smuzhiyun ret = bf3925_write_array(client, size->regs);
1020*4882a593Smuzhiyun if (ret)
1021*4882a593Smuzhiyun goto unlock;
1022*4882a593Smuzhiyun bf3925->frame_size = size;
1023*4882a593Smuzhiyun bf3925->fps = fps;
1024*4882a593Smuzhiyun }
1025*4882a593Smuzhiyun unlock:
1026*4882a593Smuzhiyun mutex_unlock(&bf3925->lock);
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun return ret;
1029*4882a593Smuzhiyun }
1030*4882a593Smuzhiyun
bf3925_get_module_inf(struct bf3925 * bf3925,struct rkmodule_inf * inf)1031*4882a593Smuzhiyun static void bf3925_get_module_inf(struct bf3925 *bf3925,
1032*4882a593Smuzhiyun struct rkmodule_inf *inf)
1033*4882a593Smuzhiyun {
1034*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
1035*4882a593Smuzhiyun strlcpy(inf->base.sensor, DRIVER_NAME, sizeof(inf->base.sensor));
1036*4882a593Smuzhiyun strlcpy(inf->base.module, bf3925->module_name,
1037*4882a593Smuzhiyun sizeof(inf->base.module));
1038*4882a593Smuzhiyun strlcpy(inf->base.lens, bf3925->len_name, sizeof(inf->base.lens));
1039*4882a593Smuzhiyun }
1040*4882a593Smuzhiyun
bf3925_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1041*4882a593Smuzhiyun static long bf3925_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1042*4882a593Smuzhiyun {
1043*4882a593Smuzhiyun struct bf3925 *bf3925 = to_bf3925(sd);
1044*4882a593Smuzhiyun long ret = 0;
1045*4882a593Smuzhiyun u32 stream = 0;
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun switch (cmd) {
1048*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
1049*4882a593Smuzhiyun bf3925_get_module_inf(bf3925, (struct rkmodule_inf *)arg);
1050*4882a593Smuzhiyun break;
1051*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
1052*4882a593Smuzhiyun stream = *((u32 *)arg);
1053*4882a593Smuzhiyun if (stream)
1054*4882a593Smuzhiyun bf3925_set_streaming(bf3925, 0x00);
1055*4882a593Smuzhiyun else
1056*4882a593Smuzhiyun bf3925_set_streaming(bf3925, 0x02);
1057*4882a593Smuzhiyun break;
1058*4882a593Smuzhiyun default:
1059*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
1060*4882a593Smuzhiyun break;
1061*4882a593Smuzhiyun }
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun return ret;
1064*4882a593Smuzhiyun }
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
bf3925_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1067*4882a593Smuzhiyun static long bf3925_compat_ioctl32(struct v4l2_subdev *sd,
1068*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
1069*4882a593Smuzhiyun {
1070*4882a593Smuzhiyun void __user *up = compat_ptr(arg);
1071*4882a593Smuzhiyun struct rkmodule_inf *inf;
1072*4882a593Smuzhiyun struct rkmodule_awb_cfg *cfg;
1073*4882a593Smuzhiyun long ret;
1074*4882a593Smuzhiyun u32 stream = 0;
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun switch (cmd) {
1077*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
1078*4882a593Smuzhiyun inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1079*4882a593Smuzhiyun if (!inf) {
1080*4882a593Smuzhiyun ret = -ENOMEM;
1081*4882a593Smuzhiyun return ret;
1082*4882a593Smuzhiyun }
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun ret = bf3925_ioctl(sd, cmd, inf);
1085*4882a593Smuzhiyun if (!ret)
1086*4882a593Smuzhiyun ret = copy_to_user(up, inf, sizeof(*inf));
1087*4882a593Smuzhiyun kfree(inf);
1088*4882a593Smuzhiyun break;
1089*4882a593Smuzhiyun case RKMODULE_AWB_CFG:
1090*4882a593Smuzhiyun cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1091*4882a593Smuzhiyun if (!cfg) {
1092*4882a593Smuzhiyun ret = -ENOMEM;
1093*4882a593Smuzhiyun return ret;
1094*4882a593Smuzhiyun }
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun ret = copy_from_user(cfg, up, sizeof(*cfg));
1097*4882a593Smuzhiyun if (!ret)
1098*4882a593Smuzhiyun ret = bf3925_ioctl(sd, cmd, cfg);
1099*4882a593Smuzhiyun kfree(cfg);
1100*4882a593Smuzhiyun break;
1101*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
1102*4882a593Smuzhiyun ret = copy_from_user(&stream, up, sizeof(u32));
1103*4882a593Smuzhiyun if (!ret)
1104*4882a593Smuzhiyun ret = bf3925_ioctl(sd, cmd, &stream);
1105*4882a593Smuzhiyun break;
1106*4882a593Smuzhiyun default:
1107*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
1108*4882a593Smuzhiyun break;
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun return ret;
1112*4882a593Smuzhiyun }
1113*4882a593Smuzhiyun #endif
1114*4882a593Smuzhiyun
bf3925_init(struct v4l2_subdev * sd,u32 val)1115*4882a593Smuzhiyun static int bf3925_init(struct v4l2_subdev *sd, u32 val)
1116*4882a593Smuzhiyun {
1117*4882a593Smuzhiyun int ret;
1118*4882a593Smuzhiyun struct bf3925 *bf3925 = to_bf3925(sd);
1119*4882a593Smuzhiyun struct i2c_client *client = bf3925->client;
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun dev_info(&client->dev, "%s(%d)\n", __func__, __LINE__);
1122*4882a593Smuzhiyun /* soft reset */
1123*4882a593Smuzhiyun ret = bf3925_write(client, 0xf2, 0x03);
1124*4882a593Smuzhiyun ret = bf3925_write_array(client, bf3925_init_regs);
1125*4882a593Smuzhiyun return ret;
1126*4882a593Smuzhiyun }
1127*4882a593Smuzhiyun
bf3925_power(struct v4l2_subdev * sd,int on)1128*4882a593Smuzhiyun static int bf3925_power(struct v4l2_subdev *sd, int on)
1129*4882a593Smuzhiyun {
1130*4882a593Smuzhiyun int ret;
1131*4882a593Smuzhiyun struct bf3925 *bf3925 = to_bf3925(sd);
1132*4882a593Smuzhiyun struct i2c_client *client = bf3925->client;
1133*4882a593Smuzhiyun struct device *dev = &bf3925->client->dev;
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
1136*4882a593Smuzhiyun if (on) {
1137*4882a593Smuzhiyun if (!IS_ERR(bf3925->pwdn_gpio)) {
1138*4882a593Smuzhiyun gpiod_set_value_cansleep(bf3925->pwdn_gpio, 0);
1139*4882a593Smuzhiyun usleep_range(2000, 5000);
1140*4882a593Smuzhiyun }
1141*4882a593Smuzhiyun ret = bf3925_init(sd, 0);
1142*4882a593Smuzhiyun usleep_range(10000, 20000);
1143*4882a593Smuzhiyun if (ret)
1144*4882a593Smuzhiyun dev_err(dev, "init error\n");
1145*4882a593Smuzhiyun } else {
1146*4882a593Smuzhiyun if (!IS_ERR(bf3925->pwdn_gpio)) {
1147*4882a593Smuzhiyun gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
1148*4882a593Smuzhiyun usleep_range(2000, 5000);
1149*4882a593Smuzhiyun }
1150*4882a593Smuzhiyun }
1151*4882a593Smuzhiyun return 0;
1152*4882a593Smuzhiyun }
1153*4882a593Smuzhiyun
bf3925_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1154*4882a593Smuzhiyun static int bf3925_enum_frame_interval(struct v4l2_subdev *sd,
1155*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
1156*4882a593Smuzhiyun struct v4l2_subdev_frame_interval_enum *fie)
1157*4882a593Smuzhiyun {
1158*4882a593Smuzhiyun if (fie->index >= ARRAY_SIZE(bf3925_framesizes))
1159*4882a593Smuzhiyun return -EINVAL;
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8)
1162*4882a593Smuzhiyun return -EINVAL;
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun fie->width = bf3925_framesizes[fie->index].width;
1165*4882a593Smuzhiyun fie->height = bf3925_framesizes[fie->index].height;
1166*4882a593Smuzhiyun fie->interval = bf3925_framesizes[fie->index].max_fps;
1167*4882a593Smuzhiyun return 0;
1168*4882a593Smuzhiyun }
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops bf3925_subdev_core_ops = {
1171*4882a593Smuzhiyun .log_status = v4l2_ctrl_subdev_log_status,
1172*4882a593Smuzhiyun .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1173*4882a593Smuzhiyun .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1174*4882a593Smuzhiyun .ioctl = bf3925_ioctl,
1175*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1176*4882a593Smuzhiyun .compat_ioctl32 = bf3925_compat_ioctl32,
1177*4882a593Smuzhiyun #endif
1178*4882a593Smuzhiyun .s_power = bf3925_power,
1179*4882a593Smuzhiyun };
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops bf3925_subdev_video_ops = {
1182*4882a593Smuzhiyun .s_stream = bf3925_s_stream,
1183*4882a593Smuzhiyun .g_mbus_config = bf3925_g_mbus_config,
1184*4882a593Smuzhiyun .g_frame_interval = bf3925_g_frame_interval,
1185*4882a593Smuzhiyun .s_frame_interval = bf3925_s_frame_interval,
1186*4882a593Smuzhiyun };
1187*4882a593Smuzhiyun
1188*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops bf3925_subdev_pad_ops = {
1189*4882a593Smuzhiyun .enum_mbus_code = bf3925_enum_mbus_code,
1190*4882a593Smuzhiyun .enum_frame_size = bf3925_enum_frame_sizes,
1191*4882a593Smuzhiyun .enum_frame_interval = bf3925_enum_frame_interval,
1192*4882a593Smuzhiyun .get_fmt = bf3925_get_fmt,
1193*4882a593Smuzhiyun .set_fmt = bf3925_set_fmt,
1194*4882a593Smuzhiyun };
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1197*4882a593Smuzhiyun static const struct v4l2_subdev_ops bf3925_subdev_ops = {
1198*4882a593Smuzhiyun .core = &bf3925_subdev_core_ops,
1199*4882a593Smuzhiyun .video = &bf3925_subdev_video_ops,
1200*4882a593Smuzhiyun .pad = &bf3925_subdev_pad_ops,
1201*4882a593Smuzhiyun };
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops bf3925_subdev_internal_ops = {
1204*4882a593Smuzhiyun .open = bf3925_open,
1205*4882a593Smuzhiyun };
1206*4882a593Smuzhiyun #endif
1207*4882a593Smuzhiyun
bf3925_detect(struct bf3925 * bf3925)1208*4882a593Smuzhiyun static int bf3925_detect(struct bf3925 *bf3925)
1209*4882a593Smuzhiyun {
1210*4882a593Smuzhiyun struct i2c_client *client = bf3925->client;
1211*4882a593Smuzhiyun u8 pid, ver;
1212*4882a593Smuzhiyun int ret;
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun dev_dbg(&client->dev, "%s:\n", __func__);
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun /* Check sensor revision */
1217*4882a593Smuzhiyun ret = bf3925_read(client, REG_SC_CHIP_ID_H, &pid);
1218*4882a593Smuzhiyun if (!ret)
1219*4882a593Smuzhiyun ret = bf3925_read(client, REG_SC_CHIP_ID_L, &ver);
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun if (!ret) {
1222*4882a593Smuzhiyun unsigned short id;
1223*4882a593Smuzhiyun
1224*4882a593Smuzhiyun id = SENSOR_ID(pid, ver);
1225*4882a593Smuzhiyun if (id != BF3925_ID) {
1226*4882a593Smuzhiyun ret = -1;
1227*4882a593Smuzhiyun dev_err(&client->dev,
1228*4882a593Smuzhiyun "Sensor detection failed (%04X, %d)\n",
1229*4882a593Smuzhiyun id, ret);
1230*4882a593Smuzhiyun } else {
1231*4882a593Smuzhiyun dev_info(&client->dev, "Found BF%04X sensor\n", id);
1232*4882a593Smuzhiyun if (!IS_ERR(bf3925->pwdn_gpio))
1233*4882a593Smuzhiyun gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
1234*4882a593Smuzhiyun }
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun return ret;
1238*4882a593Smuzhiyun }
1239*4882a593Smuzhiyun
__bf3925_power_on(struct bf3925 * bf3925)1240*4882a593Smuzhiyun static int __bf3925_power_on(struct bf3925 *bf3925)
1241*4882a593Smuzhiyun {
1242*4882a593Smuzhiyun int ret;
1243*4882a593Smuzhiyun struct device *dev = &bf3925->client->dev;
1244*4882a593Smuzhiyun
1245*4882a593Smuzhiyun dev_info(dev, "power on!!!\n");
1246*4882a593Smuzhiyun if (!IS_ERR(bf3925->xvclk)) {
1247*4882a593Smuzhiyun ret = clk_set_rate(bf3925->xvclk, 24000000);
1248*4882a593Smuzhiyun if (ret < 0)
1249*4882a593Smuzhiyun dev_info(dev, "Failed to set xvclk rate (24MHz)\n");
1250*4882a593Smuzhiyun }
1251*4882a593Smuzhiyun if (!IS_ERR(bf3925->xvclk)) {
1252*4882a593Smuzhiyun ret = clk_prepare_enable(bf3925->xvclk);
1253*4882a593Smuzhiyun if (ret < 0)
1254*4882a593Smuzhiyun dev_info(dev, "Failed to enable xvclk\n");
1255*4882a593Smuzhiyun }
1256*4882a593Smuzhiyun usleep_range(7000, 10000);
1257*4882a593Smuzhiyun
1258*4882a593Smuzhiyun if (!IS_ERR(bf3925->pwdn_gpio)) {
1259*4882a593Smuzhiyun gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
1260*4882a593Smuzhiyun usleep_range(2000, 5000);
1261*4882a593Smuzhiyun }
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun if (!IS_ERR(bf3925->supplies)) {
1264*4882a593Smuzhiyun ret = regulator_bulk_enable(BF3925_NUM_SUPPLIES,
1265*4882a593Smuzhiyun bf3925->supplies);
1266*4882a593Smuzhiyun if (ret < 0)
1267*4882a593Smuzhiyun dev_info(dev, "Failed to enable regulators\n");
1268*4882a593Smuzhiyun
1269*4882a593Smuzhiyun usleep_range(20000, 50000);
1270*4882a593Smuzhiyun }
1271*4882a593Smuzhiyun
1272*4882a593Smuzhiyun if (!IS_ERR(bf3925->pwdn2_gpio)) {
1273*4882a593Smuzhiyun gpiod_set_value_cansleep(bf3925->pwdn2_gpio, 1);
1274*4882a593Smuzhiyun usleep_range(2000, 5000);
1275*4882a593Smuzhiyun }
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun if (!IS_ERR(bf3925->pwdn_gpio)) {
1278*4882a593Smuzhiyun gpiod_set_value_cansleep(bf3925->pwdn_gpio, 0);
1279*4882a593Smuzhiyun usleep_range(2000, 5000);
1280*4882a593Smuzhiyun }
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun return 0;
1283*4882a593Smuzhiyun }
1284*4882a593Smuzhiyun
__bf3925_power_off(struct bf3925 * bf3925)1285*4882a593Smuzhiyun static void __bf3925_power_off(struct bf3925 *bf3925)
1286*4882a593Smuzhiyun {
1287*4882a593Smuzhiyun if (!IS_ERR(bf3925->xvclk))
1288*4882a593Smuzhiyun clk_disable_unprepare(bf3925->xvclk);
1289*4882a593Smuzhiyun if (!IS_ERR(bf3925->supplies))
1290*4882a593Smuzhiyun regulator_bulk_disable(BF3925_NUM_SUPPLIES, bf3925->supplies);
1291*4882a593Smuzhiyun if (!IS_ERR(bf3925->pwdn_gpio))
1292*4882a593Smuzhiyun gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
1293*4882a593Smuzhiyun }
1294*4882a593Smuzhiyun
bf3925_configure_regulators(struct bf3925 * bf3925)1295*4882a593Smuzhiyun static int bf3925_configure_regulators(struct bf3925 *bf3925)
1296*4882a593Smuzhiyun {
1297*4882a593Smuzhiyun unsigned int i;
1298*4882a593Smuzhiyun
1299*4882a593Smuzhiyun for (i = 0; i < BF3925_NUM_SUPPLIES; i++)
1300*4882a593Smuzhiyun bf3925->supplies[i].supply = bf3925_supply_names[i];
1301*4882a593Smuzhiyun
1302*4882a593Smuzhiyun return devm_regulator_bulk_get(&bf3925->client->dev,
1303*4882a593Smuzhiyun BF3925_NUM_SUPPLIES,
1304*4882a593Smuzhiyun bf3925->supplies);
1305*4882a593Smuzhiyun }
1306*4882a593Smuzhiyun
bf3925_parse_of(struct bf3925 * bf3925)1307*4882a593Smuzhiyun static int bf3925_parse_of(struct bf3925 *bf3925)
1308*4882a593Smuzhiyun {
1309*4882a593Smuzhiyun struct device *dev = &bf3925->client->dev;
1310*4882a593Smuzhiyun struct device_node *node = dev->of_node;
1311*4882a593Smuzhiyun struct gpio_desc *pwdn_gpio;
1312*4882a593Smuzhiyun unsigned int pwdn = -1;
1313*4882a593Smuzhiyun enum of_gpio_flags flags;
1314*4882a593Smuzhiyun int ret;
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun bf3925->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1317*4882a593Smuzhiyun if (IS_ERR(bf3925->pwdn_gpio)) {
1318*4882a593Smuzhiyun dev_info(dev, "Failed to get pwdn-gpios, maybe no use\n");
1319*4882a593Smuzhiyun pwdn = of_get_named_gpio_flags(node, "pwdn-gpios", 0, &flags);
1320*4882a593Smuzhiyun pwdn_gpio = gpio_to_desc(pwdn);
1321*4882a593Smuzhiyun if (IS_ERR(pwdn_gpio))
1322*4882a593Smuzhiyun dev_info(dev, "Failed to get pwdn-gpios again\n");
1323*4882a593Smuzhiyun else
1324*4882a593Smuzhiyun bf3925->pwdn_gpio = pwdn_gpio;
1325*4882a593Smuzhiyun }
1326*4882a593Smuzhiyun
1327*4882a593Smuzhiyun bf3925->pwdn2_gpio = devm_gpiod_get(dev, "pwdn2", GPIOD_OUT_LOW);
1328*4882a593Smuzhiyun if (IS_ERR(bf3925->pwdn2_gpio)) {
1329*4882a593Smuzhiyun dev_info(dev, "Failed to get pwdn2-gpios, maybe no use\n");
1330*4882a593Smuzhiyun pwdn = of_get_named_gpio_flags(node, "pwdn2-gpios", 0, &flags);
1331*4882a593Smuzhiyun pwdn_gpio = gpio_to_desc(pwdn);
1332*4882a593Smuzhiyun if (IS_ERR(pwdn_gpio))
1333*4882a593Smuzhiyun dev_info(dev, "Failed to get pwdn2-gpios again\n");
1334*4882a593Smuzhiyun else
1335*4882a593Smuzhiyun bf3925->pwdn2_gpio = pwdn_gpio;
1336*4882a593Smuzhiyun }
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun ret = bf3925_configure_regulators(bf3925);
1339*4882a593Smuzhiyun if (ret)
1340*4882a593Smuzhiyun dev_info(dev, "Failed to get power regulators\n");
1341*4882a593Smuzhiyun
1342*4882a593Smuzhiyun return __bf3925_power_on(bf3925);
1343*4882a593Smuzhiyun }
1344*4882a593Smuzhiyun
bf3925_probe(struct i2c_client * client,const struct i2c_device_id * id)1345*4882a593Smuzhiyun static int bf3925_probe(struct i2c_client *client,
1346*4882a593Smuzhiyun const struct i2c_device_id *id)
1347*4882a593Smuzhiyun {
1348*4882a593Smuzhiyun struct device *dev = &client->dev;
1349*4882a593Smuzhiyun struct device_node *node = dev->of_node;
1350*4882a593Smuzhiyun struct v4l2_subdev *sd;
1351*4882a593Smuzhiyun struct bf3925 *bf3925;
1352*4882a593Smuzhiyun char facing[2] = "b";
1353*4882a593Smuzhiyun int ret;
1354*4882a593Smuzhiyun
1355*4882a593Smuzhiyun dev_info(dev, "driver version: %02x.%02x.%02x",
1356*4882a593Smuzhiyun DRIVER_VERSION >> 16,
1357*4882a593Smuzhiyun (DRIVER_VERSION & 0xff00) >> 8,
1358*4882a593Smuzhiyun DRIVER_VERSION & 0x00ff);
1359*4882a593Smuzhiyun
1360*4882a593Smuzhiyun bf3925 = devm_kzalloc(&client->dev, sizeof(*bf3925), GFP_KERNEL);
1361*4882a593Smuzhiyun if (!bf3925)
1362*4882a593Smuzhiyun return -ENOMEM;
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1365*4882a593Smuzhiyun &bf3925->module_index);
1366*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1367*4882a593Smuzhiyun &bf3925->module_facing);
1368*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1369*4882a593Smuzhiyun &bf3925->module_name);
1370*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1371*4882a593Smuzhiyun &bf3925->len_name);
1372*4882a593Smuzhiyun if (ret) {
1373*4882a593Smuzhiyun dev_err(&client->dev, "could not get module information!\n");
1374*4882a593Smuzhiyun return -EINVAL;
1375*4882a593Smuzhiyun }
1376*4882a593Smuzhiyun
1377*4882a593Smuzhiyun bf3925->client = client;
1378*4882a593Smuzhiyun bf3925->xvclk = devm_clk_get(&client->dev, "xvclk");
1379*4882a593Smuzhiyun if (IS_ERR(bf3925->xvclk)) {
1380*4882a593Smuzhiyun dev_err(&client->dev, "Failed to get xvclk\n");
1381*4882a593Smuzhiyun return -EINVAL;
1382*4882a593Smuzhiyun }
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun bf3925_parse_of(bf3925);
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun bf3925->xvclk_frequency = clk_get_rate(bf3925->xvclk);
1387*4882a593Smuzhiyun if (bf3925->xvclk_frequency < 6000000 ||
1388*4882a593Smuzhiyun bf3925->xvclk_frequency > 27000000)
1389*4882a593Smuzhiyun return -EINVAL;
1390*4882a593Smuzhiyun
1391*4882a593Smuzhiyun v4l2_ctrl_handler_init(&bf3925->ctrls, 2);
1392*4882a593Smuzhiyun bf3925->link_frequency =
1393*4882a593Smuzhiyun v4l2_ctrl_new_std(&bf3925->ctrls, &bf3925_ctrl_ops,
1394*4882a593Smuzhiyun V4L2_CID_PIXEL_RATE, 0,
1395*4882a593Smuzhiyun BF3925_PIXEL_RATE, 1,
1396*4882a593Smuzhiyun BF3925_PIXEL_RATE);
1397*4882a593Smuzhiyun
1398*4882a593Smuzhiyun v4l2_ctrl_new_std_menu_items(&bf3925->ctrls, &bf3925_ctrl_ops,
1399*4882a593Smuzhiyun V4L2_CID_TEST_PATTERN,
1400*4882a593Smuzhiyun ARRAY_SIZE(bf3925_test_pattern_menu) - 1,
1401*4882a593Smuzhiyun 0, 0, bf3925_test_pattern_menu);
1402*4882a593Smuzhiyun bf3925->sd.ctrl_handler = &bf3925->ctrls;
1403*4882a593Smuzhiyun
1404*4882a593Smuzhiyun if (bf3925->ctrls.error) {
1405*4882a593Smuzhiyun dev_err(&client->dev, "%s: control initialization error %d\n",
1406*4882a593Smuzhiyun __func__, bf3925->ctrls.error);
1407*4882a593Smuzhiyun return bf3925->ctrls.error;
1408*4882a593Smuzhiyun }
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun sd = &bf3925->sd;
1411*4882a593Smuzhiyun client->flags |= I2C_CLIENT_SCCB;
1412*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1413*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &bf3925_subdev_ops);
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun sd->internal_ops = &bf3925_subdev_internal_ops;
1416*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1417*4882a593Smuzhiyun V4L2_SUBDEV_FL_HAS_EVENTS;
1418*4882a593Smuzhiyun #endif
1419*4882a593Smuzhiyun
1420*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1421*4882a593Smuzhiyun bf3925->pad.flags = MEDIA_PAD_FL_SOURCE;
1422*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1423*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, 1, &bf3925->pad);
1424*4882a593Smuzhiyun if (ret < 0) {
1425*4882a593Smuzhiyun v4l2_ctrl_handler_free(&bf3925->ctrls);
1426*4882a593Smuzhiyun return ret;
1427*4882a593Smuzhiyun }
1428*4882a593Smuzhiyun #endif
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun mutex_init(&bf3925->lock);
1431*4882a593Smuzhiyun
1432*4882a593Smuzhiyun bf3925_get_default_format(&bf3925->format);
1433*4882a593Smuzhiyun bf3925->frame_size = &bf3925_framesizes[0];
1434*4882a593Smuzhiyun bf3925->format.width = bf3925_framesizes[0].width;
1435*4882a593Smuzhiyun bf3925->format.height = bf3925_framesizes[0].height;
1436*4882a593Smuzhiyun bf3925->fps = DIV_ROUND_CLOSEST(bf3925_framesizes[0].max_fps.denominator,
1437*4882a593Smuzhiyun bf3925_framesizes[0].max_fps.numerator);
1438*4882a593Smuzhiyun
1439*4882a593Smuzhiyun ret = bf3925_detect(bf3925);
1440*4882a593Smuzhiyun if (ret < 0)
1441*4882a593Smuzhiyun goto error;
1442*4882a593Smuzhiyun
1443*4882a593Smuzhiyun memset(facing, 0, sizeof(facing));
1444*4882a593Smuzhiyun if (strcmp(bf3925->module_facing, "back") == 0)
1445*4882a593Smuzhiyun facing[0] = 'b';
1446*4882a593Smuzhiyun else
1447*4882a593Smuzhiyun facing[0] = 'f';
1448*4882a593Smuzhiyun
1449*4882a593Smuzhiyun snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1450*4882a593Smuzhiyun bf3925->module_index, facing,
1451*4882a593Smuzhiyun DRIVER_NAME, dev_name(sd->dev));
1452*4882a593Smuzhiyun ret = v4l2_async_register_subdev_sensor_common(&bf3925->sd);
1453*4882a593Smuzhiyun if (ret)
1454*4882a593Smuzhiyun goto error;
1455*4882a593Smuzhiyun
1456*4882a593Smuzhiyun dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
1457*4882a593Smuzhiyun
1458*4882a593Smuzhiyun return 0;
1459*4882a593Smuzhiyun
1460*4882a593Smuzhiyun error:
1461*4882a593Smuzhiyun v4l2_ctrl_handler_free(&bf3925->ctrls);
1462*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1463*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1464*4882a593Smuzhiyun #endif
1465*4882a593Smuzhiyun mutex_destroy(&bf3925->lock);
1466*4882a593Smuzhiyun __bf3925_power_off(bf3925);
1467*4882a593Smuzhiyun return ret;
1468*4882a593Smuzhiyun }
1469*4882a593Smuzhiyun
bf3925_remove(struct i2c_client * client)1470*4882a593Smuzhiyun static int bf3925_remove(struct i2c_client *client)
1471*4882a593Smuzhiyun {
1472*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1473*4882a593Smuzhiyun struct bf3925 *bf3925 = to_bf3925(sd);
1474*4882a593Smuzhiyun
1475*4882a593Smuzhiyun v4l2_ctrl_handler_free(&bf3925->ctrls);
1476*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
1477*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1478*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1479*4882a593Smuzhiyun #endif
1480*4882a593Smuzhiyun mutex_destroy(&bf3925->lock);
1481*4882a593Smuzhiyun
1482*4882a593Smuzhiyun __bf3925_power_off(bf3925);
1483*4882a593Smuzhiyun
1484*4882a593Smuzhiyun return 0;
1485*4882a593Smuzhiyun }
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun static const struct i2c_device_id bf3925_id[] = {
1488*4882a593Smuzhiyun { "bf3925", 0 },
1489*4882a593Smuzhiyun { /* sentinel */ },
1490*4882a593Smuzhiyun };
1491*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, bf3925_id);
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1494*4882a593Smuzhiyun static const struct of_device_id bf3925_of_match[] = {
1495*4882a593Smuzhiyun { .compatible = "byd,bf3925", },
1496*4882a593Smuzhiyun { /* sentinel */ },
1497*4882a593Smuzhiyun };
1498*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, bf3925_of_match);
1499*4882a593Smuzhiyun #endif
1500*4882a593Smuzhiyun
1501*4882a593Smuzhiyun static struct i2c_driver bf3925_i2c_driver = {
1502*4882a593Smuzhiyun .driver = {
1503*4882a593Smuzhiyun .name = DRIVER_NAME,
1504*4882a593Smuzhiyun .of_match_table = of_match_ptr(bf3925_of_match),
1505*4882a593Smuzhiyun },
1506*4882a593Smuzhiyun .probe = bf3925_probe,
1507*4882a593Smuzhiyun .remove = bf3925_remove,
1508*4882a593Smuzhiyun .id_table = bf3925_id,
1509*4882a593Smuzhiyun };
1510*4882a593Smuzhiyun
sensor_mod_init(void)1511*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1512*4882a593Smuzhiyun {
1513*4882a593Smuzhiyun return i2c_add_driver(&bf3925_i2c_driver);
1514*4882a593Smuzhiyun }
1515*4882a593Smuzhiyun
sensor_mod_exit(void)1516*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1517*4882a593Smuzhiyun {
1518*4882a593Smuzhiyun i2c_del_driver(&bf3925_i2c_driver);
1519*4882a593Smuzhiyun }
1520*4882a593Smuzhiyun
1521*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1522*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1523*4882a593Smuzhiyun
1524*4882a593Smuzhiyun MODULE_AUTHOR("Benoit Parrot <bparrot@ti.com>");
1525*4882a593Smuzhiyun MODULE_DESCRIPTION("BF3925 CMOS Image Sensor driver");
1526*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1527