1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * BF3925 CMOS Image Sensor driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 * V0.0X01.0X01 add enum_frame_interval function.
7 * V0.0X01.0X02 add quick stream on/off
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/i2c.h>
18 #include <linux/kernel.h>
19 #include <linux/media.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_graph.h>
23 #include <linux/of_gpio.h>
24
25 #include <linux/regulator/consumer.h>
26 #include <linux/slab.h>
27 #include <linux/uaccess.h>
28 #include <linux/videodev2.h>
29 #include <linux/rk-camera-module.h>
30 #include <linux/version.h>
31 #include <media/media-entity.h>
32 #include <media/v4l2-common.h>
33 #include <media/v4l2-ctrls.h>
34 #include <media/v4l2-device.h>
35 #include <media/v4l2-event.h>
36 #include <media/v4l2-fwnode.h>
37 #include <media/v4l2-image-sizes.h>
38 #include <media/v4l2-mediabus.h>
39 #include <media/v4l2-subdev.h>
40
41 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x2)
42 #define DRIVER_NAME "bf3925"
43 #define BF3925_PIXEL_RATE (120 * 1000 * 1000)
44
45 /*
46 * BF3925 register definitions
47 */
48 #define REG_SOFTWARE_STANDBY 0xf2
49
50 #define REG_SC_CHIP_ID_H 0xfc
51 #define REG_SC_CHIP_ID_L 0xfd
52
53 #define REG_NULL 0xFFFF /* Array end token */
54
55 #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
56 #define BF3925_ID 0x3925
57
58 struct sensor_register {
59 u16 addr;
60 u8 value;
61 };
62
63 struct bf3925_framesize {
64 u16 width;
65 u16 height;
66 struct v4l2_fract max_fps;
67 u16 max_exp_lines;
68 const struct sensor_register *regs;
69 };
70
71 struct bf3925_pll_ctrl {
72 u8 ctrl1;
73 u8 ctrl2;
74 u8 ctrl3;
75 };
76
77 struct bf3925_pixfmt {
78 u32 code;
79 /* Output format Register Value (REG_FORMAT_CTRL00) */
80 struct sensor_register *format_ctrl_regs;
81 };
82
83 struct pll_ctrl_reg {
84 unsigned int div;
85 unsigned char reg;
86 };
87
88 static const char * const bf3925_supply_names[] = {
89 "dovdd", /* Digital I/O power */
90 "avdd", /* Analog power */
91 "dvdd", /* Digital core power */
92 };
93
94 #define BF3925_NUM_SUPPLIES ARRAY_SIZE(bf3925_supply_names)
95
96 struct bf3925 {
97 struct v4l2_subdev sd;
98 struct media_pad pad;
99 struct v4l2_mbus_framefmt format;
100 unsigned int fps;
101 unsigned int xvclk_frequency;
102 struct clk *xvclk;
103 struct gpio_desc *power_gpio;
104 struct gpio_desc *reset_gpio;
105 struct gpio_desc *pwdn_gpio;
106 struct gpio_desc *pwdn2_gpio;
107 struct regulator_bulk_data supplies[BF3925_NUM_SUPPLIES];
108 struct mutex lock;
109 struct i2c_client *client;
110 struct v4l2_ctrl_handler ctrls;
111 struct v4l2_ctrl *link_frequency;
112 const struct bf3925_framesize *frame_size;
113 int streaming;
114 u32 module_index;
115 const char *module_facing;
116 const char *module_name;
117 const char *len_name;
118 };
119
120 static const struct sensor_register bf3925_init_regs[] = {
121 {0xff, 0x01}, //Bit[0]: select reg page
122 {0xff, 0x01}, //Bit[0]: select reg page
123 {0x50, 0x00}, //bit[4]: digital subsample Data format selection
124 {0x51, 0x02}, //YUV Sequence
125 {0xe0, 0x00},
126 {0xe2, 0x64},
127 {0xe3, 0x48},
128 {0xe4, 0x83}, //Drive capability //0x81 ljx
129 {0xe7, 0x9b},
130
131 //clock, dummy
132 {0xff, 0x01}, //Bit[0]: select reg page
133 {0xe9, 0x2a}, //08 PLL setting
134 {0xff, 0x00}, //Bit[0]: select reg page
135 {0x01, 0x00},
136 {0x02, 0x90}, //Dummy Pixel Insert LSB
137 {0x03, 0x00}, ///02 //yang
138 {0x04, 0x00}, //Dummy line Insert LSB
139 {0xff, 0x01},
140 {0xe5, 0x32},
141 //init black
142 {0xff, 0x00},
143 {0x3d, 0x00},
144 {0x30, 0x61},
145 {0x31, 0x63},
146 {0x32, 0x60},
147 {0x33, 0x63},
148
149 //resolution
150 {0xff, 0x00},
151 {0x05, 0xa2}, ///a0
152 {0x09, 0x90}, ///00
153 {0x0a, 0x48},
154 {0x0b, 0x60},
155 {0x0c, 0x00},
156 {0x0d, 0xb8},
157 {0x0e, 0x40},
158 {0xff, 0x01},
159 {0x52, 0x01}, //Bit[1]: VSYNC option Bit[0]: HSYNC option
160 {0x5d, 0x02},
161 {0x5a, 0x00},
162 {0x5b, 0x00},
163 {0x5c, 0x00},
164 {0xff, 0x01},
165 {0x53, 0x30}, ///60
166 {0x54, 0x20}, ///40
167 {0x55, 0x00},
168 {0x56, 0x20}, ///40
169 {0x57, 0x00},
170 {0x58, 0x58}, ///b0
171 {0xff, 0x01},
172 {0x50, 0x00}, //bit[4]: digital subsample Data format selection
173
174 //initial AWB and AE
175 {0xff, 0x00}, //Bit[0]: select reg page
176 {0xb2, 0x81}, //Manual AWB & AE
177 {0xb0, 0x16},
178 {0xb1, 0x1d},
179 {0xb2, 0x89},
180 {0xff, 0x01},
181 {0x00, 0x00},
182 {0x0e, 0x0a},
183 {0x0f, 0x64},
184 {0x10, 0x28},
185 {0x00, 0x05},
186
187 //black control
188 {0xff, 0x00},
189 {0x3c, 0x97},
190
191 //black sun
192 {0xff, 0x01}, //Bit[0]: select reg page
193 {0xe1, 0xf8}, //28 bit[7:4]: Pixel bias current
194 {0xff, 0x00}, //Bit[0]: select reg page
195 {0x00, 0x47}, //bit[6]: black sun control bit[5:4]: mirror/flip
196 {0x18, 0x0c}, //PRST indoor
197 {0x19, 0x1a}, //PRST outdoor
198
199 //lens shading
200 {0xff, 0x00}, //Bit[0]: select reg page
201 {0x52, 0x13},
202 {0x53, 0x5c},
203 {0x54, 0x24},
204 {0x55, 0x13},
205 {0x56, 0x5c},
206 {0x57, 0x24},
207 {0x58, 0xd3},
208 {0x59, 0x5c},
209 {0x5a, 0x24},
210 {0x5b, 0x44}, ///46 lens shading gain of R
211 {0x5c, 0x3C}, ///43 lens shading gain of G1
212 {0x5d, 0x40}, //lens shading gain of B
213 {0x5e, 0x3C}, /// 43lens shading gain of G0
214
215 #if 0
216 /*gamma default */
217 {0xff, 0x00}, //Bit[0]: select reg page
218 {0x60, 0x30},
219 {0x61, 0x2a},
220 {0x62, 0x24},
221 {0x63, 0x1b},
222 {0x64, 0x18},
223 {0x65, 0x16},
224 {0x66, 0x14},
225 {0x67, 0x12},
226 {0x68, 0x10},
227 {0x69, 0x0e},
228 {0x6a, 0x0d},
229 {0x6b, 0x0c},
230 {0x6c, 0x0a},
231 {0x6d, 0x09},
232 {0x6e, 0x09},
233 #endif
234 {0x6f, 0xf0},
235 {0x70, 0x20},
236 {0x71, 0x60},
237 {0x72, 0x24},///10
238 {0x73, 0x24},///10
239 #if 1
240 //gamma hi-lit,nice over-ex.
241 {0xff, 0x00}, //Bit[0]: select reg page
242 {0x60, 0x33},
243 {0x61, 0x2b},
244 {0x62, 0x27},
245 {0x63, 0x22},
246 {0x64, 0x1b},
247 {0x65, 0x17},
248 {0x66, 0x14},
249 {0x67, 0x11},
250 {0x68, 0x0e},
251 {0x69, 0x0c},
252 {0x6a, 0x0b},
253 {0x6b, 0x0a},
254 {0x6c, 0x09},
255 {0x6d, 0x08},
256 {0x6e, 0x07},
257 #else
258 //gamma nice color
259 {0xff, 0x00}, //Bit[0]: select reg page
260 {0x60, 0x28},
261 {0x61, 0x28},
262 {0x62, 0x26},
263 {0x63, 0x22},
264 {0x64, 0x1f},
265 {0x65, 0x1c},
266 {0x66, 0x18},
267 {0x67, 0x13},
268 {0x68, 0x10},
269 {0x69, 0x0d},
270 {0x6a, 0x0c},
271 {0x6b, 0x0a},
272 {0x6c, 0x08},
273 {0x6d, 0x07},
274 {0x6e, 0x06},
275
276 ///gamma low denoise
277 {0xff, 0x00}, //Bit[0]: select reg page
278 {0x60, 0x24},
279 {0x61, 0x30},
280 {0x62, 0x20},
281 {0x63, 0x1a},
282 {0x64, 0x16},
283 {0x65, 0x13},
284 {0x66, 0x11},
285 {0x67, 0x0e},
286 {0x68, 0x0d},
287 {0x69, 0x0c},
288 {0x6a, 0x0b},
289 {0x6b, 0x09},
290 {0x6c, 0x09},
291 {0x6d, 0x08},
292 {0x6e, 0x07},
293 #endif
294
295 #if 1
296 //clearer
297 //denoise and edge enhancement
298 {0xff, 0x00}, //Bit[0]: select reg page
299 {0x80, 0x0f},
300 {0x81, 0x1e},
301 {0x83, 0x37}, //0x83[7:4]: de_noise threshhole; 0x83[3:0]: de_noise
302 {0x84, 0xe6},
303 {0x85, 0x00},
304 {0x86, 0xfc},
305 {0x87, 0x00},
306 {0x88, 0xa2}, //bit[7:6] 0 is low noise;
307 {0x89, 0xca},
308 {0x8a, 0x44},
309 {0x8b, 0x12},
310 {0x91, 0x48},
311 {0x92, 0x11},
312 {0x93, 0x0c},
313 #else
314 //denoise and edge enhancement
315 {0xff, 0x00}, //Bit[0]: select reg page
316 {0x80, 0x0f},
317 {0x81, 0x0c},
318 {0x83, 0x27}, //0x83[7:4]: de_noise threshhole; 0x83[3:0]: de_noise
319 {0x84, 0xe6},
320 {0x85, 0x88},
321 {0x86, 0xfa},
322 {0x87, 0x1a},
323 {0x88, 0xa2}, //bit[7:6] 0 is low noise;
324 {0x89, 0xca},
325 {0x8b, 0x11}, //12 Bright/Dark edge enhancement
326 {0x91, 0x48}, //45 0x91:40
327 #endif
328
329 //AWB
330 {0xff, 0x00}, //Bit[0]: select reg page
331 {0xa2, 0x06}, //the low limit of blue gain for indoor scene
332 {0xa3, 0x28}, //the upper limit of blue gain for indoor scene
333 {0xa4, 0x0a}, //the low limit of red gain for indoor scene
334 {0xa5, 0x2c}, //the upper limit of red gain for indoor scene
335 {0xa7, 0x1b}, //Base B gain
336 {0xa8, 0x14}, //Base R gain
337 {0xa9, 0x15},
338 {0xaa, 0x18},
339 {0xab, 0x26},
340 {0xac, 0x5c},
341 {0xae, 0x47},
342 {0xb2, 0x89},
343 {0xb3, 0x66}, // green gain
344 {0xb4, 0x03}, //the offset of F light
345 {0xb5, 0x00}, //the offset of non-F light
346 {0xb6, 0xd9}, //bit[7]: outdoor control
347 {0xb8, 0xca},
348 {0xbb, 0x0d},
349 {0xbc, 0x15},
350 {0xbd, 0x09},
351 {0xbe, 0x24},
352 {0xbf, 0x66},
353
354 #if 1
355 // color default
356 {0xff, 0x00}, //Bit[0]: select reg page
357 {0xc0, 0x8a},
358 {0xc1, 0x05},
359 {0xc2, 0x84},
360 {0xc3, 0x86},
361 {0xc4, 0x03},
362 {0xc5, 0x93},
363
364 #else
365 //color Gorgeous
366 {0xff, 0x00}, //Bit[0]: select reg page
367 {0xc0, 0x83},
368 {0xc1, 0x86},
369 {0xc2, 0x82},
370 {0xc3, 0x8a},
371 {0xc4, 0x07},
372 {0xc5, 0x9f},
373
374 //color light
375 {0xff, 0x00}, //Bit[0]: select reg page
376 {0xc0, 0x83},
377 {0xc1, 0x02},
378 {0xc2, 0x84},
379 {0xc3, 0x84},
380 {0xc4, 0x03},
381 {0xc5, 0x8d},
382 #endif
383
384 // A color
385 {0xff, 0x00}, //Bit[0]: select reg page
386 {0xc6, 0x8a},
387 {0xc7, 0x82},
388 {0xc8, 0x8b},
389 {0xc9, 0x87},
390 {0xca, 0x83},
391 {0xcb, 0x91},
392
393 //Outdoor color
394 {0xff, 0x00}, //Bit[0]: select reg page
395 {0xd0, 0x90},
396 {0xd1, 0x05},
397 {0xd2, 0x82},
398 {0xd3, 0x88},
399 {0xd4, 0x03},
400 {0xd5, 0x93},
401 {0xcd, 0x30},
402 {0xd6, 0x61},
403
404 //AE
405 {0xff, 0x01}, //Bit[0]: select reg page
406 {0x00, 0x05},
407 {0x01, 0x8a}, // AE window and weight
408 {0x04, 0x48}, //4f AE Target//40
409 {0x05, 0x48}, //4f Y target value1//48
410 {0x07, 0x92}, //Bit[3:2]: the bigger, Y_AVER_MODIFY is smaller
411 {0x09, 0x8a}, //92 Bit[5:0]: INT_MAX//8c
412 {0x0a, 0xa5},
413 {0x0b, 0x82}, //Bit[5:0]: INT_MIN
414 {0x0c, 0xb4}, //78 50hz banding
415 {0x0d, 0x96}, //64 60hz banding
416 {0x15, 0x02}, //AEC
417 {0x16, 0x8c},
418 {0x17, 0xb5},
419 {0x18, 0x50}, ///30
420 {0x1b, 0x30}, ///33 minimum global gain
421 {0x1c, 0x58}, ///66
422 {0x1d, 0x38}, ///55
423 {0x1e, 0x58}, ///80
424 {0x1f, 0x60}, /// c0 maximum gain//a0
425
426 // saturation
427 {0xff, 0x01}, //Bit[0]: select reg page
428 {0x30, 0xff}, ///e0
429 {0x31, 0x48},
430 {0x32, 0x60}, ///f0
431 {0x34, 0xd8}, ///da Cb Saturation Coefficient low 8 bit for NF light
432 {0x35, 0xc8}, ///ca Cr Saturation Coefficient low 8 bit for NF light
433 {0x36, 0xff}, //Cb Saturation Coefficient low 8 bit for F light
434 {0x37, 0xd0}, //Cr Saturation Coefficient low 8 bit for F light
435
436 //skin
437 {0xff, 0x01}, //Bit[0]: select reg page
438 {0x3b, 0x08},
439
440 // auto contrast
441 {0xff, 0x01}, //Bit[0]: select reg page
442 {0x3e, 0x02}, //
443 {0x3e, 0x82}, //do not change
444 {0x38, 0x40},
445 //yang add start switch to 1600*1200 UXGA
446 //1600*1200
447 //window
448 //yang add end switch to 1600*1200 UXGA
449 {REG_NULL, 0x00},
450 };
451
452 /* Senor full resolution setting */
453 static const struct sensor_register bf3925_full_regs[] = {
454 //1600*1200
455 //window
456 {0xff, 0x00},
457 {0x05, 0xa0},
458 {0x09, 0x00},
459 {0x0a, 0x48},
460 {0x0b, 0x60},
461 {0x0c, 0x00},
462 {0x0d, 0xb8},
463 {0x0e, 0x40},
464 {0xff, 0x01},
465 {0x52, 0x01}, //Bit[1]: VSYNC option Bit[0]: HSYNC option
466 {0x5d, 0x02},
467 {0x5a, 0x00},
468 {0x5b, 0x00},
469 {0x5c, 0x00},
470 {0xff, 0x01},
471 {0x53, 0x60},
472 {0x54, 0x40},
473 {0x55, 0x00},
474 {0x56, 0x40},
475 {0x57, 0x00},
476 {0x58, 0xb0},
477 {0xff, 0x01},
478 {0x50, 0x00},
479
480 //clock, dummy
481 {0xff, 0x01}, //Bit[0]: select reg page
482 {0x09, 0x86},
483 {0xe9, 0x2a}, //08 PLL setting
484 {0xff, 0x00}, //Bit[0]: select reg page
485 {0x01, 0x00},
486 {0x02, 0x00}, //Dummy Pixel Insert LSB
487 {0x03, 0x00}, ///02 //yang
488 {0x04, 0x00}, //Dummy line Insert LSB
489
490 {REG_NULL, 0x00},
491 };
492
493 /* Preview resolution setting*/
494 static const struct sensor_register bf3925_svga_regs_15fps[] = {
495 //800*600
496 //window
497 {0xff, 0x00},
498 {0x05, 0xa0},
499 {0x09, 0x00},
500 {0x0a, 0x48},
501 {0x0b, 0x60},
502 {0x0c, 0x00},
503 {0x0d, 0xb8},
504 {0x0e, 0x40},
505 {0xff, 0x01},
506 {0x52, 0x01}, //Bit[1]: VSYNC option Bit[0]: HSYNC option
507 {0x5d, 0x02},
508 {0x5a, 0x00},
509 {0x5b, 0x00},
510 {0x5c, 0x00},
511 {0xff, 0x01},
512 {0x53, 0x30},
513 {0x54, 0x20},
514 {0x55, 0x02},
515 {0x56, 0x22},
516 {0x57, 0x01},
517 {0x58, 0x59},
518 {0xff, 0x01},
519 {0x50, 0x00},
520
521 //clock, dummy
522 {0xff, 0x01}, //Bit[0]: select reg page
523 {0x09, 0x86},
524 {0xe9, 0x2a}, //08 PLL setting
525 {0xff, 0x00}, //Bit[0]: select reg page
526 {0x01, 0x00},
527 {0x02, 0x00}, //Dummy Pixel Insert LSB
528 {0x03, 0x00}, ///02 //yang
529 {0x04, 0x00}, //Dummy line Insert LSB
530
531 {REG_NULL, 0x00},
532 };
533
534 /* Preview resolution setting*/
535 static const struct sensor_register bf3925_svga_regs_30fps[] = {
536 //800*600
537 {0xff, 0x00},
538 {0x05, 0xa2},
539 {0x09, 0x04},
540
541 {0x0a, 0x4c},
542 {0x0b, 0x60},
543 {0x0c, 0x04},
544 {0x0d, 0xbc},
545 {0x0e, 0x40},
546 {0xff, 0x01},
547 {0x52, 0x01},
548 {0x5d, 0x02},
549 {0x5a, 0x00},
550 {0x5b, 0x00},
551 {0x5c, 0x00},
552 {0xff, 0x01},
553 {0x09, 0x83},
554 {0x53, 0x30},
555 {0x54, 0x20},
556 {0x55, 0x02},
557 {0x56, 0x22},
558 {0x57, 0x01},
559 {0x58, 0x59},
560 {0xff, 0x01},
561 {0x50, 0x00},
562 {0xe9, 0x2a},
563 //clock, dummy
564 {0xff, 0x01}, //Bit[0]: select reg page
565 {0x09, 0x83},
566
567 /* 08 PLL setting 0x09: 1 times
568 * 0x1b: multiply 5/4 0x2b: 3/2 multiply
569 * 0x08:double 0x1a: 5/2 multiply
570 * 0x2a: triple 0x2a ljx 2017-6
571 */
572 {0xe9, 0x08},
573 {0xff, 0x00}, //Bit[0]: select reg page
574 {0x01, 0x00},
575 {0x02, 0xea}, //Dummy Pixel Insert LSB
576 {0x03, 0x00}, ///02 //yang
577 {0x04, 0x00}, //Dummy line Insert LSB
578
579 {REG_NULL, 0x00},
580 };
581
582 static const struct bf3925_framesize bf3925_framesizes[] = {
583 { /* SVGA */
584 .width = 800,
585 .height = 600,
586 .max_fps = {
587 .numerator = 10000,
588 .denominator = 150000,
589 },
590 .regs = bf3925_svga_regs_15fps,
591 }, { /* SVGA */
592 .width = 800,
593 .height = 600,
594 .max_fps = {
595 .numerator = 10000,
596 .denominator = 300000,
597 },
598 .regs = bf3925_svga_regs_30fps,
599 }, { /* FULL */
600 .width = 1600,
601 .height = 1200,
602 .max_fps = {
603 .numerator = 10000,
604 .denominator = 150000,
605 },
606 .regs = bf3925_full_regs,
607 }
608 };
609
610 static const struct bf3925_pixfmt bf3925_formats[] = {
611 {
612 .code = MEDIA_BUS_FMT_UYVY8_2X8,
613 }
614 };
615
to_bf3925(struct v4l2_subdev * sd)616 static inline struct bf3925 *to_bf3925(struct v4l2_subdev *sd)
617 {
618 return container_of(sd, struct bf3925, sd);
619 }
620
621 /* sensor register write */
bf3925_write(struct i2c_client * client,u8 reg,u8 val)622 static int bf3925_write(struct i2c_client *client, u8 reg, u8 val)
623 {
624 struct i2c_msg msg;
625 u8 buf[2];
626 int ret;
627
628 dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
629 buf[0] = reg & 0xFF;
630 buf[1] = val;
631
632 msg.addr = client->addr;
633 msg.flags = client->flags;
634 msg.buf = buf;
635 msg.len = sizeof(buf);
636
637 ret = i2c_transfer(client->adapter, &msg, 1);
638 if (ret >= 0)
639 return 0;
640
641 dev_err(&client->dev,
642 "bf3925 write reg(0x%x val:0x%x) failed !\n", reg, val);
643
644 return ret;
645 }
646
647 /* sensor register read */
bf3925_read(struct i2c_client * client,u8 reg,u8 * val)648 static int bf3925_read(struct i2c_client *client, u8 reg, u8 *val)
649 {
650 struct i2c_msg msg[2];
651 u8 buf[1];
652 int ret;
653
654 buf[0] = reg & 0xFF;
655
656 msg[0].addr = client->addr;
657 msg[0].flags = client->flags;
658 msg[0].buf = buf;
659 msg[0].len = sizeof(buf);
660
661 msg[1].addr = client->addr;
662 msg[1].flags = client->flags | I2C_M_RD;
663 msg[1].buf = buf;
664 msg[1].len = 1;
665
666 ret = i2c_transfer(client->adapter, msg, 2);
667 if (ret >= 0) {
668 *val = buf[0];
669 return 0;
670 }
671
672 dev_err(&client->dev,
673 "bf3925 read reg:0x%x failed !\n", reg);
674
675 return ret;
676 }
677
bf3925_write_array(struct i2c_client * client,const struct sensor_register * regs)678 static int bf3925_write_array(struct i2c_client *client,
679 const struct sensor_register *regs)
680 {
681 int i, ret = 0;
682
683 i = 0;
684 while (regs[i].addr != REG_NULL) {
685 ret = bf3925_write(client, regs[i].addr, regs[i].value);
686 if (ret) {
687 dev_err(&client->dev, "%s failed !\n", __func__);
688 break;
689 }
690
691 i++;
692 }
693
694 return ret;
695 }
696
bf3925_get_default_format(struct v4l2_mbus_framefmt * format)697 static void bf3925_get_default_format(struct v4l2_mbus_framefmt *format)
698 {
699 format->width = bf3925_framesizes[0].width;
700 format->height = bf3925_framesizes[0].height;
701 format->colorspace = V4L2_COLORSPACE_SRGB;
702 format->code = bf3925_formats[0].code;
703 format->field = V4L2_FIELD_NONE;
704 }
705
bf3925_set_streaming(struct bf3925 * bf3925,int on)706 static void bf3925_set_streaming(struct bf3925 *bf3925, int on)
707 {
708 struct i2c_client *client = bf3925->client;
709 int ret;
710
711 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
712
713 ret = bf3925_write(client, REG_SOFTWARE_STANDBY, on);
714 if (ret)
715 dev_err(&client->dev, "bf3925 soft standby failed\n");
716 }
717
718 /*
719 * V4L2 subdev video and pad level operations
720 */
721
bf3925_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)722 static int bf3925_enum_mbus_code(struct v4l2_subdev *sd,
723 struct v4l2_subdev_pad_config *cfg,
724 struct v4l2_subdev_mbus_code_enum *code)
725 {
726 struct i2c_client *client = v4l2_get_subdevdata(sd);
727
728 dev_dbg(&client->dev, "%s:\n", __func__);
729
730 if (code->index >= ARRAY_SIZE(bf3925_formats))
731 return -EINVAL;
732
733 code->code = bf3925_formats[code->index].code;
734
735 return 0;
736 }
737
bf3925_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)738 static int bf3925_enum_frame_sizes(struct v4l2_subdev *sd,
739 struct v4l2_subdev_pad_config *cfg,
740 struct v4l2_subdev_frame_size_enum *fse)
741 {
742 struct i2c_client *client = v4l2_get_subdevdata(sd);
743 int i = ARRAY_SIZE(bf3925_formats);
744
745 dev_dbg(&client->dev, "%s:\n", __func__);
746
747 if (fse->index >= ARRAY_SIZE(bf3925_framesizes))
748 return -EINVAL;
749
750 while (--i)
751 if (fse->code == bf3925_formats[i].code)
752 break;
753
754 fse->code = bf3925_formats[i].code;
755
756 fse->min_width = bf3925_framesizes[fse->index].width;
757 fse->max_width = fse->min_width;
758 fse->max_height = bf3925_framesizes[fse->index].height;
759 fse->min_height = fse->max_height;
760
761 return 0;
762 }
763
bf3925_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)764 static int bf3925_get_fmt(struct v4l2_subdev *sd,
765 struct v4l2_subdev_pad_config *cfg,
766 struct v4l2_subdev_format *fmt)
767 {
768 struct i2c_client *client = v4l2_get_subdevdata(sd);
769 struct bf3925 *bf3925 = to_bf3925(sd);
770
771 dev_dbg(&client->dev, "%s enter\n", __func__);
772
773 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
774 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
775 struct v4l2_mbus_framefmt *mf;
776
777 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
778 mutex_lock(&bf3925->lock);
779 fmt->format = *mf;
780 mutex_unlock(&bf3925->lock);
781 return 0;
782 #else
783 return -ENOTTY;
784 #endif
785 }
786
787 mutex_lock(&bf3925->lock);
788 fmt->format = bf3925->format;
789 mutex_unlock(&bf3925->lock);
790
791 dev_dbg(&client->dev, "%s: %x %dx%d\n", __func__,
792 bf3925->format.code, bf3925->format.width,
793 bf3925->format.height);
794
795 return 0;
796 }
797
__bf3925_try_frame_size_fps(struct v4l2_mbus_framefmt * mf,const struct bf3925_framesize ** size,unsigned int fps)798 static void __bf3925_try_frame_size_fps(struct v4l2_mbus_framefmt *mf,
799 const struct bf3925_framesize **size,
800 unsigned int fps)
801 {
802 const struct bf3925_framesize *fsize = &bf3925_framesizes[0];
803 const struct bf3925_framesize *match = NULL;
804 unsigned int i = ARRAY_SIZE(bf3925_framesizes);
805 unsigned int min_err = UINT_MAX;
806
807 while (i--) {
808 unsigned int err = abs(fsize->width - mf->width)
809 + abs(fsize->height - mf->height);
810 if (err < min_err && fsize->regs[0].addr) {
811 min_err = err;
812 match = fsize;
813 }
814 fsize++;
815 }
816
817 if (!match) {
818 match = &bf3925_framesizes[0];
819 } else {
820 fsize = &bf3925_framesizes[0];
821 for (i = 0; i < ARRAY_SIZE(bf3925_framesizes); i++) {
822 if (fsize->width == match->width &&
823 fsize->height == match->height &&
824 fps >= DIV_ROUND_CLOSEST(fsize->max_fps.denominator,
825 fsize->max_fps.numerator))
826 match = fsize;
827
828 fsize++;
829 }
830 }
831
832 mf->width = match->width;
833 mf->height = match->height;
834
835 if (size)
836 *size = match;
837 }
838
bf3925_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)839 static int bf3925_set_fmt(struct v4l2_subdev *sd,
840 struct v4l2_subdev_pad_config *cfg,
841 struct v4l2_subdev_format *fmt)
842 {
843 struct i2c_client *client = v4l2_get_subdevdata(sd);
844 int index = ARRAY_SIZE(bf3925_formats);
845 struct v4l2_mbus_framefmt *mf = &fmt->format;
846 const struct bf3925_framesize *size = NULL;
847 struct bf3925 *bf3925 = to_bf3925(sd);
848 int ret = 0;
849
850 dev_dbg(&client->dev, "%s enter\n", __func__);
851
852 __bf3925_try_frame_size_fps(mf, &size, bf3925->fps);
853
854 while (--index >= 0)
855 if (bf3925_formats[index].code == mf->code)
856 break;
857
858 if (index < 0)
859 return -EINVAL;
860
861 mf->colorspace = V4L2_COLORSPACE_SRGB;
862 mf->code = bf3925_formats[index].code;
863 mf->field = V4L2_FIELD_NONE;
864
865 mutex_lock(&bf3925->lock);
866
867 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
868 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
869 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
870 *mf = fmt->format;
871 #else
872 return -ENOTTY;
873 #endif
874 } else {
875 if (bf3925->streaming) {
876 mutex_unlock(&bf3925->lock);
877 return -EBUSY;
878 }
879
880 bf3925->frame_size = size;
881 bf3925->format = fmt->format;
882 }
883
884 mutex_unlock(&bf3925->lock);
885 return ret;
886 }
887
bf3925_s_stream(struct v4l2_subdev * sd,int on)888 static int bf3925_s_stream(struct v4l2_subdev *sd, int on)
889 {
890 struct i2c_client *client = v4l2_get_subdevdata(sd);
891 struct bf3925 *bf3925 = to_bf3925(sd);
892 int ret = 0;
893
894 dev_info(&client->dev, "%s: on: %d, %dx%d\n", __func__, on,
895 bf3925->frame_size->width,
896 bf3925->frame_size->height);
897
898 mutex_lock(&bf3925->lock);
899
900 on = !!on;
901
902 if (bf3925->streaming == on)
903 goto unlock;
904
905 if (!on) {
906 /* Stop Streaming Sequence */
907 bf3925_set_streaming(bf3925, 0x02);
908 bf3925->streaming = on;
909 goto unlock;
910 }
911
912 ret = bf3925_write_array(client, bf3925->frame_size->regs);
913 if (ret)
914 goto unlock;
915
916 bf3925_set_streaming(bf3925, 0x00);
917 bf3925->streaming = on;
918
919 unlock:
920 mutex_unlock(&bf3925->lock);
921 return ret;
922 }
923
bf3925_set_test_pattern(struct bf3925 * bf3925,int value)924 static int bf3925_set_test_pattern(struct bf3925 *bf3925, int value)
925 {
926 return 0;
927 }
928
bf3925_s_ctrl(struct v4l2_ctrl * ctrl)929 static int bf3925_s_ctrl(struct v4l2_ctrl *ctrl)
930 {
931 struct bf3925 *bf3925 =
932 container_of(ctrl->handler, struct bf3925, ctrls);
933
934 switch (ctrl->id) {
935 case V4L2_CID_TEST_PATTERN:
936 return bf3925_set_test_pattern(bf3925, ctrl->val);
937 }
938
939 return 0;
940 }
941
942 static const struct v4l2_ctrl_ops bf3925_ctrl_ops = {
943 .s_ctrl = bf3925_s_ctrl,
944 };
945
946 static const char * const bf3925_test_pattern_menu[] = {
947 "Disabled",
948 "Vertical Color Bars",
949 };
950
951 /* -----------------------------------------------------------------------------
952 * V4L2 subdev internal operations
953 */
954
955 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
bf3925_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)956 static int bf3925_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
957 {
958 struct i2c_client *client = v4l2_get_subdevdata(sd);
959 struct v4l2_mbus_framefmt *format =
960 v4l2_subdev_get_try_format(sd, fh->pad, 0);
961
962 dev_dbg(&client->dev, "%s:\n", __func__);
963
964 bf3925_get_default_format(format);
965
966 return 0;
967 }
968 #endif
969
bf3925_g_mbus_config(struct v4l2_subdev * sd,struct v4l2_mbus_config * config)970 static int bf3925_g_mbus_config(struct v4l2_subdev *sd,
971 struct v4l2_mbus_config *config)
972 {
973 config->type = V4L2_MBUS_PARALLEL;
974 config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
975 V4L2_MBUS_VSYNC_ACTIVE_LOW |
976 V4L2_MBUS_PCLK_SAMPLE_RISING;
977
978 return 0;
979 }
980
bf3925_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)981 static int bf3925_g_frame_interval(struct v4l2_subdev *sd,
982 struct v4l2_subdev_frame_interval *fi)
983 {
984 struct bf3925 *bf3925 = to_bf3925(sd);
985
986 mutex_lock(&bf3925->lock);
987 fi->interval = bf3925->frame_size->max_fps;
988 mutex_unlock(&bf3925->lock);
989
990 return 0;
991 }
992
bf3925_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)993 static int bf3925_s_frame_interval(struct v4l2_subdev *sd,
994 struct v4l2_subdev_frame_interval *fi)
995 {
996 struct i2c_client *client = v4l2_get_subdevdata(sd);
997 struct bf3925 *bf3925 = to_bf3925(sd);
998 const struct bf3925_framesize *size = NULL;
999 struct v4l2_mbus_framefmt mf;
1000 unsigned int fps;
1001 int ret = 0;
1002
1003 dev_dbg(&client->dev, "Setting %d/%d frame interval\n",
1004 fi->interval.numerator, fi->interval.denominator);
1005
1006 mutex_lock(&bf3925->lock);
1007 if (bf3925->format.width == 1600)
1008 goto unlock;
1009 fps = DIV_ROUND_CLOSEST(fi->interval.denominator,
1010 fi->interval.numerator);
1011 mf = bf3925->format;
1012 __bf3925_try_frame_size_fps(&mf, &size, fps);
1013
1014 if (bf3925->frame_size != size) {
1015 dev_info(&client->dev, "%s match wxh@FPS is %dx%d@%d\n",
1016 __func__, size->width, size->height,
1017 DIV_ROUND_CLOSEST(size->max_fps.denominator,
1018 size->max_fps.numerator));
1019 ret = bf3925_write_array(client, size->regs);
1020 if (ret)
1021 goto unlock;
1022 bf3925->frame_size = size;
1023 bf3925->fps = fps;
1024 }
1025 unlock:
1026 mutex_unlock(&bf3925->lock);
1027
1028 return ret;
1029 }
1030
bf3925_get_module_inf(struct bf3925 * bf3925,struct rkmodule_inf * inf)1031 static void bf3925_get_module_inf(struct bf3925 *bf3925,
1032 struct rkmodule_inf *inf)
1033 {
1034 memset(inf, 0, sizeof(*inf));
1035 strlcpy(inf->base.sensor, DRIVER_NAME, sizeof(inf->base.sensor));
1036 strlcpy(inf->base.module, bf3925->module_name,
1037 sizeof(inf->base.module));
1038 strlcpy(inf->base.lens, bf3925->len_name, sizeof(inf->base.lens));
1039 }
1040
bf3925_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1041 static long bf3925_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1042 {
1043 struct bf3925 *bf3925 = to_bf3925(sd);
1044 long ret = 0;
1045 u32 stream = 0;
1046
1047 switch (cmd) {
1048 case RKMODULE_GET_MODULE_INFO:
1049 bf3925_get_module_inf(bf3925, (struct rkmodule_inf *)arg);
1050 break;
1051 case RKMODULE_SET_QUICK_STREAM:
1052 stream = *((u32 *)arg);
1053 if (stream)
1054 bf3925_set_streaming(bf3925, 0x00);
1055 else
1056 bf3925_set_streaming(bf3925, 0x02);
1057 break;
1058 default:
1059 ret = -ENOIOCTLCMD;
1060 break;
1061 }
1062
1063 return ret;
1064 }
1065
1066 #ifdef CONFIG_COMPAT
bf3925_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1067 static long bf3925_compat_ioctl32(struct v4l2_subdev *sd,
1068 unsigned int cmd, unsigned long arg)
1069 {
1070 void __user *up = compat_ptr(arg);
1071 struct rkmodule_inf *inf;
1072 struct rkmodule_awb_cfg *cfg;
1073 long ret;
1074 u32 stream = 0;
1075
1076 switch (cmd) {
1077 case RKMODULE_GET_MODULE_INFO:
1078 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1079 if (!inf) {
1080 ret = -ENOMEM;
1081 return ret;
1082 }
1083
1084 ret = bf3925_ioctl(sd, cmd, inf);
1085 if (!ret)
1086 ret = copy_to_user(up, inf, sizeof(*inf));
1087 kfree(inf);
1088 break;
1089 case RKMODULE_AWB_CFG:
1090 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1091 if (!cfg) {
1092 ret = -ENOMEM;
1093 return ret;
1094 }
1095
1096 ret = copy_from_user(cfg, up, sizeof(*cfg));
1097 if (!ret)
1098 ret = bf3925_ioctl(sd, cmd, cfg);
1099 kfree(cfg);
1100 break;
1101 case RKMODULE_SET_QUICK_STREAM:
1102 ret = copy_from_user(&stream, up, sizeof(u32));
1103 if (!ret)
1104 ret = bf3925_ioctl(sd, cmd, &stream);
1105 break;
1106 default:
1107 ret = -ENOIOCTLCMD;
1108 break;
1109 }
1110
1111 return ret;
1112 }
1113 #endif
1114
bf3925_init(struct v4l2_subdev * sd,u32 val)1115 static int bf3925_init(struct v4l2_subdev *sd, u32 val)
1116 {
1117 int ret;
1118 struct bf3925 *bf3925 = to_bf3925(sd);
1119 struct i2c_client *client = bf3925->client;
1120
1121 dev_info(&client->dev, "%s(%d)\n", __func__, __LINE__);
1122 /* soft reset */
1123 ret = bf3925_write(client, 0xf2, 0x03);
1124 ret = bf3925_write_array(client, bf3925_init_regs);
1125 return ret;
1126 }
1127
bf3925_power(struct v4l2_subdev * sd,int on)1128 static int bf3925_power(struct v4l2_subdev *sd, int on)
1129 {
1130 int ret;
1131 struct bf3925 *bf3925 = to_bf3925(sd);
1132 struct i2c_client *client = bf3925->client;
1133 struct device *dev = &bf3925->client->dev;
1134
1135 dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
1136 if (on) {
1137 if (!IS_ERR(bf3925->pwdn_gpio)) {
1138 gpiod_set_value_cansleep(bf3925->pwdn_gpio, 0);
1139 usleep_range(2000, 5000);
1140 }
1141 ret = bf3925_init(sd, 0);
1142 usleep_range(10000, 20000);
1143 if (ret)
1144 dev_err(dev, "init error\n");
1145 } else {
1146 if (!IS_ERR(bf3925->pwdn_gpio)) {
1147 gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
1148 usleep_range(2000, 5000);
1149 }
1150 }
1151 return 0;
1152 }
1153
bf3925_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1154 static int bf3925_enum_frame_interval(struct v4l2_subdev *sd,
1155 struct v4l2_subdev_pad_config *cfg,
1156 struct v4l2_subdev_frame_interval_enum *fie)
1157 {
1158 if (fie->index >= ARRAY_SIZE(bf3925_framesizes))
1159 return -EINVAL;
1160
1161 if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8)
1162 return -EINVAL;
1163
1164 fie->width = bf3925_framesizes[fie->index].width;
1165 fie->height = bf3925_framesizes[fie->index].height;
1166 fie->interval = bf3925_framesizes[fie->index].max_fps;
1167 return 0;
1168 }
1169
1170 static const struct v4l2_subdev_core_ops bf3925_subdev_core_ops = {
1171 .log_status = v4l2_ctrl_subdev_log_status,
1172 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1173 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1174 .ioctl = bf3925_ioctl,
1175 #ifdef CONFIG_COMPAT
1176 .compat_ioctl32 = bf3925_compat_ioctl32,
1177 #endif
1178 .s_power = bf3925_power,
1179 };
1180
1181 static const struct v4l2_subdev_video_ops bf3925_subdev_video_ops = {
1182 .s_stream = bf3925_s_stream,
1183 .g_mbus_config = bf3925_g_mbus_config,
1184 .g_frame_interval = bf3925_g_frame_interval,
1185 .s_frame_interval = bf3925_s_frame_interval,
1186 };
1187
1188 static const struct v4l2_subdev_pad_ops bf3925_subdev_pad_ops = {
1189 .enum_mbus_code = bf3925_enum_mbus_code,
1190 .enum_frame_size = bf3925_enum_frame_sizes,
1191 .enum_frame_interval = bf3925_enum_frame_interval,
1192 .get_fmt = bf3925_get_fmt,
1193 .set_fmt = bf3925_set_fmt,
1194 };
1195
1196 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1197 static const struct v4l2_subdev_ops bf3925_subdev_ops = {
1198 .core = &bf3925_subdev_core_ops,
1199 .video = &bf3925_subdev_video_ops,
1200 .pad = &bf3925_subdev_pad_ops,
1201 };
1202
1203 static const struct v4l2_subdev_internal_ops bf3925_subdev_internal_ops = {
1204 .open = bf3925_open,
1205 };
1206 #endif
1207
bf3925_detect(struct bf3925 * bf3925)1208 static int bf3925_detect(struct bf3925 *bf3925)
1209 {
1210 struct i2c_client *client = bf3925->client;
1211 u8 pid, ver;
1212 int ret;
1213
1214 dev_dbg(&client->dev, "%s:\n", __func__);
1215
1216 /* Check sensor revision */
1217 ret = bf3925_read(client, REG_SC_CHIP_ID_H, &pid);
1218 if (!ret)
1219 ret = bf3925_read(client, REG_SC_CHIP_ID_L, &ver);
1220
1221 if (!ret) {
1222 unsigned short id;
1223
1224 id = SENSOR_ID(pid, ver);
1225 if (id != BF3925_ID) {
1226 ret = -1;
1227 dev_err(&client->dev,
1228 "Sensor detection failed (%04X, %d)\n",
1229 id, ret);
1230 } else {
1231 dev_info(&client->dev, "Found BF%04X sensor\n", id);
1232 if (!IS_ERR(bf3925->pwdn_gpio))
1233 gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
1234 }
1235 }
1236
1237 return ret;
1238 }
1239
__bf3925_power_on(struct bf3925 * bf3925)1240 static int __bf3925_power_on(struct bf3925 *bf3925)
1241 {
1242 int ret;
1243 struct device *dev = &bf3925->client->dev;
1244
1245 dev_info(dev, "power on!!!\n");
1246 if (!IS_ERR(bf3925->xvclk)) {
1247 ret = clk_set_rate(bf3925->xvclk, 24000000);
1248 if (ret < 0)
1249 dev_info(dev, "Failed to set xvclk rate (24MHz)\n");
1250 }
1251 if (!IS_ERR(bf3925->xvclk)) {
1252 ret = clk_prepare_enable(bf3925->xvclk);
1253 if (ret < 0)
1254 dev_info(dev, "Failed to enable xvclk\n");
1255 }
1256 usleep_range(7000, 10000);
1257
1258 if (!IS_ERR(bf3925->pwdn_gpio)) {
1259 gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
1260 usleep_range(2000, 5000);
1261 }
1262
1263 if (!IS_ERR(bf3925->supplies)) {
1264 ret = regulator_bulk_enable(BF3925_NUM_SUPPLIES,
1265 bf3925->supplies);
1266 if (ret < 0)
1267 dev_info(dev, "Failed to enable regulators\n");
1268
1269 usleep_range(20000, 50000);
1270 }
1271
1272 if (!IS_ERR(bf3925->pwdn2_gpio)) {
1273 gpiod_set_value_cansleep(bf3925->pwdn2_gpio, 1);
1274 usleep_range(2000, 5000);
1275 }
1276
1277 if (!IS_ERR(bf3925->pwdn_gpio)) {
1278 gpiod_set_value_cansleep(bf3925->pwdn_gpio, 0);
1279 usleep_range(2000, 5000);
1280 }
1281
1282 return 0;
1283 }
1284
__bf3925_power_off(struct bf3925 * bf3925)1285 static void __bf3925_power_off(struct bf3925 *bf3925)
1286 {
1287 if (!IS_ERR(bf3925->xvclk))
1288 clk_disable_unprepare(bf3925->xvclk);
1289 if (!IS_ERR(bf3925->supplies))
1290 regulator_bulk_disable(BF3925_NUM_SUPPLIES, bf3925->supplies);
1291 if (!IS_ERR(bf3925->pwdn_gpio))
1292 gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
1293 }
1294
bf3925_configure_regulators(struct bf3925 * bf3925)1295 static int bf3925_configure_regulators(struct bf3925 *bf3925)
1296 {
1297 unsigned int i;
1298
1299 for (i = 0; i < BF3925_NUM_SUPPLIES; i++)
1300 bf3925->supplies[i].supply = bf3925_supply_names[i];
1301
1302 return devm_regulator_bulk_get(&bf3925->client->dev,
1303 BF3925_NUM_SUPPLIES,
1304 bf3925->supplies);
1305 }
1306
bf3925_parse_of(struct bf3925 * bf3925)1307 static int bf3925_parse_of(struct bf3925 *bf3925)
1308 {
1309 struct device *dev = &bf3925->client->dev;
1310 struct device_node *node = dev->of_node;
1311 struct gpio_desc *pwdn_gpio;
1312 unsigned int pwdn = -1;
1313 enum of_gpio_flags flags;
1314 int ret;
1315
1316 bf3925->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1317 if (IS_ERR(bf3925->pwdn_gpio)) {
1318 dev_info(dev, "Failed to get pwdn-gpios, maybe no use\n");
1319 pwdn = of_get_named_gpio_flags(node, "pwdn-gpios", 0, &flags);
1320 pwdn_gpio = gpio_to_desc(pwdn);
1321 if (IS_ERR(pwdn_gpio))
1322 dev_info(dev, "Failed to get pwdn-gpios again\n");
1323 else
1324 bf3925->pwdn_gpio = pwdn_gpio;
1325 }
1326
1327 bf3925->pwdn2_gpio = devm_gpiod_get(dev, "pwdn2", GPIOD_OUT_LOW);
1328 if (IS_ERR(bf3925->pwdn2_gpio)) {
1329 dev_info(dev, "Failed to get pwdn2-gpios, maybe no use\n");
1330 pwdn = of_get_named_gpio_flags(node, "pwdn2-gpios", 0, &flags);
1331 pwdn_gpio = gpio_to_desc(pwdn);
1332 if (IS_ERR(pwdn_gpio))
1333 dev_info(dev, "Failed to get pwdn2-gpios again\n");
1334 else
1335 bf3925->pwdn2_gpio = pwdn_gpio;
1336 }
1337
1338 ret = bf3925_configure_regulators(bf3925);
1339 if (ret)
1340 dev_info(dev, "Failed to get power regulators\n");
1341
1342 return __bf3925_power_on(bf3925);
1343 }
1344
bf3925_probe(struct i2c_client * client,const struct i2c_device_id * id)1345 static int bf3925_probe(struct i2c_client *client,
1346 const struct i2c_device_id *id)
1347 {
1348 struct device *dev = &client->dev;
1349 struct device_node *node = dev->of_node;
1350 struct v4l2_subdev *sd;
1351 struct bf3925 *bf3925;
1352 char facing[2] = "b";
1353 int ret;
1354
1355 dev_info(dev, "driver version: %02x.%02x.%02x",
1356 DRIVER_VERSION >> 16,
1357 (DRIVER_VERSION & 0xff00) >> 8,
1358 DRIVER_VERSION & 0x00ff);
1359
1360 bf3925 = devm_kzalloc(&client->dev, sizeof(*bf3925), GFP_KERNEL);
1361 if (!bf3925)
1362 return -ENOMEM;
1363
1364 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1365 &bf3925->module_index);
1366 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1367 &bf3925->module_facing);
1368 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1369 &bf3925->module_name);
1370 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1371 &bf3925->len_name);
1372 if (ret) {
1373 dev_err(&client->dev, "could not get module information!\n");
1374 return -EINVAL;
1375 }
1376
1377 bf3925->client = client;
1378 bf3925->xvclk = devm_clk_get(&client->dev, "xvclk");
1379 if (IS_ERR(bf3925->xvclk)) {
1380 dev_err(&client->dev, "Failed to get xvclk\n");
1381 return -EINVAL;
1382 }
1383
1384 bf3925_parse_of(bf3925);
1385
1386 bf3925->xvclk_frequency = clk_get_rate(bf3925->xvclk);
1387 if (bf3925->xvclk_frequency < 6000000 ||
1388 bf3925->xvclk_frequency > 27000000)
1389 return -EINVAL;
1390
1391 v4l2_ctrl_handler_init(&bf3925->ctrls, 2);
1392 bf3925->link_frequency =
1393 v4l2_ctrl_new_std(&bf3925->ctrls, &bf3925_ctrl_ops,
1394 V4L2_CID_PIXEL_RATE, 0,
1395 BF3925_PIXEL_RATE, 1,
1396 BF3925_PIXEL_RATE);
1397
1398 v4l2_ctrl_new_std_menu_items(&bf3925->ctrls, &bf3925_ctrl_ops,
1399 V4L2_CID_TEST_PATTERN,
1400 ARRAY_SIZE(bf3925_test_pattern_menu) - 1,
1401 0, 0, bf3925_test_pattern_menu);
1402 bf3925->sd.ctrl_handler = &bf3925->ctrls;
1403
1404 if (bf3925->ctrls.error) {
1405 dev_err(&client->dev, "%s: control initialization error %d\n",
1406 __func__, bf3925->ctrls.error);
1407 return bf3925->ctrls.error;
1408 }
1409
1410 sd = &bf3925->sd;
1411 client->flags |= I2C_CLIENT_SCCB;
1412 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1413 v4l2_i2c_subdev_init(sd, client, &bf3925_subdev_ops);
1414
1415 sd->internal_ops = &bf3925_subdev_internal_ops;
1416 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1417 V4L2_SUBDEV_FL_HAS_EVENTS;
1418 #endif
1419
1420 #if defined(CONFIG_MEDIA_CONTROLLER)
1421 bf3925->pad.flags = MEDIA_PAD_FL_SOURCE;
1422 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1423 ret = media_entity_pads_init(&sd->entity, 1, &bf3925->pad);
1424 if (ret < 0) {
1425 v4l2_ctrl_handler_free(&bf3925->ctrls);
1426 return ret;
1427 }
1428 #endif
1429
1430 mutex_init(&bf3925->lock);
1431
1432 bf3925_get_default_format(&bf3925->format);
1433 bf3925->frame_size = &bf3925_framesizes[0];
1434 bf3925->format.width = bf3925_framesizes[0].width;
1435 bf3925->format.height = bf3925_framesizes[0].height;
1436 bf3925->fps = DIV_ROUND_CLOSEST(bf3925_framesizes[0].max_fps.denominator,
1437 bf3925_framesizes[0].max_fps.numerator);
1438
1439 ret = bf3925_detect(bf3925);
1440 if (ret < 0)
1441 goto error;
1442
1443 memset(facing, 0, sizeof(facing));
1444 if (strcmp(bf3925->module_facing, "back") == 0)
1445 facing[0] = 'b';
1446 else
1447 facing[0] = 'f';
1448
1449 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1450 bf3925->module_index, facing,
1451 DRIVER_NAME, dev_name(sd->dev));
1452 ret = v4l2_async_register_subdev_sensor_common(&bf3925->sd);
1453 if (ret)
1454 goto error;
1455
1456 dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
1457
1458 return 0;
1459
1460 error:
1461 v4l2_ctrl_handler_free(&bf3925->ctrls);
1462 #if defined(CONFIG_MEDIA_CONTROLLER)
1463 media_entity_cleanup(&sd->entity);
1464 #endif
1465 mutex_destroy(&bf3925->lock);
1466 __bf3925_power_off(bf3925);
1467 return ret;
1468 }
1469
bf3925_remove(struct i2c_client * client)1470 static int bf3925_remove(struct i2c_client *client)
1471 {
1472 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1473 struct bf3925 *bf3925 = to_bf3925(sd);
1474
1475 v4l2_ctrl_handler_free(&bf3925->ctrls);
1476 v4l2_async_unregister_subdev(sd);
1477 #if defined(CONFIG_MEDIA_CONTROLLER)
1478 media_entity_cleanup(&sd->entity);
1479 #endif
1480 mutex_destroy(&bf3925->lock);
1481
1482 __bf3925_power_off(bf3925);
1483
1484 return 0;
1485 }
1486
1487 static const struct i2c_device_id bf3925_id[] = {
1488 { "bf3925", 0 },
1489 { /* sentinel */ },
1490 };
1491 MODULE_DEVICE_TABLE(i2c, bf3925_id);
1492
1493 #if IS_ENABLED(CONFIG_OF)
1494 static const struct of_device_id bf3925_of_match[] = {
1495 { .compatible = "byd,bf3925", },
1496 { /* sentinel */ },
1497 };
1498 MODULE_DEVICE_TABLE(of, bf3925_of_match);
1499 #endif
1500
1501 static struct i2c_driver bf3925_i2c_driver = {
1502 .driver = {
1503 .name = DRIVER_NAME,
1504 .of_match_table = of_match_ptr(bf3925_of_match),
1505 },
1506 .probe = bf3925_probe,
1507 .remove = bf3925_remove,
1508 .id_table = bf3925_id,
1509 };
1510
sensor_mod_init(void)1511 static int __init sensor_mod_init(void)
1512 {
1513 return i2c_add_driver(&bf3925_i2c_driver);
1514 }
1515
sensor_mod_exit(void)1516 static void __exit sensor_mod_exit(void)
1517 {
1518 i2c_del_driver(&bf3925_i2c_driver);
1519 }
1520
1521 device_initcall_sync(sensor_mod_init);
1522 module_exit(sensor_mod_exit);
1523
1524 MODULE_AUTHOR("Benoit Parrot <bparrot@ti.com>");
1525 MODULE_DESCRIPTION("BF3925 CMOS Image Sensor driver");
1526 MODULE_LICENSE("GPL v2");
1527