xref: /OK3568_Linux_fs/kernel/drivers/mailbox/rockchip-mailbox.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/interrupt.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/mailbox_controller.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/spinlock.h>
15*4882a593Smuzhiyun #include <soc/rockchip/rockchip-mailbox.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define MAILBOX_A2B_INTEN		0x00
18*4882a593Smuzhiyun #define MAILBOX_A2B_STATUS		0x04
19*4882a593Smuzhiyun #define MAILBOX_A2B_CMD(x)		(0x08 + (x) * 8)
20*4882a593Smuzhiyun #define MAILBOX_A2B_DAT(x)		(0x0c + (x) * 8)
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define MAILBOX_B2A_INTEN		0x28
23*4882a593Smuzhiyun #define MAILBOX_B2A_STATUS		0x2C
24*4882a593Smuzhiyun #define MAILBOX_B2A_CMD(x)		(0x30 + (x) * 8)
25*4882a593Smuzhiyun #define MAILBOX_B2A_DAT(x)		(0x34 + (x) * 8)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define MAILBOX_POLLING_MS		5 /* default polling interval 5ms */
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun struct rockchip_mbox_data {
30*4882a593Smuzhiyun 	int num_chans;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun struct rockchip_mbox_chan {
34*4882a593Smuzhiyun 	int idx;
35*4882a593Smuzhiyun 	int irq;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun struct rockchip_mbox {
39*4882a593Smuzhiyun 	struct mbox_controller mbox;
40*4882a593Smuzhiyun 	struct clk *pclk;
41*4882a593Smuzhiyun 	void __iomem *mbox_base;
42*4882a593Smuzhiyun 	spinlock_t cfg_lock; /* Serialise access to the register */
43*4882a593Smuzhiyun 	struct rockchip_mbox_msg *msg;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	struct rockchip_mbox_chan *chans;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
rockchip_mbox_send_data(struct mbox_chan * chan,void * data)48*4882a593Smuzhiyun static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
51*4882a593Smuzhiyun 	struct rockchip_mbox_msg *msg = data;
52*4882a593Smuzhiyun 	struct rockchip_mbox_chan *chans = chan->con_priv;
53*4882a593Smuzhiyun 	u32 status;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	if (!msg)
56*4882a593Smuzhiyun 		return -EINVAL;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	status = readl_relaxed(mb->mbox_base + MAILBOX_A2B_STATUS);
59*4882a593Smuzhiyun 	if (status & (1U << chans->idx)) {
60*4882a593Smuzhiyun 		dev_err(mb->mbox.dev, "The mailbox channel is busy\n");
61*4882a593Smuzhiyun 		return -EBUSY;
62*4882a593Smuzhiyun 	}
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x, data 0x%08x\n",
65*4882a593Smuzhiyun 		chans->idx, msg->cmd, msg->data);
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
68*4882a593Smuzhiyun 	writel_relaxed(msg->data, mb->mbox_base +
69*4882a593Smuzhiyun 		       MAILBOX_A2B_DAT(chans->idx));
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
rockchip_mbox_startup(struct mbox_chan * chan)74*4882a593Smuzhiyun static int rockchip_mbox_startup(struct mbox_chan *chan)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
77*4882a593Smuzhiyun 	struct rockchip_mbox_chan *chans = chan->con_priv;
78*4882a593Smuzhiyun 	u32 val = 0U;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/* Enable the corresponding B2A interrupt */
81*4882a593Smuzhiyun 	spin_lock(&mb->cfg_lock);
82*4882a593Smuzhiyun 	val = readl_relaxed(mb->mbox_base + MAILBOX_B2A_INTEN) |
83*4882a593Smuzhiyun 		(1U << chans->idx);
84*4882a593Smuzhiyun 	writel_relaxed(val, mb->mbox_base + MAILBOX_B2A_INTEN);
85*4882a593Smuzhiyun 	spin_unlock(&mb->cfg_lock);
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
rockchip_mbox_shutdown(struct mbox_chan * chan)90*4882a593Smuzhiyun static void rockchip_mbox_shutdown(struct mbox_chan *chan)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
93*4882a593Smuzhiyun 	struct rockchip_mbox_chan *chans = chan->con_priv;
94*4882a593Smuzhiyun 	u32 val = 0U;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	/* Disable the corresponding B2A interrupt */
97*4882a593Smuzhiyun 	spin_lock(&mb->cfg_lock);
98*4882a593Smuzhiyun 	val = readl_relaxed(mb->mbox_base + MAILBOX_B2A_INTEN) &
99*4882a593Smuzhiyun 		~(1U << chans->idx);
100*4882a593Smuzhiyun 	writel_relaxed(val, mb->mbox_base + MAILBOX_B2A_INTEN);
101*4882a593Smuzhiyun 	spin_unlock(&mb->cfg_lock);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
rockchip_mbox_last_tx_done(struct mbox_chan * chan)104*4882a593Smuzhiyun static bool rockchip_mbox_last_tx_done(struct mbox_chan *chan)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
107*4882a593Smuzhiyun 	struct rockchip_mbox_chan *chans = chan->con_priv;
108*4882a593Smuzhiyun 	u32 status;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	status = readl_relaxed(mb->mbox_base + MAILBOX_A2B_STATUS);
111*4882a593Smuzhiyun 	return !(status & (1U << chans->idx));
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
115*4882a593Smuzhiyun 	.send_data	= rockchip_mbox_send_data,
116*4882a593Smuzhiyun 	.startup	= rockchip_mbox_startup,
117*4882a593Smuzhiyun 	.shutdown	= rockchip_mbox_shutdown,
118*4882a593Smuzhiyun 	.last_tx_done	= rockchip_mbox_last_tx_done,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun 
rockchip_mbox_read_msg(struct mbox_chan * chan,struct rockchip_mbox_msg * msg)121*4882a593Smuzhiyun int rockchip_mbox_read_msg(struct mbox_chan *chan,
122*4882a593Smuzhiyun 			   struct rockchip_mbox_msg *msg)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun 	struct rockchip_mbox *mb;
125*4882a593Smuzhiyun 	struct rockchip_mbox_chan *chans;
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	if (!chan || !msg)
128*4882a593Smuzhiyun 		return -EINVAL;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	mb = dev_get_drvdata(chan->mbox->dev);
131*4882a593Smuzhiyun 	chans = chan->con_priv;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	msg->cmd  = mb->msg[chans->idx].cmd;
134*4882a593Smuzhiyun 	msg->data = mb->msg[chans->idx].data;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rockchip_mbox_read_msg);
139*4882a593Smuzhiyun 
rockchip_mbox_irq(int irq,void * dev_id)140*4882a593Smuzhiyun static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	int idx;
143*4882a593Smuzhiyun 	struct rockchip_mbox_msg *msg;
144*4882a593Smuzhiyun 	struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
145*4882a593Smuzhiyun 	u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
148*4882a593Smuzhiyun 		if ((status & (1U << idx)) && irq == mb->chans[idx].irq) {
149*4882a593Smuzhiyun 			/* Get cmd/data from the channel of B2A */
150*4882a593Smuzhiyun 			msg = &mb->msg[idx];
151*4882a593Smuzhiyun 			msg->cmd = readl_relaxed(mb->mbox_base +
152*4882a593Smuzhiyun 						 MAILBOX_B2A_CMD(idx));
153*4882a593Smuzhiyun 			msg->data = readl_relaxed(mb->mbox_base +
154*4882a593Smuzhiyun 						  MAILBOX_B2A_DAT(idx));
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 			dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x, data 0x%08x\n",
157*4882a593Smuzhiyun 				idx, msg->cmd, msg->data);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 			if (mb->mbox.chans[idx].cl)
160*4882a593Smuzhiyun 				mbox_chan_received_data(&mb->mbox.chans[idx], msg);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 			/* Clear mbox interrupt */
163*4882a593Smuzhiyun 			writel_relaxed(1U << idx,
164*4882a593Smuzhiyun 				       mb->mbox_base + MAILBOX_B2A_STATUS);
165*4882a593Smuzhiyun 		}
166*4882a593Smuzhiyun 	}
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	return IRQ_HANDLED;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun static const struct rockchip_mbox_data rk3368_drv_data = {
172*4882a593Smuzhiyun 	.num_chans = 4,
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun static const struct of_device_id rockchip_mbox_of_match[] = {
176*4882a593Smuzhiyun 	{ .compatible = "rockchip,rk3368-mailbox", .data = &rk3368_drv_data},
177*4882a593Smuzhiyun 	{ },
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rockchip_mbox_of_match);
180*4882a593Smuzhiyun 
rockchip_mbox_probe(struct platform_device * pdev)181*4882a593Smuzhiyun static int rockchip_mbox_probe(struct platform_device *pdev)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	struct rockchip_mbox *mb;
184*4882a593Smuzhiyun 	const struct of_device_id *match;
185*4882a593Smuzhiyun 	const struct rockchip_mbox_data *drv_data;
186*4882a593Smuzhiyun 	struct resource *res;
187*4882a593Smuzhiyun 	int ret, irq, i;
188*4882a593Smuzhiyun 	u32 txpoll_period;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	if (!pdev->dev.of_node)
191*4882a593Smuzhiyun 		return -ENODEV;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node);
194*4882a593Smuzhiyun 	drv_data = (const struct rockchip_mbox_data *)match->data;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
197*4882a593Smuzhiyun 	if (!mb)
198*4882a593Smuzhiyun 		return -ENOMEM;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	mb->msg = devm_kcalloc(&pdev->dev, drv_data->num_chans,
201*4882a593Smuzhiyun 			       sizeof(*mb->msg), GFP_KERNEL);
202*4882a593Smuzhiyun 	if (!mb->msg)
203*4882a593Smuzhiyun 		return -ENOMEM;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
206*4882a593Smuzhiyun 				 sizeof(*mb->chans), GFP_KERNEL);
207*4882a593Smuzhiyun 	if (!mb->chans)
208*4882a593Smuzhiyun 		return -ENOMEM;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
211*4882a593Smuzhiyun 				      sizeof(*mb->mbox.chans), GFP_KERNEL);
212*4882a593Smuzhiyun 	if (!mb->mbox.chans)
213*4882a593Smuzhiyun 		return -ENOMEM;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	platform_set_drvdata(pdev, mb);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	mb->mbox.dev = &pdev->dev;
218*4882a593Smuzhiyun 	mb->mbox.num_chans = drv_data->num_chans;
219*4882a593Smuzhiyun 	mb->mbox.ops = &rockchip_mbox_chan_ops;
220*4882a593Smuzhiyun 	spin_lock_init(&mb->cfg_lock);
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	mb->mbox.txdone_poll = true;
223*4882a593Smuzhiyun 	ret = device_property_read_u32(&pdev->dev, "rockchip,txpoll-period-ms", &txpoll_period);
224*4882a593Smuzhiyun 	mb->mbox.txpoll_period = !ret ? txpoll_period : MAILBOX_POLLING_MS;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
227*4882a593Smuzhiyun 	if (!res)
228*4882a593Smuzhiyun 		return -ENODEV;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	mb->mbox_base = devm_ioremap_resource(&pdev->dev, res);
231*4882a593Smuzhiyun 	if (IS_ERR(mb->mbox_base))
232*4882a593Smuzhiyun 		return PTR_ERR(mb->mbox_base);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox");
235*4882a593Smuzhiyun 	if (IS_ERR(mb->pclk)) {
236*4882a593Smuzhiyun 		ret = PTR_ERR(mb->pclk);
237*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to get pclk_mailbox clock: %d\n",
238*4882a593Smuzhiyun 			ret);
239*4882a593Smuzhiyun 		return ret;
240*4882a593Smuzhiyun 	}
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	ret = clk_prepare_enable(mb->pclk);
243*4882a593Smuzhiyun 	if (ret) {
244*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to enable pclk: %d\n", ret);
245*4882a593Smuzhiyun 		return ret;
246*4882a593Smuzhiyun 	}
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	for (i = 0; i < mb->mbox.num_chans; i++) {
249*4882a593Smuzhiyun 		irq = platform_get_irq(pdev, i);
250*4882a593Smuzhiyun 		if (irq < 0) {
251*4882a593Smuzhiyun 			/* For shared irq case, only could be got one time */
252*4882a593Smuzhiyun 			if (i > 0 && irq == -ENXIO) {
253*4882a593Smuzhiyun 				mb->chans[i].irq = mb->chans[0].irq;
254*4882a593Smuzhiyun 			} else {
255*4882a593Smuzhiyun 				ret = irq;
256*4882a593Smuzhiyun 				goto disable_clk;
257*4882a593Smuzhiyun 			}
258*4882a593Smuzhiyun 		} else {
259*4882a593Smuzhiyun 			mb->chans[i].irq = irq;
260*4882a593Smuzhiyun 		}
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 		mb->chans[i].idx = i;
263*4882a593Smuzhiyun 		mb->mbox.chans[i].con_priv = &mb->chans[i];
264*4882a593Smuzhiyun 	}
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
267*4882a593Smuzhiyun 	if (ret < 0) {
268*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);
269*4882a593Smuzhiyun 		goto disable_clk;
270*4882a593Smuzhiyun 	}
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	for (i = 0; i < mb->mbox.num_chans; i++) {
273*4882a593Smuzhiyun 		/* For shared irq case, only request irq thread one time */
274*4882a593Smuzhiyun 		if (i > 0 && mb->chans[i].irq == mb->chans[0].irq)
275*4882a593Smuzhiyun 			break;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 		ret = devm_request_threaded_irq(&pdev->dev, mb->chans[i].irq,
278*4882a593Smuzhiyun 						NULL,
279*4882a593Smuzhiyun 						rockchip_mbox_irq,
280*4882a593Smuzhiyun 						IRQF_ONESHOT,
281*4882a593Smuzhiyun 						dev_name(&pdev->dev),
282*4882a593Smuzhiyun 						mb);
283*4882a593Smuzhiyun 		if (ret < 0)
284*4882a593Smuzhiyun 			goto disable_clk;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 		if (device_property_present(&pdev->dev, "wakeup-source"))
287*4882a593Smuzhiyun 			enable_irq_wake(mb->chans[i].irq);
288*4882a593Smuzhiyun 	}
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	return 0;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun disable_clk:
293*4882a593Smuzhiyun 	clk_disable_unprepare(mb->pclk);
294*4882a593Smuzhiyun 	return ret;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun static struct platform_driver rockchip_mbox_driver = {
298*4882a593Smuzhiyun 	.probe	= rockchip_mbox_probe,
299*4882a593Smuzhiyun 	.driver = {
300*4882a593Smuzhiyun 		.name = "rockchip-mailbox",
301*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(rockchip_mbox_of_match),
302*4882a593Smuzhiyun 	},
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun #if defined(CONFIG_ROCKCHIP_THUNDER_BOOT)
rockchip_mbox_driver_init(void)306*4882a593Smuzhiyun static int __init rockchip_mbox_driver_init(void)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun 	return platform_driver_register(&rockchip_mbox_driver);
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun core_initcall(rockchip_mbox_driver_init);
311*4882a593Smuzhiyun #else
312*4882a593Smuzhiyun module_platform_driver(rockchip_mbox_driver);
313*4882a593Smuzhiyun #endif
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
316*4882a593Smuzhiyun MODULE_DESCRIPTION("Rockchip mailbox: communicate between CPU cores and MCU");
317*4882a593Smuzhiyun MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
318*4882a593Smuzhiyun MODULE_AUTHOR("Caesar Wang <wxt@rock-chips.com>");
319