1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6 #include <linux/clk.h>
7 #include <linux/interrupt.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/mailbox_controller.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/spinlock.h>
15 #include <soc/rockchip/rockchip-mailbox.h>
16
17 #define MAILBOX_A2B_INTEN 0x00
18 #define MAILBOX_A2B_STATUS 0x04
19 #define MAILBOX_A2B_CMD(x) (0x08 + (x) * 8)
20 #define MAILBOX_A2B_DAT(x) (0x0c + (x) * 8)
21
22 #define MAILBOX_B2A_INTEN 0x28
23 #define MAILBOX_B2A_STATUS 0x2C
24 #define MAILBOX_B2A_CMD(x) (0x30 + (x) * 8)
25 #define MAILBOX_B2A_DAT(x) (0x34 + (x) * 8)
26
27 #define MAILBOX_POLLING_MS 5 /* default polling interval 5ms */
28
29 struct rockchip_mbox_data {
30 int num_chans;
31 };
32
33 struct rockchip_mbox_chan {
34 int idx;
35 int irq;
36 };
37
38 struct rockchip_mbox {
39 struct mbox_controller mbox;
40 struct clk *pclk;
41 void __iomem *mbox_base;
42 spinlock_t cfg_lock; /* Serialise access to the register */
43 struct rockchip_mbox_msg *msg;
44
45 struct rockchip_mbox_chan *chans;
46 };
47
rockchip_mbox_send_data(struct mbox_chan * chan,void * data)48 static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
49 {
50 struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
51 struct rockchip_mbox_msg *msg = data;
52 struct rockchip_mbox_chan *chans = chan->con_priv;
53 u32 status;
54
55 if (!msg)
56 return -EINVAL;
57
58 status = readl_relaxed(mb->mbox_base + MAILBOX_A2B_STATUS);
59 if (status & (1U << chans->idx)) {
60 dev_err(mb->mbox.dev, "The mailbox channel is busy\n");
61 return -EBUSY;
62 }
63
64 dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x, data 0x%08x\n",
65 chans->idx, msg->cmd, msg->data);
66
67 writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
68 writel_relaxed(msg->data, mb->mbox_base +
69 MAILBOX_A2B_DAT(chans->idx));
70
71 return 0;
72 }
73
rockchip_mbox_startup(struct mbox_chan * chan)74 static int rockchip_mbox_startup(struct mbox_chan *chan)
75 {
76 struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
77 struct rockchip_mbox_chan *chans = chan->con_priv;
78 u32 val = 0U;
79
80 /* Enable the corresponding B2A interrupt */
81 spin_lock(&mb->cfg_lock);
82 val = readl_relaxed(mb->mbox_base + MAILBOX_B2A_INTEN) |
83 (1U << chans->idx);
84 writel_relaxed(val, mb->mbox_base + MAILBOX_B2A_INTEN);
85 spin_unlock(&mb->cfg_lock);
86
87 return 0;
88 }
89
rockchip_mbox_shutdown(struct mbox_chan * chan)90 static void rockchip_mbox_shutdown(struct mbox_chan *chan)
91 {
92 struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
93 struct rockchip_mbox_chan *chans = chan->con_priv;
94 u32 val = 0U;
95
96 /* Disable the corresponding B2A interrupt */
97 spin_lock(&mb->cfg_lock);
98 val = readl_relaxed(mb->mbox_base + MAILBOX_B2A_INTEN) &
99 ~(1U << chans->idx);
100 writel_relaxed(val, mb->mbox_base + MAILBOX_B2A_INTEN);
101 spin_unlock(&mb->cfg_lock);
102 }
103
rockchip_mbox_last_tx_done(struct mbox_chan * chan)104 static bool rockchip_mbox_last_tx_done(struct mbox_chan *chan)
105 {
106 struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
107 struct rockchip_mbox_chan *chans = chan->con_priv;
108 u32 status;
109
110 status = readl_relaxed(mb->mbox_base + MAILBOX_A2B_STATUS);
111 return !(status & (1U << chans->idx));
112 }
113
114 static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
115 .send_data = rockchip_mbox_send_data,
116 .startup = rockchip_mbox_startup,
117 .shutdown = rockchip_mbox_shutdown,
118 .last_tx_done = rockchip_mbox_last_tx_done,
119 };
120
rockchip_mbox_read_msg(struct mbox_chan * chan,struct rockchip_mbox_msg * msg)121 int rockchip_mbox_read_msg(struct mbox_chan *chan,
122 struct rockchip_mbox_msg *msg)
123 {
124 struct rockchip_mbox *mb;
125 struct rockchip_mbox_chan *chans;
126
127 if (!chan || !msg)
128 return -EINVAL;
129
130 mb = dev_get_drvdata(chan->mbox->dev);
131 chans = chan->con_priv;
132
133 msg->cmd = mb->msg[chans->idx].cmd;
134 msg->data = mb->msg[chans->idx].data;
135
136 return 0;
137 }
138 EXPORT_SYMBOL_GPL(rockchip_mbox_read_msg);
139
rockchip_mbox_irq(int irq,void * dev_id)140 static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id)
141 {
142 int idx;
143 struct rockchip_mbox_msg *msg;
144 struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
145 u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);
146
147 for (idx = 0; idx < mb->mbox.num_chans; idx++) {
148 if ((status & (1U << idx)) && irq == mb->chans[idx].irq) {
149 /* Get cmd/data from the channel of B2A */
150 msg = &mb->msg[idx];
151 msg->cmd = readl_relaxed(mb->mbox_base +
152 MAILBOX_B2A_CMD(idx));
153 msg->data = readl_relaxed(mb->mbox_base +
154 MAILBOX_B2A_DAT(idx));
155
156 dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x, data 0x%08x\n",
157 idx, msg->cmd, msg->data);
158
159 if (mb->mbox.chans[idx].cl)
160 mbox_chan_received_data(&mb->mbox.chans[idx], msg);
161
162 /* Clear mbox interrupt */
163 writel_relaxed(1U << idx,
164 mb->mbox_base + MAILBOX_B2A_STATUS);
165 }
166 }
167
168 return IRQ_HANDLED;
169 }
170
171 static const struct rockchip_mbox_data rk3368_drv_data = {
172 .num_chans = 4,
173 };
174
175 static const struct of_device_id rockchip_mbox_of_match[] = {
176 { .compatible = "rockchip,rk3368-mailbox", .data = &rk3368_drv_data},
177 { },
178 };
179 MODULE_DEVICE_TABLE(of, rockchip_mbox_of_match);
180
rockchip_mbox_probe(struct platform_device * pdev)181 static int rockchip_mbox_probe(struct platform_device *pdev)
182 {
183 struct rockchip_mbox *mb;
184 const struct of_device_id *match;
185 const struct rockchip_mbox_data *drv_data;
186 struct resource *res;
187 int ret, irq, i;
188 u32 txpoll_period;
189
190 if (!pdev->dev.of_node)
191 return -ENODEV;
192
193 match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node);
194 drv_data = (const struct rockchip_mbox_data *)match->data;
195
196 mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
197 if (!mb)
198 return -ENOMEM;
199
200 mb->msg = devm_kcalloc(&pdev->dev, drv_data->num_chans,
201 sizeof(*mb->msg), GFP_KERNEL);
202 if (!mb->msg)
203 return -ENOMEM;
204
205 mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
206 sizeof(*mb->chans), GFP_KERNEL);
207 if (!mb->chans)
208 return -ENOMEM;
209
210 mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
211 sizeof(*mb->mbox.chans), GFP_KERNEL);
212 if (!mb->mbox.chans)
213 return -ENOMEM;
214
215 platform_set_drvdata(pdev, mb);
216
217 mb->mbox.dev = &pdev->dev;
218 mb->mbox.num_chans = drv_data->num_chans;
219 mb->mbox.ops = &rockchip_mbox_chan_ops;
220 spin_lock_init(&mb->cfg_lock);
221
222 mb->mbox.txdone_poll = true;
223 ret = device_property_read_u32(&pdev->dev, "rockchip,txpoll-period-ms", &txpoll_period);
224 mb->mbox.txpoll_period = !ret ? txpoll_period : MAILBOX_POLLING_MS;
225
226 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
227 if (!res)
228 return -ENODEV;
229
230 mb->mbox_base = devm_ioremap_resource(&pdev->dev, res);
231 if (IS_ERR(mb->mbox_base))
232 return PTR_ERR(mb->mbox_base);
233
234 mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox");
235 if (IS_ERR(mb->pclk)) {
236 ret = PTR_ERR(mb->pclk);
237 dev_err(&pdev->dev, "failed to get pclk_mailbox clock: %d\n",
238 ret);
239 return ret;
240 }
241
242 ret = clk_prepare_enable(mb->pclk);
243 if (ret) {
244 dev_err(&pdev->dev, "failed to enable pclk: %d\n", ret);
245 return ret;
246 }
247
248 for (i = 0; i < mb->mbox.num_chans; i++) {
249 irq = platform_get_irq(pdev, i);
250 if (irq < 0) {
251 /* For shared irq case, only could be got one time */
252 if (i > 0 && irq == -ENXIO) {
253 mb->chans[i].irq = mb->chans[0].irq;
254 } else {
255 ret = irq;
256 goto disable_clk;
257 }
258 } else {
259 mb->chans[i].irq = irq;
260 }
261
262 mb->chans[i].idx = i;
263 mb->mbox.chans[i].con_priv = &mb->chans[i];
264 }
265
266 ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
267 if (ret < 0) {
268 dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);
269 goto disable_clk;
270 }
271
272 for (i = 0; i < mb->mbox.num_chans; i++) {
273 /* For shared irq case, only request irq thread one time */
274 if (i > 0 && mb->chans[i].irq == mb->chans[0].irq)
275 break;
276
277 ret = devm_request_threaded_irq(&pdev->dev, mb->chans[i].irq,
278 NULL,
279 rockchip_mbox_irq,
280 IRQF_ONESHOT,
281 dev_name(&pdev->dev),
282 mb);
283 if (ret < 0)
284 goto disable_clk;
285
286 if (device_property_present(&pdev->dev, "wakeup-source"))
287 enable_irq_wake(mb->chans[i].irq);
288 }
289
290 return 0;
291
292 disable_clk:
293 clk_disable_unprepare(mb->pclk);
294 return ret;
295 }
296
297 static struct platform_driver rockchip_mbox_driver = {
298 .probe = rockchip_mbox_probe,
299 .driver = {
300 .name = "rockchip-mailbox",
301 .of_match_table = of_match_ptr(rockchip_mbox_of_match),
302 },
303 };
304
305 #if defined(CONFIG_ROCKCHIP_THUNDER_BOOT)
rockchip_mbox_driver_init(void)306 static int __init rockchip_mbox_driver_init(void)
307 {
308 return platform_driver_register(&rockchip_mbox_driver);
309 }
310 core_initcall(rockchip_mbox_driver_init);
311 #else
312 module_platform_driver(rockchip_mbox_driver);
313 #endif
314
315 MODULE_LICENSE("GPL v2");
316 MODULE_DESCRIPTION("Rockchip mailbox: communicate between CPU cores and MCU");
317 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
318 MODULE_AUTHOR("Caesar Wang <wxt@rock-chips.com>");
319