1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 #include <linux/types.h>
4 #include <linux/i2c.h>
5 #include <linux/delay.h>
6
7
8 #include "vtl_ts.h"
9
10 #define FLASH_I2C_ADDR 0X7F
11 #define CHIP_ID_ADDR 0xf000
12 #define RW_FLAG 0xff
13
14 #define CHIP_WRITE_FLASH_CMD 0x55
15 #define CHIP_FLASH_SOURCE_SIZE 8
16
17 #define TB1_USE_F402 0
18
19 struct chip_cmd {
20 unsigned short addr;
21 unsigned char data;
22 };
23
24
25 static struct ts_info * ts_object = NULL;
26 static struct chip_cmd (*chip) = NULL;
27
28
29
30 enum cmd_index {
31
32 FW_VERSION = 0X00,
33 FW_CHECKSUM_CMD,
34 FW_CHECKSUM_VAL,
35 CHIP_SLEEP,
36 CHIP_ID_CMD,
37
38 /***********flash***********/
39 FLASH_SECTOR_ERASE_CMD,
40 FLASH_SECTOR_NUM,
41 FLASH_SECTOR_SIZE,
42 FLASH_MASS_ERASE_CMD
43 };
44
45 static struct chip_cmd ct360_cmd[] = {
46 {0x0f2a,RW_FLAG}, //fw version
47
48 {0x0fff,0xe1}, //fw checksum cmd
49 {0x0a0d,RW_FLAG}, //fw checksum val
50
51 {0x0f2b,0x00}, //chip sleep cmd
52
53 {0xf000,RW_FLAG}, //chip id cmd
54
55 /************flash*************/
56 {0x33,RW_FLAG}, //FLASH_SECTOR_ERASE_CMD
57 {8,RW_FLAG}, //FLASH_SECTOR_NUM
58 {2048,RW_FLAG}, //FLASH_SECTOR_SIZE
59 {RW_FLAG,RW_FLAG}, //FLASH_MASS_ERASE_CMD
60 };
61
62 static struct chip_cmd ct36x_cmd[] = {
63 {0x3fff,RW_FLAG}, //fw version
64
65 {0x8fff,0xe1}, //fw checksum cmd
66 {0x8e0e,RW_FLAG}, //fw checksum val
67
68 {0x8fff,0xaf}, //chip sleep cmd
69
70 {0xf000,RW_FLAG}, //chip id cmd
71
72 /************flash*************/
73 {0x30,RW_FLAG}, //FLASH_SECTOR_ERASE_CMD
74 {256,RW_FLAG}, //FLASH_SECTOR_NUM
75 {128,RW_FLAG}, //FLASH_SECTOR_SIZE
76 {0x33,RW_FLAG}, //FLASH_MASS_ERASE_CMD
77 };
78
79 #if 0
80 unsigned int ct36x_cmd[4][2] = {
81 {0x3fff,0x00}, //fw version
82
83 {0x0fff,0xe1}, //fw checksum cmd
84 {0x0a0d,0x00}, //fw checksum val
85
86 {0x8fff,0xaf},//chip sleep cmd
87 };
88
89 unsigned int (*chip)[2] = ct36x_cmd;
90 #endif
91
92
chip_i2c_read(struct i2c_client * client,__u16 addr,__u8 * buf,__u16 len)93 static int chip_i2c_read(struct i2c_client *client, __u16 addr, __u8 *buf, __u16 len)
94 {
95 struct i2c_msg msgs;
96 int ret;
97
98 DEBUG();
99 msgs.addr = addr;
100 msgs.flags = 0x01; // 0x00: write 0x01:read
101 msgs.len = len;
102 msgs.buf = buf;
103 //#if(PLATFORM == ROCKCHIP)
104 //msgs.scl_rate = TS_I2C_SPEED;
105 //#endif
106
107 ret = i2c_transfer(client->adapter, &msgs, 1);
108 if(ret != 1){
109 printk("___%s:i2c read error___\n",__func__);
110 return -1;
111 }
112 return 0;
113 }
114
chip_i2c_write(struct i2c_client * client,__u16 addr,__u8 * buf,__u16 len)115 static int chip_i2c_write(struct i2c_client *client, __u16 addr, __u8 *buf, __u16 len)
116 {
117 struct i2c_msg msgs;
118 int ret;
119
120 DEBUG();
121 msgs.addr = addr;
122 msgs.flags = 0x00; // 0x00: write 0x01:read
123 msgs.len = len;
124 msgs.buf = buf;
125 //#if(PLATFORM == ROCKCHIP)
126 //msgs.scl_rate = TS_I2C_SPEED;
127 //#endif
128
129 ret = i2c_transfer(client->adapter, &msgs, 1);
130 if(ret != 1){
131 printk("___%s:i2c write error___\n",__func__);
132 return -1;
133 }
134 return 0;
135 }
136
137
chip_ram_write_1byte(unsigned short addr,unsigned char data)138 static int chip_ram_write_1byte(unsigned short addr,unsigned char data)
139 {
140 struct i2c_client *client = ts_object->driver->client;
141 unsigned char buf[3];
142 int ret = 0;
143
144 DEBUG();
145 buf[0] = 0xff;
146 buf[1] = addr >> 8;
147 buf[2] = addr & 0x00ff;
148 //printk("addr = %x,buf[0] = %x,buf[1] = %x,buf[2] = %x,data = %x\n",addr,buf[0],buf[1],buf[2],data);
149 ret = chip_i2c_write(client, client->addr, buf,3);
150 if(ret)
151 {
152 return ret;
153 }
154 udelay(10);
155 buf[0] = 0x00;
156 buf[1] = data;
157 ret = chip_i2c_write(client, client->addr, buf,2);
158 udelay(10);
159 return ret;
160 }
161
chip_ram_read(unsigned short addr,unsigned char * rx_buf,unsigned short len)162 static int chip_ram_read(unsigned short addr,unsigned char *rx_buf,unsigned short len)
163 {
164 struct i2c_client *client = ts_object->driver->client;
165 unsigned char buf[3];
166 int ret = 0;
167
168 DEBUG();
169 buf[0] = 0xff;
170 buf[1] = addr >> 8;
171 buf[2] = addr & 0x00ff;
172 //printk("addr = %x,buf[0] = %x,buf[1] = %x,buf[2] = %x\n",addr,buf[0],buf[1],buf[2]);
173 ret = chip_i2c_write(client, client->addr, buf,3);
174 if(ret)
175 {
176 return ret;
177 }
178 udelay(10);
179 buf[0] = 0x00;
180 ret = chip_i2c_write(client, client->addr, buf,1);
181 udelay(10);
182 if(ret)
183 {
184 return ret;
185 }
186 udelay(10);
187 ret = chip_i2c_read(client,client->addr,rx_buf,len);
188
189 return ret;
190 }
191
chip_get_fw_version(unsigned char * buf)192 int chip_get_fw_version(unsigned char *buf)
193 {
194 int ret = 0;
195
196 DEBUG();
197 ret = chip_ram_read(chip[FW_VERSION].addr,buf,1);
198 return ret;
199 }
200
201 #if 0
202 int chip_get_chip_id(unsigned char *buf)
203 {
204 int ret = 0;
205
206 DEBUG();
207 ret = chip_ram_read(chip[CHIP_ID_CMD].addr,buf,1);
208
209 return ret;
210 }
211 #endif
212
chip_enter_sleep_mode(void)213 int chip_enter_sleep_mode(void)
214 {
215 int ret = 0;
216
217 DEBUG();
218 if(chip == NULL)
219 {
220 return -1;
221 }
222 ret = chip_ram_write_1byte(chip[CHIP_SLEEP].addr,chip[CHIP_SLEEP].data);
223 return ret;
224 }
225
226
chip_function(enum cmd_index cmd_index,unsigned char * rx_buf,unsigned char len)227 int chip_function(enum cmd_index cmd_index,unsigned char *rx_buf,unsigned char len)
228 {
229 int ret = 0;
230
231 DEBUG();
232
233 if(chip[cmd_index].data != RW_FLAG) //write
234 {
235 ret = chip_ram_write_1byte(chip[cmd_index].addr,chip[cmd_index].data);
236 }
237 else //read
238 {
239 ret = chip_ram_read(chip[cmd_index].addr,rx_buf,len);
240 }
241
242 return ret;
243 }
244
245 /***************flash********************/
246 #if 0
247 static int chip_flash_init(struct i2c_client *client)
248 {
249 unsigned char buf[2];
250 int ret = 0;
251
252 DEBUG();
253
254 buf[0] = 0x00;
255 buf[1] = 0x00;
256 ret = chip_i2c_write(client, FLASH_I2C_ADDR, buf,2);
257
258 return ret;
259 }
260 #endif
261
chip_read_bus_status(struct i2c_client * client,unsigned char * rx_buf)262 static int chip_read_bus_status(struct i2c_client *client,unsigned char *rx_buf)
263 {
264 unsigned char buf[1];
265 int ret = 0;
266
267 DEBUG();
268
269 buf[0] = 0x00;
270 ret = chip_i2c_write(client, FLASH_I2C_ADDR, buf,1);
271 if(ret)
272 {
273 return ret;
274 }
275 mdelay(1);
276 ret = chip_i2c_read(client,FLASH_I2C_ADDR,rx_buf,1);
277
278 return ret;
279 }
280
chip_enter_idle_mode(struct i2c_client * client)281 static int chip_enter_idle_mode(struct i2c_client *client)
282 {
283 unsigned char buf[2];
284 int ret = 0;
285
286 DEBUG();
287
288 buf[0] = 0x00;
289 buf[1] = 0xa5;
290 ret = chip_i2c_write(client, FLASH_I2C_ADDR, buf,2);
291 mdelay(5);
292 //mdelay(10);
293 return ret;
294 }
295
chip_solfware_reset(struct i2c_client * client)296 int chip_solfware_reset(struct i2c_client *client)
297 {
298 unsigned char buf[2];
299 int ret = 0;
300
301 DEBUG();
302
303 buf[0] = 0x00;
304 buf[1] = 0x5a;
305 ret = chip_i2c_write(client, FLASH_I2C_ADDR, buf,2);
306 msleep(200);//ct36x
307 //msleep(100);
308 return ret;
309 }
310
chip_erase_flash(struct i2c_client * client)311 static int chip_erase_flash(struct i2c_client *client)
312 {
313 unsigned char buf[4];
314 int sec,sec_addr;
315 int ret = 0;
316
317 DEBUG();
318 if(chip[FLASH_MASS_ERASE_CMD].addr == 0x33)//ct36x mass erase
319 {
320 ret = chip_read_bus_status(client,buf);
321 if(buf[0] != 0xaa)
322 {
323 printk("___i2c bus busy,bus_status = %d___\n",buf[0]);
324 return -1;
325 }
326 buf[0] = 0x00;
327 buf[1] = chip[FLASH_MASS_ERASE_CMD].addr;
328 buf[2] = 0x00;
329 buf[3] = 0x00;
330 ret = chip_i2c_write(client, FLASH_I2C_ADDR, buf,4);
331 if(ret)
332 {
333 printk("vtl chip flash erase fail\n");
334 return ret;
335 }
336 //printk("mass erase\n");
337 //mdelay(10);
338 msleep(10);
339 }
340 else //ct360/ct36x sector erase
341 {
342 for(sec = 0;sec < chip[FLASH_SECTOR_NUM].addr;sec++)
343 {
344 ret = chip_read_bus_status(client,buf);
345 if(buf[0] != 0xaa)
346 {
347 printk("___i2c bus busy,bus_status = %x,sec = %d___\n",buf[0],sec);
348 return -1;
349 }
350 sec_addr = sec * chip[FLASH_SECTOR_SIZE].addr;
351 buf[0] = 0x00;
352 buf[1] = chip[FLASH_SECTOR_ERASE_CMD].addr;
353 buf[2] = sec_addr >> 8;
354 buf[3] = sec_addr & 0x00ff;
355 ret = chip_i2c_write(client, FLASH_I2C_ADDR, buf,4);
356 if(ret)
357 {
358 printk("vtl chip flash erase fail\n");
359 return ret;
360 }
361 //msleep(10);//ct36x
362 msleep(100);//ct360
363 }
364 //printk("sector erase\n");
365 }
366 return 0;
367 }
368
369 extern unsigned char *gtpfw;
chip_set_code(unsigned int flash_addr,unsigned char * buf)370 static int chip_set_code(unsigned int flash_addr, unsigned char *buf)
371 {
372 unsigned char i;
373 static unsigned char *binary_data = NULL;
374
375 if (binary_data == NULL) {
376 binary_data = gtpfw;
377 }
378
379 buf[2] = (flash_addr >> 8);
380 buf[3] = (flash_addr & 0xFF);
381 buf[4] = 0x08;
382
383 DEBUG();
384 if ( (flash_addr == 160) || (flash_addr == 168) )
385 {
386 for(i=0;i<8;i++)
387 {
388 buf[i+6] = ~binary_data[flash_addr + i];
389 }
390 }
391 else
392 {
393 for(i=0;i<8;i++)
394 {
395 buf[i+6] = binary_data[flash_addr + i];
396 }
397 }
398 buf[5] = ~(buf[2]+buf[3]+buf[4]+buf[6]+buf[7]+buf[8]+buf[9]+buf[10]+buf[11]+buf[12]+buf[13]) + 1;
399 return buf[5];
400 }
401
chip_get_bin_checksum(void)402 static int chip_get_bin_checksum(void)
403 {
404 unsigned char buf[14];
405 int sec,cod;
406 int flash_addr;
407 unsigned short bin_checksum = 0;
408
409 DEBUG();
410 flash_addr = 0x00;
411 cod = chip[FLASH_SECTOR_NUM].addr * (chip[FLASH_SECTOR_SIZE].addr/CHIP_FLASH_SOURCE_SIZE);
412 for(sec=0;sec<cod;sec++)
413 {
414 bin_checksum += chip_set_code(flash_addr,buf);
415 flash_addr += CHIP_FLASH_SOURCE_SIZE;
416 //printk("sec = %d\n",sec);
417 }
418 return bin_checksum;
419 }
420
chip_get_fwchksum(struct i2c_client * client,int * fwchksum)421 int chip_get_fwchksum(struct i2c_client *client,int *fwchksum)
422 {
423 unsigned char buf[2];
424 int ret = 0;
425
426 DEBUG();
427 if(chip == NULL){
428 return -1;
429 }
430 ret = chip_ram_write_1byte(chip[FW_CHECKSUM_CMD].addr,chip[FW_CHECKSUM_CMD].data);
431 if(ret)
432 {
433 return -1;
434 }
435 msleep(700);
436 ret = chip_ram_read(chip[FW_CHECKSUM_VAL].addr,buf,2);
437 *fwchksum = (buf[0]<<8)|buf[1];
438 //chip_solfware_reset(client);
439 vtl_ts_hw_reset();
440 return 0;
441 }
442
chip_write_flash(struct i2c_client * client)443 static int chip_write_flash(struct i2c_client *client)
444 {
445 unsigned char buf[14];
446 #if 0
447 unsigned char bus_status[1];
448 #endif
449 int sec,cod,sec_8byte_num;
450 int flash_addr;
451 int ret = 0;
452
453 DEBUG();
454
455 buf[0] = 0x00;
456 buf[1] = CHIP_WRITE_FLASH_CMD;
457 sec_8byte_num = chip[FLASH_SECTOR_SIZE].addr/CHIP_FLASH_SOURCE_SIZE;
458 cod = chip[FLASH_SECTOR_NUM].addr * sec_8byte_num;
459 flash_addr = 0x00;
460 for(sec=0;sec<cod;)
461 {
462 chip_set_code(flash_addr,buf);
463 flash_addr += CHIP_FLASH_SOURCE_SIZE;
464 #if 0
465 ret = chip_read_bus_status(client,bus_status);
466 if(bus_status[0] != 0xaa)
467 {
468 printk("i2c bus busy,sec = %d,bus_status = %x\n",sec,bus_status[0]);
469 return -1;
470 }
471 #endif
472 ret = chip_i2c_write(client,FLASH_I2C_ADDR, buf,14);
473 if(ret)
474 {
475 return ret;
476 }
477 sec++;
478 if(!(sec%sec_8byte_num))
479 {
480 msleep(10);
481 //mdelay(10);
482 }
483 mdelay(1);//ct360
484 }
485 return 0;
486 }
487
chip_get_checksum(struct i2c_client * client,int * bin_checksum,int * fw_checksum)488 int chip_get_checksum(struct i2c_client *client,int *bin_checksum,int *fw_checksum)
489 {
490 DEBUG();
491
492 if(chip == NULL){
493 return -1;
494 }
495 *bin_checksum = chip_get_bin_checksum();
496 chip_get_fwchksum(client,fw_checksum);
497 //printk("bin_checksum = 0x%x,fw_checksum = 0x%x\n",*bin_checksum,*fw_checksum);
498 return 0;
499 }
500
update(struct i2c_client * client)501 int update(struct i2c_client *client)
502 {
503 unsigned char buf[20];
504 int ret = 0;
505 DEBUG();
506
507 if(chip == NULL)
508 {
509 return -1;
510 }
511
512 printk("___chip update start___\n");
513 ret = chip_enter_idle_mode(client);
514 if(ret)
515 {
516 return -1;
517 }
518 ret = chip_read_bus_status(client,buf);
519 if(buf[0] != 0xaa)
520 {
521 printk("___i2c bus busy,bus_status = %x___\n",buf[0]);
522 return -1;
523 }
524 ret = chip_erase_flash(client);
525 if(ret)
526 {
527 printk("___erase flash fail___\n");
528 return -1;
529 }
530 ret = chip_write_flash(client);
531 if(ret)
532 {
533 printk("___write flash fail___\n");
534 return -1;
535 }
536 vtl_ts_hw_reset();
537 printk("___chip update end___\n");
538
539 return 0;
540 }
541
542
chip_update(struct i2c_client * client)543 int chip_update(struct i2c_client *client)
544 {
545 int bin_checksum = 0xff;
546 int fw_checksum = 0;
547 int cnt = 0;
548
549 DEBUG();
550 if(chip == NULL)
551 {
552 return -1;
553 }
554
555 chip_get_checksum(client,&bin_checksum,&fw_checksum);
556 printk("bin_checksum = 0x%x,fw_checksum = 0x%x\n",bin_checksum,fw_checksum);
557 cnt = 2;
558 while((bin_checksum != fw_checksum) && (cnt--))
559 {
560 if(update(client) < 0)
561 {
562 vtl_ts_hw_reset();
563 continue;
564 }
565 chip_get_fwchksum(client,&fw_checksum);
566 printk("bin_checksum = %x,fw_checksum = %x,cnt = %d\n",bin_checksum,fw_checksum,cnt);
567 }
568
569 if(bin_checksum != fw_checksum)
570 {
571 return -1;
572 }
573 return 0;
574 }
575
576 /*
577 int chip_update(struct i2c_client *client)
578 {
579 unsigned char buf[20];
580 int bin_checksum,fw_checksum,cnt;
581 int ret = 0;
582
583 DEBUG();
584
585 if(chip == NULL)
586 {
587 return -1;
588 }
589 bin_checksum = chip_get_bin_checksum();
590 chip_get_fwchksum(client,&fw_checksum);
591 printk("bin_checksum = %x,fw_checksum = %x\n",bin_checksum,fw_checksum);
592 cnt = 2;
593 while((bin_checksum != fw_checksum) && (cnt--))
594 //while(cnt--)
595 {
596 printk("___chip update start___\n");
597 ret = chip_enter_idle_mode(client);
598 if(ret)
599 {
600 //return ret;
601 continue;
602 }
603 ret = chip_read_bus_status(client,buf);
604 if(buf[0] != 0xaa)
605 {
606 printk("___i2c bus busy,bus_status = %x___\n",buf[0]);
607 //return ret;
608 continue;
609 }
610 ret = chip_erase_flash(client);
611 if(ret)
612 {
613 printk("___erase flash fail___\n");
614 //return ret;
615 continue;
616 }
617 ret = chip_write_flash(client);
618 if(ret)
619 {
620 printk("___write flash fail___\n");
621 //return ret;
622 continue;
623 }
624 vtl_ts_hw_reset();
625 //chip_solfware_reset(client);
626 ret = chip_get_fwchksum(client,&fw_checksum);
627 if(ret)
628 {
629 printk("___get fwchksum fail___\n");
630 //return ret;
631 continue;
632 }
633 printk("___chip update end___\n");
634 printk("bin_checksum = %x,fw_checksum = %x\n",bin_checksum,fw_checksum);
635 }
636 //vtl_ts_hw_reset();
637 if(bin_checksum != fw_checksum)
638 {
639 return -1;
640 }
641 return 0;
642 }
643 */
644
chip_get_chip_id(struct i2c_client * client,unsigned char * rx_buf)645 int chip_get_chip_id(struct i2c_client *client,unsigned char *rx_buf)
646 {
647 unsigned char buf[3];
648 int ret = 0;
649
650 DEBUG();
651 ret = chip_enter_idle_mode(client);
652 if(ret)
653 {
654 return ret;
655 }
656 ret = chip_read_bus_status(client,buf);
657 if(buf[0]!= 0xaa)
658 {
659 printk("___i2c bus status = %x,ret = %d___\n",buf[0],ret);
660 return -1;
661 }
662 mdelay(1);
663
664 buf[0] = 0xff;
665 buf[1] = CHIP_ID_ADDR>>8;
666 buf[2] = CHIP_ID_ADDR & 0x00ff;
667 ret = chip_i2c_write(client,0x01, buf,3);
668 if(ret)
669 {
670 return ret;
671 }
672 mdelay(1);
673 buf[0] = 0x00;
674 ret = chip_i2c_write(client,0x01, buf,1);
675 if(ret)
676 {
677 return ret;
678 }
679 mdelay(1);
680 ret = chip_i2c_read(client,0x01,rx_buf,1);
681 //chip_solfware_reset(client);
682 vtl_ts_hw_reset();
683
684 //printk("___chip ID = %d___\n",*rx_buf);
685 return ret;
686
687 }
688
689
chip_read_infoblk(struct i2c_client * client)690 static int chip_read_infoblk(struct i2c_client *client)
691 {
692 unsigned char buf[20] = {0};
693
694 DEBUG();
695
696 buf[0] = 0x00;
697 buf[1] = 0x62;
698 buf[2] = 0x00;
699 buf[3] = 0x00;
700 buf[4] = 0x08;
701
702 chip_i2c_write(client,0x7F, buf,5);
703 mdelay(1);
704 chip_i2c_read(client,0x7f, buf,14);
705
706 if(buf[5] & 0x10)
707 {
708
709 return 0;
710 }
711 return 1;
712 }
713
chip_erase_infoblk(struct i2c_client * client)714 static int chip_erase_infoblk(struct i2c_client *client)
715 {
716 unsigned char buf[20]={0};
717 int ret = -1;
718
719 DEBUG();
720
721 // info block erase command
722 buf[0] = 0x00;
723 buf[1] = 0x60;
724 buf[2] = 0x00;
725 chip_i2c_write(client, 0x7F, buf, 3);
726 mdelay(10);
727
728 ret = chip_read_bus_status(client,buf);
729 if(buf[0]!= 0xaa)
730 {
731 printk("___i2c bus status = %x,ret = %d___\n",buf[0],ret);
732 return -1;
733 }
734 return 0;
735 }
736
chip_write_infoblk(struct i2c_client * client)737 static int chip_write_infoblk(struct i2c_client *client)
738 {
739 //int ret = -1;
740 unsigned char buf[20]={0};
741 int cod;
742 unsigned int flash_addr;
743
744 DEBUG();
745
746 flash_addr = 0x00;
747
748 // write info block 0
749 buf[0] = 0x00;
750 buf[1] = 0x61;
751
752 for ( cod = 0; cod < 16; cod++ ) {
753 // Flash address
754 // data length
755 buf[2] = (char)(flash_addr >> 8);
756 buf[3] = (char)(flash_addr & 0xFF);
757 buf[4] = 0x08;
758 if ( flash_addr == 0x0000 )
759 buf[6] = 0x17;
760 else
761 buf[6] = 0x00;
762
763 buf[7] = 0x00;
764 buf[8] = 0x00;
765 buf[9] = 0x00;
766 buf[10] = 0x00;
767 buf[11] = 0x00;
768 buf[12] = 0x00;
769 buf[13] = 0x00;
770
771 buf[5] = (~(buf[2]+buf[3]+buf[4]+buf[6]+buf[7]+buf[8]+buf[9]+buf[10]+buf[11]+buf[12]+buf[13]))+1;
772
773 chip_i2c_write(client, 0x7F, buf, 14);
774 mdelay(10);
775
776 flash_addr += 8;
777 }
778
779 return 0;
780 }
781
chip_trim_info_init(struct i2c_client * client)782 static int chip_trim_info_init(struct i2c_client *client)
783 {
784 int retry =5;
785
786 while(chip_read_infoblk(client) && (retry--))
787 {
788 chip_erase_infoblk(client);
789 chip_write_infoblk(client);
790 }
791 vtl_ts_hw_reset();
792 return 0;
793 }
794
chip_init(void)795 int chip_init(void)
796 {
797 struct i2c_client *client;
798 unsigned char chip_id = 0xff;
799 unsigned char retry;
800 int ret = 0;
801
802 DEBUG();
803
804 ts_object = vtl_ts_get_object();
805
806 if(ts_object == NULL)
807 {
808 return -1;
809 }
810 client = ts_object->driver->client;
811
812 chip = NULL;
813 for(retry = 0;retry<3;retry++)
814 {
815 ret = chip_get_chip_id(client,&chip_id);
816 printk("___chip ID = %d___cnt = %d\n",chip_id,retry);
817 switch(chip_id)
818 {
819 case 1: { //chip: CT362, CT363, CT365, CT368, CT369
820 chip = ct36x_cmd;
821 chip_trim_info_init(client);
822 }break;
823
824 case 2: { //chip: CT360
825 chip = ct360_cmd;
826 }break;
827
828 case 6: { //chip: CT362M, CT363M, CT365M, CT368M, CT369M
829 chip = ct36x_cmd;
830 }break;
831
832 default : {
833
834 chip = NULL;
835 }
836 }
837 if(chip != NULL)
838 {
839 break;
840 }
841 }
842
843 if(chip == NULL)
844 {
845 return -1;
846 }
847
848 #if(CHIP_UPDATE_ENABLE)
849 if(chip_update(client)<0)
850 {
851 printk("___chip updata faile___\n");
852 return -1;
853 }
854 #endif
855
856 return 0;
857 }
858
859
860
861