1 /* 2 * Copyright (C) 2012 UPI semi <Finley_huang@upi-semi.com>. All Rights Reserved. 3 * 5152 Light Sensor Driver for Linux 2.6 4 */ 5 6 /* 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #ifndef __us5152_H__ 23 #define __us5152_H__ 24 25 #include <linux/types.h> 26 27 #define PWR_MODE_DOWN_MASK 0x80 28 #define PWR_MODE_OPERATE_MASK 0x7F 29 30 31 /*us5152 Slave Addr*/ 32 #define LIGHT_ADDR 0x72 33 34 /*Interrupt PIN for S3C6410*/ 35 #define IRQ_LIGHT_INT IRQ_EINT(6) 36 37 /*Register Set*/ 38 #define REGS_CR0 0x00 39 #define REGS_CR1 0x01 40 #define REGS_CR2 0x02 41 #define REGS_CR3 0x03 42 //ALS 43 #define REGS_INT_LSB_TH_LO 0x04 44 #define REGS_INT_MSB_TH_LO 0x05 45 #define REGS_INT_LSB_TH_HI 0x06 46 #define REGS_INT_MSB_TH_HI 0x07 47 //ALS data 48 #define REGS_LBS_SENSOR 0x0C 49 #define REGS_MBS_SENSOR 0x0D 50 51 #define REGS_CR10 0x10 52 #define REGS_CR11 0x11 53 #define REGS_VERSION_ID 0x1F 54 #define REGS_CHIP_ID 0xB2 55 56 /*ShutDown_EN*/ 57 #define CR0_OPERATION 0x0 58 #define CR0_SHUTDOWN_EN 0x1 59 60 #define CR0_SHUTDOWN_SHIFT (7) 61 #define CR0_SHUTDOWN_MASK (0x1 << CR0_SHUTDOWN_SHIFT) 62 63 /*OneShot_EN*/ 64 #define CR0_ONESHOT_EN 0x01 65 66 #define CR0_ONESHOT_SHIFT (6) 67 #define CR0_ONESHOT_MASK (0x1 << CR0_ONESHOT_SHIFT) 68 69 /*Operation Mode*/ 70 #define CR0_OPMODE_ALSANDPS 0x0 71 #define CR0_OPMODE_ALSONLY 0x1 72 #define CR0_OPMODE_IRONLY 0x2 73 74 #define CR0_OPMODE_SHIFT (4) 75 #define CR0_OPMODE_MASK (0x3 << CR0_OPMODE_SHIFT) 76 77 /*all int flag (PROX, INT_A, INT_P)*/ 78 #define CR0_ALL_INT_CLEAR 0x0 79 80 #define CR0_ALL_INT_SHIFT (1) 81 #define CR0_ALL_INT_MASK (0x7 << CR0_ALL_INT_SHIFT) 82 83 84 /*indicator of object proximity detection*/ 85 #define CR0_PROX_CLEAR 0x0 86 87 #define CR0_PROX_SHIFT (3) 88 #define CR0_PROX_MASK (0x1 << CR0_PROX_SHIFT) 89 90 /*interrupt status of proximity sensor*/ 91 #define CR0_INTP_CLEAR 0x0 92 93 #define CR0_INTP_SHIFT (2) 94 #define CR0_INTP_MASK (0x1 << CR0_INTP_SHIFT) 95 96 /*interrupt status of ambient sensor*/ 97 #define CR0_INTA_CLEAR 0x0 98 99 #define CR0_INTA_SHIFT (1) 100 #define CR0_INTA_MASK (0x1 << CR0_INTA_SHIFT) 101 102 /*Word mode enable*/ 103 #define CR0_WORD_EN 0x1 104 105 #define CR0_WORD_SHIFT (0) 106 #define CR0_WORD_MASK (0x1 << CR0_WORD_SHIFT) 107 108 109 /*ALS fault queue depth for interrupt enent output*/ 110 #define CR1_ALS_FQ_1 0x0 111 #define CR1_ALS_FQ_4 0x1 112 #define CR1_ALS_FQ_8 0x2 113 #define CR1_ALS_FQ_16 0x3 114 #define CR1_ALS_FQ_24 0x4 115 #define CR1_ALS_FQ_32 0x5 116 #define CR1_ALS_FQ_48 0x6 117 #define CR1_ALS_FQ_63 0x7 118 119 #define CR1_ALS_FQ_SHIFT (5) 120 #define CR1_ALS_FQ_MASK (0x7 << CR1_ALS_FQ_SHIFT) 121 122 /*resolution for ALS*/ 123 #define CR1_ALS_RES_12BIT 0x0 124 #define CR1_ALS_RES_14BIT 0x1 125 #define CR1_ALS_RES_16BIT 0x2 126 #define CR1_ALS_RES_16BIT_2 0x3 127 128 #define CR1_ALS_RES_SHIFT (3) 129 #define CR1_ALS_RES_MASK (0x3 << CR1_ALS_RES_SHIFT) 130 131 /*sensing amplifier selection for ALS*/ 132 #define CR1_ALS_GAIN_X1 0x0 133 #define CR1_ALS_GAIN_X2 0x1 134 #define CR1_ALS_GAIN_X4 0x2 135 #define CR1_ALS_GAIN_X8 0x3 136 #define CR1_ALS_GAIN_X16 0x4 137 #define CR1_ALS_GAIN_X32 0x5 138 #define CR1_ALS_GAIN_X64 0x6 139 #define CR1_ALS_GAIN_X128 0x7 140 141 #define CR1_ALS_GAIN_SHIFT (0) 142 #define CR1_ALS_GAIN_MASK (0x7 << CR1_ALS_GAIN_SHIFT) 143 144 145 /*PS fault queue depth for interrupt event output*/ 146 #define CR2_PS_FQ_1 0x0 147 #define CR2_PS_FQ_4 0x1 148 #define CR2_PS_FQ_8 0x2 149 #define CR2_PS_FQ_15 0x3 150 151 #define CR2_PS_FQ_SHIFT (6) 152 #define CR2_PS_FQ_MASK (0x3 << CR2_PS_FQ_SHIFT) 153 154 /*interrupt type setting */ 155 /*low active*/ 156 #define CR2_INT_LEVEL 0x0 157 /*low pulse*/ 158 #define CR2_INT_PULSE 0x1 159 160 #define CR2_INT_SHIFT (5) 161 #define CR2_INT_MASK (0x1 << CR2_INT_SHIFT) 162 163 /*resolution for PS*/ 164 #define CR2_PS_RES_12 0x0 165 #define CR2_PS_RES_14 0x1 166 #define CR2_PS_RES_16 0x2 167 #define CR2_PS_RES_16_2 0x3 168 169 #define CR2_PS_RES_SHIFT (3) 170 #define CR2_PS_RES_MASK (0x3 << CR2_PS_RES_SHIFT) 171 172 /*sensing amplifier selection for PS*/ 173 #define CR2_PS_GAIN_1 0x0 174 #define CR2_PS_GAIN_2 0x1 175 #define CR2_PS_GAIN_4 0x2 176 #define CR2_PS_GAIN_8 0x3 177 #define CR2_PS_GAIN_16 0x4 178 #define CR2_PS_GAIN_32 0x5 179 #define CR2_PS_GAIN_64 0x6 180 #define CR2_PS_GAIN_128 0x7 181 182 #define CR2_PS_GAIN_SHIFT (0) 183 #define CR2_PS_GAIN_MASK (0x7 << CR2_PS_GAIN_SHIFT) 184 185 /*wait-time slot selection*/ 186 #define CR3_WAIT_SEL_0 0x0 187 #define CR3_WAIT_SEL_4 0x1 188 #define CR3_WAIT_SEL_8 0x2 189 #define CR3_WAIT_SEL_16 0x3 190 191 #define CR3_WAIT_SEL_SHIFT (6) 192 #define CR3_WAIT_SEL_MASK (0x3 << CR3_WAIT_SEL_SHIFT) 193 194 /*IR-LED drive peak current setting*/ 195 #define CR3_LEDDR_12_5 0x0 196 #define CR3_LEDDR_25 0x1 197 #define CR3_LEDDR_50 0x2 198 #define CR3_LEDDR_100 0x3 199 200 #define CR3_LEDDR_SHIFT (4) 201 #define CR3_LEDDR_MASK (0x3 << CR3_LEDDR_SHIFT) 202 203 /*INT pin source selection*/ 204 #define CR3_INT_SEL_BATH 0x0 205 #define CR3_INT_SEL_ALS 0x1 206 #define CR3_INT_SEL_PS 0x2 207 #define CR3_INT_SEL_PSAPP 0x3 208 209 #define CR3_INT_SEL_SHIFT (2) 210 #define CR3_INT_SEL_MASK (0x3 << CR3_INT_SEL_SHIFT) 211 212 /*software reset for register and core*/ 213 #define CR3_SOFTRST_EN 0x1 214 215 #define CR3_SOFTRST_SHIFT (0) 216 #define CR3_SOFTRST_MASK (0x1 << CR3_SOFTRST_SHIFT) 217 218 /*modulation frequency of LED driver*/ 219 #define CR10_FREQ_DIV2 0x0 220 #define CR10_FREQ_DIV4 0x1 221 #define CR10_FREQ_DIV8 0x2 222 #define CR10_FREQ_DIV16 0x3 223 224 #define CR10_FREQ_SHIFT (1) 225 #define CR10_FREQ_MASK (0x3 << CR10_FREQ_SHIFT) 226 227 /*50/60 Rejection enable*/ 228 #define CR10_REJ_5060_DIS 0x00 229 #define CR10_REJ_5060_EN 0x01 230 231 #define CR10_REJ_5060_SHIFT (0) 232 #define CR10_REJ_5060_MASK (0x1 << CR10_REJ_5060_SHIFT) 233 234 #define us5152_NUM_CACHABLE_REGS 0x12 235 #endif 236