1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * UCS12CM0 illuminance and correlated color temperature sensor
4 *
5 * Copyright (C) 2022-2025 ROCKCHIP.
6 * Author: Jason Zhang <jason.zhang@rock-chips.com>
7 *
8 * IIO driver for UCS12CM0 (7-bit I2C slave address 0x38)
9 */
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/i2c.h>
13 #include <linux/mutex.h>
14 #include <linux/err.h>
15 #include <linux/of.h>
16 #include <linux/delay.h>
17 #include <linux/util_macros.h>
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
20 #include <linux/gpio.h>
21 #include <linux/of_gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/iio/triggered_buffer.h>
24 #include <linux/iio/kfifo_buf.h>
25 #include <linux/iio/buffer.h>
26
27 #define UCS12CM0_SYS_CTRL 0x00
28 #define UCS12CM0_INT_CTRL 0x01
29 #define UCS12CM0_INT_FLAG 0x02
30 #define UCS12CM0_WAIT 0x03
31 #define UCS12CM0_ALS_GAIN 0x04
32 #define UCS12CM0_ALS_TIME 0x05
33 #define UCS12CM0_PS_LED 0x06
34 #define UCS12CM0_PS_GAIN 0x07
35 #define UCS12CM0_PS_PULSE 0x08
36 #define UCS12CM0_PS_TIME 0x09
37 #define UCS12CM0_PS_AVERAGE 0x0a
38 #define UCS12CM0_PS_PERSIST 0x0b
39 #define UCS12CM0_ALS_THDLL 0x0c
40 #define UCS12CM0_ALS_THDLH 0x0d
41 #define UCS12CM0_ALS_THDHL 0x0e
42 #define UCS12CM0_ALS_THDHH 0x0f
43 #define UCS12CM0_PS_THDLL 0x10
44 #define UCS12CM0_PS_THDLH 0x11
45 #define UCS12CM0_PS_THDHL 0x12
46 #define UCS12CM0_PS_THDHH 0x13
47 #define UCS12CM0_PS_OFFSET_L 0x14
48 #define UCS12CM0_PS_OFFSET_H 0x15
49 #define UCS12CM0_PS_DATA_L 0x18
50 #define UCS12CM0_PS_DATA_H 0x19
51 #define UCS12CM0_CLS_R_DATA_L 0x1c
52 #define UCS12CM0_CLS_R_DATA_H 0x1d
53 #define UCS12CM0_CLS_G_DATA_L 0x1e
54 #define UCS12CM0_CLS_G_DATA_H 0x1f
55 #define UCS12CM0_CLS_B_DATA_L 0x20
56 #define UCS12CM0_CLS_B_DATA_H 0x21
57 #define UCS12CM0_CLS_W_DATA_L 0x22
58 #define UCS12CM0_CLS_W_DATA_H 0x23
59 #define UCS12CM0_IR_DATA_L 0x24
60 #define UCS12CM0_IR_DATA_H 0x25
61 #define UCS12CM0_ID 0xbc
62
63 /* bis of the SYS_CTRL register */
64 #define UCS12CM0_EN_CLS BIT(0) /* Enables CLS function */
65 #define UCS12CM0_EN_IR BIT(1) /* Enables IR function */
66 #define UCS12CM0_EN_FRST BIT(5) /* Enables Brown Out Reset circuit */
67 #define UCS12CM0_EN_WAIT BIT(6) /* Waiting time will be inserted between two
68 * measurements
69 */
70 #define UCS12CM0_SWRST BIT(7) /* Software reset. Reset all register to
71 * default value
72 */
73
74 /* bis of the INT_FLAG register */
75 #define UCS12CM0_INT_CLS BIT(0) /* CLS Interrupt flag. It correlation with
76 * sensor data and CLS high/low threshold.
77 * Write zero to clear the flag.
78 */
79 #define UCS12CM0_INT_DATA BIT(6)/* It shows if any data is invalid after
80 * completion of each conversion cycle. This
81 * bit is read-only.
82 */
83 #define UCS12CM0_INT_POR BIT(7) /* Power-On-Reset Interrupt flag trigger the
84 * INT pin when the flag sets to one. Write
85 * zero to clear the flag.
86 */
87
88 #define UCS12CM0_CCT_CHANNEL(_si, _mod) { \
89 .type = IIO_CCT, \
90 .address = _si, \
91 .channel2 = _mod, \
92 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
93 BIT(IIO_CHAN_INFO_SCALE) | \
94 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
95 .modified = 1, \
96 .scan_index = _si, \
97 .scan_type = { \
98 .sign = 'u', \
99 .realbits = 16, \
100 .storagebits = 16, \
101 }, \
102 }
103
104 enum {
105 UCS12CM0_CCT_READ,
106 UCS12CM0_CCT_GREEN,
107 UCS12CM0_CCT_BLUE,
108 UCS12CM0_CCT_WHITE,
109 UCS12CM0_CCT_ALL
110 };
111
112 struct ucs12cm0_scan {
113 u16 chans[4];
114 /* Ensure natural alignment of timestamp */
115 s64 timestamp;
116 };
117
118 struct ucs12cm0_data {
119 struct i2c_client *client;
120 int calibrated;
121 u32 raw[UCS12CM0_CCT_ALL];
122 u32 average[UCS12CM0_CCT_ALL];
123 };
124
125 static const u8 ucs12cm0_chan_regs[UCS12CM0_CCT_ALL] = {
126 UCS12CM0_CLS_R_DATA_L,
127 UCS12CM0_CLS_G_DATA_L,
128 UCS12CM0_CLS_B_DATA_L,
129 UCS12CM0_CLS_W_DATA_L
130 };
131
132 static const struct iio_chan_spec ucs12cm0_channels[] = {
133 UCS12CM0_CCT_CHANNEL(UCS12CM0_CCT_READ, IIO_MOD_LIGHT_RED),
134 UCS12CM0_CCT_CHANNEL(UCS12CM0_CCT_GREEN, IIO_MOD_LIGHT_GREEN),
135 UCS12CM0_CCT_CHANNEL(UCS12CM0_CCT_BLUE, IIO_MOD_LIGHT_BLUE),
136 UCS12CM0_CCT_CHANNEL(UCS12CM0_CCT_WHITE, IIO_MOD_LIGHT_CLEAR),
137 IIO_CHAN_SOFT_TIMESTAMP(4),
138 };
139
ucs12cm0_read(struct i2c_client * client,u8 cmd,void * databuf,u8 len)140 static int ucs12cm0_read(struct i2c_client *client, u8 cmd, void *databuf,
141 u8 len)
142 {
143 struct i2c_msg msgs[2] = {
144 {
145 .addr = client->addr,
146 .len = sizeof(cmd),
147 .buf = (u8 *) &cmd
148 }, {
149 .addr = client->addr,
150 .len = len,
151 .buf = databuf,
152 .flags = I2C_M_RD
153 }
154 };
155 int ret;
156
157 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
158 if (ret < 0)
159 dev_err(&client->dev, "failed reading register 0x%04x\n", cmd);
160
161 return ret;
162 }
163
ucs12cm0_read_byte(struct i2c_client * client,u8 cmd)164 static int ucs12cm0_read_byte(struct i2c_client *client, u8 cmd)
165 {
166 u8 data;
167 int ret;
168
169 ret = ucs12cm0_read(client, cmd, &data, sizeof(data));
170 if (ret < 0)
171 return ret;
172
173 return data;
174 }
175
ucs12cm0_read_word(struct i2c_client * client,u8 cmd)176 static int ucs12cm0_read_word(struct i2c_client *client, u8 cmd)
177 {
178 __le16 data;
179 int ret;
180
181 ret = ucs12cm0_read(client, cmd, &data, sizeof(data));
182 if (ret < 0)
183 return ret;
184
185 return le16_to_cpu(data);
186 }
187
ucs12cm0_read_average(struct ucs12cm0_data * data,int chan)188 static int ucs12cm0_read_average(struct ucs12cm0_data *data, int chan)
189 {
190 u8 cmd;
191 int sum = 0;
192 int average;
193 int i;
194 int ret;
195
196 cmd = ucs12cm0_chan_regs[chan];
197 for (i = 0; i < 10; ++i) {
198 ret = ucs12cm0_read_word(data->client, cmd);
199 if (ret < 0)
200 return ret;
201
202 sum += ret;
203 }
204
205 average = sum / 10;
206
207 return average;
208 }
209
ucs12cm0_write_byte(struct i2c_client * client,u8 cmd,u8 val)210 static int ucs12cm0_write_byte(struct i2c_client *client, u8 cmd, u8 val)
211 {
212 u8 buf[2];
213 struct i2c_msg msgs[1] = {
214 {
215 .addr = client->addr,
216 .len = sizeof(buf),
217 .buf = (u8 *) &buf
218 }
219 };
220 int ret;
221
222 buf[0] = cmd;
223 buf[1] = val;
224
225 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
226 if (ret < 0) {
227 dev_err(&client->dev, "failed writing register 0x%04x\n", cmd);
228 return ret;
229 }
230
231 return 0;
232 }
233
ucs12cm0_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)234 static int ucs12cm0_read_raw(struct iio_dev *indio_dev,
235 struct iio_chan_spec const *chan,
236 int *val, int *val2, long mask)
237 {
238 struct ucs12cm0_data *data = iio_priv(indio_dev);
239 u8 cmd;
240 int ret;
241
242 switch (mask) {
243 case IIO_CHAN_INFO_RAW:
244 cmd = ucs12cm0_chan_regs[chan->address];
245 ret = ucs12cm0_read_word(data->client, cmd);
246 if (ret < 0)
247 return ret;
248 *val = ret;
249
250 return IIO_VAL_INT;
251
252 case IIO_CHAN_INFO_SCALE:
253 if (data->calibrated) {
254 *val = data->average[chan->address];
255 *val2 = data->raw[chan->address];
256 } else {
257 *val = 1;
258 *val2 = 1;
259 }
260
261 return IIO_VAL_FRACTIONAL;
262
263 case IIO_CHAN_INFO_AVERAGE_RAW:
264 *val = data->average[chan->address];
265
266 return IIO_VAL_INT;
267
268 default:
269 return -EINVAL;
270 }
271 }
272
ucs12cm0_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)273 static int ucs12cm0_write_raw(struct iio_dev *indio_dev,
274 struct iio_chan_spec const *chan,
275 int val, int val2, long mask)
276 {
277 struct ucs12cm0_data *data = iio_priv(indio_dev);
278
279 switch (mask) {
280 case IIO_CHAN_INFO_RAW:
281 data->raw[chan->address] = val;
282
283 return 0;
284
285 case IIO_CHAN_INFO_SCALE:
286 return -EPERM;
287
288 case IIO_CHAN_INFO_AVERAGE_RAW:
289 return -EPERM;
290
291 default:
292 return -EINVAL;
293 }
294 }
295
ucs12cm0_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)296 static int ucs12cm0_write_raw_get_fmt(struct iio_dev *indio_dev,
297 struct iio_chan_spec const *chan,
298 long mask)
299 {
300 switch (mask) {
301 case IIO_CHAN_INFO_RAW:
302 return IIO_VAL_INT;
303 case IIO_CHAN_INFO_SCALE:
304 return IIO_VAL_FRACTIONAL;
305 case IIO_CHAN_INFO_AVERAGE_RAW:
306 return IIO_VAL_INT;
307 default:
308 return -EINVAL;
309 }
310 }
311
start_calibrating_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)312 static ssize_t start_calibrating_store(struct device *dev,
313 struct device_attribute *attr,
314 const char *buf, size_t len)
315 {
316 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
317 struct ucs12cm0_data *data = iio_priv(indio_dev);
318 int i;
319 long chans = 0;
320 int ret;
321
322 if (!strncmp(buf, "red", 3)) {
323 set_bit(UCS12CM0_CCT_READ, &chans);
324 } else if (!strncmp(buf, "green", 5)) {
325 set_bit(UCS12CM0_CCT_GREEN, &chans);
326 } else if (!strncmp(buf, "blue", 4)) {
327 set_bit(UCS12CM0_CCT_BLUE, &chans);
328 } else if (!strncmp(buf, "white", 5)) {
329 set_bit(UCS12CM0_CCT_WHITE, &chans);
330 } else if (!strncmp(buf, "all", 3)) {
331 set_bit(UCS12CM0_CCT_READ, &chans);
332 set_bit(UCS12CM0_CCT_GREEN, &chans);
333 set_bit(UCS12CM0_CCT_BLUE, &chans);
334 set_bit(UCS12CM0_CCT_WHITE, &chans);
335 } else {
336 return -EINVAL;
337 }
338
339 for_each_set_bit(i, &chans, UCS12CM0_CCT_ALL) {
340 if (!data->raw[i])
341 return -EPERM;
342
343 dev_info(&data->client->dev, "raw = %d\n",
344 data->raw[i]);
345 }
346
347 for_each_set_bit(i, &chans, UCS12CM0_CCT_ALL) {
348 ret = ucs12cm0_read_average(data, i);
349 if (ret < 0)
350 return ret;
351 else if (ret == 0)
352 return -EINVAL;
353
354 data->average[i] = ret;
355
356 dev_info(&data->client->dev, "average = %d\n",
357 data->average[i]);
358 }
359
360 /*
361 * TODO: store the calibration data in the ROM because UCS12CM0
362 * doesn't have any rom-related register.
363 */
364 data->calibrated = 1;
365
366 return len;
367 }
368
369 static IIO_DEVICE_ATTR_WO(start_calibrating, 0);
370
371 static struct attribute *ucs12cm0_attributes[] = {
372 &iio_dev_attr_start_calibrating.dev_attr.attr,
373 NULL
374 };
375
376 static const struct attribute_group ucs12cm0_attribute_group = {
377 .attrs = ucs12cm0_attributes,
378 };
379
380 static const struct iio_info ucs12cm0_info = {
381 .read_raw = ucs12cm0_read_raw,
382 .write_raw = ucs12cm0_write_raw,
383 .write_raw_get_fmt = ucs12cm0_write_raw_get_fmt,
384 .attrs = &ucs12cm0_attribute_group,
385 };
386
387 /**
388 * ucs12cm0_active - enable or disable the CLS
389 * @client: the i2c client used by the driver.
390 * @enable: enable/disable the CLS of ucs12cm0.
391 *
392 * Returns negative errno, else the number of messages executed.
393 */
ucs12cm0_active(struct i2c_client * client,int enable)394 static int ucs12cm0_active(struct i2c_client *client, int enable)
395 {
396 u8 val;
397 int ret = 0;
398
399 ret = ucs12cm0_read_byte(client, UCS12CM0_SYS_CTRL);
400 if (ret < 0)
401 goto out;
402
403 val = ret;
404 if (enable)
405 val |= UCS12CM0_EN_CLS;
406 else
407 val &= ~UCS12CM0_EN_CLS;
408
409 ret = ucs12cm0_write_byte(client, UCS12CM0_SYS_CTRL, val);
410 if (ret < 0)
411 dev_err(&client->dev, "Failed to active sensor\n");
412
413 out:
414 return ret;
415 }
416
ucs12cm0_buffer_postenable(struct iio_dev * indio_dev)417 static int ucs12cm0_buffer_postenable(struct iio_dev *indio_dev)
418 {
419 struct ucs12cm0_data *data = iio_priv(indio_dev);
420
421 return ucs12cm0_active(data->client, 1);
422 }
423
ucs12cm0_buffer_predisable(struct iio_dev * indio_dev)424 static int ucs12cm0_buffer_predisable(struct iio_dev *indio_dev)
425 {
426 struct ucs12cm0_data *data = iio_priv(indio_dev);
427
428 return ucs12cm0_active(data->client, 0);
429 }
430
431 static const struct iio_buffer_setup_ops ucs12cm0_buffer_setup_ops = {
432 .postenable = ucs12cm0_buffer_postenable,
433 .predisable = ucs12cm0_buffer_predisable,
434 };
435
ucs12cm0_init(struct ucs12cm0_data * data)436 static int ucs12cm0_init(struct ucs12cm0_data *data)
437 {
438 int ret;
439 struct i2c_client *client = data->client;
440
441 ret = ucs12cm0_write_byte(client, UCS12CM0_SYS_CTRL, 0x00);
442 if (ret < 0)
443 goto err;
444
445 ret = ucs12cm0_write_byte(client, UCS12CM0_INT_CTRL, 0x13);
446 if (ret < 0)
447 goto err;
448
449 ret = ucs12cm0_write_byte(client, UCS12CM0_INT_FLAG, 0x00);
450 if (ret < 0)
451 goto err;
452
453 ret = ucs12cm0_write_byte(client, UCS12CM0_WAIT, 0x00);
454 if (ret < 0)
455 goto err;
456
457 ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_GAIN, 0x84);
458 if (ret < 0)
459 goto err;
460
461 ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_TIME, 0x33);
462 if (ret < 0)
463 goto err;
464
465 ret = ucs12cm0_write_byte(client, UCS12CM0_PS_LED, 0x00);
466 if (ret < 0)
467 goto err;
468
469 ret = ucs12cm0_write_byte(client, UCS12CM0_PS_GAIN, 0x00);
470 if (ret < 0)
471 goto err;
472
473 ret = ucs12cm0_write_byte(client, UCS12CM0_PS_PULSE, 0x00);
474 if (ret < 0)
475 goto err;
476
477 ret = ucs12cm0_write_byte(client, UCS12CM0_PS_TIME, 0x0f);
478 if (ret < 0)
479 goto err;
480
481 ret = ucs12cm0_write_byte(client, UCS12CM0_PS_AVERAGE, 0x0f);
482 if (ret < 0)
483 goto err;
484
485 ret = ucs12cm0_write_byte(client, UCS12CM0_PS_PERSIST, 0x00);
486 if (ret < 0)
487 goto err;
488
489 ret = ucs12cm0_write_byte(client, UCS12CM0_PS_OFFSET_L, 0x0000);
490 if (ret < 0)
491 goto err;
492
493 ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_THDHL, 0xff);
494 if (ret < 0)
495 goto err;
496
497 ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_THDHH, 0xff);
498 if (ret < 0)
499 goto err;
500
501 ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_THDLL, 0x00);
502 if (ret < 0)
503 goto err;
504
505 ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_THDLH, 0x00);
506 if (ret < 0)
507 goto err;
508
509 return 0;
510
511 err:
512 return ret;
513 }
514
ucs12cm0_interrupt_handler(int irq,void * priv)515 static irqreturn_t ucs12cm0_interrupt_handler(int irq, void *priv)
516 {
517 struct iio_dev *indio_dev = priv;
518 struct ucs12cm0_data *data = iio_priv(indio_dev);
519 struct i2c_client *client = data->client;
520 struct ucs12cm0_scan scan;
521 int ret;
522
523 ret = ucs12cm0_read_byte(client, UCS12CM0_INT_FLAG);
524 if (ret < 0)
525 goto out;
526
527 if (ret & UCS12CM0_INT_CLS) {
528 if (ucs12cm0_read(client, UCS12CM0_CLS_R_DATA_L, scan.chans,
529 sizeof(scan.chans)) < 0)
530 goto clear_irq;
531
532 iio_push_to_buffers_with_timestamp(indio_dev, &scan,
533 ktime_get_boottime_ns());
534 }
535
536 clear_irq:
537 if (ret & UCS12CM0_INT_CLS) {
538 ret &= ~UCS12CM0_INT_CLS;
539 ucs12cm0_write_byte(client, UCS12CM0_INT_FLAG, ret);
540 }
541
542 if (ret & UCS12CM0_INT_POR) {
543 ret &= ~UCS12CM0_INT_POR;
544 ucs12cm0_write_byte(client, UCS12CM0_INT_FLAG, ret);
545 }
546
547 out:
548 return IRQ_HANDLED;
549 }
550
ucs12cm0_probe(struct i2c_client * client,const struct i2c_device_id * id)551 static int ucs12cm0_probe(struct i2c_client *client,
552 const struct i2c_device_id *id)
553 {
554 struct ucs12cm0_data *data;
555 struct iio_dev *indio_dev;
556 struct iio_buffer *buffer;
557 u32 type;
558 int ret;
559
560 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
561 if (!indio_dev)
562 return -ENOMEM;
563
564 buffer = devm_iio_kfifo_allocate(&client->dev);
565 if (!buffer)
566 return -ENOMEM;
567
568 iio_device_attach_buffer(indio_dev, buffer);
569
570 data = iio_priv(indio_dev);
571 i2c_set_clientdata(client, indio_dev);
572 data->client = client;
573
574 indio_dev->info = &ucs12cm0_info;
575 indio_dev->channels = ucs12cm0_channels;
576 indio_dev->num_channels = ARRAY_SIZE(ucs12cm0_channels);
577 indio_dev->name = "ucs12cm0";
578 indio_dev->modes = (INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE);
579 indio_dev->setup_ops = &ucs12cm0_buffer_setup_ops;
580
581 ret = ucs12cm0_init(data);
582 if (ret < 0)
583 return ret;
584
585 if (client->irq <= 0) {
586 dev_err(&client->dev, "no valid irq defined\n");
587 return -EINVAL;
588 }
589
590 type = irqd_get_trigger_type(irq_get_irq_data(client->irq));
591 if (type != IRQF_TRIGGER_LOW && type != IRQF_TRIGGER_FALLING) {
592 dev_err(&client->dev,
593 "unsupported IRQ trigger specified (%x)\n", type);
594 return -EINVAL;
595 }
596
597 ret = devm_request_threaded_irq(&client->dev, client->irq,
598 NULL, ucs12cm0_interrupt_handler,
599 type | IRQF_ONESHOT, "ucs12cm0_irq",
600 indio_dev);
601 if (ret) {
602 dev_err(&client->dev, "request irq (%d) failed\n",
603 client->irq);
604 return ret;
605 }
606
607 return devm_iio_device_register(&client->dev, indio_dev);
608 }
609
610 static const struct of_device_id ucs12cm0_of_match[] = {
611 { .compatible = "ultracapteur,ucs12cm0", },
612 { },
613 };
614 MODULE_DEVICE_TABLE(of, ucs12cm0_of_match);
615
616 static const struct i2c_device_id ucs12cm0_id[] = {
617 { "ucs12cm0", 0 },
618 { }
619 };
620 MODULE_DEVICE_TABLE(i2c, ucs12cm0_id);
621
ucs12cm0_resume(struct device * dev)622 static int ucs12cm0_resume(struct device *dev)
623 {
624 struct i2c_client *client = to_i2c_client(dev);
625 struct iio_dev *indio_dev = i2c_get_clientdata(client);
626 struct ucs12cm0_data *data = iio_priv(indio_dev);
627 int ret;
628
629 ret = ucs12cm0_init(data);
630 if (ret < 0)
631 return ret;
632
633 return 0;
634 }
635
636 static const struct dev_pm_ops ucs12cm0_pm_ops = {
637 .resume = ucs12cm0_resume,
638 };
639
640 static struct i2c_driver ucs12cm0_driver = {
641 .driver = {
642 .name = "ucs12cm0",
643 .of_match_table = ucs12cm0_of_match,
644 .pm = &ucs12cm0_pm_ops,
645 },
646 .probe = ucs12cm0_probe,
647 .id_table = ucs12cm0_id,
648 };
649
650 module_i2c_driver(ucs12cm0_driver);
651
652 MODULE_AUTHOR("Jason Zhang <jason.zhang@rock-chips.com>");
653 MODULE_DESCRIPTION("UCS12CM0 illuminance and correlated color temperature sensor driver");
654 MODULE_LICENSE("GPL");
655