xref: /OK3568_Linux_fs/kernel/drivers/iio/adc/gpio_muxadc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Ziyuan Xu <xzy.xu@rock-chips.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/iio/consumer.h>
14*4882a593Smuzhiyun #include <linux/iio/iio.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /**
17*4882a593Smuzhiyun  * id:			the index of analog switch inputs
18*4882a593Smuzhiyun  * saradc_chan_id:	the index of analog switch 'x' output
19*4882a593Smuzhiyun  * gpio_mask:		set the value of switch-gpios with mask, that
20*4882a593Smuzhiyun  *			makes the 'id' connect to 'saradc_chan_id'.
21*4882a593Smuzhiyun  */
22*4882a593Smuzhiyun struct gpio_muxadc_chan_data {
23*4882a593Smuzhiyun 	u32 id;
24*4882a593Smuzhiyun 	u32 saradc_chan_id;
25*4882a593Smuzhiyun 	u32 gpio_mask;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define MUXADC_CHANNEL(_index, _id, _mask) {		\
29*4882a593Smuzhiyun 	.id = _index,					\
30*4882a593Smuzhiyun 	.saradc_chan_id = _id,				\
31*4882a593Smuzhiyun 	.gpio_mask = _mask,				\
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /**
35*4882a593Smuzhiyun  * nr_chans:		the number of analog switch 'x' output
36*4882a593Smuzhiyun  * saradc_nr_chans:	the number of analog switch inputs
37*4882a593Smuzhiyun  * chans:		pointer to get the muxadc channel information
38*4882a593Smuzhiyun  */
39*4882a593Smuzhiyun struct gpio_muxadc_data {
40*4882a593Smuzhiyun 	u32 nr_chans;
41*4882a593Smuzhiyun 	u32 saradc_nr_chans;
42*4882a593Smuzhiyun 	const struct gpio_muxadc_chan_data *chans;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /**
46*4882a593Smuzhiyun  * gpios:		pointer of digital enable input gpios
47*4882a593Smuzhiyun  * adc_chans:		pointer of the 'saraadc' channel
48*4882a593Smuzhiyun  * muxchans:		specification of a single analog switch 'x'
49*4882a593Smuzhiyun  *			output channel
50*4882a593Smuzhiyun  * data:		pointer to get the muxadc channels information
51*4882a593Smuzhiyun  * nr_chans:		the number of analog switch 'x' output
52*4882a593Smuzhiyun  */
53*4882a593Smuzhiyun struct gpio_muxadc {
54*4882a593Smuzhiyun 	struct gpio_descs *gpios;
55*4882a593Smuzhiyun 	struct iio_channel *adc_chans;
56*4882a593Smuzhiyun 	struct iio_chan_spec *muxchans;
57*4882a593Smuzhiyun 	const struct gpio_muxadc_data *data;
58*4882a593Smuzhiyun 	u32 nr_chans;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
gpio_muxadc_chan_read_by_index(struct gpio_muxadc * muxadc,int index,int * val)61*4882a593Smuzhiyun static int gpio_muxadc_chan_read_by_index(struct gpio_muxadc *muxadc,
62*4882a593Smuzhiyun 					      int index, int *val)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	struct iio_channel *saradc_chan;
65*4882a593Smuzhiyun 	const struct gpio_muxadc_chan_data *chan_data;
66*4882a593Smuzhiyun 	u32 i, saradc_chan_id;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	chan_data = &muxadc->data->chans[index];
69*4882a593Smuzhiyun 	for (i = 0; i < muxadc->gpios->ndescs; i++) {
70*4882a593Smuzhiyun 		struct gpio_desc *gpiod = muxadc->gpios->desc[i];
71*4882a593Smuzhiyun 		int gpio_val = chan_data->gpio_mask & BIT(i) ? 1 : 0;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 		gpiod_set_value(gpiod, gpio_val);
74*4882a593Smuzhiyun 	}
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	saradc_chan_id = chan_data->saradc_chan_id;
77*4882a593Smuzhiyun 	saradc_chan = &muxadc->adc_chans[saradc_chan_id];
78*4882a593Smuzhiyun 	return iio_read_channel_raw(saradc_chan, val);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
gpio_muxadc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)81*4882a593Smuzhiyun static int gpio_muxadc_read_raw(struct iio_dev *indio_dev,
82*4882a593Smuzhiyun 				    struct iio_chan_spec const *chan,
83*4882a593Smuzhiyun 				    int *val, int *val2, long mask)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	struct gpio_muxadc *muxadc = iio_priv(indio_dev);
86*4882a593Smuzhiyun 	int ret = IIO_VAL_INT;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	switch (mask) {
89*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
90*4882a593Smuzhiyun 		ret = gpio_muxadc_chan_read_by_index(muxadc,
91*4882a593Smuzhiyun 						     chan->channel, val);
92*4882a593Smuzhiyun 		break;
93*4882a593Smuzhiyun 	default:
94*4882a593Smuzhiyun 		return -EINVAL;
95*4882a593Smuzhiyun 	}
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	return ret;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun static const struct iio_info gpio_muxadc_iio_info = {
101*4882a593Smuzhiyun 	.read_raw = gpio_muxadc_read_raw,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun static const struct gpio_muxadc_chan_data mux_sgm3699_chans_data[] = {
105*4882a593Smuzhiyun 	MUXADC_CHANNEL(0, 0, 0b00),
106*4882a593Smuzhiyun 	MUXADC_CHANNEL(1, 1, 0b00),
107*4882a593Smuzhiyun 	MUXADC_CHANNEL(2, 2, 0b00),
108*4882a593Smuzhiyun 	MUXADC_CHANNEL(3, 3, 0b00),
109*4882a593Smuzhiyun 	MUXADC_CHANNEL(4, 0, 0b01),
110*4882a593Smuzhiyun 	MUXADC_CHANNEL(5, 1, 0b01),
111*4882a593Smuzhiyun 	MUXADC_CHANNEL(6, 2, 0b11),
112*4882a593Smuzhiyun 	MUXADC_CHANNEL(7, 3, 0b11),
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun static const struct gpio_muxadc_data mux_sgm3699_data = {
116*4882a593Smuzhiyun 	.saradc_nr_chans = 4,
117*4882a593Smuzhiyun 	.nr_chans = ARRAY_SIZE(mux_sgm3699_chans_data),
118*4882a593Smuzhiyun 	.chans = mux_sgm3699_chans_data,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun static const struct gpio_muxadc_chan_data mux_sgm48752_chans_data[] = {
122*4882a593Smuzhiyun 	MUXADC_CHANNEL(0, 0, 0b00),
123*4882a593Smuzhiyun 	MUXADC_CHANNEL(1, 1, 0b00),
124*4882a593Smuzhiyun 	MUXADC_CHANNEL(2, 0, 0b10),
125*4882a593Smuzhiyun 	MUXADC_CHANNEL(3, 1, 0b10),
126*4882a593Smuzhiyun 	MUXADC_CHANNEL(4, 0, 0b01),
127*4882a593Smuzhiyun 	MUXADC_CHANNEL(5, 1, 0b01),
128*4882a593Smuzhiyun 	MUXADC_CHANNEL(6, 0, 0b11),
129*4882a593Smuzhiyun 	MUXADC_CHANNEL(7, 1, 0b11),
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun static const struct gpio_muxadc_data mux_sgm48752_data = {
133*4882a593Smuzhiyun 	.saradc_nr_chans = 2,
134*4882a593Smuzhiyun 	.nr_chans = ARRAY_SIZE(mux_sgm48752_chans_data),
135*4882a593Smuzhiyun 	.chans = mux_sgm48752_chans_data,
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun static const struct of_device_id of_gpio_muxadc_match[] = {
139*4882a593Smuzhiyun 	{
140*4882a593Smuzhiyun 		.compatible = "sgm3699",
141*4882a593Smuzhiyun 		.data = &mux_sgm3699_data,
142*4882a593Smuzhiyun 	},
143*4882a593Smuzhiyun 	{
144*4882a593Smuzhiyun 		.compatible = "sgm48752",
145*4882a593Smuzhiyun 		.data = &mux_sgm48752_data,
146*4882a593Smuzhiyun 	},
147*4882a593Smuzhiyun 	{},
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_gpio_muxadc_match);
150*4882a593Smuzhiyun 
gpio_muxadc_probe(struct platform_device * pdev)151*4882a593Smuzhiyun static int gpio_muxadc_probe(struct platform_device *pdev)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	struct gpio_muxadc *muxadc;
154*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
155*4882a593Smuzhiyun 	const struct of_device_id *match;
156*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
157*4882a593Smuzhiyun 	struct device_node *np = pdev->dev.of_node;
158*4882a593Smuzhiyun 	u32 i, nr_adc_chans = 0;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(dev, sizeof(*muxadc));
161*4882a593Smuzhiyun 	if (!indio_dev)
162*4882a593Smuzhiyun 		return -ENOMEM;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	muxadc = iio_priv(indio_dev);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	match = of_match_device(of_gpio_muxadc_match, dev);
167*4882a593Smuzhiyun 	if (!match) {
168*4882a593Smuzhiyun 		dev_err(dev, "failed to match device\n");
169*4882a593Smuzhiyun 		return -ENODEV;
170*4882a593Smuzhiyun 	}
171*4882a593Smuzhiyun 	muxadc->data = match->data;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	muxadc->gpios = devm_gpiod_get_array(dev, "switch", GPIOD_OUT_LOW);
174*4882a593Smuzhiyun 	if (IS_ERR(muxadc->gpios)) {
175*4882a593Smuzhiyun 		dev_err(dev, "property of switch-gpios not specified\n");
176*4882a593Smuzhiyun 		return PTR_ERR(muxadc->gpios);
177*4882a593Smuzhiyun 	}
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	muxadc->adc_chans = iio_channel_get_all(dev);
180*4882a593Smuzhiyun 	if (IS_ERR(muxadc->adc_chans))
181*4882a593Smuzhiyun 		return PTR_ERR(muxadc->adc_chans);
182*4882a593Smuzhiyun 	/*
183*4882a593Smuzhiyun 	 * It's necessary to get the number of input ADC, and make a
184*4882a593Smuzhiyun 	 * comparison with chan_data->saradc_nr_chans. Otherwise it
185*4882a593Smuzhiyun 	 * might fall in to trap.
186*4882a593Smuzhiyun 	 */
187*4882a593Smuzhiyun 	while (muxadc->adc_chans[nr_adc_chans].indio_dev)
188*4882a593Smuzhiyun 		nr_adc_chans++;
189*4882a593Smuzhiyun 	if (muxadc->data->saradc_nr_chans != nr_adc_chans) {
190*4882a593Smuzhiyun 		dev_err(dev, "the number of io-channels is mismatch\n");
191*4882a593Smuzhiyun 		return -EINVAL;
192*4882a593Smuzhiyun 	}
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	muxadc->nr_chans = of_property_count_strings(np, "labels");
195*4882a593Smuzhiyun 	if (muxadc->nr_chans != muxadc->data->nr_chans) {
196*4882a593Smuzhiyun 		dev_err(dev, "should provide %d label\n",
197*4882a593Smuzhiyun 			muxadc->nr_chans);
198*4882a593Smuzhiyun 		return -EINVAL;
199*4882a593Smuzhiyun 	}
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	muxadc->muxchans = devm_kcalloc(dev, muxadc->nr_chans,
202*4882a593Smuzhiyun 					sizeof(struct iio_chan_spec),
203*4882a593Smuzhiyun 					GFP_KERNEL);
204*4882a593Smuzhiyun 	if (!muxadc->muxchans)
205*4882a593Smuzhiyun 		return -ENOMEM;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	for (i = 0; i < muxadc->nr_chans; i++) {
208*4882a593Smuzhiyun 		/*
209*4882a593Smuzhiyun 		 * The specification of each muxadc channel will be
210*4882a593Smuzhiyun 		 * in_voltage_<label> without been indexed.
211*4882a593Smuzhiyun 		 */
212*4882a593Smuzhiyun 		muxadc->muxchans[i].type = IIO_VOLTAGE;
213*4882a593Smuzhiyun 		muxadc->muxchans[i].channel = i;
214*4882a593Smuzhiyun 		muxadc->muxchans[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
215*4882a593Smuzhiyun 		of_property_read_string_index(np, "labels", i,
216*4882a593Smuzhiyun 					      &muxadc->muxchans[i].extend_name);
217*4882a593Smuzhiyun 	}
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	indio_dev->name = dev_name(dev);
220*4882a593Smuzhiyun 	indio_dev->dev.parent = dev;
221*4882a593Smuzhiyun 	indio_dev->dev.of_node = dev->of_node;
222*4882a593Smuzhiyun 	indio_dev->info = &gpio_muxadc_iio_info;
223*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
224*4882a593Smuzhiyun 	indio_dev->channels = muxadc->muxchans;
225*4882a593Smuzhiyun 	indio_dev->num_channels = muxadc->nr_chans;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	return iio_device_register(indio_dev);
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun 
gpio_muxadc_remove(struct platform_device * pdev)230*4882a593Smuzhiyun static int gpio_muxadc_remove(struct platform_device *pdev)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun 	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
235*4882a593Smuzhiyun 	return 0;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun static struct platform_driver gpio_muxadc_driver = {
239*4882a593Smuzhiyun 	.probe		= gpio_muxadc_probe,
240*4882a593Smuzhiyun 	.remove		= gpio_muxadc_remove,
241*4882a593Smuzhiyun 	.driver		= {
242*4882a593Smuzhiyun 		.name	= "gpio-muxadc",
243*4882a593Smuzhiyun 		.of_match_table = of_gpio_muxadc_match,
244*4882a593Smuzhiyun 	},
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun module_platform_driver(gpio_muxadc_driver);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun MODULE_AUTHOR("Ziyuan Xu <xzy.xu@rock-chips.com>");
250*4882a593Smuzhiyun MODULE_DESCRIPTION("GPIO MUX ADC driver");
251*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
252