1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitops.h>
7 #include <linux/kernel.h>
8 #include <linux/moduleparam.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/device.h>
12 #include <linux/io.h>
13 #include <linux/err.h>
14 #include <linux/fs.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/smp.h>
18 #include <linux/sysfs.h>
19 #include <linux/stat.h>
20 #include <linux/clk.h>
21 #include <linux/cpu.h>
22 #include <linux/cpu_pm.h>
23 #include <linux/coresight.h>
24 #include <linux/coresight-pmu.h>
25 #include <linux/pm_wakeup.h>
26 #include <linux/amba/bus.h>
27 #include <linux/seq_file.h>
28 #include <linux/uaccess.h>
29 #include <linux/perf_event.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/property.h>
33
34 #include <asm/barrier.h>
35 #include <asm/sections.h>
36 #include <asm/sysreg.h>
37 #include <asm/local.h>
38 #include <asm/virt.h>
39
40 #include "coresight-etm4x.h"
41 #include "coresight-etm-perf.h"
42 #include "coresight-self-hosted-trace.h"
43
44 static int boot_enable;
45 module_param(boot_enable, int, 0444);
46 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
47
48 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
49 #define PARAM_PM_SAVE_NEVER 1 /* never save any state */
50 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
51
52 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
53 module_param(pm_save_enable, int, 0444);
54 MODULE_PARM_DESC(pm_save_enable,
55 "Save/restore state on power down: 1 = never, 2 = self-hosted");
56
57 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
58 static void etm4_set_default_config(struct etmv4_config *config);
59 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
60 struct perf_event *event);
61 static u64 etm4_get_access_type(struct etmv4_config *config);
62
63 static enum cpuhp_state hp_online;
64
65 struct etm4_init_arg {
66 unsigned int pid;
67 struct etmv4_drvdata *drvdata;
68 struct csdev_access *csa;
69 };
70
71 /*
72 * Check if TRCSSPCICRn(i) is implemented for a given instance.
73 *
74 * TRCSSPCICRn is implemented only if :
75 * TRCSSPCICR<n> is present only if all of the following are true:
76 * TRCIDR4.NUMSSCC > n.
77 * TRCIDR4.NUMPC > 0b0000 .
78 * TRCSSCSR<n>.PC == 0b1
79 */
etm4x_sspcicrn_present(struct etmv4_drvdata * drvdata,int n)80 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
81 {
82 return (n < drvdata->nr_ss_cmp) &&
83 drvdata->nr_pe &&
84 (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
85 }
86
etm4x_sysreg_read(u32 offset,bool _relaxed,bool _64bit)87 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
88 {
89 u64 res = 0;
90
91 switch (offset) {
92 ETM4x_READ_SYSREG_CASES(res)
93 default :
94 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
95 offset);
96 }
97
98 if (!_relaxed)
99 __iormb(res); /* Imitate the !relaxed I/O helpers */
100
101 return res;
102 }
103
etm4x_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)104 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
105 {
106 if (!_relaxed)
107 __iowmb(); /* Imitate the !relaxed I/O helpers */
108 if (!_64bit)
109 val &= GENMASK(31, 0);
110
111 switch (offset) {
112 ETM4x_WRITE_SYSREG_CASES(val)
113 default :
114 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
115 offset);
116 }
117 }
118
ete_sysreg_read(u32 offset,bool _relaxed,bool _64bit)119 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
120 {
121 u64 res = 0;
122
123 switch (offset) {
124 ETE_READ_CASES(res)
125 default :
126 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
127 offset);
128 }
129
130 if (!_relaxed)
131 __iormb(res); /* Imitate the !relaxed I/O helpers */
132
133 return res;
134 }
135
ete_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)136 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
137 {
138 if (!_relaxed)
139 __iowmb(); /* Imitate the !relaxed I/O helpers */
140 if (!_64bit)
141 val &= GENMASK(31, 0);
142
143 switch (offset) {
144 ETE_WRITE_CASES(val)
145 default :
146 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
147 offset);
148 }
149 }
150
etm_detect_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)151 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
152 struct csdev_access *csa)
153 {
154 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
155
156 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
157 }
158
etm_write_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa,u32 val)159 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
160 struct csdev_access *csa, u32 val)
161 {
162 val = !!val;
163
164 switch (drvdata->os_lock_model) {
165 case ETM_OSLOCK_PRESENT:
166 etm4x_relaxed_write32(csa, val, TRCOSLAR);
167 break;
168 case ETM_OSLOCK_PE:
169 write_sysreg_s(val, SYS_OSLAR_EL1);
170 break;
171 default:
172 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
173 smp_processor_id(), drvdata->os_lock_model);
174 fallthrough;
175 case ETM_OSLOCK_NI:
176 return;
177 }
178 isb();
179 }
180
etm4_os_unlock_csa(struct etmv4_drvdata * drvdata,struct csdev_access * csa)181 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
182 struct csdev_access *csa)
183 {
184 WARN_ON(drvdata->cpu != smp_processor_id());
185
186 /* Writing 0 to OS Lock unlocks the trace unit registers */
187 etm_write_os_lock(drvdata, csa, 0x0);
188 drvdata->os_unlock = true;
189 }
190
etm4_os_unlock(struct etmv4_drvdata * drvdata)191 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
192 {
193 if (!WARN_ON(!drvdata->csdev))
194 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
195 }
196
etm4_os_lock(struct etmv4_drvdata * drvdata)197 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
198 {
199 if (WARN_ON(!drvdata->csdev))
200 return;
201 /* Writing 0x1 to OS Lock locks the trace registers */
202 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
203 drvdata->os_unlock = false;
204 }
205
etm4_cs_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)206 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
207 struct csdev_access *csa)
208 {
209 /* Software Lock is only accessible via memory mapped interface */
210 if (csa->io_mem)
211 CS_LOCK(csa->base);
212 }
213
etm4_cs_unlock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)214 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
215 struct csdev_access *csa)
216 {
217 if (csa->io_mem)
218 CS_UNLOCK(csa->base);
219 }
220
etm4_cpu_id(struct coresight_device * csdev)221 static int etm4_cpu_id(struct coresight_device *csdev)
222 {
223 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
224
225 return drvdata->cpu;
226 }
227
etm4_trace_id(struct coresight_device * csdev)228 static int etm4_trace_id(struct coresight_device *csdev)
229 {
230 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
231
232 return drvdata->trcid;
233 }
234
235 struct etm4_enable_arg {
236 struct etmv4_drvdata *drvdata;
237 int rc;
238 };
239
240 /*
241 * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
242 * When the CPU supports FEAT_TRF, we could move the ETM to a trace
243 * prohibited state by filtering the Exception levels via TRFCR_EL1.
244 */
etm4x_prohibit_trace(struct etmv4_drvdata * drvdata)245 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
246 {
247 /* If the CPU doesn't support FEAT_TRF, nothing to do */
248 if (!drvdata->trfcr)
249 return;
250 cpu_prohibit_trace();
251 }
252
253 /*
254 * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
255 * as configured by the drvdata->config.mode for the current
256 * session. Even though we have TRCVICTLR bits to filter the
257 * trace in the ELs, it doesn't prevent the ETM from generating
258 * a packet (e.g, TraceInfo) that might contain the addresses from
259 * the excluded levels. Thus we use the additional controls provided
260 * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
261 * is generated for the excluded ELs.
262 */
etm4x_allow_trace(struct etmv4_drvdata * drvdata)263 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
264 {
265 u64 trfcr = drvdata->trfcr;
266
267 /* If the CPU doesn't support FEAT_TRF, nothing to do */
268 if (!trfcr)
269 return;
270
271 if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
272 trfcr &= ~TRFCR_ELx_ExTRE;
273 if (drvdata->config.mode & ETM_MODE_EXCL_USER)
274 trfcr &= ~TRFCR_ELx_E0TRE;
275
276 write_trfcr(trfcr);
277 }
278
279 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
280
281 #define HISI_HIP08_AMBA_ID 0x000b6d01
282 #define ETM4_AMBA_MASK 0xfffff
283 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000
284 #define HISI_HIP08_CORE_COMMIT_SHIFT 12
285 #define HISI_HIP08_CORE_COMMIT_FULL 0b00
286 #define HISI_HIP08_CORE_COMMIT_LVL_1 0b01
287 #define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)
288
289 struct etm4_arch_features {
290 void (*arch_callback)(bool enable);
291 };
292
etm4_hisi_match_pid(unsigned int id)293 static bool etm4_hisi_match_pid(unsigned int id)
294 {
295 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
296 }
297
etm4_hisi_config_core_commit(bool enable)298 static void etm4_hisi_config_core_commit(bool enable)
299 {
300 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
301 HISI_HIP08_CORE_COMMIT_FULL;
302 u64 val;
303
304 /*
305 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
306 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
307 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
308 * speed(minimun value). So bit 12 and 13 should be cleared together.
309 */
310 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
311 val &= ~HISI_HIP08_CORE_COMMIT_MASK;
312 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
313 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
314 }
315
316 static struct etm4_arch_features etm4_features[] = {
317 [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
318 .arch_callback = etm4_hisi_config_core_commit,
319 },
320 {},
321 };
322
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)323 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
324 {
325 struct etm4_arch_features *ftr;
326 int bit;
327
328 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
329 ftr = &etm4_features[bit];
330
331 if (ftr->arch_callback)
332 ftr->arch_callback(true);
333 }
334 }
335
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)336 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
337 {
338 struct etm4_arch_features *ftr;
339 int bit;
340
341 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
342 ftr = &etm4_features[bit];
343
344 if (ftr->arch_callback)
345 ftr->arch_callback(false);
346 }
347 }
348
etm4_check_arch_features(struct etmv4_drvdata * drvdata,unsigned int id)349 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
350 unsigned int id)
351 {
352 if (etm4_hisi_match_pid(id))
353 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
354 }
355 #else
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)356 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
357 {
358 }
359
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)360 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
361 {
362 }
363
etm4_check_arch_features(struct etmv4_drvdata * drvdata,unsigned int id)364 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
365 unsigned int id)
366 {
367 }
368 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
369
etm4_enable_hw(struct etmv4_drvdata * drvdata)370 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
371 {
372 int i, rc;
373 struct etmv4_config *config = &drvdata->config;
374 struct coresight_device *csdev = drvdata->csdev;
375 struct device *etm_dev = &csdev->dev;
376 struct csdev_access *csa = &csdev->access;
377
378
379 etm4_cs_unlock(drvdata, csa);
380 etm4_enable_arch_specific(drvdata);
381
382 etm4_os_unlock(drvdata);
383
384 rc = coresight_claim_device_unlocked(csdev);
385 if (rc)
386 goto done;
387
388 /* Disable the trace unit before programming trace registers */
389 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
390
391 /*
392 * If we use system instructions, we need to synchronize the
393 * write to the TRCPRGCTLR, before accessing the TRCSTATR.
394 * See ARM IHI0064F, section
395 * "4.3.7 Synchronization of register updates"
396 */
397 if (!csa->io_mem)
398 isb();
399
400 /* wait for TRCSTATR.IDLE to go up */
401 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
402 dev_err(etm_dev,
403 "timeout while waiting for Idle Trace Status\n");
404 if (drvdata->nr_pe)
405 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
406 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
407 /* nothing specific implemented */
408 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
409 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
410 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
411 if (drvdata->stallctl)
412 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
413 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
414 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
415 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
416 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
417 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
418 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
419 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
420 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
421 if (drvdata->nr_pe_cmp)
422 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
423 for (i = 0; i < drvdata->nrseqstate - 1; i++)
424 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
425 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
426 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
427 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
428 for (i = 0; i < drvdata->nr_cntr; i++) {
429 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
430 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
431 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
432 }
433
434 /*
435 * Resource selector pair 0 is always implemented and reserved. As
436 * such start at 2.
437 */
438 for (i = 2; i < drvdata->nr_resource * 2; i++)
439 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
440
441 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
442 /* always clear status bit on restart if using single-shot */
443 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
444 config->ss_status[i] &= ~BIT(31);
445 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
446 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
447 if (etm4x_sspcicrn_present(drvdata, i))
448 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
449 }
450 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
451 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
452 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
453 }
454 for (i = 0; i < drvdata->numcidc; i++)
455 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
456 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
457 if (drvdata->numcidc > 4)
458 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
459
460 for (i = 0; i < drvdata->numvmidc; i++)
461 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
462 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
463 if (drvdata->numvmidc > 4)
464 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
465
466 if (!drvdata->skip_power_up) {
467 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
468
469 /*
470 * Request to keep the trace unit powered and also
471 * emulation of powerdown
472 */
473 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
474 }
475
476 /*
477 * ETE mandates that the TRCRSR is written to before
478 * enabling it.
479 */
480 if (etm4x_is_ete(drvdata))
481 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
482
483 etm4x_allow_trace(drvdata);
484 /* Enable the trace unit */
485 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
486
487 /* Synchronize the register updates for sysreg access */
488 if (!csa->io_mem)
489 isb();
490
491 /* wait for TRCSTATR.IDLE to go back down to '0' */
492 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
493 dev_err(etm_dev,
494 "timeout while waiting for Idle Trace Status\n");
495
496 /*
497 * As recommended by section 4.3.7 ("Synchronization when using the
498 * memory-mapped interface") of ARM IHI 0064D
499 */
500 dsb(sy);
501 isb();
502
503 done:
504 etm4_cs_lock(drvdata, csa);
505
506 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
507 drvdata->cpu, rc);
508 return rc;
509 }
510
etm4_enable_hw_smp_call(void * info)511 static void etm4_enable_hw_smp_call(void *info)
512 {
513 struct etm4_enable_arg *arg = info;
514
515 if (WARN_ON(!arg))
516 return;
517 arg->rc = etm4_enable_hw(arg->drvdata);
518 }
519
520 /*
521 * The goal of function etm4_config_timestamp_event() is to configure a
522 * counter that will tell the tracer to emit a timestamp packet when it
523 * reaches zero. This is done in order to get a more fine grained idea
524 * of when instructions are executed so that they can be correlated
525 * with execution on other CPUs.
526 *
527 * To do this the counter itself is configured to self reload and
528 * TRCRSCTLR1 (always true) used to get the counter to decrement. From
529 * there a resource selector is configured with the counter and the
530 * timestamp control register to use the resource selector to trigger the
531 * event that will insert a timestamp packet in the stream.
532 */
etm4_config_timestamp_event(struct etmv4_drvdata * drvdata)533 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
534 {
535 int ctridx, ret = -EINVAL;
536 int counter, rselector;
537 u32 val = 0;
538 struct etmv4_config *config = &drvdata->config;
539
540 /* No point in trying if we don't have at least one counter */
541 if (!drvdata->nr_cntr)
542 goto out;
543
544 /* Find a counter that hasn't been initialised */
545 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
546 if (config->cntr_val[ctridx] == 0)
547 break;
548
549 /* All the counters have been configured already, bail out */
550 if (ctridx == drvdata->nr_cntr) {
551 pr_debug("%s: no available counter found\n", __func__);
552 ret = -ENOSPC;
553 goto out;
554 }
555
556 /*
557 * Searching for an available resource selector to use, starting at
558 * '2' since every implementation has at least 2 resource selector.
559 * ETMIDR4 gives the number of resource selector _pairs_,
560 * hence multiply by 2.
561 */
562 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
563 if (!config->res_ctrl[rselector])
564 break;
565
566 if (rselector == drvdata->nr_resource * 2) {
567 pr_debug("%s: no available resource selector found\n",
568 __func__);
569 ret = -ENOSPC;
570 goto out;
571 }
572
573 /* Remember what counter we used */
574 counter = 1 << ctridx;
575
576 /*
577 * Initialise original and reload counter value to the smallest
578 * possible value in order to get as much precision as we can.
579 */
580 config->cntr_val[ctridx] = 1;
581 config->cntrldvr[ctridx] = 1;
582
583 /* Set the trace counter control register */
584 val = 0x1 << 16 | /* Bit 16, reload counter automatically */
585 0x0 << 7 | /* Select single resource selector */
586 0x1; /* Resource selector 1, i.e always true */
587
588 config->cntr_ctrl[ctridx] = val;
589
590 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */
591 counter << 0; /* Counter to use */
592
593 config->res_ctrl[rselector] = val;
594
595 val = 0x0 << 7 | /* Select single resource selector */
596 rselector; /* Resource selector */
597
598 config->ts_ctrl = val;
599
600 ret = 0;
601 out:
602 return ret;
603 }
604
etm4_parse_event_config(struct etmv4_drvdata * drvdata,struct perf_event * event)605 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
606 struct perf_event *event)
607 {
608 int ret = 0;
609 struct etmv4_config *config = &drvdata->config;
610 struct perf_event_attr *attr = &event->attr;
611
612 if (!attr) {
613 ret = -EINVAL;
614 goto out;
615 }
616
617 /* Clear configuration from previous run */
618 memset(config, 0, sizeof(struct etmv4_config));
619
620 if (attr->exclude_kernel)
621 config->mode = ETM_MODE_EXCL_KERN;
622
623 if (attr->exclude_user)
624 config->mode = ETM_MODE_EXCL_USER;
625
626 /* Always start from the default config */
627 etm4_set_default_config(config);
628
629 /* Configure filters specified on the perf cmd line, if any. */
630 ret = etm4_set_event_filters(drvdata, event);
631 if (ret)
632 goto out;
633
634 /* Go from generic option to ETMv4 specifics */
635 if (attr->config & BIT(ETM_OPT_CYCACC)) {
636 config->cfg |= BIT(4);
637 /* TRM: Must program this for cycacc to work */
638 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
639 }
640 if (attr->config & BIT(ETM_OPT_TS)) {
641 /*
642 * Configure timestamps to be emitted at regular intervals in
643 * order to correlate instructions executed on different CPUs
644 * (CPU-wide trace scenarios).
645 */
646 ret = etm4_config_timestamp_event(drvdata);
647
648 /*
649 * No need to go further if timestamp intervals can't
650 * be configured.
651 */
652 if (ret)
653 goto out;
654
655 /* bit[11], Global timestamp tracing bit */
656 config->cfg |= BIT(11);
657 }
658
659 if (attr->config & BIT(ETM_OPT_CTXTID))
660 /* bit[6], Context ID tracing bit */
661 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
662
663 /*
664 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
665 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the
666 * kernel is not running in EL2.
667 */
668 if (attr->config & BIT(ETM_OPT_CTXTID2)) {
669 if (!is_kernel_in_hyp_mode()) {
670 ret = -EINVAL;
671 goto out;
672 }
673 config->cfg |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT);
674 }
675
676 /* return stack - enable if selected and supported */
677 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
678 /* bit[12], Return stack enable bit */
679 config->cfg |= BIT(12);
680
681 out:
682 return ret;
683 }
684
etm4_enable_perf(struct coresight_device * csdev,struct perf_event * event)685 static int etm4_enable_perf(struct coresight_device *csdev,
686 struct perf_event *event)
687 {
688 int ret = 0;
689 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
690
691 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
692 ret = -EINVAL;
693 goto out;
694 }
695
696 /* Configure the tracer based on the session's specifics */
697 ret = etm4_parse_event_config(drvdata, event);
698 if (ret)
699 goto out;
700 /* And enable it */
701 ret = etm4_enable_hw(drvdata);
702
703 out:
704 return ret;
705 }
706
etm4_enable_sysfs(struct coresight_device * csdev)707 static int etm4_enable_sysfs(struct coresight_device *csdev)
708 {
709 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
710 struct etm4_enable_arg arg = { };
711 int ret;
712
713 spin_lock(&drvdata->spinlock);
714
715 /*
716 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
717 * ensures that register writes occur when cpu is powered.
718 */
719 arg.drvdata = drvdata;
720 ret = smp_call_function_single(drvdata->cpu,
721 etm4_enable_hw_smp_call, &arg, 1);
722 if (!ret)
723 ret = arg.rc;
724 if (!ret)
725 drvdata->sticky_enable = true;
726 spin_unlock(&drvdata->spinlock);
727
728 if (!ret)
729 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
730 return ret;
731 }
732
etm4_enable(struct coresight_device * csdev,struct perf_event * event,u32 mode)733 static int etm4_enable(struct coresight_device *csdev,
734 struct perf_event *event, u32 mode)
735 {
736 int ret;
737 u32 val;
738 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
739
740 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
741
742 /* Someone is already using the tracer */
743 if (val)
744 return -EBUSY;
745
746 switch (mode) {
747 case CS_MODE_SYSFS:
748 ret = etm4_enable_sysfs(csdev);
749 break;
750 case CS_MODE_PERF:
751 ret = etm4_enable_perf(csdev, event);
752 break;
753 default:
754 ret = -EINVAL;
755 }
756
757 /* The tracer didn't start */
758 if (ret)
759 local_set(&drvdata->mode, CS_MODE_DISABLED);
760
761 return ret;
762 }
763
etm4_disable_hw(void * info)764 static void etm4_disable_hw(void *info)
765 {
766 u32 control;
767 struct etmv4_drvdata *drvdata = info;
768 struct etmv4_config *config = &drvdata->config;
769 struct coresight_device *csdev = drvdata->csdev;
770 struct device *etm_dev = &csdev->dev;
771 struct csdev_access *csa = &csdev->access;
772 int i;
773
774 etm4_cs_unlock(drvdata, csa);
775 etm4_disable_arch_specific(drvdata);
776
777 if (!drvdata->skip_power_up) {
778 /* power can be removed from the trace unit now */
779 control = etm4x_relaxed_read32(csa, TRCPDCR);
780 control &= ~TRCPDCR_PU;
781 etm4x_relaxed_write32(csa, control, TRCPDCR);
782 }
783
784 control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
785
786 /* EN, bit[0] Trace unit enable bit */
787 control &= ~0x1;
788
789 /*
790 * If the CPU supports v8.4 Trace filter Control,
791 * set the ETM to trace prohibited region.
792 */
793 etm4x_prohibit_trace(drvdata);
794 /*
795 * Make sure everything completes before disabling, as recommended
796 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
797 * SSTATUS") of ARM IHI 0064D
798 */
799 dsb(sy);
800 isb();
801 /* Trace synchronization barrier, is a nop if not supported */
802 tsb_csync();
803 etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
804
805 /* wait for TRCSTATR.PMSTABLE to go to '1' */
806 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
807 dev_err(etm_dev,
808 "timeout while waiting for PM stable Trace Status\n");
809 /* read the status of the single shot comparators */
810 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
811 config->ss_status[i] =
812 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
813 }
814
815 /* read back the current counter values */
816 for (i = 0; i < drvdata->nr_cntr; i++) {
817 config->cntr_val[i] =
818 etm4x_relaxed_read32(csa, TRCCNTVRn(i));
819 }
820
821 coresight_disclaim_device_unlocked(csdev);
822 etm4_cs_lock(drvdata, csa);
823
824 dev_dbg(&drvdata->csdev->dev,
825 "cpu: %d disable smp call done\n", drvdata->cpu);
826 }
827
etm4_disable_perf(struct coresight_device * csdev,struct perf_event * event)828 static int etm4_disable_perf(struct coresight_device *csdev,
829 struct perf_event *event)
830 {
831 u32 control;
832 struct etm_filters *filters = event->hw.addr_filters;
833 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
834
835 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
836 return -EINVAL;
837
838 etm4_disable_hw(drvdata);
839
840 /*
841 * Check if the start/stop logic was active when the unit was stopped.
842 * That way we can re-enable the start/stop logic when the process is
843 * scheduled again. Configuration of the start/stop logic happens in
844 * function etm4_set_event_filters().
845 */
846 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
847 /* TRCVICTLR::SSSTATUS, bit[9] */
848 filters->ssstatus = (control & BIT(9));
849
850 return 0;
851 }
852
etm4_disable_sysfs(struct coresight_device * csdev)853 static void etm4_disable_sysfs(struct coresight_device *csdev)
854 {
855 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
856
857 /*
858 * Taking hotplug lock here protects from clocks getting disabled
859 * with tracing being left on (crash scenario) if user disable occurs
860 * after cpu online mask indicates the cpu is offline but before the
861 * DYING hotplug callback is serviced by the ETM driver.
862 */
863 cpus_read_lock();
864 spin_lock(&drvdata->spinlock);
865
866 /*
867 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
868 * ensures that register writes occur when cpu is powered.
869 */
870 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
871
872 spin_unlock(&drvdata->spinlock);
873 cpus_read_unlock();
874
875 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
876 }
877
etm4_disable(struct coresight_device * csdev,struct perf_event * event)878 static void etm4_disable(struct coresight_device *csdev,
879 struct perf_event *event)
880 {
881 u32 mode;
882 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
883
884 /*
885 * For as long as the tracer isn't disabled another entity can't
886 * change its status. As such we can read the status here without
887 * fearing it will change under us.
888 */
889 mode = local_read(&drvdata->mode);
890
891 switch (mode) {
892 case CS_MODE_DISABLED:
893 break;
894 case CS_MODE_SYSFS:
895 etm4_disable_sysfs(csdev);
896 break;
897 case CS_MODE_PERF:
898 etm4_disable_perf(csdev, event);
899 break;
900 }
901
902 if (mode)
903 local_set(&drvdata->mode, CS_MODE_DISABLED);
904 }
905
906 static const struct coresight_ops_source etm4_source_ops = {
907 .cpu_id = etm4_cpu_id,
908 .trace_id = etm4_trace_id,
909 .enable = etm4_enable,
910 .disable = etm4_disable,
911 };
912
913 static const struct coresight_ops etm4_cs_ops = {
914 .source_ops = &etm4_source_ops,
915 };
916
cpu_supports_sysreg_trace(void)917 static inline bool cpu_supports_sysreg_trace(void)
918 {
919 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
920
921 return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
922 }
923
etm4_init_sysreg_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)924 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
925 struct csdev_access *csa)
926 {
927 u32 devarch;
928
929 if (!cpu_supports_sysreg_trace())
930 return false;
931
932 /*
933 * ETMs implementing sysreg access must implement TRCDEVARCH.
934 */
935 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
936 switch (devarch & ETM_DEVARCH_ID_MASK) {
937 case ETM_DEVARCH_ETMv4x_ARCH:
938 *csa = (struct csdev_access) {
939 .io_mem = false,
940 .read = etm4x_sysreg_read,
941 .write = etm4x_sysreg_write,
942 };
943 break;
944 case ETM_DEVARCH_ETE_ARCH:
945 *csa = (struct csdev_access) {
946 .io_mem = false,
947 .read = ete_sysreg_read,
948 .write = ete_sysreg_write,
949 };
950 break;
951 default:
952 return false;
953 }
954
955 drvdata->arch = etm_devarch_to_arch(devarch);
956 return true;
957 }
958
etm4_init_iomem_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)959 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
960 struct csdev_access *csa)
961 {
962 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
963 u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);
964
965 /*
966 * All ETMs must implement TRCDEVARCH to indicate that
967 * the component is an ETMv4. To support any broken
968 * implementations we fall back to TRCIDR1 check, which
969 * is not really reliable.
970 */
971 if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {
972 drvdata->arch = etm_devarch_to_arch(devarch);
973 } else {
974 pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",
975 smp_processor_id(), devarch);
976
977 if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)
978 return false;
979 drvdata->arch = etm_trcidr_to_arch(idr1);
980 }
981
982 *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
983 return true;
984 }
985
etm4_init_csdev_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)986 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
987 struct csdev_access *csa)
988 {
989 /*
990 * Always choose the memory mapped io, if there is
991 * a memory map to prevent sysreg access on broken
992 * systems.
993 */
994 if (drvdata->base)
995 return etm4_init_iomem_access(drvdata, csa);
996
997 if (etm4_init_sysreg_access(drvdata, csa))
998 return true;
999
1000 return false;
1001 }
1002
cpu_detect_trace_filtering(struct etmv4_drvdata * drvdata)1003 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1004 {
1005 u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1006 u64 trfcr;
1007
1008 drvdata->trfcr = 0;
1009 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT))
1010 return;
1011
1012 /*
1013 * If the CPU supports v8.4 SelfHosted Tracing, enable
1014 * tracing at the kernel EL and EL0, forcing to use the
1015 * virtual time as the timestamp.
1016 */
1017 trfcr = (TRFCR_ELx_TS_VIRTUAL |
1018 TRFCR_ELx_ExTRE |
1019 TRFCR_ELx_E0TRE);
1020
1021 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1022 if (is_kernel_in_hyp_mode())
1023 trfcr |= TRFCR_EL2_CX;
1024
1025 drvdata->trfcr = trfcr;
1026 }
1027
etm4_init_arch_data(void * info)1028 static void etm4_init_arch_data(void *info)
1029 {
1030 u32 etmidr0;
1031 u32 etmidr2;
1032 u32 etmidr3;
1033 u32 etmidr4;
1034 u32 etmidr5;
1035 struct etm4_init_arg *init_arg = info;
1036 struct etmv4_drvdata *drvdata;
1037 struct csdev_access *csa;
1038 int i;
1039
1040 drvdata = init_arg->drvdata;
1041 csa = init_arg->csa;
1042
1043 /*
1044 * If we are unable to detect the access mechanism,
1045 * or unable to detect the trace unit type, fail
1046 * early.
1047 */
1048 if (!etm4_init_csdev_access(drvdata, csa))
1049 return;
1050
1051 /* Detect the support for OS Lock before we actually use it */
1052 etm_detect_os_lock(drvdata, csa);
1053
1054 /* Make sure all registers are accessible */
1055 etm4_os_unlock_csa(drvdata, csa);
1056 etm4_cs_unlock(drvdata, csa);
1057
1058 etm4_check_arch_features(drvdata, init_arg->pid);
1059
1060 /* find all capabilities of the tracing unit */
1061 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1062
1063 /* INSTP0, bits[2:1] P0 tracing support field */
1064 if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
1065 drvdata->instrp0 = true;
1066 else
1067 drvdata->instrp0 = false;
1068
1069 /* TRCBB, bit[5] Branch broadcast tracing support bit */
1070 if (BMVAL(etmidr0, 5, 5))
1071 drvdata->trcbb = true;
1072 else
1073 drvdata->trcbb = false;
1074
1075 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1076 if (BMVAL(etmidr0, 6, 6))
1077 drvdata->trccond = true;
1078 else
1079 drvdata->trccond = false;
1080
1081 /* TRCCCI, bit[7] Cycle counting instruction bit */
1082 if (BMVAL(etmidr0, 7, 7))
1083 drvdata->trccci = true;
1084 else
1085 drvdata->trccci = false;
1086
1087 /* RETSTACK, bit[9] Return stack bit */
1088 if (BMVAL(etmidr0, 9, 9))
1089 drvdata->retstack = true;
1090 else
1091 drvdata->retstack = false;
1092
1093 /* NUMEVENT, bits[11:10] Number of events field */
1094 drvdata->nr_event = BMVAL(etmidr0, 10, 11);
1095 /* QSUPP, bits[16:15] Q element support field */
1096 drvdata->q_support = BMVAL(etmidr0, 15, 16);
1097 /* TSSIZE, bits[28:24] Global timestamp size field */
1098 drvdata->ts_size = BMVAL(etmidr0, 24, 28);
1099
1100 /* maximum size of resources */
1101 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1102 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1103 drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
1104 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1105 drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
1106 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1107 drvdata->ccsize = BMVAL(etmidr2, 25, 28);
1108
1109 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1110 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1111 drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
1112 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1113 drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
1114 drvdata->config.s_ex_level = drvdata->s_ex_level;
1115 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1116 drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
1117
1118 /*
1119 * TRCERR, bit[24] whether a trace unit can trace a
1120 * system error exception.
1121 */
1122 if (BMVAL(etmidr3, 24, 24))
1123 drvdata->trc_error = true;
1124 else
1125 drvdata->trc_error = false;
1126
1127 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1128 if (BMVAL(etmidr3, 25, 25))
1129 drvdata->syncpr = true;
1130 else
1131 drvdata->syncpr = false;
1132
1133 /* STALLCTL, bit[26] is stall control implemented? */
1134 if (BMVAL(etmidr3, 26, 26))
1135 drvdata->stallctl = true;
1136 else
1137 drvdata->stallctl = false;
1138
1139 /* SYSSTALL, bit[27] implementation can support stall control? */
1140 if (BMVAL(etmidr3, 27, 27))
1141 drvdata->sysstall = true;
1142 else
1143 drvdata->sysstall = false;
1144
1145 /* NUMPROC, bits[30:28] the number of PEs available for tracing */
1146 drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
1147
1148 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1149 if (BMVAL(etmidr3, 31, 31))
1150 drvdata->nooverflow = true;
1151 else
1152 drvdata->nooverflow = false;
1153
1154 /* number of resources trace unit supports */
1155 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1156 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1157 drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
1158 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1159 drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
1160 /*
1161 * NUMRSPAIR, bits[19:16]
1162 * The number of resource pairs conveyed by the HW starts at 0, i.e a
1163 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1164 * As such add 1 to the value of NUMRSPAIR for a better representation.
1165 *
1166 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1167 * the default TRUE and FALSE resource selectors are omitted.
1168 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1169 */
1170 drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
1171 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1172 drvdata->nr_resource += 1;
1173 /*
1174 * NUMSSCC, bits[23:20] the number of single-shot
1175 * comparator control for tracing. Read any status regs as these
1176 * also contain RO capability data.
1177 */
1178 drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
1179 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1180 drvdata->config.ss_status[i] =
1181 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1182 }
1183 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1184 drvdata->numcidc = BMVAL(etmidr4, 24, 27);
1185 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1186 drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
1187
1188 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1189 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1190 drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
1191 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1192 drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
1193 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1194 if (BMVAL(etmidr5, 22, 22))
1195 drvdata->atbtrig = true;
1196 else
1197 drvdata->atbtrig = false;
1198 /*
1199 * LPOVERRIDE, bit[23] implementation supports
1200 * low-power state override
1201 */
1202 if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
1203 drvdata->lpoverride = true;
1204 else
1205 drvdata->lpoverride = false;
1206 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1207 drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
1208 /* NUMCNTR, bits[30:28] number of counters available for tracing */
1209 drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
1210 etm4_cs_lock(drvdata, csa);
1211 cpu_detect_trace_filtering(drvdata);
1212 }
1213
etm4_get_victlr_access_type(struct etmv4_config * config)1214 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1215 {
1216 return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT;
1217 }
1218
1219 /* Set ELx trace filter access in the TRCVICTLR register */
etm4_set_victlr_access(struct etmv4_config * config)1220 static void etm4_set_victlr_access(struct etmv4_config *config)
1221 {
1222 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1223 config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1224 }
1225
etm4_set_default_config(struct etmv4_config * config)1226 static void etm4_set_default_config(struct etmv4_config *config)
1227 {
1228 /* disable all events tracing */
1229 config->eventctrl0 = 0x0;
1230 config->eventctrl1 = 0x0;
1231
1232 /* disable stalling */
1233 config->stall_ctrl = 0x0;
1234
1235 /* enable trace synchronization every 4096 bytes, if available */
1236 config->syncfreq = 0xC;
1237
1238 /* disable timestamp event */
1239 config->ts_ctrl = 0x0;
1240
1241 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1242 config->vinst_ctrl = BIT(0);
1243
1244 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1245 etm4_set_victlr_access(config);
1246 }
1247
etm4_get_ns_access_type(struct etmv4_config * config)1248 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1249 {
1250 u64 access_type = 0;
1251
1252 /*
1253 * EXLEVEL_NS, for NonSecure Exception levels.
1254 * The mask here is a generic value and must be
1255 * shifted to the corresponding field for the registers
1256 */
1257 if (!is_kernel_in_hyp_mode()) {
1258 /* Stay away from hypervisor mode for non-VHE */
1259 access_type = ETM_EXLEVEL_NS_HYP;
1260 if (config->mode & ETM_MODE_EXCL_KERN)
1261 access_type |= ETM_EXLEVEL_NS_OS;
1262 } else if (config->mode & ETM_MODE_EXCL_KERN) {
1263 access_type = ETM_EXLEVEL_NS_HYP;
1264 }
1265
1266 if (config->mode & ETM_MODE_EXCL_USER)
1267 access_type |= ETM_EXLEVEL_NS_APP;
1268
1269 return access_type;
1270 }
1271
1272 /*
1273 * Construct the exception level masks for a given config.
1274 * This must be shifted to the corresponding register field
1275 * for usage.
1276 */
etm4_get_access_type(struct etmv4_config * config)1277 static u64 etm4_get_access_type(struct etmv4_config *config)
1278 {
1279 /* All Secure exception levels are excluded from the trace */
1280 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1281 }
1282
etm4_get_comparator_access_type(struct etmv4_config * config)1283 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1284 {
1285 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1286 }
1287
etm4_set_comparator_filter(struct etmv4_config * config,u64 start,u64 stop,int comparator)1288 static void etm4_set_comparator_filter(struct etmv4_config *config,
1289 u64 start, u64 stop, int comparator)
1290 {
1291 u64 access_type = etm4_get_comparator_access_type(config);
1292
1293 /* First half of default address comparator */
1294 config->addr_val[comparator] = start;
1295 config->addr_acc[comparator] = access_type;
1296 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1297
1298 /* Second half of default address comparator */
1299 config->addr_val[comparator + 1] = stop;
1300 config->addr_acc[comparator + 1] = access_type;
1301 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1302
1303 /*
1304 * Configure the ViewInst function to include this address range
1305 * comparator.
1306 *
1307 * @comparator is divided by two since it is the index in the
1308 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1309 * address range comparator _pairs_.
1310 *
1311 * Therefore:
1312 * index 0 -> compatator pair 0
1313 * index 2 -> comparator pair 1
1314 * index 4 -> comparator pair 2
1315 * ...
1316 * index 14 -> comparator pair 7
1317 */
1318 config->viiectlr |= BIT(comparator / 2);
1319 }
1320
etm4_set_start_stop_filter(struct etmv4_config * config,u64 address,int comparator,enum etm_addr_type type)1321 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1322 u64 address, int comparator,
1323 enum etm_addr_type type)
1324 {
1325 int shift;
1326 u64 access_type = etm4_get_comparator_access_type(config);
1327
1328 /* Configure the comparator */
1329 config->addr_val[comparator] = address;
1330 config->addr_acc[comparator] = access_type;
1331 config->addr_type[comparator] = type;
1332
1333 /*
1334 * Configure ViewInst Start-Stop control register.
1335 * Addresses configured to start tracing go from bit 0 to n-1,
1336 * while those configured to stop tracing from 16 to 16 + n-1.
1337 */
1338 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1339 config->vissctlr |= BIT(shift + comparator);
1340 }
1341
etm4_set_default_filter(struct etmv4_config * config)1342 static void etm4_set_default_filter(struct etmv4_config *config)
1343 {
1344 /* Trace everything 'default' filter achieved by no filtering */
1345 config->viiectlr = 0x0;
1346
1347 /*
1348 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1349 * in the started state
1350 */
1351 config->vinst_ctrl |= BIT(9);
1352 config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1353
1354 /* No start-stop filtering for ViewInst */
1355 config->vissctlr = 0x0;
1356 }
1357
etm4_set_default(struct etmv4_config * config)1358 static void etm4_set_default(struct etmv4_config *config)
1359 {
1360 if (WARN_ON_ONCE(!config))
1361 return;
1362
1363 /*
1364 * Make default initialisation trace everything
1365 *
1366 * This is done by a minimum default config sufficient to enable
1367 * full instruction trace - with a default filter for trace all
1368 * achieved by having no filtering.
1369 */
1370 etm4_set_default_config(config);
1371 etm4_set_default_filter(config);
1372 }
1373
etm4_get_next_comparator(struct etmv4_drvdata * drvdata,u32 type)1374 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1375 {
1376 int nr_comparator, index = 0;
1377 struct etmv4_config *config = &drvdata->config;
1378
1379 /*
1380 * nr_addr_cmp holds the number of comparator _pair_, so time 2
1381 * for the total number of comparators.
1382 */
1383 nr_comparator = drvdata->nr_addr_cmp * 2;
1384
1385 /* Go through the tally of comparators looking for a free one. */
1386 while (index < nr_comparator) {
1387 switch (type) {
1388 case ETM_ADDR_TYPE_RANGE:
1389 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1390 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1391 return index;
1392
1393 /* Address range comparators go in pairs */
1394 index += 2;
1395 break;
1396 case ETM_ADDR_TYPE_START:
1397 case ETM_ADDR_TYPE_STOP:
1398 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1399 return index;
1400
1401 /* Start/stop address can have odd indexes */
1402 index += 1;
1403 break;
1404 default:
1405 return -EINVAL;
1406 }
1407 }
1408
1409 /* If we are here all the comparators have been used. */
1410 return -ENOSPC;
1411 }
1412
etm4_set_event_filters(struct etmv4_drvdata * drvdata,struct perf_event * event)1413 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1414 struct perf_event *event)
1415 {
1416 int i, comparator, ret = 0;
1417 u64 address;
1418 struct etmv4_config *config = &drvdata->config;
1419 struct etm_filters *filters = event->hw.addr_filters;
1420
1421 if (!filters)
1422 goto default_filter;
1423
1424 /* Sync events with what Perf got */
1425 perf_event_addr_filters_sync(event);
1426
1427 /*
1428 * If there are no filters to deal with simply go ahead with
1429 * the default filter, i.e the entire address range.
1430 */
1431 if (!filters->nr_filters)
1432 goto default_filter;
1433
1434 for (i = 0; i < filters->nr_filters; i++) {
1435 struct etm_filter *filter = &filters->etm_filter[i];
1436 enum etm_addr_type type = filter->type;
1437
1438 /* See if a comparator is free. */
1439 comparator = etm4_get_next_comparator(drvdata, type);
1440 if (comparator < 0) {
1441 ret = comparator;
1442 goto out;
1443 }
1444
1445 switch (type) {
1446 case ETM_ADDR_TYPE_RANGE:
1447 etm4_set_comparator_filter(config,
1448 filter->start_addr,
1449 filter->stop_addr,
1450 comparator);
1451 /*
1452 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1453 * in the started state
1454 */
1455 config->vinst_ctrl |= BIT(9);
1456
1457 /* No start-stop filtering for ViewInst */
1458 config->vissctlr = 0x0;
1459 break;
1460 case ETM_ADDR_TYPE_START:
1461 case ETM_ADDR_TYPE_STOP:
1462 /* Get the right start or stop address */
1463 address = (type == ETM_ADDR_TYPE_START ?
1464 filter->start_addr :
1465 filter->stop_addr);
1466
1467 /* Configure comparator */
1468 etm4_set_start_stop_filter(config, address,
1469 comparator, type);
1470
1471 /*
1472 * If filters::ssstatus == 1, trace acquisition was
1473 * started but the process was yanked away before the
1474 * the stop address was hit. As such the start/stop
1475 * logic needs to be re-started so that tracing can
1476 * resume where it left.
1477 *
1478 * The start/stop logic status when a process is
1479 * scheduled out is checked in function
1480 * etm4_disable_perf().
1481 */
1482 if (filters->ssstatus)
1483 config->vinst_ctrl |= BIT(9);
1484
1485 /* No include/exclude filtering for ViewInst */
1486 config->viiectlr = 0x0;
1487 break;
1488 default:
1489 ret = -EINVAL;
1490 goto out;
1491 }
1492 }
1493
1494 goto out;
1495
1496
1497 default_filter:
1498 etm4_set_default_filter(config);
1499
1500 out:
1501 return ret;
1502 }
1503
etm4_config_trace_mode(struct etmv4_config * config)1504 void etm4_config_trace_mode(struct etmv4_config *config)
1505 {
1506 u32 mode;
1507
1508 mode = config->mode;
1509 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1510
1511 /* excluding kernel AND user space doesn't make sense */
1512 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1513
1514 /* nothing to do if neither flags are set */
1515 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1516 return;
1517
1518 etm4_set_victlr_access(config);
1519 }
1520
etm4_online_cpu(unsigned int cpu)1521 static int etm4_online_cpu(unsigned int cpu)
1522 {
1523 if (!etmdrvdata[cpu])
1524 return 0;
1525
1526 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1527 coresight_enable(etmdrvdata[cpu]->csdev);
1528 return 0;
1529 }
1530
etm4_starting_cpu(unsigned int cpu)1531 static int etm4_starting_cpu(unsigned int cpu)
1532 {
1533 if (!etmdrvdata[cpu])
1534 return 0;
1535
1536 spin_lock(&etmdrvdata[cpu]->spinlock);
1537 if (!etmdrvdata[cpu]->os_unlock)
1538 etm4_os_unlock(etmdrvdata[cpu]);
1539
1540 if (local_read(&etmdrvdata[cpu]->mode))
1541 etm4_enable_hw(etmdrvdata[cpu]);
1542 spin_unlock(&etmdrvdata[cpu]->spinlock);
1543 return 0;
1544 }
1545
etm4_dying_cpu(unsigned int cpu)1546 static int etm4_dying_cpu(unsigned int cpu)
1547 {
1548 if (!etmdrvdata[cpu])
1549 return 0;
1550
1551 spin_lock(&etmdrvdata[cpu]->spinlock);
1552 if (local_read(&etmdrvdata[cpu]->mode))
1553 etm4_disable_hw(etmdrvdata[cpu]);
1554 spin_unlock(&etmdrvdata[cpu]->spinlock);
1555 return 0;
1556 }
1557
etm4_init_trace_id(struct etmv4_drvdata * drvdata)1558 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1559 {
1560 drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1561 }
1562
__etm4_cpu_save(struct etmv4_drvdata * drvdata)1563 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1564 {
1565 int i, ret = 0;
1566 struct etmv4_save_state *state;
1567 struct coresight_device *csdev = drvdata->csdev;
1568 struct csdev_access *csa;
1569 struct device *etm_dev;
1570
1571 if (WARN_ON(!csdev))
1572 return -ENODEV;
1573
1574 etm_dev = &csdev->dev;
1575 csa = &csdev->access;
1576
1577 /*
1578 * As recommended by 3.4.1 ("The procedure when powering down the PE")
1579 * of ARM IHI 0064D
1580 */
1581 dsb(sy);
1582 isb();
1583
1584 etm4_cs_unlock(drvdata, csa);
1585 /* Lock the OS lock to disable trace and external debugger access */
1586 etm4_os_lock(drvdata);
1587
1588 /* wait for TRCSTATR.PMSTABLE to go up */
1589 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1590 dev_err(etm_dev,
1591 "timeout while waiting for PM Stable Status\n");
1592 etm4_os_unlock(drvdata);
1593 ret = -EBUSY;
1594 goto out;
1595 }
1596
1597 state = drvdata->save_state;
1598
1599 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1600 if (drvdata->nr_pe)
1601 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1602 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1603 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1604 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1605 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1606 if (drvdata->stallctl)
1607 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1608 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1609 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1610 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1611 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1612 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1613 state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1614
1615 state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1616 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1617 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1618 if (drvdata->nr_pe_cmp)
1619 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1620 state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1621 state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1622 state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1623
1624 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1625 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1626
1627 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1628 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1629 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1630
1631 for (i = 0; i < drvdata->nr_cntr; i++) {
1632 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1633 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1634 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1635 }
1636
1637 for (i = 0; i < drvdata->nr_resource * 2; i++)
1638 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1639
1640 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1641 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1642 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1643 if (etm4x_sspcicrn_present(drvdata, i))
1644 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1645 }
1646
1647 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1648 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1649 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1650 }
1651
1652 /*
1653 * Data trace stream is architecturally prohibited for A profile cores
1654 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1655 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1656 * unit") of ARM IHI 0064D.
1657 */
1658
1659 for (i = 0; i < drvdata->numcidc; i++)
1660 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1661
1662 for (i = 0; i < drvdata->numvmidc; i++)
1663 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1664
1665 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1666 if (drvdata->numcidc > 4)
1667 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1668
1669 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1670 if (drvdata->numvmidc > 4)
1671 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1672
1673 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1674
1675 if (!drvdata->skip_power_up)
1676 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1677
1678 /* wait for TRCSTATR.IDLE to go up */
1679 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1680 dev_err(etm_dev,
1681 "timeout while waiting for Idle Trace Status\n");
1682 etm4_os_unlock(drvdata);
1683 ret = -EBUSY;
1684 goto out;
1685 }
1686
1687 drvdata->state_needs_restore = true;
1688
1689 /*
1690 * Power can be removed from the trace unit now. We do this to
1691 * potentially save power on systems that respect the TRCPDCR_PU
1692 * despite requesting software to save/restore state.
1693 */
1694 if (!drvdata->skip_power_up)
1695 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1696 TRCPDCR);
1697 out:
1698 etm4_cs_lock(drvdata, csa);
1699 return ret;
1700 }
1701
etm4_cpu_save(struct etmv4_drvdata * drvdata)1702 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1703 {
1704 int ret = 0;
1705
1706 /* Save the TRFCR irrespective of whether the ETM is ON */
1707 if (drvdata->trfcr)
1708 drvdata->save_trfcr = read_trfcr();
1709 /*
1710 * Save and restore the ETM Trace registers only if
1711 * the ETM is active.
1712 */
1713 if (local_read(&drvdata->mode) && drvdata->save_state)
1714 ret = __etm4_cpu_save(drvdata);
1715 return ret;
1716 }
1717
__etm4_cpu_restore(struct etmv4_drvdata * drvdata)1718 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1719 {
1720 int i;
1721 struct etmv4_save_state *state = drvdata->save_state;
1722 struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1723 struct csdev_access *csa = &tmp_csa;
1724
1725 etm4_cs_unlock(drvdata, csa);
1726 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1727
1728 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1729 if (drvdata->nr_pe)
1730 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1731 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1732 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1733 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1734 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1735 if (drvdata->stallctl)
1736 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1737 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1738 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1739 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1740 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1741 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1742 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1743
1744 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1745 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1746 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1747 if (drvdata->nr_pe_cmp)
1748 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1749 etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1750 etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1751 etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1752
1753 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1754 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1755
1756 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1757 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1758 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1759
1760 for (i = 0; i < drvdata->nr_cntr; i++) {
1761 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1762 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1763 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1764 }
1765
1766 for (i = 0; i < drvdata->nr_resource * 2; i++)
1767 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1768
1769 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1770 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1771 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1772 if (etm4x_sspcicrn_present(drvdata, i))
1773 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1774 }
1775
1776 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1777 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1778 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1779 }
1780
1781 for (i = 0; i < drvdata->numcidc; i++)
1782 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1783
1784 for (i = 0; i < drvdata->numvmidc; i++)
1785 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1786
1787 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1788 if (drvdata->numcidc > 4)
1789 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1790
1791 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1792 if (drvdata->numvmidc > 4)
1793 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1794
1795 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1796
1797 if (!drvdata->skip_power_up)
1798 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1799
1800 drvdata->state_needs_restore = false;
1801
1802 /*
1803 * As recommended by section 4.3.7 ("Synchronization when using the
1804 * memory-mapped interface") of ARM IHI 0064D
1805 */
1806 dsb(sy);
1807 isb();
1808
1809 /* Unlock the OS lock to re-enable trace and external debug access */
1810 etm4_os_unlock(drvdata);
1811 etm4_cs_lock(drvdata, csa);
1812 }
1813
etm4_cpu_restore(struct etmv4_drvdata * drvdata)1814 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1815 {
1816 if (drvdata->trfcr)
1817 write_trfcr(drvdata->save_trfcr);
1818 if (drvdata->state_needs_restore)
1819 __etm4_cpu_restore(drvdata);
1820 }
1821
etm4_cpu_pm_notify(struct notifier_block * nb,unsigned long cmd,void * v)1822 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1823 void *v)
1824 {
1825 struct etmv4_drvdata *drvdata;
1826 unsigned int cpu = smp_processor_id();
1827
1828 if (!etmdrvdata[cpu])
1829 return NOTIFY_OK;
1830
1831 drvdata = etmdrvdata[cpu];
1832
1833 if (WARN_ON_ONCE(drvdata->cpu != cpu))
1834 return NOTIFY_BAD;
1835
1836 switch (cmd) {
1837 case CPU_PM_ENTER:
1838 if (etm4_cpu_save(drvdata))
1839 return NOTIFY_BAD;
1840 break;
1841 case CPU_PM_EXIT:
1842 case CPU_PM_ENTER_FAILED:
1843 etm4_cpu_restore(drvdata);
1844 break;
1845 default:
1846 return NOTIFY_DONE;
1847 }
1848
1849 return NOTIFY_OK;
1850 }
1851
1852 static struct notifier_block etm4_cpu_pm_nb = {
1853 .notifier_call = etm4_cpu_pm_notify,
1854 };
1855
1856 /* Setup PM. Deals with error conditions and counts */
etm4_pm_setup(void)1857 static int __init etm4_pm_setup(void)
1858 {
1859 int ret;
1860
1861 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1862 if (ret)
1863 return ret;
1864
1865 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1866 "arm/coresight4:starting",
1867 etm4_starting_cpu, etm4_dying_cpu);
1868
1869 if (ret)
1870 goto unregister_notifier;
1871
1872 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1873 "arm/coresight4:online",
1874 etm4_online_cpu, NULL);
1875
1876 /* HP dyn state ID returned in ret on success */
1877 if (ret > 0) {
1878 hp_online = ret;
1879 return 0;
1880 }
1881
1882 /* failed dyn state - remove others */
1883 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1884
1885 unregister_notifier:
1886 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1887 return ret;
1888 }
1889
etm4_pm_clear(void)1890 static void etm4_pm_clear(void)
1891 {
1892 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1893 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1894 if (hp_online) {
1895 cpuhp_remove_state_nocalls(hp_online);
1896 hp_online = 0;
1897 }
1898 }
1899
etm4_probe(struct device * dev,void __iomem * base,u32 etm_pid)1900 static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
1901 {
1902 int ret;
1903 struct coresight_platform_data *pdata = NULL;
1904 struct etmv4_drvdata *drvdata;
1905 struct coresight_desc desc = { 0 };
1906 struct etm4_init_arg init_arg = { 0 };
1907 u8 major, minor;
1908 char *type_name;
1909
1910 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1911 if (!drvdata)
1912 return -ENOMEM;
1913
1914 dev_set_drvdata(dev, drvdata);
1915
1916 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1917 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1918 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1919
1920 if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1921 drvdata->save_state = devm_kmalloc(dev,
1922 sizeof(struct etmv4_save_state), GFP_KERNEL);
1923 if (!drvdata->save_state)
1924 return -ENOMEM;
1925 }
1926
1927 drvdata->base = base;
1928
1929 spin_lock_init(&drvdata->spinlock);
1930
1931 drvdata->cpu = coresight_get_cpu(dev);
1932 if (drvdata->cpu < 0)
1933 return drvdata->cpu;
1934
1935 init_arg.drvdata = drvdata;
1936 init_arg.csa = &desc.access;
1937 init_arg.pid = etm_pid;
1938
1939 if (smp_call_function_single(drvdata->cpu,
1940 etm4_init_arch_data, &init_arg, 1))
1941 dev_err(dev, "ETM arch init failed\n");
1942
1943 if (!drvdata->arch)
1944 return -EINVAL;
1945
1946 /* TRCPDCR is not accessible with system instructions. */
1947 if (!desc.access.io_mem ||
1948 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1949 drvdata->skip_power_up = true;
1950
1951 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
1952 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
1953
1954 if (etm4x_is_ete(drvdata)) {
1955 type_name = "ete";
1956 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
1957 major -= 4;
1958 } else {
1959 type_name = "etm";
1960 }
1961
1962 desc.name = devm_kasprintf(dev, GFP_KERNEL,
1963 "%s%d", type_name, drvdata->cpu);
1964 if (!desc.name)
1965 return -ENOMEM;
1966
1967 etm4_init_trace_id(drvdata);
1968 etm4_set_default(&drvdata->config);
1969
1970 pdata = coresight_get_platform_data(dev);
1971 if (IS_ERR(pdata))
1972 return PTR_ERR(pdata);
1973
1974 dev->platform_data = pdata;
1975
1976 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1977 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1978 desc.ops = &etm4_cs_ops;
1979 desc.pdata = pdata;
1980 desc.dev = dev;
1981 desc.groups = coresight_etmv4_groups;
1982 drvdata->csdev = coresight_register(&desc);
1983 if (IS_ERR(drvdata->csdev))
1984 return PTR_ERR(drvdata->csdev);
1985
1986 ret = etm_perf_symlink(drvdata->csdev, true);
1987 if (ret) {
1988 coresight_unregister(drvdata->csdev);
1989 return ret;
1990 }
1991
1992 etmdrvdata[drvdata->cpu] = drvdata;
1993
1994 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
1995 drvdata->cpu, type_name, major, minor);
1996
1997 if (boot_enable) {
1998 coresight_enable(drvdata->csdev);
1999 drvdata->boot_enable = true;
2000 }
2001
2002 return 0;
2003 }
2004
etm4_probe_amba(struct amba_device * adev,const struct amba_id * id)2005 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2006 {
2007 void __iomem *base;
2008 struct device *dev = &adev->dev;
2009 struct resource *res = &adev->res;
2010 int ret;
2011
2012 /* Validity for the resource is already checked by the AMBA core */
2013 base = devm_ioremap_resource(dev, res);
2014 if (IS_ERR(base))
2015 return PTR_ERR(base);
2016
2017 ret = etm4_probe(dev, base, id->id);
2018 if (!ret)
2019 pm_runtime_put(&adev->dev);
2020
2021 return ret;
2022 }
2023
etm4_probe_platform_dev(struct platform_device * pdev)2024 static int etm4_probe_platform_dev(struct platform_device *pdev)
2025 {
2026 int ret;
2027
2028 pm_runtime_get_noresume(&pdev->dev);
2029 pm_runtime_set_active(&pdev->dev);
2030 pm_runtime_enable(&pdev->dev);
2031
2032 /*
2033 * System register based devices could match the
2034 * HW by reading appropriate registers on the HW
2035 * and thus we could skip the PID.
2036 */
2037 ret = etm4_probe(&pdev->dev, NULL, 0);
2038
2039 pm_runtime_put(&pdev->dev);
2040 return ret;
2041 }
2042
2043 static struct amba_cs_uci_id uci_id_etm4[] = {
2044 {
2045 /* ETMv4 UCI data */
2046 .devarch = ETM_DEVARCH_ETMv4x_ARCH,
2047 .devarch_mask = ETM_DEVARCH_ID_MASK,
2048 .devtype = 0x00000013,
2049 }
2050 };
2051
clear_etmdrvdata(void * info)2052 static void clear_etmdrvdata(void *info)
2053 {
2054 int cpu = *(int *)info;
2055
2056 etmdrvdata[cpu] = NULL;
2057 }
2058
etm4_remove_dev(struct etmv4_drvdata * drvdata)2059 static void __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
2060 {
2061 etm_perf_symlink(drvdata->csdev, false);
2062 /*
2063 * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2064 * and CPU hotplug call backs.
2065 */
2066 cpus_read_lock();
2067 /*
2068 * The readers for etmdrvdata[] are CPU hotplug call backs
2069 * and PM notification call backs. Change etmdrvdata[i] on
2070 * CPU i ensures these call backs has consistent view
2071 * inside one call back function.
2072 */
2073 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2074 etmdrvdata[drvdata->cpu] = NULL;
2075
2076 cpus_read_unlock();
2077
2078 coresight_unregister(drvdata->csdev);
2079 }
2080
etm4_remove_amba(struct amba_device * adev)2081 static void __exit etm4_remove_amba(struct amba_device *adev)
2082 {
2083 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2084
2085 if (drvdata)
2086 etm4_remove_dev(drvdata);
2087 }
2088
etm4_remove_platform_dev(struct platform_device * pdev)2089 static int __exit etm4_remove_platform_dev(struct platform_device *pdev)
2090 {
2091 int ret = 0;
2092 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2093
2094 if (drvdata)
2095 etm4_remove_dev(drvdata);
2096 pm_runtime_disable(&pdev->dev);
2097 return ret;
2098 }
2099
2100 static const struct amba_id etm4_ids[] = {
2101 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
2102 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
2103 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
2104 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
2105 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2106 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2107 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2108 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2109 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2110 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2111 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2112 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2113 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2114 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2115 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2116 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2117 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2118 {},
2119 };
2120
2121 MODULE_DEVICE_TABLE(amba, etm4_ids);
2122
2123 static struct amba_driver etm4x_amba_driver = {
2124 .drv = {
2125 .name = "coresight-etm4x",
2126 .owner = THIS_MODULE,
2127 .suppress_bind_attrs = true,
2128 },
2129 .probe = etm4_probe_amba,
2130 .remove = etm4_remove_amba,
2131 .id_table = etm4_ids,
2132 };
2133
2134 static const struct of_device_id etm4_sysreg_match[] = {
2135 { .compatible = "arm,coresight-etm4x-sysreg" },
2136 { .compatible = "arm,embedded-trace-extension" },
2137 {}
2138 };
2139
2140 static struct platform_driver etm4_platform_driver = {
2141 .probe = etm4_probe_platform_dev,
2142 .remove = etm4_remove_platform_dev,
2143 .driver = {
2144 .name = "coresight-etm4x",
2145 .of_match_table = etm4_sysreg_match,
2146 .suppress_bind_attrs = true,
2147 },
2148 };
2149
etm4x_init(void)2150 static int __init etm4x_init(void)
2151 {
2152 int ret;
2153
2154 ret = etm4_pm_setup();
2155
2156 /* etm4_pm_setup() does its own cleanup - exit on error */
2157 if (ret)
2158 return ret;
2159
2160 ret = amba_driver_register(&etm4x_amba_driver);
2161 if (ret) {
2162 pr_err("Error registering etm4x AMBA driver\n");
2163 goto clear_pm;
2164 }
2165
2166 ret = platform_driver_register(&etm4_platform_driver);
2167 if (!ret)
2168 return 0;
2169
2170 pr_err("Error registering etm4x platform driver\n");
2171 amba_driver_unregister(&etm4x_amba_driver);
2172
2173 clear_pm:
2174 etm4_pm_clear();
2175 return ret;
2176 }
2177
etm4x_exit(void)2178 static void __exit etm4x_exit(void)
2179 {
2180 amba_driver_unregister(&etm4x_amba_driver);
2181 platform_driver_unregister(&etm4_platform_driver);
2182 etm4_pm_clear();
2183 }
2184
2185 module_init(etm4x_init);
2186 module_exit(etm4x_exit);
2187
2188 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2189 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2190 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2191 MODULE_LICENSE("GPL v2");
2192