1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4*4882a593Smuzhiyun * Author:
5*4882a593Smuzhiyun * Sandy Huang <hjc@rock-chips.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/component.h>
9*4882a593Smuzhiyun #include <linux/of_device.h>
10*4882a593Smuzhiyun #include <linux/of_graph.h>
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
13*4882a593Smuzhiyun #include <linux/phy/phy.h>
14*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
15*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <video/of_display_timing.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
20*4882a593Smuzhiyun #include <drm/drm_crtc_helper.h>
21*4882a593Smuzhiyun #include <drm/drm_dp_helper.h>
22*4882a593Smuzhiyun #include <drm/drm_of.h>
23*4882a593Smuzhiyun #include <drm/drm_panel.h>
24*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <uapi/linux/videodev2.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include "rockchip_drm_drv.h"
29*4882a593Smuzhiyun #include "rockchip_drm_vop.h"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define HIWORD_UPDATE(v, l, h) (((v) << (l)) | (GENMASK(h, l) << 16))
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define PX30_GRF_PD_VO_CON1 0x0438
34*4882a593Smuzhiyun #define PX30_RGB_DATA_SYNC_BYPASS(v) HIWORD_UPDATE(v, 3, 3)
35*4882a593Smuzhiyun #define PX30_RGB_VOP_SEL(v) HIWORD_UPDATE(v, 2, 2)
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define RK1808_GRF_PD_VO_CON1 0x0444
38*4882a593Smuzhiyun #define RK1808_RGB_DATA_SYNC_BYPASS(v) HIWORD_UPDATE(v, 3, 3)
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define RV1106_VENC_GRF_VOP_IO_WRAPPER 0x1000c
41*4882a593Smuzhiyun #define RV1106_IO_BYPASS_SEL(v) HIWORD_UPDATE(v, 0, 1)
42*4882a593Smuzhiyun #define RV1106_VOGRF_VOP_PIPE_BYPASS 0x60034
43*4882a593Smuzhiyun #define RV1106_VOP_PIPE_BYPASS(v) HIWORD_UPDATE(v, 0, 1)
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define RV1126_GRF_IOFUNC_CON3 0x1026c
46*4882a593Smuzhiyun #define RV1126_LCDC_IO_BYPASS(v) HIWORD_UPDATE(v, 0, 0)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON6 0x025c
49*4882a593Smuzhiyun #define RK3288_LVDS_LCDC_SEL(x) HIWORD_UPDATE(x, 3, 3)
50*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON7 0x0260
51*4882a593Smuzhiyun #define RK3288_LVDS_PWRDWN(x) HIWORD_UPDATE(x, 15, 15)
52*4882a593Smuzhiyun #define RK3288_LVDS_CON_ENABLE_2(x) HIWORD_UPDATE(x, 12, 12)
53*4882a593Smuzhiyun #define RK3288_LVDS_CON_ENABLE_1(x) HIWORD_UPDATE(x, 11, 11)
54*4882a593Smuzhiyun #define RK3288_LVDS_CON_CLKINV(x) HIWORD_UPDATE(x, 8, 8)
55*4882a593Smuzhiyun #define RK3288_LVDS_CON_TTL_EN(x) HIWORD_UPDATE(x, 6, 6)
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define RK3562_GRF_IOC_VO_IO_CON 0x10500
58*4882a593Smuzhiyun #define RK3562_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6)
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define RK3568_GRF_VO_CON1 0X0364
61*4882a593Smuzhiyun #define RK3568_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6)
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun struct rockchip_rgb;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct rockchip_rgb_funcs {
66*4882a593Smuzhiyun void (*enable)(struct rockchip_rgb *rgb);
67*4882a593Smuzhiyun void (*disable)(struct rockchip_rgb *rgb);
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun struct rockchip_rgb_data {
71*4882a593Smuzhiyun u32 max_dclk_rate;
72*4882a593Smuzhiyun const struct rockchip_rgb_funcs *funcs;
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun struct mcu_cmd_header {
76*4882a593Smuzhiyun u8 data_type;
77*4882a593Smuzhiyun u8 delay;
78*4882a593Smuzhiyun u8 payload_length;
79*4882a593Smuzhiyun } __packed;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun struct mcu_cmd_desc {
82*4882a593Smuzhiyun struct mcu_cmd_header header;
83*4882a593Smuzhiyun u8 *payload;
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun struct mcu_cmd_seq {
87*4882a593Smuzhiyun struct mcu_cmd_desc *cmds;
88*4882a593Smuzhiyun unsigned int cmd_cnt;
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct rockchip_mcu_panel_desc {
92*4882a593Smuzhiyun struct drm_display_mode *mode;
93*4882a593Smuzhiyun struct mcu_cmd_seq *init_seq;
94*4882a593Smuzhiyun struct mcu_cmd_seq *exit_seq;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun struct {
97*4882a593Smuzhiyun unsigned int width;
98*4882a593Smuzhiyun unsigned int height;
99*4882a593Smuzhiyun } size;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun struct {
102*4882a593Smuzhiyun unsigned int prepare;
103*4882a593Smuzhiyun unsigned int enable;
104*4882a593Smuzhiyun unsigned int disable;
105*4882a593Smuzhiyun unsigned int unprepare;
106*4882a593Smuzhiyun unsigned int reset;
107*4882a593Smuzhiyun unsigned int init;
108*4882a593Smuzhiyun } delay;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun unsigned int bpc;
111*4882a593Smuzhiyun u32 bus_format;
112*4882a593Smuzhiyun u32 bus_flags;
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun struct rockchip_mcu_panel {
116*4882a593Smuzhiyun struct drm_panel base;
117*4882a593Smuzhiyun struct drm_device *drm_dev;
118*4882a593Smuzhiyun struct rockchip_mcu_panel_desc *desc;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun struct gpio_desc *enable_gpio;
121*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun struct device_node *np_crtc;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun bool prepared;
126*4882a593Smuzhiyun bool enabled;
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun struct rockchip_rgb {
130*4882a593Smuzhiyun u8 id;
131*4882a593Smuzhiyun u32 max_dclk_rate;
132*4882a593Smuzhiyun struct device *dev;
133*4882a593Smuzhiyun struct drm_panel *panel;
134*4882a593Smuzhiyun struct drm_bridge *bridge;
135*4882a593Smuzhiyun struct drm_connector connector;
136*4882a593Smuzhiyun struct drm_encoder encoder;
137*4882a593Smuzhiyun struct phy *phy;
138*4882a593Smuzhiyun struct regmap *grf;
139*4882a593Smuzhiyun bool data_sync_bypass;
140*4882a593Smuzhiyun bool is_mcu_panel;
141*4882a593Smuzhiyun bool phy_enabled;
142*4882a593Smuzhiyun const struct rockchip_rgb_funcs *funcs;
143*4882a593Smuzhiyun struct rockchip_drm_sub_dev sub_dev;
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun
connector_to_rgb(struct drm_connector * c)146*4882a593Smuzhiyun static inline struct rockchip_rgb *connector_to_rgb(struct drm_connector *c)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun return container_of(c, struct rockchip_rgb, connector);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
encoder_to_rgb(struct drm_encoder * e)151*4882a593Smuzhiyun static inline struct rockchip_rgb *encoder_to_rgb(struct drm_encoder *e)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun return container_of(e, struct rockchip_rgb, encoder);
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
to_rockchip_mcu_panel(struct drm_panel * panel)156*4882a593Smuzhiyun static inline struct rockchip_mcu_panel *to_rockchip_mcu_panel(struct drm_panel *panel)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun return container_of(panel, struct rockchip_mcu_panel, base);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun static enum drm_connector_status
rockchip_rgb_connector_detect(struct drm_connector * connector,bool force)162*4882a593Smuzhiyun rockchip_rgb_connector_detect(struct drm_connector *connector, bool force)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun return connector_status_connected;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun static int
rockchip_rgb_atomic_connector_get_property(struct drm_connector * connector,const struct drm_connector_state * state,struct drm_property * property,uint64_t * val)168*4882a593Smuzhiyun rockchip_rgb_atomic_connector_get_property(struct drm_connector *connector,
169*4882a593Smuzhiyun const struct drm_connector_state *state,
170*4882a593Smuzhiyun struct drm_property *property,
171*4882a593Smuzhiyun uint64_t *val)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun struct rockchip_rgb *rgb = connector_to_rgb(connector);
174*4882a593Smuzhiyun struct rockchip_drm_private *private = connector->dev->dev_private;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun if (property == private->connector_id_prop) {
177*4882a593Smuzhiyun *val = rgb->id;
178*4882a593Smuzhiyun return 0;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun DRM_ERROR("failed to get rockchip RGB property\n");
182*4882a593Smuzhiyun return -EINVAL;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun static const struct drm_connector_funcs rockchip_rgb_connector_funcs = {
186*4882a593Smuzhiyun .detect = rockchip_rgb_connector_detect,
187*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
188*4882a593Smuzhiyun .destroy = drm_connector_cleanup,
189*4882a593Smuzhiyun .reset = drm_atomic_helper_connector_reset,
190*4882a593Smuzhiyun .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
191*4882a593Smuzhiyun .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
192*4882a593Smuzhiyun .atomic_get_property = rockchip_rgb_atomic_connector_get_property,
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun
rockchip_rgb_connector_get_modes(struct drm_connector * connector)195*4882a593Smuzhiyun static int rockchip_rgb_connector_get_modes(struct drm_connector *connector)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun struct rockchip_rgb *rgb = connector_to_rgb(connector);
198*4882a593Smuzhiyun struct drm_panel *panel = rgb->panel;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return drm_panel_get_modes(panel, connector);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static struct drm_encoder *
rockchip_rgb_connector_best_encoder(struct drm_connector * connector)204*4882a593Smuzhiyun rockchip_rgb_connector_best_encoder(struct drm_connector *connector)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun struct rockchip_rgb *rgb = connector_to_rgb(connector);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun return &rgb->encoder;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun static const
212*4882a593Smuzhiyun struct drm_connector_helper_funcs rockchip_rgb_connector_helper_funcs = {
213*4882a593Smuzhiyun .get_modes = rockchip_rgb_connector_get_modes,
214*4882a593Smuzhiyun .best_encoder = rockchip_rgb_connector_best_encoder,
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
rockchip_rgb_encoder_enable(struct drm_encoder * encoder)217*4882a593Smuzhiyun static void rockchip_rgb_encoder_enable(struct drm_encoder *encoder)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun struct rockchip_rgb *rgb = encoder_to_rgb(encoder);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun pinctrl_pm_select_default_state(rgb->dev);
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun if (rgb->funcs && rgb->funcs->enable)
224*4882a593Smuzhiyun rgb->funcs->enable(rgb);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun if (rgb->phy && !rgb->phy_enabled) {
227*4882a593Smuzhiyun phy_power_on(rgb->phy);
228*4882a593Smuzhiyun rgb->phy_enabled = true;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun if (rgb->panel) {
232*4882a593Smuzhiyun drm_panel_prepare(rgb->panel);
233*4882a593Smuzhiyun drm_panel_enable(rgb->panel);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
rockchip_rgb_encoder_disable(struct drm_encoder * encoder)237*4882a593Smuzhiyun static void rockchip_rgb_encoder_disable(struct drm_encoder *encoder)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun struct rockchip_rgb *rgb = encoder_to_rgb(encoder);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun if (rgb->panel) {
242*4882a593Smuzhiyun drm_panel_disable(rgb->panel);
243*4882a593Smuzhiyun drm_panel_unprepare(rgb->panel);
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (rgb->phy && rgb->phy_enabled) {
247*4882a593Smuzhiyun phy_power_off(rgb->phy);
248*4882a593Smuzhiyun rgb->phy_enabled = false;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun if (rgb->funcs && rgb->funcs->disable)
252*4882a593Smuzhiyun rgb->funcs->disable(rgb);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun pinctrl_pm_select_sleep_state(rgb->dev);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun static int
rockchip_rgb_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)258*4882a593Smuzhiyun rockchip_rgb_encoder_atomic_check(struct drm_encoder *encoder,
259*4882a593Smuzhiyun struct drm_crtc_state *crtc_state,
260*4882a593Smuzhiyun struct drm_connector_state *conn_state)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
263*4882a593Smuzhiyun struct drm_connector *connector = conn_state->connector;
264*4882a593Smuzhiyun struct drm_display_info *info = &connector->display_info;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun if (info->num_bus_formats)
267*4882a593Smuzhiyun s->bus_format = info->bus_formats[0];
268*4882a593Smuzhiyun else
269*4882a593Smuzhiyun s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun switch (s->bus_format) {
272*4882a593Smuzhiyun case MEDIA_BUS_FMT_RGB666_1X18:
273*4882a593Smuzhiyun s->output_mode = ROCKCHIP_OUT_MODE_P666;
274*4882a593Smuzhiyun s->output_if = VOP_OUTPUT_IF_RGB;
275*4882a593Smuzhiyun break;
276*4882a593Smuzhiyun case MEDIA_BUS_FMT_RGB565_1X16:
277*4882a593Smuzhiyun s->output_mode = ROCKCHIP_OUT_MODE_P565;
278*4882a593Smuzhiyun s->output_if = VOP_OUTPUT_IF_RGB;
279*4882a593Smuzhiyun break;
280*4882a593Smuzhiyun case MEDIA_BUS_FMT_RGB565_2X8_LE:
281*4882a593Smuzhiyun case MEDIA_BUS_FMT_BGR565_2X8_LE:
282*4882a593Smuzhiyun s->output_mode = ROCKCHIP_OUT_MODE_S565;
283*4882a593Smuzhiyun s->output_if = VOP_OUTPUT_IF_RGB;
284*4882a593Smuzhiyun break;
285*4882a593Smuzhiyun case MEDIA_BUS_FMT_RGB666_3X6:
286*4882a593Smuzhiyun s->output_mode = ROCKCHIP_OUT_MODE_S666;
287*4882a593Smuzhiyun s->output_if = VOP_OUTPUT_IF_RGB;
288*4882a593Smuzhiyun break;
289*4882a593Smuzhiyun case MEDIA_BUS_FMT_RGB888_3X8:
290*4882a593Smuzhiyun case MEDIA_BUS_FMT_BGR888_3X8:
291*4882a593Smuzhiyun s->output_mode = ROCKCHIP_OUT_MODE_S888;
292*4882a593Smuzhiyun s->output_if = VOP_OUTPUT_IF_RGB;
293*4882a593Smuzhiyun break;
294*4882a593Smuzhiyun case MEDIA_BUS_FMT_RGB888_DUMMY_4X8:
295*4882a593Smuzhiyun case MEDIA_BUS_FMT_BGR888_DUMMY_4X8:
296*4882a593Smuzhiyun s->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY;
297*4882a593Smuzhiyun s->output_if = VOP_OUTPUT_IF_RGB;
298*4882a593Smuzhiyun break;
299*4882a593Smuzhiyun case MEDIA_BUS_FMT_YUYV8_2X8:
300*4882a593Smuzhiyun case MEDIA_BUS_FMT_YVYU8_2X8:
301*4882a593Smuzhiyun case MEDIA_BUS_FMT_UYVY8_2X8:
302*4882a593Smuzhiyun case MEDIA_BUS_FMT_VYUY8_2X8:
303*4882a593Smuzhiyun s->output_mode = ROCKCHIP_OUT_MODE_BT656;
304*4882a593Smuzhiyun s->output_if = VOP_OUTPUT_IF_BT656;
305*4882a593Smuzhiyun break;
306*4882a593Smuzhiyun case MEDIA_BUS_FMT_YUYV8_1X16:
307*4882a593Smuzhiyun case MEDIA_BUS_FMT_YVYU8_1X16:
308*4882a593Smuzhiyun case MEDIA_BUS_FMT_UYVY8_1X16:
309*4882a593Smuzhiyun case MEDIA_BUS_FMT_VYUY8_1X16:
310*4882a593Smuzhiyun s->output_mode = ROCKCHIP_OUT_MODE_BT1120;
311*4882a593Smuzhiyun s->output_if = VOP_OUTPUT_IF_BT1120;
312*4882a593Smuzhiyun break;
313*4882a593Smuzhiyun case MEDIA_BUS_FMT_RGB888_1X24:
314*4882a593Smuzhiyun case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
315*4882a593Smuzhiyun default:
316*4882a593Smuzhiyun s->output_mode = ROCKCHIP_OUT_MODE_P888;
317*4882a593Smuzhiyun s->output_if = VOP_OUTPUT_IF_RGB;
318*4882a593Smuzhiyun break;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun s->output_type = DRM_MODE_CONNECTOR_DPI;
322*4882a593Smuzhiyun s->bus_flags = info->bus_flags;
323*4882a593Smuzhiyun s->tv_state = &conn_state->tv;
324*4882a593Smuzhiyun s->eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR;
325*4882a593Smuzhiyun s->color_space = V4L2_COLORSPACE_DEFAULT;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun return 0;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
rockchip_rgb_encoder_loader_protect(struct drm_encoder * encoder,bool on)330*4882a593Smuzhiyun static int rockchip_rgb_encoder_loader_protect(struct drm_encoder *encoder,
331*4882a593Smuzhiyun bool on)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun struct rockchip_rgb *rgb = encoder_to_rgb(encoder);
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun if (rgb->is_mcu_panel) {
336*4882a593Smuzhiyun struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(rgb->panel);
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun mcu_panel->prepared = true;
339*4882a593Smuzhiyun mcu_panel->enabled = true;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun return 0;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun if (rgb->panel)
345*4882a593Smuzhiyun panel_simple_loader_protect(rgb->panel);
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun if (on) {
348*4882a593Smuzhiyun phy_init(rgb->phy);
349*4882a593Smuzhiyun if (rgb->phy) {
350*4882a593Smuzhiyun rgb->phy->power_count++;
351*4882a593Smuzhiyun rgb->phy_enabled = true;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun } else {
354*4882a593Smuzhiyun phy_exit(rgb->phy);
355*4882a593Smuzhiyun if (rgb->phy) {
356*4882a593Smuzhiyun rgb->phy->power_count--;
357*4882a593Smuzhiyun rgb->phy_enabled = false;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun return 0;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun static enum drm_mode_status
rockchip_rgb_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)365*4882a593Smuzhiyun rockchip_rgb_encoder_mode_valid(struct drm_encoder *encoder,
366*4882a593Smuzhiyun const struct drm_display_mode *mode)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun struct rockchip_rgb *rgb = encoder_to_rgb(encoder);
369*4882a593Smuzhiyun struct device *dev = rgb->dev;
370*4882a593Smuzhiyun u32 request_clock = mode->clock;
371*4882a593Smuzhiyun u32 max_clock = rgb->max_dclk_rate;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun if (mode->flags & DRM_MODE_FLAG_DBLCLK)
374*4882a593Smuzhiyun request_clock *= 2;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun if (max_clock != 0 && request_clock > max_clock) {
377*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "mode [%dx%d] clock %d is higher than max_clock %d\n",
378*4882a593Smuzhiyun mode->hdisplay, mode->vdisplay, request_clock, max_clock);
379*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun return MODE_OK;
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun static const
386*4882a593Smuzhiyun struct drm_encoder_helper_funcs rockchip_rgb_encoder_helper_funcs = {
387*4882a593Smuzhiyun .enable = rockchip_rgb_encoder_enable,
388*4882a593Smuzhiyun .disable = rockchip_rgb_encoder_disable,
389*4882a593Smuzhiyun .atomic_check = rockchip_rgb_encoder_atomic_check,
390*4882a593Smuzhiyun .mode_valid = rockchip_rgb_encoder_mode_valid,
391*4882a593Smuzhiyun };
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun static const struct drm_encoder_funcs rockchip_rgb_encoder_funcs = {
394*4882a593Smuzhiyun .destroy = drm_encoder_cleanup,
395*4882a593Smuzhiyun };
396*4882a593Smuzhiyun
rockchip_mcu_panel_parse_cmd_seq(struct device * dev,const u8 * data,int length,struct mcu_cmd_seq * seq)397*4882a593Smuzhiyun static int rockchip_mcu_panel_parse_cmd_seq(struct device *dev,
398*4882a593Smuzhiyun const u8 *data, int length,
399*4882a593Smuzhiyun struct mcu_cmd_seq *seq)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun struct mcu_cmd_header *header;
402*4882a593Smuzhiyun struct mcu_cmd_desc *desc;
403*4882a593Smuzhiyun char *buf, *d;
404*4882a593Smuzhiyun unsigned int i, cnt, len;
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun if (!seq)
407*4882a593Smuzhiyun return -EINVAL;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun buf = devm_kmemdup(dev, data, length, GFP_KERNEL);
410*4882a593Smuzhiyun if (!buf)
411*4882a593Smuzhiyun return -ENOMEM;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun d = buf;
414*4882a593Smuzhiyun len = length;
415*4882a593Smuzhiyun cnt = 0;
416*4882a593Smuzhiyun while (len > sizeof(*header)) {
417*4882a593Smuzhiyun header = (struct mcu_cmd_header *)d;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun d += sizeof(*header);
420*4882a593Smuzhiyun len -= sizeof(*header);
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun if (header->payload_length > len)
423*4882a593Smuzhiyun return -EINVAL;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun d += header->payload_length;
426*4882a593Smuzhiyun len -= header->payload_length;
427*4882a593Smuzhiyun cnt++;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun if (len)
431*4882a593Smuzhiyun return -EINVAL;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun seq->cmd_cnt = cnt;
434*4882a593Smuzhiyun seq->cmds = devm_kcalloc(dev, cnt, sizeof(*desc), GFP_KERNEL);
435*4882a593Smuzhiyun if (!seq->cmds)
436*4882a593Smuzhiyun return -ENOMEM;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun d = buf;
439*4882a593Smuzhiyun len = length;
440*4882a593Smuzhiyun for (i = 0; i < cnt; i++) {
441*4882a593Smuzhiyun header = (struct mcu_cmd_header *)d;
442*4882a593Smuzhiyun len -= sizeof(*header);
443*4882a593Smuzhiyun d += sizeof(*header);
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun desc = &seq->cmds[i];
446*4882a593Smuzhiyun desc->header = *header;
447*4882a593Smuzhiyun desc->payload = d;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun d += header->payload_length;
450*4882a593Smuzhiyun len -= header->payload_length;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun return 0;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
rockchip_mcu_panel_init(struct rockchip_rgb * rgb,struct device_node * np_mcu_panel)456*4882a593Smuzhiyun static int rockchip_mcu_panel_init(struct rockchip_rgb *rgb, struct device_node *np_mcu_panel)
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun struct device *dev = rgb->dev;
459*4882a593Smuzhiyun struct device_node *port, *endpoint, *np_crtc, *remote;
460*4882a593Smuzhiyun struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(rgb->panel);
461*4882a593Smuzhiyun struct drm_display_mode *mode;
462*4882a593Smuzhiyun const void *data;
463*4882a593Smuzhiyun int len;
464*4882a593Smuzhiyun int ret;
465*4882a593Smuzhiyun u32 bus_flags;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun mcu_panel->enable_gpio = devm_fwnode_gpiod_get_index(dev, &np_mcu_panel->fwnode,
468*4882a593Smuzhiyun "enable", 0, GPIOD_ASIS,
469*4882a593Smuzhiyun fwnode_get_name(&np_mcu_panel->fwnode));
470*4882a593Smuzhiyun if (IS_ERR(mcu_panel->enable_gpio)) {
471*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "failed to find mcu panel enable GPIO\n");
472*4882a593Smuzhiyun return PTR_ERR(mcu_panel->enable_gpio);
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun mcu_panel->reset_gpio = devm_fwnode_gpiod_get_index(dev, &np_mcu_panel->fwnode,
476*4882a593Smuzhiyun "reset", 0, GPIOD_ASIS,
477*4882a593Smuzhiyun fwnode_get_name(&np_mcu_panel->fwnode));
478*4882a593Smuzhiyun if (IS_ERR(mcu_panel->reset_gpio)) {
479*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "failed to find mcu panel reset GPIO\n");
480*4882a593Smuzhiyun return PTR_ERR(mcu_panel->reset_gpio);
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun mcu_panel->desc = devm_kzalloc(dev, sizeof(*mcu_panel->desc), GFP_KERNEL);
484*4882a593Smuzhiyun if (!mcu_panel->desc)
485*4882a593Smuzhiyun return -ENOMEM;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun mode = devm_kzalloc(dev, sizeof(*mode), GFP_KERNEL);
488*4882a593Smuzhiyun if (!mode)
489*4882a593Smuzhiyun return -ENOMEM;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun if (!of_get_drm_display_mode(np_mcu_panel, mode, &bus_flags,
492*4882a593Smuzhiyun OF_USE_NATIVE_MODE)) {
493*4882a593Smuzhiyun mcu_panel->desc->mode = mode;
494*4882a593Smuzhiyun mcu_panel->desc->bus_flags = bus_flags;
495*4882a593Smuzhiyun } else {
496*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "failed to parse display mode\n");
497*4882a593Smuzhiyun return -EINVAL;
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun of_property_read_u32(np_mcu_panel, "bpc", &mcu_panel->desc->bpc);
501*4882a593Smuzhiyun of_property_read_u32(np_mcu_panel, "bus-format", &mcu_panel->desc->bus_format);
502*4882a593Smuzhiyun of_property_read_u32(np_mcu_panel, "width-mm", &mcu_panel->desc->size.width);
503*4882a593Smuzhiyun of_property_read_u32(np_mcu_panel, "height-mm", &mcu_panel->desc->size.height);
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun of_property_read_u32(np_mcu_panel, "prepare-delay-ms", &mcu_panel->desc->delay.prepare);
506*4882a593Smuzhiyun of_property_read_u32(np_mcu_panel, "enable-delay-ms", &mcu_panel->desc->delay.enable);
507*4882a593Smuzhiyun of_property_read_u32(np_mcu_panel, "disable-delay-ms", &mcu_panel->desc->delay.disable);
508*4882a593Smuzhiyun of_property_read_u32(np_mcu_panel, "unprepare-delay-ms",
509*4882a593Smuzhiyun &mcu_panel->desc->delay.unprepare);
510*4882a593Smuzhiyun of_property_read_u32(np_mcu_panel, "reset-delay-ms", &mcu_panel->desc->delay.reset);
511*4882a593Smuzhiyun of_property_read_u32(np_mcu_panel, "init-delay-ms", &mcu_panel->desc->delay.init);
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun data = of_get_property(np_mcu_panel, "panel-init-sequence", &len);
514*4882a593Smuzhiyun if (data) {
515*4882a593Smuzhiyun mcu_panel->desc->init_seq = devm_kzalloc(dev, sizeof(*mcu_panel->desc->init_seq),
516*4882a593Smuzhiyun GFP_KERNEL);
517*4882a593Smuzhiyun if (!mcu_panel->desc->init_seq)
518*4882a593Smuzhiyun return -ENOMEM;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun ret = rockchip_mcu_panel_parse_cmd_seq(dev, data, len,
521*4882a593Smuzhiyun mcu_panel->desc->init_seq);
522*4882a593Smuzhiyun if (ret < 0) {
523*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "failed to parse init sequence\n");
524*4882a593Smuzhiyun return ret;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun data = of_get_property(np_mcu_panel, "panel-exit-sequence", &len);
529*4882a593Smuzhiyun if (data) {
530*4882a593Smuzhiyun mcu_panel->desc->exit_seq = devm_kzalloc(dev, sizeof(*mcu_panel->desc->exit_seq),
531*4882a593Smuzhiyun GFP_KERNEL);
532*4882a593Smuzhiyun if (!mcu_panel->desc->exit_seq)
533*4882a593Smuzhiyun return -ENOMEM;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun ret = rockchip_mcu_panel_parse_cmd_seq(dev, data, len,
536*4882a593Smuzhiyun mcu_panel->desc->exit_seq);
537*4882a593Smuzhiyun if (ret < 0) {
538*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "failed to parse exit sequence\n");
539*4882a593Smuzhiyun return ret;
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun /*
544*4882a593Smuzhiyun * Support to find crtc device for both vop and vop3:
545*4882a593Smuzhiyun * vopl/vopb -> rgb
546*4882a593Smuzhiyun * vop2/vop3 -> vp -> rgb
547*4882a593Smuzhiyun */
548*4882a593Smuzhiyun port = of_graph_get_port_by_id(dev->of_node, 0);
549*4882a593Smuzhiyun if (port) {
550*4882a593Smuzhiyun for_each_child_of_node(port, endpoint) {
551*4882a593Smuzhiyun if (of_device_is_available(endpoint)) {
552*4882a593Smuzhiyun remote = of_graph_get_remote_endpoint(endpoint);
553*4882a593Smuzhiyun if (remote) {
554*4882a593Smuzhiyun np_crtc = of_get_next_parent(remote);
555*4882a593Smuzhiyun mcu_panel->np_crtc = np_crtc;
556*4882a593Smuzhiyun break;
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun if (!mcu_panel->np_crtc) {
562*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "failed to find available crtc for mcu panel\n");
563*4882a593Smuzhiyun return -EINVAL;
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun return 0;
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun
rockchip_mcu_panel_sleep(unsigned int msec)570*4882a593Smuzhiyun static void rockchip_mcu_panel_sleep(unsigned int msec)
571*4882a593Smuzhiyun {
572*4882a593Smuzhiyun if (msec > 20)
573*4882a593Smuzhiyun msleep(msec);
574*4882a593Smuzhiyun else
575*4882a593Smuzhiyun usleep_range(msec * 1000, (msec + 1) * 1000);
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun
rockchip_mcu_panel_xfer_mcu_cmd_seq(struct rockchip_mcu_panel * mcu_panel,struct mcu_cmd_seq * cmds)578*4882a593Smuzhiyun static int rockchip_mcu_panel_xfer_mcu_cmd_seq(struct rockchip_mcu_panel *mcu_panel,
579*4882a593Smuzhiyun struct mcu_cmd_seq *cmds)
580*4882a593Smuzhiyun {
581*4882a593Smuzhiyun struct drm_device *drm_dev = mcu_panel->drm_dev;
582*4882a593Smuzhiyun struct drm_panel *panel = &mcu_panel->base;
583*4882a593Smuzhiyun struct device_node *np_crtc = mcu_panel->np_crtc;
584*4882a593Smuzhiyun struct drm_crtc *crtc;
585*4882a593Smuzhiyun struct mcu_cmd_desc *cmd;
586*4882a593Smuzhiyun struct rockchip_drm_private *priv;
587*4882a593Smuzhiyun int i;
588*4882a593Smuzhiyun int pipe = 0;
589*4882a593Smuzhiyun u32 value;
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun if (!cmds)
592*4882a593Smuzhiyun return -EINVAL;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun drm_for_each_crtc(crtc, drm_dev) {
595*4882a593Smuzhiyun if (crtc->port == np_crtc)
596*4882a593Smuzhiyun break;
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun pipe = drm_crtc_index(crtc);
600*4882a593Smuzhiyun priv = crtc->dev->dev_private;
601*4882a593Smuzhiyun if (!priv->crtc_funcs[pipe]->crtc_send_mcu_cmd) {
602*4882a593Smuzhiyun DRM_DEV_ERROR(panel->dev, "crtc not supported to send mcu cmds\n");
603*4882a593Smuzhiyun return -EINVAL;
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun priv->crtc_funcs[pipe]->crtc_send_mcu_cmd(crtc, MCU_SETBYPASS, 1);
607*4882a593Smuzhiyun for (i = 0; i < cmds->cmd_cnt; i++) {
608*4882a593Smuzhiyun cmd = &cmds->cmds[i];
609*4882a593Smuzhiyun value = cmd->payload[0];
610*4882a593Smuzhiyun priv->crtc_funcs[pipe]->crtc_send_mcu_cmd(crtc, cmd->header.data_type, value);
611*4882a593Smuzhiyun if (cmd->header.delay)
612*4882a593Smuzhiyun rockchip_mcu_panel_sleep(cmd->header.delay);
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun priv->crtc_funcs[pipe]->crtc_send_mcu_cmd(crtc, MCU_SETBYPASS, 0);
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun return 0;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
rockchip_mcu_panel_disable(struct drm_panel * panel)619*4882a593Smuzhiyun static int rockchip_mcu_panel_disable(struct drm_panel *panel)
620*4882a593Smuzhiyun {
621*4882a593Smuzhiyun struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
622*4882a593Smuzhiyun int ret = 0;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun if (!mcu_panel->enabled)
625*4882a593Smuzhiyun return 0;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun if (mcu_panel->desc->delay.disable)
628*4882a593Smuzhiyun msleep(mcu_panel->desc->delay.disable);
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun ret = rockchip_mcu_panel_xfer_mcu_cmd_seq(mcu_panel, mcu_panel->desc->exit_seq);
631*4882a593Smuzhiyun if (ret)
632*4882a593Smuzhiyun DRM_DEV_ERROR(panel->dev, "failed to send exit cmds seq\n");
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun mcu_panel->enabled = false;
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun return 0;
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun
rockchip_mcu_panel_unprepare(struct drm_panel * panel)639*4882a593Smuzhiyun static int rockchip_mcu_panel_unprepare(struct drm_panel *panel)
640*4882a593Smuzhiyun {
641*4882a593Smuzhiyun struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun if (!mcu_panel->prepared)
644*4882a593Smuzhiyun return 0;
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun gpiod_direction_output(mcu_panel->reset_gpio, 1);
647*4882a593Smuzhiyun gpiod_direction_output(mcu_panel->enable_gpio, 0);
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun if (mcu_panel->desc->delay.unprepare)
650*4882a593Smuzhiyun msleep(mcu_panel->desc->delay.unprepare);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun mcu_panel->prepared = false;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun return 0;
655*4882a593Smuzhiyun }
656*4882a593Smuzhiyun
rockchip_mcu_panel_prepare(struct drm_panel * panel)657*4882a593Smuzhiyun static int rockchip_mcu_panel_prepare(struct drm_panel *panel)
658*4882a593Smuzhiyun {
659*4882a593Smuzhiyun struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
660*4882a593Smuzhiyun unsigned int delay;
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun if (mcu_panel->prepared)
663*4882a593Smuzhiyun return 0;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun gpiod_direction_output(mcu_panel->enable_gpio, 1);
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun delay = mcu_panel->desc->delay.prepare;
668*4882a593Smuzhiyun if (delay)
669*4882a593Smuzhiyun msleep(delay);
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun gpiod_direction_output(mcu_panel->reset_gpio, 1);
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun if (mcu_panel->desc->delay.reset)
674*4882a593Smuzhiyun msleep(mcu_panel->desc->delay.reset);
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun gpiod_direction_output(mcu_panel->reset_gpio, 0);
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun if (mcu_panel->desc->delay.init)
679*4882a593Smuzhiyun msleep(mcu_panel->desc->delay.init);
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun mcu_panel->prepared = true;
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun return 0;
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun
rockchip_mcu_panel_enable(struct drm_panel * panel)686*4882a593Smuzhiyun static int rockchip_mcu_panel_enable(struct drm_panel *panel)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
689*4882a593Smuzhiyun int ret = 0;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun if (mcu_panel->enabled)
692*4882a593Smuzhiyun return 0;
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun ret = rockchip_mcu_panel_xfer_mcu_cmd_seq(mcu_panel, mcu_panel->desc->init_seq);
695*4882a593Smuzhiyun if (ret)
696*4882a593Smuzhiyun DRM_DEV_ERROR(panel->dev, "failed to send init cmds seq\n");
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun if (mcu_panel->desc->delay.enable)
699*4882a593Smuzhiyun msleep(mcu_panel->desc->delay.enable);
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun mcu_panel->enabled = true;
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun return 0;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun
rockchip_mcu_panel_get_modes(struct drm_panel * panel,struct drm_connector * connector)706*4882a593Smuzhiyun static int rockchip_mcu_panel_get_modes(struct drm_panel *panel,
707*4882a593Smuzhiyun struct drm_connector *connector)
708*4882a593Smuzhiyun {
709*4882a593Smuzhiyun struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
710*4882a593Smuzhiyun struct drm_display_mode *m, *mode;
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun if (!mcu_panel->desc)
713*4882a593Smuzhiyun return 0;
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun m = mcu_panel->desc->mode;
716*4882a593Smuzhiyun mode = drm_mode_duplicate(connector->dev, m);
717*4882a593Smuzhiyun if (!mode) {
718*4882a593Smuzhiyun DRM_DEV_ERROR(mcu_panel->base.dev, "failed to add mode %ux%u@%u\n",
719*4882a593Smuzhiyun m->hdisplay, m->vdisplay,
720*4882a593Smuzhiyun drm_mode_vrefresh(m));
721*4882a593Smuzhiyun return 0;
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun drm_mode_set_name(mode);
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun drm_mode_probed_add(connector, mode);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun if (mcu_panel->desc->bpc)
731*4882a593Smuzhiyun connector->display_info.bpc = mcu_panel->desc->bpc;
732*4882a593Smuzhiyun if (mcu_panel->desc->size.width)
733*4882a593Smuzhiyun connector->display_info.width_mm = mcu_panel->desc->size.width;
734*4882a593Smuzhiyun if (mcu_panel->desc->size.height)
735*4882a593Smuzhiyun connector->display_info.height_mm = mcu_panel->desc->size.height;
736*4882a593Smuzhiyun if (mcu_panel->desc->bus_format)
737*4882a593Smuzhiyun drm_display_info_set_bus_formats(&connector->display_info,
738*4882a593Smuzhiyun &mcu_panel->desc->bus_format, 1);
739*4882a593Smuzhiyun if (mcu_panel->desc->bus_flags)
740*4882a593Smuzhiyun connector->display_info.bus_flags = mcu_panel->desc->bus_flags;
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun return 1;
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun static const struct drm_panel_funcs rockchip_mcu_panel_funcs = {
746*4882a593Smuzhiyun .disable = rockchip_mcu_panel_disable,
747*4882a593Smuzhiyun .unprepare = rockchip_mcu_panel_unprepare,
748*4882a593Smuzhiyun .prepare = rockchip_mcu_panel_prepare,
749*4882a593Smuzhiyun .enable = rockchip_mcu_panel_enable,
750*4882a593Smuzhiyun .get_modes = rockchip_mcu_panel_get_modes,
751*4882a593Smuzhiyun };
752*4882a593Smuzhiyun
rockchip_mcu_panel_find_backlight(struct device_node * np_mcu_panel)753*4882a593Smuzhiyun static struct backlight_device *rockchip_mcu_panel_find_backlight(struct device_node *np_mcu_panel)
754*4882a593Smuzhiyun {
755*4882a593Smuzhiyun struct backlight_device *bd = NULL;
756*4882a593Smuzhiyun struct device_node *np = NULL;
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun np = of_parse_phandle(np_mcu_panel, "backlight", 0);
759*4882a593Smuzhiyun if (np) {
760*4882a593Smuzhiyun bd = of_find_backlight_by_node(np);
761*4882a593Smuzhiyun if (IS_ERR_OR_NULL(bd))
762*4882a593Smuzhiyun return NULL;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun of_node_put(np);
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun if (!bd->props.brightness)
767*4882a593Smuzhiyun bd->props.brightness = bd->props.max_brightness;
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun return bd;
771*4882a593Smuzhiyun }
772*4882a593Smuzhiyun
rockchip_rgb_bind(struct device * dev,struct device * master,void * data)773*4882a593Smuzhiyun static int rockchip_rgb_bind(struct device *dev, struct device *master,
774*4882a593Smuzhiyun void *data)
775*4882a593Smuzhiyun {
776*4882a593Smuzhiyun struct rockchip_rgb *rgb = dev_get_drvdata(dev);
777*4882a593Smuzhiyun struct drm_device *drm_dev = data;
778*4882a593Smuzhiyun struct drm_encoder *encoder = &rgb->encoder;
779*4882a593Smuzhiyun struct drm_connector *connector;
780*4882a593Smuzhiyun struct fwnode_handle *fwnode_mcu_panel;
781*4882a593Smuzhiyun int ret;
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun fwnode_mcu_panel = device_get_named_child_node(dev, "mcu-panel");
784*4882a593Smuzhiyun if (fwnode_mcu_panel) {
785*4882a593Smuzhiyun struct rockchip_mcu_panel *mcu_panel;
786*4882a593Smuzhiyun struct device_node *np_mcu_panel = to_of_node(fwnode_mcu_panel);
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun mcu_panel = devm_kzalloc(dev, sizeof(*mcu_panel), GFP_KERNEL);
789*4882a593Smuzhiyun if (!mcu_panel) {
790*4882a593Smuzhiyun of_node_put(np_mcu_panel);
791*4882a593Smuzhiyun return -ENOMEM;
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun mcu_panel->drm_dev = drm_dev;
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun rgb->panel = &mcu_panel->base;
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun ret = rockchip_mcu_panel_init(rgb, np_mcu_panel);
798*4882a593Smuzhiyun if (ret < 0) {
799*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "failed to init mcu panel: %d\n", ret);
800*4882a593Smuzhiyun of_node_put(np_mcu_panel);
801*4882a593Smuzhiyun return ret;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun rgb->panel->backlight = rockchip_mcu_panel_find_backlight(np_mcu_panel);
805*4882a593Smuzhiyun if (!rgb->panel->backlight) {
806*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "failed to find backlight device");
807*4882a593Smuzhiyun of_node_put(np_mcu_panel);
808*4882a593Smuzhiyun return -EINVAL;
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun of_node_put(np_mcu_panel);
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun drm_panel_init(&mcu_panel->base, dev, &rockchip_mcu_panel_funcs,
814*4882a593Smuzhiyun DRM_MODE_CONNECTOR_DPI);
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun drm_panel_add(&mcu_panel->base);
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun rgb->is_mcu_panel = true;
819*4882a593Smuzhiyun } else {
820*4882a593Smuzhiyun ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
821*4882a593Smuzhiyun &rgb->panel, &rgb->bridge);
822*4882a593Smuzhiyun if (ret) {
823*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "failed to find panel or bridge: %d\n", ret);
824*4882a593Smuzhiyun return ret;
825*4882a593Smuzhiyun }
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev,
829*4882a593Smuzhiyun dev->of_node);
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun ret = drm_encoder_init(drm_dev, encoder, &rockchip_rgb_encoder_funcs,
832*4882a593Smuzhiyun DRM_MODE_ENCODER_DPI, NULL);
833*4882a593Smuzhiyun if (ret < 0) {
834*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "failed to initialize encoder: %d\n", ret);
835*4882a593Smuzhiyun return ret;
836*4882a593Smuzhiyun }
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun drm_encoder_helper_add(encoder, &rockchip_rgb_encoder_helper_funcs);
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun if (rgb->panel) {
841*4882a593Smuzhiyun struct rockchip_drm_private *private = drm_dev->dev_private;
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun connector = &rgb->connector;
844*4882a593Smuzhiyun connector->interlace_allowed = true;
845*4882a593Smuzhiyun ret = drm_connector_init(drm_dev, connector,
846*4882a593Smuzhiyun &rockchip_rgb_connector_funcs,
847*4882a593Smuzhiyun DRM_MODE_CONNECTOR_DPI);
848*4882a593Smuzhiyun if (ret < 0) {
849*4882a593Smuzhiyun DRM_DEV_ERROR(dev,
850*4882a593Smuzhiyun "failed to initialize connector: %d\n",
851*4882a593Smuzhiyun ret);
852*4882a593Smuzhiyun goto err_free_encoder;
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun drm_connector_helper_add(connector,
856*4882a593Smuzhiyun &rockchip_rgb_connector_helper_funcs);
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun ret = drm_connector_attach_encoder(connector, encoder);
859*4882a593Smuzhiyun if (ret < 0) {
860*4882a593Smuzhiyun DRM_DEV_ERROR(dev,
861*4882a593Smuzhiyun "failed to attach encoder: %d\n", ret);
862*4882a593Smuzhiyun goto err_free_connector;
863*4882a593Smuzhiyun }
864*4882a593Smuzhiyun rgb->sub_dev.connector = &rgb->connector;
865*4882a593Smuzhiyun rgb->sub_dev.of_node = rgb->dev->of_node;
866*4882a593Smuzhiyun rgb->sub_dev.loader_protect = rockchip_rgb_encoder_loader_protect;
867*4882a593Smuzhiyun drm_object_attach_property(&connector->base, private->connector_id_prop, 0);
868*4882a593Smuzhiyun rockchip_drm_register_sub_dev(&rgb->sub_dev);
869*4882a593Smuzhiyun } else {
870*4882a593Smuzhiyun rgb->bridge->encoder = encoder;
871*4882a593Smuzhiyun ret = drm_bridge_attach(encoder, rgb->bridge, NULL, 0);
872*4882a593Smuzhiyun if (ret) {
873*4882a593Smuzhiyun DRM_DEV_ERROR(dev,
874*4882a593Smuzhiyun "failed to attach bridge: %d\n", ret);
875*4882a593Smuzhiyun goto err_free_encoder;
876*4882a593Smuzhiyun }
877*4882a593Smuzhiyun }
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun return 0;
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun err_free_connector:
882*4882a593Smuzhiyun drm_connector_cleanup(connector);
883*4882a593Smuzhiyun err_free_encoder:
884*4882a593Smuzhiyun drm_encoder_cleanup(encoder);
885*4882a593Smuzhiyun return ret;
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun
rockchip_rgb_unbind(struct device * dev,struct device * master,void * data)888*4882a593Smuzhiyun static void rockchip_rgb_unbind(struct device *dev, struct device *master,
889*4882a593Smuzhiyun void *data)
890*4882a593Smuzhiyun {
891*4882a593Smuzhiyun struct rockchip_rgb *rgb = dev_get_drvdata(dev);
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun if (rgb->sub_dev.connector)
894*4882a593Smuzhiyun rockchip_drm_unregister_sub_dev(&rgb->sub_dev);
895*4882a593Smuzhiyun if (rgb->panel)
896*4882a593Smuzhiyun drm_connector_cleanup(&rgb->connector);
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun drm_encoder_cleanup(&rgb->encoder);
899*4882a593Smuzhiyun }
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun static const struct component_ops rockchip_rgb_component_ops = {
902*4882a593Smuzhiyun .bind = rockchip_rgb_bind,
903*4882a593Smuzhiyun .unbind = rockchip_rgb_unbind,
904*4882a593Smuzhiyun };
905*4882a593Smuzhiyun
rockchip_rgb_probe(struct platform_device * pdev)906*4882a593Smuzhiyun static int rockchip_rgb_probe(struct platform_device *pdev)
907*4882a593Smuzhiyun {
908*4882a593Smuzhiyun struct device *dev = &pdev->dev;
909*4882a593Smuzhiyun struct rockchip_rgb *rgb;
910*4882a593Smuzhiyun const struct rockchip_rgb_data *rgb_data;
911*4882a593Smuzhiyun int ret, id;
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun rgb = devm_kzalloc(&pdev->dev, sizeof(*rgb), GFP_KERNEL);
914*4882a593Smuzhiyun if (!rgb)
915*4882a593Smuzhiyun return -ENOMEM;
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun id = of_alias_get_id(dev->of_node, "rgb");
918*4882a593Smuzhiyun if (id < 0)
919*4882a593Smuzhiyun id = 0;
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun rgb_data = of_device_get_match_data(dev);
922*4882a593Smuzhiyun if (rgb_data) {
923*4882a593Smuzhiyun rgb->max_dclk_rate = rgb_data->max_dclk_rate;
924*4882a593Smuzhiyun rgb->funcs = rgb_data->funcs;
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun rgb->id = id;
927*4882a593Smuzhiyun rgb->dev = dev;
928*4882a593Smuzhiyun platform_set_drvdata(pdev, rgb);
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun rgb->data_sync_bypass =
931*4882a593Smuzhiyun of_property_read_bool(dev->of_node, "rockchip,data-sync-bypass");
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun if (dev->parent && dev->parent->of_node) {
934*4882a593Smuzhiyun rgb->grf = syscon_node_to_regmap(dev->parent->of_node);
935*4882a593Smuzhiyun if (IS_ERR(rgb->grf)) {
936*4882a593Smuzhiyun ret = PTR_ERR(rgb->grf);
937*4882a593Smuzhiyun dev_err(dev, "Unable to get grf: %d\n", ret);
938*4882a593Smuzhiyun return ret;
939*4882a593Smuzhiyun }
940*4882a593Smuzhiyun }
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun rgb->phy = devm_phy_optional_get(dev, "phy");
943*4882a593Smuzhiyun if (IS_ERR(rgb->phy)) {
944*4882a593Smuzhiyun ret = PTR_ERR(rgb->phy);
945*4882a593Smuzhiyun dev_err(dev, "failed to get phy: %d\n", ret);
946*4882a593Smuzhiyun return ret;
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun return component_add(dev, &rockchip_rgb_component_ops);
950*4882a593Smuzhiyun }
951*4882a593Smuzhiyun
rockchip_rgb_remove(struct platform_device * pdev)952*4882a593Smuzhiyun static int rockchip_rgb_remove(struct platform_device *pdev)
953*4882a593Smuzhiyun {
954*4882a593Smuzhiyun component_del(&pdev->dev, &rockchip_rgb_component_ops);
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun return 0;
957*4882a593Smuzhiyun }
958*4882a593Smuzhiyun
px30_rgb_enable(struct rockchip_rgb * rgb)959*4882a593Smuzhiyun static void px30_rgb_enable(struct rockchip_rgb *rgb)
960*4882a593Smuzhiyun {
961*4882a593Smuzhiyun int pipe = drm_of_encoder_active_endpoint_id(rgb->dev->of_node,
962*4882a593Smuzhiyun &rgb->encoder);
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun regmap_write(rgb->grf, PX30_GRF_PD_VO_CON1, PX30_RGB_VOP_SEL(pipe) |
965*4882a593Smuzhiyun PX30_RGB_DATA_SYNC_BYPASS(rgb->data_sync_bypass));
966*4882a593Smuzhiyun }
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun static const struct rockchip_rgb_funcs px30_rgb_funcs = {
969*4882a593Smuzhiyun .enable = px30_rgb_enable,
970*4882a593Smuzhiyun };
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun static const struct rockchip_rgb_data px30_rgb = {
973*4882a593Smuzhiyun .funcs = &px30_rgb_funcs,
974*4882a593Smuzhiyun };
975*4882a593Smuzhiyun
rk1808_rgb_enable(struct rockchip_rgb * rgb)976*4882a593Smuzhiyun static void rk1808_rgb_enable(struct rockchip_rgb *rgb)
977*4882a593Smuzhiyun {
978*4882a593Smuzhiyun regmap_write(rgb->grf, RK1808_GRF_PD_VO_CON1,
979*4882a593Smuzhiyun RK1808_RGB_DATA_SYNC_BYPASS(rgb->data_sync_bypass));
980*4882a593Smuzhiyun }
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun static const struct rockchip_rgb_funcs rk1808_rgb_funcs = {
983*4882a593Smuzhiyun .enable = rk1808_rgb_enable,
984*4882a593Smuzhiyun };
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun static const struct rockchip_rgb_data rk1808_rgb = {
987*4882a593Smuzhiyun .funcs = &rk1808_rgb_funcs,
988*4882a593Smuzhiyun };
989*4882a593Smuzhiyun
rk3288_rgb_enable(struct rockchip_rgb * rgb)990*4882a593Smuzhiyun static void rk3288_rgb_enable(struct rockchip_rgb *rgb)
991*4882a593Smuzhiyun {
992*4882a593Smuzhiyun int pipe = drm_of_encoder_active_endpoint_id(rgb->dev->of_node,
993*4882a593Smuzhiyun &rgb->encoder);
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun regmap_write(rgb->grf, RK3288_GRF_SOC_CON6, RK3288_LVDS_LCDC_SEL(pipe));
996*4882a593Smuzhiyun regmap_write(rgb->grf, RK3288_GRF_SOC_CON7,
997*4882a593Smuzhiyun RK3288_LVDS_PWRDWN(0) | RK3288_LVDS_CON_ENABLE_2(1) |
998*4882a593Smuzhiyun RK3288_LVDS_CON_ENABLE_1(1) | RK3288_LVDS_CON_CLKINV(0) |
999*4882a593Smuzhiyun RK3288_LVDS_CON_TTL_EN(1));
1000*4882a593Smuzhiyun }
1001*4882a593Smuzhiyun
rk3288_rgb_disable(struct rockchip_rgb * rgb)1002*4882a593Smuzhiyun static void rk3288_rgb_disable(struct rockchip_rgb *rgb)
1003*4882a593Smuzhiyun {
1004*4882a593Smuzhiyun regmap_write(rgb->grf, RK3288_GRF_SOC_CON7,
1005*4882a593Smuzhiyun RK3288_LVDS_PWRDWN(1) | RK3288_LVDS_CON_ENABLE_2(0) |
1006*4882a593Smuzhiyun RK3288_LVDS_CON_ENABLE_1(0) | RK3288_LVDS_CON_TTL_EN(0));
1007*4882a593Smuzhiyun }
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun static const struct rockchip_rgb_funcs rk3288_rgb_funcs = {
1010*4882a593Smuzhiyun .enable = rk3288_rgb_enable,
1011*4882a593Smuzhiyun .disable = rk3288_rgb_disable,
1012*4882a593Smuzhiyun };
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun static const struct rockchip_rgb_data rk3288_rgb = {
1015*4882a593Smuzhiyun .funcs = &rk3288_rgb_funcs,
1016*4882a593Smuzhiyun };
1017*4882a593Smuzhiyun
rk3562_rgb_enable(struct rockchip_rgb * rgb)1018*4882a593Smuzhiyun static void rk3562_rgb_enable(struct rockchip_rgb *rgb)
1019*4882a593Smuzhiyun {
1020*4882a593Smuzhiyun regmap_write(rgb->grf, RK3562_GRF_IOC_VO_IO_CON,
1021*4882a593Smuzhiyun RK3562_RGB_DATA_BYPASS(rgb->data_sync_bypass));
1022*4882a593Smuzhiyun }
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun static const struct rockchip_rgb_funcs rk3562_rgb_funcs = {
1025*4882a593Smuzhiyun .enable = rk3562_rgb_enable,
1026*4882a593Smuzhiyun };
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun static const struct rockchip_rgb_data rk3562_rgb = {
1029*4882a593Smuzhiyun .funcs = &rk3562_rgb_funcs,
1030*4882a593Smuzhiyun };
1031*4882a593Smuzhiyun
rk3568_rgb_enable(struct rockchip_rgb * rgb)1032*4882a593Smuzhiyun static void rk3568_rgb_enable(struct rockchip_rgb *rgb)
1033*4882a593Smuzhiyun {
1034*4882a593Smuzhiyun regmap_write(rgb->grf, RK3568_GRF_VO_CON1,
1035*4882a593Smuzhiyun RK3568_RGB_DATA_BYPASS(rgb->data_sync_bypass));
1036*4882a593Smuzhiyun }
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun static const struct rockchip_rgb_funcs rk3568_rgb_funcs = {
1039*4882a593Smuzhiyun .enable = rk3568_rgb_enable,
1040*4882a593Smuzhiyun };
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun static const struct rockchip_rgb_data rk3568_rgb = {
1043*4882a593Smuzhiyun .funcs = &rk3568_rgb_funcs,
1044*4882a593Smuzhiyun };
1045*4882a593Smuzhiyun
rv1126_rgb_enable(struct rockchip_rgb * rgb)1046*4882a593Smuzhiyun static void rv1126_rgb_enable(struct rockchip_rgb *rgb)
1047*4882a593Smuzhiyun {
1048*4882a593Smuzhiyun regmap_write(rgb->grf, RV1126_GRF_IOFUNC_CON3,
1049*4882a593Smuzhiyun RV1126_LCDC_IO_BYPASS(rgb->data_sync_bypass));
1050*4882a593Smuzhiyun }
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun static const struct rockchip_rgb_funcs rv1126_rgb_funcs = {
1053*4882a593Smuzhiyun .enable = rv1126_rgb_enable,
1054*4882a593Smuzhiyun };
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun static const struct rockchip_rgb_data rv1126_rgb = {
1057*4882a593Smuzhiyun .funcs = &rv1126_rgb_funcs,
1058*4882a593Smuzhiyun };
1059*4882a593Smuzhiyun
rv1106_rgb_enable(struct rockchip_rgb * rgb)1060*4882a593Smuzhiyun static void rv1106_rgb_enable(struct rockchip_rgb *rgb)
1061*4882a593Smuzhiyun {
1062*4882a593Smuzhiyun regmap_write(rgb->grf, RV1106_VENC_GRF_VOP_IO_WRAPPER,
1063*4882a593Smuzhiyun RV1106_IO_BYPASS_SEL(rgb->data_sync_bypass ? 0x3 : 0x0));
1064*4882a593Smuzhiyun regmap_write(rgb->grf, RV1106_VOGRF_VOP_PIPE_BYPASS,
1065*4882a593Smuzhiyun RV1106_VOP_PIPE_BYPASS(rgb->data_sync_bypass ? 0x3 : 0x0));
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun static const struct rockchip_rgb_funcs rv1106_rgb_funcs = {
1069*4882a593Smuzhiyun .enable = rv1106_rgb_enable,
1070*4882a593Smuzhiyun };
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun static const struct rockchip_rgb_data rv1106_rgb = {
1073*4882a593Smuzhiyun .max_dclk_rate = 74250,
1074*4882a593Smuzhiyun .funcs = &rv1106_rgb_funcs,
1075*4882a593Smuzhiyun };
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun static const struct of_device_id rockchip_rgb_dt_ids[] = {
1078*4882a593Smuzhiyun { .compatible = "rockchip,px30-rgb", .data = &px30_rgb },
1079*4882a593Smuzhiyun { .compatible = "rockchip,rk1808-rgb", .data = &rk1808_rgb },
1080*4882a593Smuzhiyun { .compatible = "rockchip,rk3066-rgb", },
1081*4882a593Smuzhiyun { .compatible = "rockchip,rk3128-rgb", },
1082*4882a593Smuzhiyun { .compatible = "rockchip,rk3288-rgb", .data = &rk3288_rgb },
1083*4882a593Smuzhiyun { .compatible = "rockchip,rk3308-rgb", },
1084*4882a593Smuzhiyun { .compatible = "rockchip,rk3368-rgb", },
1085*4882a593Smuzhiyun { .compatible = "rockchip,rk3562-rgb", .data = &rk3562_rgb },
1086*4882a593Smuzhiyun { .compatible = "rockchip,rk3568-rgb", .data = &rk3568_rgb },
1087*4882a593Smuzhiyun { .compatible = "rockchip,rk3588-rgb", },
1088*4882a593Smuzhiyun { .compatible = "rockchip,rv1106-rgb", .data = &rv1106_rgb},
1089*4882a593Smuzhiyun { .compatible = "rockchip,rv1108-rgb", },
1090*4882a593Smuzhiyun { .compatible = "rockchip,rv1126-rgb", .data = &rv1126_rgb},
1091*4882a593Smuzhiyun {}
1092*4882a593Smuzhiyun };
1093*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rockchip_rgb_dt_ids);
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun struct platform_driver rockchip_rgb_driver = {
1096*4882a593Smuzhiyun .probe = rockchip_rgb_probe,
1097*4882a593Smuzhiyun .remove = rockchip_rgb_remove,
1098*4882a593Smuzhiyun .driver = {
1099*4882a593Smuzhiyun .name = "rockchip-rgb",
1100*4882a593Smuzhiyun .of_match_table = of_match_ptr(rockchip_rgb_dt_ids),
1101*4882a593Smuzhiyun },
1102*4882a593Smuzhiyun };
1103