1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Zheng Yang <zhengyang@rock-chips.com>
5 * Yakir Yang <ykk@rock-chips.com>
6 */
7
8 #include <linux/irq.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/hdmi.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of_device.h>
17
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_edid.h>
20 #include <drm/drm_of.h>
21 #include <drm/drm_probe_helper.h>
22 #include <drm/drm_simple_kms_helper.h>
23
24 #include <sound/hdmi-codec.h>
25
26 #include "rockchip_drm_drv.h"
27 #include "rockchip_drm_vop.h"
28
29 #include "inno_hdmi.h"
30
31 #define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x)
32
33 struct audio_info {
34 int sample_rate;
35 int channels;
36 int sample_width;
37 };
38
39 struct hdmi_data_info {
40 int vic;
41 bool sink_is_hdmi;
42 bool sink_has_audio;
43 unsigned int enc_in_format;
44 unsigned int enc_out_format;
45 unsigned int colorimetry;
46 };
47
48 struct inno_hdmi_i2c {
49 struct i2c_adapter adap;
50
51 u8 ddc_addr;
52 u8 segment_addr;
53
54 struct mutex lock;
55 struct completion cmp;
56 };
57
58 enum inno_hdmi_dev_type {
59 RK3036_HDMI,
60 RK3128_HDMI,
61 };
62
63 struct inno_hdmi_phy_config {
64 unsigned long mpixelclock;
65 u8 pre_emphasis; /* pre-emphasis value */
66 u8 vlev_ctr; /* voltage level control */
67 };
68
69 struct inno_hdmi_plat_data {
70 enum inno_hdmi_dev_type dev_type;
71 struct inno_hdmi_phy_config *phy_config;
72 };
73
74 struct inno_hdmi {
75 struct device *dev;
76 struct drm_device *drm_dev;
77
78 int irq;
79 struct clk *aclk;
80 struct clk *pclk;
81 void __iomem *regs;
82
83 struct drm_connector connector;
84 struct drm_encoder encoder;
85
86 struct inno_hdmi_i2c *i2c;
87 struct i2c_adapter *ddc;
88
89 unsigned int tmds_rate;
90 struct platform_device *audio_pdev;
91 bool audio_enable;
92 const struct inno_hdmi_plat_data *plat_data;
93
94 struct hdmi_data_info hdmi_data;
95 struct drm_display_mode previous_mode;
96 };
97
98 enum {
99 CSC_ITU601_16_235_TO_RGB_0_255_8BIT,
100 CSC_ITU601_0_255_TO_RGB_0_255_8BIT,
101 CSC_ITU709_16_235_TO_RGB_0_255_8BIT,
102 CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
103 CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
104 CSC_RGB_0_255_TO_RGB_16_235_8BIT,
105 };
106
107 static const char coeff_csc[][24] = {
108 /*
109 * YUV2RGB:601 SD mode(Y[16:235], UV[16:240], RGB[0:255]):
110 * R = 1.164*Y + 1.596*V - 204
111 * G = 1.164*Y - 0.391*U - 0.813*V + 154
112 * B = 1.164*Y + 2.018*U - 258
113 */
114 {
115 0x04, 0xa7, 0x00, 0x00, 0x06, 0x62, 0x02, 0xcc,
116 0x04, 0xa7, 0x11, 0x90, 0x13, 0x40, 0x00, 0x9a,
117 0x04, 0xa7, 0x08, 0x12, 0x00, 0x00, 0x03, 0x02
118 },
119 /*
120 * YUV2RGB:601 SD mode(YUV[0:255],RGB[0:255]):
121 * R = Y + 1.402*V - 248
122 * G = Y - 0.344*U - 0.714*V + 135
123 * B = Y + 1.772*U - 227
124 */
125 {
126 0x04, 0x00, 0x00, 0x00, 0x05, 0x9b, 0x02, 0xf8,
127 0x04, 0x00, 0x11, 0x60, 0x12, 0xdb, 0x00, 0x87,
128 0x04, 0x00, 0x07, 0x16, 0x00, 0x00, 0x02, 0xe3
129 },
130 /*
131 * YUV2RGB:709 HD mode(Y[16:235],UV[16:240],RGB[0:255]):
132 * R = 1.164*Y + 1.793*V - 248
133 * G = 1.164*Y - 0.213*U - 0.534*V + 77
134 * B = 1.164*Y + 2.115*U - 289
135 */
136 {
137 0x04, 0xa7, 0x00, 0x00, 0x07, 0x2c, 0x02, 0xf8,
138 0x04, 0xa7, 0x10, 0xda, 0x12, 0x22, 0x00, 0x4d,
139 0x04, 0xa7, 0x08, 0x74, 0x00, 0x00, 0x03, 0x21
140 },
141
142 /*
143 * RGB2YUV:601 SD mode:
144 * Cb = -0.291G - 0.148R + 0.439B + 128
145 * Y = 0.504G + 0.257R + 0.098B + 16
146 * Cr = -0.368G + 0.439R - 0.071B + 128
147 */
148 {
149 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
150 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
151 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
152 },
153 /*
154 * RGB2YUV:709 HD mode:
155 * Cb = - 0.338G - 0.101R + 0.439B + 128
156 * Y = 0.614G + 0.183R + 0.062B + 16
157 * Cr = - 0.399G + 0.439R - 0.040B + 128
158 */
159 {
160 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
161 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
162 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
163 },
164 /*
165 * RGB[0:255]2RGB[16:235]:
166 * R' = R x (235-16)/255 + 16;
167 * G' = G x (235-16)/255 + 16;
168 * B' = B x (235-16)/255 + 16;
169 */
170 {
171 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
172 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
173 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
174 },
175 };
176
hdmi_readb(struct inno_hdmi * hdmi,u16 offset)177 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
178 {
179 return readl_relaxed(hdmi->regs + (offset) * 0x04);
180 }
181
hdmi_writeb(struct inno_hdmi * hdmi,u16 offset,u32 val)182 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
183 {
184 writel_relaxed(val, hdmi->regs + (offset) * 0x04);
185 }
186
hdmi_modb(struct inno_hdmi * hdmi,u16 offset,u32 msk,u32 val)187 static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset,
188 u32 msk, u32 val)
189 {
190 u8 temp = hdmi_readb(hdmi, offset) & ~msk;
191
192 temp |= val & msk;
193 hdmi_writeb(hdmi, offset, temp);
194 }
195
inno_hdmi_i2c_init(struct inno_hdmi * hdmi)196 static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi)
197 {
198 int ddc_bus_freq;
199
200 ddc_bus_freq = (hdmi->tmds_rate >> 2) / HDMI_SCL_RATE;
201
202 hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
203 hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
204
205 /* Clear the EDID interrupt flag and mute the interrupt */
206 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
207 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
208 }
209
inno_hdmi_sys_power(struct inno_hdmi * hdmi,bool enable)210 static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable)
211 {
212 if (enable)
213 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON);
214 else
215 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF);
216 }
217
inno_hdmi_set_pwr_mode(struct inno_hdmi * hdmi,int mode)218 static void inno_hdmi_set_pwr_mode(struct inno_hdmi *hdmi, int mode)
219 {
220 const struct inno_hdmi_phy_config *phy_config =
221 hdmi->plat_data->phy_config;
222
223 switch (mode) {
224 case NORMAL:
225 inno_hdmi_sys_power(hdmi, false);
226 for (; phy_config->mpixelclock != ~0UL; phy_config++)
227 if (hdmi->tmds_rate <= phy_config->mpixelclock)
228 break;
229 if (!phy_config->mpixelclock)
230 return;
231 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS,
232 phy_config->pre_emphasis);
233 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->vlev_ctr);
234
235 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
236 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
237 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
238 hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
239 hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
240 hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
241
242 inno_hdmi_sys_power(hdmi, true);
243 break;
244
245 case LOWER_PWR:
246 inno_hdmi_sys_power(hdmi, false);
247 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
248 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
249 hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
250 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
251
252 break;
253
254 default:
255 DRM_DEV_ERROR(hdmi->dev, "Unknown power mode %d\n", mode);
256 }
257 }
258
inno_hdmi_reset(struct inno_hdmi * hdmi)259 static void inno_hdmi_reset(struct inno_hdmi *hdmi)
260 {
261 u32 val;
262 u32 msk;
263
264 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
265 udelay(100);
266
267 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
268 udelay(100);
269
270 msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
271 val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
272 hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
273
274 inno_hdmi_set_pwr_mode(hdmi, NORMAL);
275 }
276
inno_hdmi_upload_frame(struct inno_hdmi * hdmi,int setup_rc,union hdmi_infoframe * frame,u32 frame_index,u32 mask,u32 disable,u32 enable)277 static int inno_hdmi_upload_frame(struct inno_hdmi *hdmi, int setup_rc,
278 union hdmi_infoframe *frame, u32 frame_index,
279 u32 mask, u32 disable, u32 enable)
280 {
281 if (mask)
282 hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, disable);
283
284 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, frame_index);
285
286 if (setup_rc >= 0) {
287 u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
288 ssize_t rc, i;
289
290 rc = hdmi_infoframe_pack(frame, packed_frame,
291 sizeof(packed_frame));
292 if (rc < 0)
293 return rc;
294
295 for (i = 0; i < rc; i++)
296 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i,
297 packed_frame[i]);
298
299 if (mask)
300 hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, enable);
301 }
302
303 return setup_rc;
304 }
305
inno_hdmi_config_video_vsi(struct inno_hdmi * hdmi,struct drm_display_mode * mode)306 static int inno_hdmi_config_video_vsi(struct inno_hdmi *hdmi,
307 struct drm_display_mode *mode)
308 {
309 union hdmi_infoframe frame;
310 int rc;
311
312 rc = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
313 &hdmi->connector,
314 mode);
315
316 return inno_hdmi_upload_frame(hdmi, rc, &frame, INFOFRAME_VSI,
317 m_PACKET_VSI_EN, v_PACKET_VSI_EN(0), v_PACKET_VSI_EN(1));
318 }
319
inno_hdmi_config_audio_aai(struct inno_hdmi * hdmi,struct audio_info * audio)320 static int inno_hdmi_config_audio_aai(struct inno_hdmi *hdmi,
321 struct audio_info *audio)
322 {
323 struct hdmi_audio_infoframe *faudio;
324 union hdmi_infoframe frame;
325 int rc;
326
327 rc = hdmi_audio_infoframe_init(&frame.audio);
328 faudio = (struct hdmi_audio_infoframe *)&frame;
329
330 faudio->channels = audio->channels;
331
332 return inno_hdmi_upload_frame(hdmi, rc, &frame, INFOFRAME_AAI, 0, 0, 0);
333 }
334
inno_hdmi_config_video_avi(struct inno_hdmi * hdmi,struct drm_display_mode * mode)335 static int inno_hdmi_config_video_avi(struct inno_hdmi *hdmi,
336 struct drm_display_mode *mode)
337 {
338 union hdmi_infoframe frame;
339 int rc;
340
341 rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
342 &hdmi->connector,
343 mode);
344
345 if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444)
346 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
347 else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422)
348 frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
349 else
350 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
351
352 return inno_hdmi_upload_frame(hdmi, rc, &frame, INFOFRAME_AVI, 0, 0, 0);
353 }
354
inno_hdmi_config_video_csc(struct inno_hdmi * hdmi)355 static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
356 {
357 struct hdmi_data_info *data = &hdmi->hdmi_data;
358 int c0_c2_change = 0;
359 int csc_enable = 0;
360 int csc_mode = 0;
361 int auto_csc = 0;
362 int value;
363 int i;
364
365 /* Input video mode is SDR RGB24bit, data enable signal from external */
366 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
367 v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
368
369 /* Input color hardcode to RGB, and output color hardcode to RGB888 */
370 value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
371 v_VIDEO_OUTPUT_COLOR(0) |
372 v_VIDEO_INPUT_CSP(0);
373 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
374
375 if (data->enc_in_format == data->enc_out_format) {
376 if ((data->enc_in_format == HDMI_COLORSPACE_RGB) ||
377 (data->enc_in_format >= HDMI_COLORSPACE_YUV444)) {
378 value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
379 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
380
381 hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
382 m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
383 v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
384 v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
385 return 0;
386 }
387 }
388
389 if (data->colorimetry == HDMI_COLORIMETRY_ITU_601) {
390 if ((data->enc_in_format == HDMI_COLORSPACE_RGB) &&
391 (data->enc_out_format == HDMI_COLORSPACE_YUV444)) {
392 csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
393 auto_csc = AUTO_CSC_DISABLE;
394 c0_c2_change = C0_C2_CHANGE_DISABLE;
395 csc_enable = v_CSC_ENABLE;
396 } else if ((data->enc_in_format == HDMI_COLORSPACE_YUV444) &&
397 (data->enc_out_format == HDMI_COLORSPACE_RGB)) {
398 csc_mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
399 auto_csc = AUTO_CSC_ENABLE;
400 c0_c2_change = C0_C2_CHANGE_DISABLE;
401 csc_enable = v_CSC_DISABLE;
402 }
403 } else {
404 if ((data->enc_in_format == HDMI_COLORSPACE_RGB) &&
405 (data->enc_out_format == HDMI_COLORSPACE_YUV444)) {
406 csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
407 auto_csc = AUTO_CSC_DISABLE;
408 c0_c2_change = C0_C2_CHANGE_DISABLE;
409 csc_enable = v_CSC_ENABLE;
410 } else if ((data->enc_in_format == HDMI_COLORSPACE_YUV444) &&
411 (data->enc_out_format == HDMI_COLORSPACE_RGB)) {
412 csc_mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
413 auto_csc = AUTO_CSC_ENABLE;
414 c0_c2_change = C0_C2_CHANGE_DISABLE;
415 csc_enable = v_CSC_DISABLE;
416 }
417 }
418
419 for (i = 0; i < 24; i++)
420 hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
421 coeff_csc[csc_mode][i]);
422
423 value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
424 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
425 hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
426 m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
427 v_VIDEO_C0_C2_SWAP(c0_c2_change));
428
429 return 0;
430 }
431
inno_hdmi_config_video_timing(struct inno_hdmi * hdmi,struct drm_display_mode * mode)432 static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi,
433 struct drm_display_mode *mode)
434 {
435 int value;
436
437 if (hdmi->plat_data->dev_type == RK3036_HDMI) {
438 value = BIT(20) | BIT(21);
439 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? BIT(4) : 0;
440 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? BIT(5) : 0;
441 hdmi_writeb(hdmi, 0x148, value);
442 }
443 /* Set detail external video timing polarity and interlace mode */
444 value = v_EXTERANL_VIDEO(1);
445 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
446 v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0);
447 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
448 v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0);
449 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
450 v_INETLACE(1) : v_INETLACE(0);
451 hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
452
453 /* Set detail external video timing */
454 value = mode->htotal;
455 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF);
456 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
457
458 value = mode->htotal - mode->hdisplay;
459 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF);
460 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
461
462 value = mode->hsync_start - mode->hdisplay;
463 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF);
464 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
465
466 value = mode->hsync_end - mode->hsync_start;
467 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF);
468 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
469
470 value = mode->vtotal;
471 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF);
472 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
473
474 value = mode->vtotal - mode->vdisplay;
475 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF);
476
477 value = mode->vsync_start - mode->vdisplay;
478 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF);
479
480 value = mode->vsync_end - mode->vsync_start;
481 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
482
483 hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
484 hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
485 hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
486
487 return 0;
488 }
489
inno_hdmi_setup(struct inno_hdmi * hdmi,struct drm_display_mode * mode)490 static int inno_hdmi_setup(struct inno_hdmi *hdmi,
491 struct drm_display_mode *mode)
492 {
493 hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
494
495 hdmi->hdmi_data.enc_in_format = HDMI_COLORSPACE_RGB;
496 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
497
498 if ((hdmi->hdmi_data.vic == 6) || (hdmi->hdmi_data.vic == 7) ||
499 (hdmi->hdmi_data.vic == 21) || (hdmi->hdmi_data.vic == 22) ||
500 (hdmi->hdmi_data.vic == 2) || (hdmi->hdmi_data.vic == 3) ||
501 (hdmi->hdmi_data.vic == 17) || (hdmi->hdmi_data.vic == 18))
502 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
503 else
504 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
505
506 /* Mute video and audio output */
507 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
508 v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
509
510 /* Set HDMI Mode */
511 hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
512 v_HDMI_DVI(hdmi->hdmi_data.sink_is_hdmi));
513
514 inno_hdmi_config_video_timing(hdmi, mode);
515
516 inno_hdmi_config_video_csc(hdmi);
517
518 if (hdmi->hdmi_data.sink_is_hdmi) {
519 inno_hdmi_config_video_avi(hdmi, mode);
520 inno_hdmi_config_video_vsi(hdmi, mode);
521 }
522
523 /*
524 * When IP controller have configured to an accurate video
525 * timing, then the TMDS clock source would be switched to
526 * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
527 * clock rate, and reconfigure the DDC clock.
528 */
529 hdmi->tmds_rate = mode->clock * 1000;
530 inno_hdmi_i2c_init(hdmi);
531
532 /* Unmute video and audio output */
533 hdmi_modb(hdmi, HDMI_AV_MUTE, m_VIDEO_BLACK, v_VIDEO_MUTE(0));
534 if (hdmi->audio_enable)
535 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE, v_AUDIO_MUTE(0));
536
537 return 0;
538 }
539
inno_hdmi_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adj_mode)540 static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder,
541 struct drm_display_mode *mode,
542 struct drm_display_mode *adj_mode)
543 {
544 struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
545
546 inno_hdmi_setup(hdmi, adj_mode);
547
548 /* Store the display mode for plugin/DPMS poweron events */
549 memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
550 }
551
inno_hdmi_encoder_enable(struct drm_encoder * encoder)552 static void inno_hdmi_encoder_enable(struct drm_encoder *encoder)
553 {
554 struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
555
556 inno_hdmi_set_pwr_mode(hdmi, NORMAL);
557 }
558
inno_hdmi_encoder_disable(struct drm_encoder * encoder)559 static void inno_hdmi_encoder_disable(struct drm_encoder *encoder)
560 {
561 struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
562
563 inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR);
564 }
565
inno_hdmi_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adj_mode)566 static bool inno_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
567 const struct drm_display_mode *mode,
568 struct drm_display_mode *adj_mode)
569 {
570 return true;
571 }
572
573 static int
inno_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)574 inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
575 struct drm_crtc_state *crtc_state,
576 struct drm_connector_state *conn_state)
577 {
578 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
579
580 s->output_mode = ROCKCHIP_OUT_MODE_P888;
581 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
582
583 return 0;
584 }
585
586 static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = {
587 .enable = inno_hdmi_encoder_enable,
588 .disable = inno_hdmi_encoder_disable,
589 .mode_fixup = inno_hdmi_encoder_mode_fixup,
590 .mode_set = inno_hdmi_encoder_mode_set,
591 .atomic_check = inno_hdmi_encoder_atomic_check,
592 };
593
594 static enum drm_connector_status
inno_hdmi_connector_detect(struct drm_connector * connector,bool force)595 inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
596 {
597 struct inno_hdmi *hdmi = to_inno_hdmi(connector);
598
599 return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
600 connector_status_connected : connector_status_disconnected;
601 }
602
inno_hdmi_connector_get_modes(struct drm_connector * connector)603 static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
604 {
605 struct inno_hdmi *hdmi = to_inno_hdmi(connector);
606 struct edid *edid;
607 int ret = 0;
608
609 if (!hdmi->ddc)
610 return 0;
611
612 edid = drm_get_edid(connector, hdmi->ddc);
613 if (edid) {
614 hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
615 hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid);
616 drm_connector_update_edid_property(connector, edid);
617 ret = drm_add_edid_modes(connector, edid);
618 kfree(edid);
619 }
620
621 return ret;
622 }
623
624 static enum drm_mode_status
inno_hdmi_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)625 inno_hdmi_connector_mode_valid(struct drm_connector *connector,
626 struct drm_display_mode *mode)
627 {
628 return MODE_OK;
629 }
630
631 static int
inno_hdmi_probe_single_connector_modes(struct drm_connector * connector,uint32_t maxX,uint32_t maxY)632 inno_hdmi_probe_single_connector_modes(struct drm_connector *connector,
633 uint32_t maxX, uint32_t maxY)
634 {
635 return drm_helper_probe_single_connector_modes(connector, 1920, 1080);
636 }
637
inno_hdmi_connector_destroy(struct drm_connector * connector)638 static void inno_hdmi_connector_destroy(struct drm_connector *connector)
639 {
640 drm_connector_unregister(connector);
641 drm_connector_cleanup(connector);
642 }
643
644 static const struct drm_connector_funcs inno_hdmi_connector_funcs = {
645 .fill_modes = inno_hdmi_probe_single_connector_modes,
646 .detect = inno_hdmi_connector_detect,
647 .destroy = inno_hdmi_connector_destroy,
648 .reset = drm_atomic_helper_connector_reset,
649 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
650 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
651 };
652
653 static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
654 .get_modes = inno_hdmi_connector_get_modes,
655 .mode_valid = inno_hdmi_connector_mode_valid,
656 };
657
658 static int
inno_hdmi_audio_config_set(struct inno_hdmi * hdmi,struct hdmi_codec_daifmt * daifmt,struct audio_info * audio)659 inno_hdmi_audio_config_set(struct inno_hdmi *hdmi,
660 struct hdmi_codec_daifmt *daifmt,
661 struct audio_info *audio)
662 {
663 int rate, N, channel;
664
665 if (audio->channels < 3)
666 channel = I2S_CHANNEL_1_2;
667 else if (audio->channels < 5)
668 channel = I2S_CHANNEL_3_4;
669 else if (audio->channels < 7)
670 channel = I2S_CHANNEL_5_6;
671 else
672 channel = I2S_CHANNEL_7_8;
673
674 switch (audio->sample_rate) {
675 case 32000:
676 rate = AUDIO_32K;
677 N = N_32K;
678 break;
679 case 44100:
680 rate = AUDIO_441K;
681 N = N_441K;
682 break;
683 case 48000:
684 rate = AUDIO_48K;
685 N = N_48K;
686 break;
687 case 88200:
688 rate = AUDIO_882K;
689 N = N_882K;
690 break;
691 case 96000:
692 rate = AUDIO_96K;
693 N = N_96K;
694 break;
695 case 176400:
696 rate = AUDIO_1764K;
697 N = N_1764K;
698 break;
699 case 192000:
700 rate = AUDIO_192K;
701 N = N_192K;
702 break;
703 default:
704 dev_err(hdmi->dev, "[%s] not support such sample rate %d\n",
705 __func__, audio->sample_rate);
706 return -ENOENT;
707 }
708
709 if (daifmt->fmt == HDMI_SPDIF) {
710 /* set_audio source SPDIF */
711 hdmi_writeb(hdmi, HDMI_AUDIO_CTRL1, 0x09);
712 } else {
713 /* set_audio source I2S */
714 hdmi_writeb(hdmi, HDMI_AUDIO_CTRL1, 0x01);
715 }
716 hdmi_writeb(hdmi, AUDIO_SAMPLE_RATE, rate);
717 hdmi_writeb(hdmi, AUDIO_I2S_MODE, v_I2S_MODE(I2S_STANDARD) |
718 v_I2S_CHANNEL(channel));
719
720 hdmi_writeb(hdmi, AUDIO_I2S_MAP, 0x00);
721 hdmi_writeb(hdmi, AUDIO_I2S_SWAPS_SPDIF, rate);
722
723 /* Set N value */
724 hdmi_writeb(hdmi, AUDIO_N_H, (N >> 16) & 0x0F);
725 hdmi_writeb(hdmi, AUDIO_N_M, (N >> 8) & 0xFF);
726 hdmi_writeb(hdmi, AUDIO_N_L, N & 0xFF);
727
728 /* Set hdmi nlpcm mode to support hdmi bitstream */
729 hdmi_writeb(hdmi, HDMI_AUDIO_CHANNEL_STATUS, v_AUDIO_STATUS_NLPCM(0));
730
731 return inno_hdmi_config_audio_aai(hdmi, audio);
732 }
733
inno_hdmi_audio_prepare(struct device * dev,void * data,struct hdmi_codec_daifmt * fmt,struct hdmi_codec_params * hparms)734 static int inno_hdmi_audio_prepare(struct device *dev, void *data,
735 struct hdmi_codec_daifmt *fmt,
736 struct hdmi_codec_params *hparms)
737 {
738 struct inno_hdmi *hdmi = dev_get_drvdata(dev);
739
740 if (!hdmi->hdmi_data.sink_has_audio) {
741 dev_err(hdmi->dev, "Sink do not support audio!\n");
742 return -ENODEV;
743 }
744
745 hdmi->audio_enable = 0;
746 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_PD, v_AUDIO_PD(1));
747 return 0;
748 }
749
inno_hdmi_audio_hw_params(struct device * dev,void * d,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)750 static int inno_hdmi_audio_hw_params(struct device *dev, void *d,
751 struct hdmi_codec_daifmt *daifmt,
752 struct hdmi_codec_params *params)
753 {
754 struct inno_hdmi *hdmi = dev_get_drvdata(dev);
755 struct audio_info audio = {
756 .sample_width = params->sample_width,
757 .sample_rate = params->sample_rate,
758 .channels = params->channels,
759 };
760
761 if (!hdmi->hdmi_data.sink_has_audio) {
762 dev_err(hdmi->dev, "Sink do not support audio!\n");
763 return -ENODEV;
764 }
765
766 if (!hdmi->encoder.crtc)
767 return -ENODEV;
768
769 switch (daifmt->fmt) {
770 case HDMI_I2S:
771 break;
772 case HDMI_SPDIF:
773 break;
774 default:
775 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
776 return -EINVAL;
777 }
778
779 return inno_hdmi_audio_config_set(hdmi, daifmt, &audio);
780 }
781
inno_hdmi_audio_shutdown(struct device * dev,void * d)782 static void inno_hdmi_audio_shutdown(struct device *dev, void *d)
783 {
784 /* do nothing */
785 }
786
inno_hdmi_audio_mute(struct device * dev,void * data,bool mute,int direction)787 static int inno_hdmi_audio_mute(struct device *dev, void *data, bool mute, int direction)
788 {
789 struct inno_hdmi *hdmi = dev_get_drvdata(dev);
790
791 if (!hdmi->hdmi_data.sink_has_audio) {
792 dev_err(hdmi->dev, "Sink do not support audio!\n");
793 return -ENODEV;
794 }
795
796 hdmi->audio_enable = !mute;
797
798 if (mute)
799 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_AUDIO_PD,
800 v_AUDIO_MUTE(1) | v_AUDIO_PD(1));
801 else
802 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_AUDIO_PD,
803 v_AUDIO_MUTE(0) | v_AUDIO_PD(0));
804
805 return 0;
806 }
807
inno_hdmi_audio_get_eld(struct device * dev,void * d,uint8_t * buf,size_t len)808 static int inno_hdmi_audio_get_eld(struct device *dev, void *d,
809 uint8_t *buf, size_t len)
810 {
811 struct inno_hdmi *hdmi = dev_get_drvdata(dev);
812 struct drm_mode_config *config = &hdmi->encoder.dev->mode_config;
813 struct drm_connector *connector;
814 int ret = -ENODEV;
815
816 mutex_lock(&config->mutex);
817 list_for_each_entry(connector, &config->connector_list, head) {
818 if (&hdmi->encoder == connector->encoder) {
819 memcpy(buf, connector->eld,
820 min(sizeof(connector->eld), len));
821 ret = 0;
822 }
823 }
824 mutex_unlock(&config->mutex);
825
826 return ret;
827 }
828
829 static const struct hdmi_codec_ops audio_codec_ops = {
830 .hw_params = inno_hdmi_audio_hw_params,
831 .prepare = inno_hdmi_audio_prepare,
832 .audio_shutdown = inno_hdmi_audio_shutdown,
833 .mute_stream = inno_hdmi_audio_mute,
834 .get_eld = inno_hdmi_audio_get_eld,
835 };
836
inno_hdmi_audio_codec_init(struct inno_hdmi * hdmi,struct device * dev)837 static int inno_hdmi_audio_codec_init(struct inno_hdmi *hdmi,
838 struct device *dev)
839 {
840 const char *str = "i2s";
841 struct hdmi_codec_pdata codec_data = {
842 .i2s = 1,
843 .spdif = 0,
844 .ops = &audio_codec_ops,
845 .max_i2s_channels = 8,
846 };
847
848 if (device_property_read_string(dev, "rockchip,format", &str))
849 dev_warn(dev, "can not get rockchip,format\n");
850
851 if (strstr(str, "spdif")) {
852 codec_data.i2s = 0;
853 codec_data.spdif = 1;
854 }
855
856 hdmi->audio_enable = false;
857 hdmi->audio_pdev = platform_device_register_data(
858 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_NONE,
859 &codec_data, sizeof(codec_data));
860
861 return PTR_ERR_OR_ZERO(hdmi->audio_pdev);
862 }
863
inno_hdmi_register(struct drm_device * drm,struct inno_hdmi * hdmi)864 static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
865 {
866 struct drm_encoder *encoder = &hdmi->encoder;
867 struct device *dev = hdmi->dev;
868
869 encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm, dev->of_node);
870
871 /*
872 * If we failed to find the CRTC(s) which this encoder is
873 * supposed to be connected to, it's because the CRTC has
874 * not been registered yet. Defer probing, and hope that
875 * the required CRTC is added later.
876 */
877 if (encoder->possible_crtcs == 0)
878 return -EPROBE_DEFER;
879
880 drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs);
881 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
882
883 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
884
885 drm_connector_helper_add(&hdmi->connector,
886 &inno_hdmi_connector_helper_funcs);
887 drm_connector_init_with_ddc(drm, &hdmi->connector,
888 &inno_hdmi_connector_funcs,
889 DRM_MODE_CONNECTOR_HDMIA,
890 hdmi->ddc);
891
892 drm_connector_attach_encoder(&hdmi->connector, encoder);
893 inno_hdmi_audio_codec_init(hdmi, dev);
894
895 return 0;
896 }
897
inno_hdmi_i2c_irq(struct inno_hdmi * hdmi)898 static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi)
899 {
900 struct inno_hdmi_i2c *i2c = hdmi->i2c;
901 u8 stat;
902
903 stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1);
904 if (!(stat & m_INT_EDID_READY))
905 return IRQ_NONE;
906
907 /* Clear HDMI EDID interrupt flag */
908 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
909
910 complete(&i2c->cmp);
911
912 return IRQ_HANDLED;
913 }
914
inno_hdmi_hardirq(int irq,void * dev_id)915 static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id)
916 {
917 struct inno_hdmi *hdmi = dev_id;
918 irqreturn_t ret = IRQ_NONE;
919 u8 interrupt;
920
921 if (hdmi->i2c)
922 ret = inno_hdmi_i2c_irq(hdmi);
923
924 interrupt = hdmi_readb(hdmi, HDMI_STATUS);
925 if (interrupt & m_INT_HOTPLUG) {
926 hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG);
927 ret = IRQ_WAKE_THREAD;
928 }
929
930 return ret;
931 }
932
inno_hdmi_irq(int irq,void * dev_id)933 static irqreturn_t inno_hdmi_irq(int irq, void *dev_id)
934 {
935 struct inno_hdmi *hdmi = dev_id;
936
937 drm_helper_hpd_irq_event(hdmi->connector.dev);
938
939 return IRQ_HANDLED;
940 }
941
inno_hdmi_i2c_read(struct inno_hdmi * hdmi,struct i2c_msg * msgs)942 static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
943 {
944 int length = msgs->len;
945 u8 *buf = msgs->buf;
946 int ret;
947
948 ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10);
949 if (!ret)
950 return -EAGAIN;
951
952 while (length--)
953 *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR);
954
955 return 0;
956 }
957
inno_hdmi_i2c_write(struct inno_hdmi * hdmi,struct i2c_msg * msgs)958 static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
959 {
960 /*
961 * The DDC module only support read EDID message, so
962 * we assume that each word write to this i2c adapter
963 * should be the offset of EDID word address.
964 */
965 if ((msgs->len != 1) ||
966 ((msgs->addr != DDC_ADDR) && (msgs->addr != DDC_SEGMENT_ADDR)))
967 return -EINVAL;
968
969 reinit_completion(&hdmi->i2c->cmp);
970
971 if (msgs->addr == DDC_SEGMENT_ADDR)
972 hdmi->i2c->segment_addr = msgs->buf[0];
973 if (msgs->addr == DDC_ADDR)
974 hdmi->i2c->ddc_addr = msgs->buf[0];
975
976 /* Set edid fifo first addr */
977 hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00);
978
979 /* Set edid word address 0x00/0x80 */
980 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
981
982 /* Set edid segment pointer */
983 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
984
985 return 0;
986 }
987
inno_hdmi_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)988 static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap,
989 struct i2c_msg *msgs, int num)
990 {
991 struct inno_hdmi *hdmi = i2c_get_adapdata(adap);
992 struct inno_hdmi_i2c *i2c = hdmi->i2c;
993 int i, ret = 0;
994
995 mutex_lock(&i2c->lock);
996
997 /* Clear the EDID interrupt flag and unmute the interrupt */
998 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY);
999 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
1000
1001 for (i = 0; i < num; i++) {
1002 DRM_DEV_DEBUG(hdmi->dev,
1003 "xfer: num: %d/%d, len: %d, flags: %#x\n",
1004 i + 1, num, msgs[i].len, msgs[i].flags);
1005
1006 if (msgs[i].flags & I2C_M_RD)
1007 ret = inno_hdmi_i2c_read(hdmi, &msgs[i]);
1008 else
1009 ret = inno_hdmi_i2c_write(hdmi, &msgs[i]);
1010
1011 if (ret < 0)
1012 break;
1013 }
1014
1015 if (!ret)
1016 ret = num;
1017
1018 /* Mute HDMI EDID interrupt */
1019 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
1020
1021 mutex_unlock(&i2c->lock);
1022
1023 return ret;
1024 }
1025
inno_hdmi_i2c_func(struct i2c_adapter * adapter)1026 static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter)
1027 {
1028 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1029 }
1030
1031 static const struct i2c_algorithm inno_hdmi_algorithm = {
1032 .master_xfer = inno_hdmi_i2c_xfer,
1033 .functionality = inno_hdmi_i2c_func,
1034 };
1035
inno_hdmi_i2c_adapter(struct inno_hdmi * hdmi)1036 static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
1037 {
1038 struct i2c_adapter *adap;
1039 struct inno_hdmi_i2c *i2c;
1040 int ret;
1041
1042 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
1043 if (!i2c)
1044 return ERR_PTR(-ENOMEM);
1045
1046 mutex_init(&i2c->lock);
1047 init_completion(&i2c->cmp);
1048
1049 adap = &i2c->adap;
1050 adap->class = I2C_CLASS_DDC;
1051 adap->owner = THIS_MODULE;
1052 adap->dev.parent = hdmi->dev;
1053 adap->dev.of_node = hdmi->dev->of_node;
1054 adap->algo = &inno_hdmi_algorithm;
1055 strlcpy(adap->name, "Inno HDMI", sizeof(adap->name));
1056 i2c_set_adapdata(adap, hdmi);
1057
1058 ret = i2c_add_adapter(adap);
1059 if (ret) {
1060 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
1061 devm_kfree(hdmi->dev, i2c);
1062 return ERR_PTR(ret);
1063 }
1064
1065 hdmi->i2c = i2c;
1066
1067 DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
1068
1069 return adap;
1070 }
1071
1072 static struct inno_hdmi_phy_config rk3036_hdmi_phy_config[] = {
1073 /* pixelclk pre-emp vlev */
1074 { 74250000, 0x3f, 0xbb },
1075 { 165000000, 0x6f, 0xbb },
1076 { ~0UL, 0x00, 0x00 }
1077 };
1078
1079 static struct inno_hdmi_phy_config rk3128_hdmi_phy_config[] = {
1080 /* pixelclk pre-emp vlev */
1081 { 74250000, 0x3f, 0xaa },
1082 { 165000000, 0x5f, 0xaa },
1083 { ~0UL, 0x00, 0x00 }
1084 };
1085
1086 static const struct inno_hdmi_plat_data rk3036_hdmi_drv_data = {
1087 .dev_type = RK3036_HDMI,
1088 .phy_config = rk3036_hdmi_phy_config,
1089 };
1090
1091 static const struct inno_hdmi_plat_data rk3128_hdmi_drv_data = {
1092 .dev_type = RK3128_HDMI,
1093 .phy_config = rk3128_hdmi_phy_config,
1094 };
1095
1096 static const struct of_device_id inno_hdmi_dt_ids[] = {
1097 { .compatible = "rockchip,rk3036-inno-hdmi",
1098 .data = &rk3036_hdmi_drv_data,
1099 },
1100 { .compatible = "rockchip,rk3128-inno-hdmi",
1101 .data = &rk3128_hdmi_drv_data,
1102 },
1103 {},
1104 };
1105 MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids);
1106
inno_hdmi_bind(struct device * dev,struct device * master,void * data)1107 static int inno_hdmi_bind(struct device *dev, struct device *master,
1108 void *data)
1109 {
1110 struct platform_device *pdev = to_platform_device(dev);
1111 struct drm_device *drm = data;
1112 struct inno_hdmi *hdmi;
1113 struct resource *iores;
1114 int irq;
1115 int ret;
1116
1117 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1118 if (!hdmi)
1119 return -ENOMEM;
1120
1121 hdmi->dev = dev;
1122 hdmi->drm_dev = drm;
1123 hdmi->plat_data = device_get_match_data(hdmi->dev);
1124
1125 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1126 hdmi->regs = devm_ioremap_resource(dev, iores);
1127 if (IS_ERR(hdmi->regs))
1128 return PTR_ERR(hdmi->regs);
1129
1130 irq = platform_get_irq(pdev, 0);
1131 if (irq < 0)
1132 return irq;
1133
1134 hdmi->aclk = devm_clk_get(hdmi->dev, "aclk");
1135 if (IS_ERR(hdmi->aclk)) {
1136 dev_err(hdmi->dev, "Unable to get HDMI aclk clk\n");
1137 return PTR_ERR(hdmi->aclk);
1138 }
1139
1140 hdmi->pclk = devm_clk_get(hdmi->dev, "pclk");
1141 if (IS_ERR(hdmi->pclk)) {
1142 DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n");
1143 return PTR_ERR(hdmi->pclk);
1144 }
1145
1146 ret = clk_prepare_enable(hdmi->aclk);
1147 if (ret) {
1148 DRM_DEV_ERROR(hdmi->dev,
1149 "Cannot enable HDMI aclk clock: %d\n", ret);
1150 return ret;
1151 }
1152
1153 ret = clk_prepare_enable(hdmi->pclk);
1154 if (ret) {
1155 dev_err(hdmi->dev, "Cannot enable HDMI pclk clock: %d\n", ret);
1156 goto err_disable_aclk;
1157 }
1158
1159 inno_hdmi_reset(hdmi);
1160
1161 hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
1162 if (IS_ERR(hdmi->ddc)) {
1163 ret = PTR_ERR(hdmi->ddc);
1164 hdmi->ddc = NULL;
1165 goto err_disable_pclk;
1166 }
1167
1168 /*
1169 * When IP controller haven't configured to an accurate video
1170 * timing, then the TMDS clock source would be switched to
1171 * PCLK_HDMI, so we need to init the TMDS rate to PCLK rate,
1172 * and reconfigure the DDC clock.
1173 */
1174 hdmi->tmds_rate = clk_get_rate(hdmi->pclk);
1175 inno_hdmi_i2c_init(hdmi);
1176
1177 ret = inno_hdmi_register(drm, hdmi);
1178 if (ret)
1179 goto err_put_adapter;
1180
1181 dev_set_drvdata(dev, hdmi);
1182
1183 /* Unmute hotplug interrupt */
1184 hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1));
1185
1186 ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq,
1187 inno_hdmi_irq, IRQF_SHARED,
1188 dev_name(dev), hdmi);
1189 if (ret) {
1190 dev_err(hdmi->dev,
1191 "failed to request hdmi irq: %d\n", ret);
1192 goto err_cleanup_hdmi;
1193 }
1194
1195 return 0;
1196
1197 err_cleanup_hdmi:
1198 hdmi->connector.funcs->destroy(&hdmi->connector);
1199 hdmi->encoder.funcs->destroy(&hdmi->encoder);
1200 err_put_adapter:
1201 i2c_put_adapter(hdmi->ddc);
1202 err_disable_pclk:
1203 clk_disable_unprepare(hdmi->pclk);
1204 err_disable_aclk:
1205 clk_disable_unprepare(hdmi->aclk);
1206 return ret;
1207 }
1208
inno_hdmi_unbind(struct device * dev,struct device * master,void * data)1209 static void inno_hdmi_unbind(struct device *dev, struct device *master,
1210 void *data)
1211 {
1212 struct inno_hdmi *hdmi = dev_get_drvdata(dev);
1213
1214 hdmi->connector.funcs->destroy(&hdmi->connector);
1215 hdmi->encoder.funcs->destroy(&hdmi->encoder);
1216
1217 i2c_put_adapter(hdmi->ddc);
1218 clk_disable_unprepare(hdmi->pclk);
1219 clk_disable_unprepare(hdmi->aclk);
1220 }
1221
1222 static const struct component_ops inno_hdmi_ops = {
1223 .bind = inno_hdmi_bind,
1224 .unbind = inno_hdmi_unbind,
1225 };
1226
inno_hdmi_probe(struct platform_device * pdev)1227 static int inno_hdmi_probe(struct platform_device *pdev)
1228 {
1229 return component_add(&pdev->dev, &inno_hdmi_ops);
1230 }
1231
inno_hdmi_remove(struct platform_device * pdev)1232 static int inno_hdmi_remove(struct platform_device *pdev)
1233 {
1234 component_del(&pdev->dev, &inno_hdmi_ops);
1235
1236 return 0;
1237 }
1238
1239 struct platform_driver inno_hdmi_driver = {
1240 .probe = inno_hdmi_probe,
1241 .remove = inno_hdmi_remove,
1242 .driver = {
1243 .name = "innohdmi-rockchip",
1244 .of_match_table = inno_hdmi_dt_ids,
1245 },
1246 };
1247