1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare Cores HDCP Controller
4 *
5 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
6 *
7 * Author: Zhang Yubing <yubing.zhang@rock-chips.com>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/miscdevice.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/uaccess.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/clk.h>
20 #include <linux/of.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/rockchip/rockchip_sip.h>
24 #include <uapi/misc/dw_hdcp2.h>
25
26 #define VO0_GRF_VO0_STS0 0x20
27 #define DP1_CONNECT_HDCP0_STATUS BIT(24)
28 #define DP0_CONNECT_HDCP0_STATUS BIT(8)
29 #define VO0_GRF_VO0_STS3 0x2C
30 #define HDCP0_BOOT_STATUS BIT(8)
31 #define VO1_GRF_VO1_STS3 0x3C
32 #define HDMITX0_CONNECT_HDCP1_STATUS BIT(20)
33 #define HDCP1_BOOT_STATUS BIT(16)
34 #define VO1_GRF_VO1_STS4 0x40
35 #define HDMITX1_CONNECT_HDCP1_STATUS BIT(0)
36 #define HDMIRX_CONNECT_HDCP1_STATUS BIT(8)
37
38 /**
39 * struct hl_device - hdcp host library device structure
40 * each hdcp controller attach to a hl_device, it include
41 * code memory info, data memory info and hpi(apb) interface
42 * info
43 */
44 struct hl_device {
45 bool allocated;
46 bool initialized;
47 bool code_loaded;
48
49 bool code_is_phys_mem;
50 dma_addr_t code_base;
51 uint32_t code_size;
52 uint8_t *code;
53 bool data_is_phys_mem;
54 dma_addr_t data_base;
55 uint32_t data_size;
56 uint8_t *data;
57
58 /** @hpi_respurce: resource of HPI interface */
59 struct resource *hpi_resource;
60 /** @hpi: base address of HPI registers */
61 uint8_t __iomem *hpi;
62 };
63
64 struct dw_hdcp {
65 struct device *dev;
66 struct miscdevice misc_dev;
67 struct hl_device hl_dev;
68
69 struct regmap *vo_grf;
70 struct reset_control *rsts_bulk;
71 struct clk_bulk_data *clks;
72 int num_clks;
73 int id;
74 bool is_suspend;
75 };
76
77 enum {
78 HDCP_PORT0 = 0,
79 HDCP_PORT1,
80 HDCP_PORT2,
81 };
82
83 static void dw_hdcp_free_hl_dev_slot(struct hl_device *hl_dev);
84
dw_hdcp_free_hl(struct dw_hdcp * hdcp)85 static void dw_hdcp_free_hl(struct dw_hdcp *hdcp)
86 {
87 dw_hdcp_free_hl_dev_slot(&hdcp->hl_dev);
88 hdcp->hl_dev.code_loaded = false;
89 }
90
dw_hdcp_reset(struct dw_hdcp * hdcp)91 static void dw_hdcp_reset(struct dw_hdcp *hdcp)
92 {
93 int ret;
94
95 reset_control_assert(hdcp->rsts_bulk);
96 udelay(20);
97 reset_control_deassert(hdcp->rsts_bulk);
98
99 ret = sip_hdcpkey_init(hdcp->id);
100 if (ret)
101 dev_err(hdcp->dev, "load hdcp key failed\n");
102 }
103
dw_hdcp_set_reset(struct dw_hdcp * hdcp,void __user * arg)104 static int dw_hdcp_set_reset(struct dw_hdcp *hdcp, void __user *arg)
105 {
106 u32 reset;
107
108 if (!arg)
109 return -EFAULT;
110
111 if (copy_from_user(&reset, arg, sizeof(reset)))
112 return -EFAULT;
113
114 if (reset) {
115 dev_info(hdcp->dev, "hdcp reset\n");
116 dw_hdcp_free_hl(hdcp);
117 dw_hdcp_reset(hdcp);
118 }
119
120 return 0;
121 }
122
dw_hdcp_get_status(struct dw_hdcp * hdcp,void __user * arg)123 static int dw_hdcp_get_status(struct dw_hdcp *hdcp, void __user *arg)
124 {
125 struct hl_drv_ioc_status status;
126 u32 val = 0;
127 u32 connected_status = 0;
128 u32 booted_status = 0;
129
130 if (!arg)
131 return -EFAULT;
132
133 if (!hdcp->is_suspend) {
134 if (hdcp->id) {
135 regmap_read(hdcp->vo_grf, VO1_GRF_VO1_STS3, &val);
136 if (val & HDMITX0_CONNECT_HDCP1_STATUS)
137 connected_status |= 1 << HDCP_PORT1;
138 if (val & HDCP1_BOOT_STATUS)
139 booted_status = 1;
140
141 regmap_read(hdcp->vo_grf, VO1_GRF_VO1_STS4, &val);
142 if (val & HDMITX1_CONNECT_HDCP1_STATUS)
143 connected_status |= 1 << HDCP_PORT2;
144 if (val & HDMIRX_CONNECT_HDCP1_STATUS)
145 connected_status |= 1 << HDCP_PORT0;
146 } else {
147 regmap_read(hdcp->vo_grf, VO0_GRF_VO0_STS0, &val);
148 if (val & DP0_CONNECT_HDCP0_STATUS)
149 connected_status |= 1 << HDCP_PORT0;
150 if (val & DP1_CONNECT_HDCP0_STATUS)
151 connected_status |= 1 << HDCP_PORT1;
152
153 regmap_read(hdcp->vo_grf, VO0_GRF_VO0_STS3, &val);
154 if (val & HDCP0_BOOT_STATUS)
155 booted_status = 1;
156 }
157 }
158
159 status.connected_status = connected_status;
160 status.booted_status = booted_status;
161
162 if (copy_to_user(arg, &status, sizeof(status)))
163 return -EFAULT;
164
165 return 0;
166 }
167
168 /* HL_DRV_IOC_MEMINFO implementation */
dw_hdcp_get_meminfo(struct hl_device * hl_dev,void __user * arg)169 static long dw_hdcp_get_meminfo(struct hl_device *hl_dev, void __user *arg)
170 {
171 struct hl_drv_ioc_meminfo info;
172
173 if (!arg)
174 return -EFAULT;
175
176 info.hpi_base = hl_dev->hpi_resource->start;
177 info.code_base = hl_dev->code_base;
178 info.code_size = hl_dev->code_size;
179 info.data_base = hl_dev->data_base;
180 info.data_size = hl_dev->data_size;
181
182 if (copy_to_user(arg, &info, sizeof(info)))
183 return -EFAULT;
184
185 return 0;
186 }
187
188 /* HL_DRV_IOC_LOAD_CODE implementation */
dw_hdcp_load_code(struct hl_device * hl_dev,struct hl_drv_ioc_code __user * arg)189 static long dw_hdcp_load_code(struct hl_device *hl_dev, struct hl_drv_ioc_code __user *arg)
190 {
191 struct hl_drv_ioc_code head;
192
193 if (!arg || !hl_dev->code)
194 return -EFAULT;
195
196 if (copy_from_user(&head, arg, sizeof(head)))
197 return -EFAULT;
198
199 if (head.len > hl_dev->code_size)
200 return -ENOSPC;
201
202 if (hl_dev->code_loaded)
203 return -EBUSY;
204
205 if (copy_from_user(hl_dev->code, &arg->data, head.len))
206 return -EFAULT;
207
208 hl_dev->code_loaded = true;
209 return 0;
210 }
211
212 /* HL_DRV_IOC_WRITE_DATA implementation */
dw_hdcp_write_data(struct hl_device * hl_dev,struct hl_drv_ioc_data __user * arg)213 static long dw_hdcp_write_data(struct hl_device *hl_dev, struct hl_drv_ioc_data __user *arg)
214 {
215 struct hl_drv_ioc_data head;
216
217 if (!arg || !hl_dev->data)
218 return -EFAULT;
219
220 if (copy_from_user(&head, arg, sizeof(head)))
221 return -EFAULT;
222
223 if (hl_dev->data_size < head.len)
224 return -ENOSPC;
225 if (hl_dev->data_size - head.len < head.offset)
226 return -ENOSPC;
227
228 if (copy_from_user(hl_dev->data + head.offset, &arg->data, head.len))
229 return -EFAULT;
230
231 return 0;
232 }
233
234 /* HL_DRV_IOC_READ_DATA implementation */
dw_hdcp_read_data(struct hl_device * hl_dev,struct hl_drv_ioc_data __user * arg)235 static long dw_hdcp_read_data(struct hl_device *hl_dev, struct hl_drv_ioc_data __user *arg)
236 {
237 struct hl_drv_ioc_data head;
238
239 if (!arg || !hl_dev->data)
240 return -EFAULT;
241
242 if (copy_from_user(&head, arg, sizeof(head)))
243 return -EFAULT;
244
245 if (hl_dev->data_size < head.len)
246 return -ENOSPC;
247 if (hl_dev->data_size - head.len < head.offset)
248 return -ENOSPC;
249
250 if (copy_to_user(&arg->data, hl_dev->data + head.offset, head.len))
251 return -EFAULT;
252
253 return 0;
254 }
255
256 /* HL_DRV_IOC_MEMSET_DATA implementation */
dw_hdcp_set_data(struct hl_device * hl_dev,void __user * arg)257 static long dw_hdcp_set_data(struct hl_device *hl_dev, void __user *arg)
258 {
259 union {
260 struct hl_drv_ioc_data data;
261 unsigned char buf[sizeof(struct hl_drv_ioc_data) + 1];
262 } u;
263
264 if (!arg || !hl_dev->data)
265 return -EFAULT;
266
267 if (copy_from_user(&u.data, arg, sizeof(u.buf)))
268 return -EFAULT;
269
270 if (hl_dev->data_size < u.data.len)
271 return -ENOSPC;
272 if (hl_dev->data_size - u.data.len < u.data.offset)
273 return -ENOSPC;
274
275 memset(hl_dev->data + u.data.offset, u.data.data[0], u.data.len);
276 return 0;
277 }
278
279 /* HL_DRV_IOC_READ_HPI implementation */
dw_hdcp_hpi_read(struct hl_device * hl_dev,void __user * arg)280 static long dw_hdcp_hpi_read(struct hl_device *hl_dev, void __user *arg)
281 {
282 struct hl_drv_ioc_hpi_reg reg;
283
284 if (!arg)
285 return -EFAULT;
286
287 if (copy_from_user(®, arg, sizeof(reg)))
288 return -EFAULT;
289
290 if ((reg.offset & 3) || reg.offset >= resource_size(hl_dev->hpi_resource))
291 return -EINVAL;
292
293 reg.value = ioread32(hl_dev->hpi + reg.offset);
294 if (copy_to_user(arg, ®, sizeof(reg)))
295 return -EFAULT;
296
297 return 0;
298 }
299
300 /* HL_DRV_IOC_WRITE_HPI implementation */
dw_hdcp_hpi_write(struct hl_device * hl_dev,void __user * arg)301 static long dw_hdcp_hpi_write(struct hl_device *hl_dev, void __user *arg)
302 {
303 struct hl_drv_ioc_hpi_reg reg;
304
305 if (!arg)
306 return -EFAULT;
307
308 if (copy_from_user(®, arg, sizeof(reg)))
309 return -EFAULT;
310
311 if ((reg.offset & 3) || reg.offset >= resource_size(hl_dev->hpi_resource))
312 return -EINVAL;
313
314 iowrite32(reg.value, hl_dev->hpi + reg.offset);
315 #ifdef TROOT_GRIFFIN
316 if ((reg.offset == 0x38) && ((reg.value & 0x000000ff) == 0x08))
317 hl_dev->code_loaded = false;
318 #endif
319 return 0;
320 }
321
dw_hdcp_check_hl_dev_slot(const struct hl_drv_ioc_meminfo * info,struct hl_device * hl_dev)322 static int dw_hdcp_check_hl_dev_slot(const struct hl_drv_ioc_meminfo *info,
323 struct hl_device *hl_dev)
324 {
325 if (info->hpi_base == hl_dev->hpi_resource->start)
326 return 0;
327
328 return -EBUSY;
329 }
330
dw_hdcp_free_dma_areas(struct hl_device * hl_dev)331 static void dw_hdcp_free_dma_areas(struct hl_device *hl_dev)
332 {
333 struct dw_hdcp *hdcp = container_of(hl_dev, struct dw_hdcp, hl_dev);
334
335 if (!hl_dev->code_is_phys_mem && hl_dev->code) {
336 dma_free_coherent(hdcp->dev, hl_dev->code_size, hl_dev->code, hl_dev->code_base);
337 hl_dev->code = NULL;
338 }
339
340 if (!hl_dev->data_is_phys_mem && hl_dev->data) {
341 dma_free_coherent(hdcp->dev, hl_dev->data_size, hl_dev->data, hl_dev->data_base);
342 hl_dev->data = NULL;
343 }
344 }
345
dw_hdcp_alloc_dma_areas(struct hl_device * hl_dev,const struct hl_drv_ioc_meminfo * info)346 static int dw_hdcp_alloc_dma_areas(struct hl_device *hl_dev, const struct hl_drv_ioc_meminfo *info)
347 {
348 struct dw_hdcp *hdcp = container_of(hl_dev, struct dw_hdcp, hl_dev);
349
350 hl_dev->code_size = info->code_size;
351 hl_dev->code_is_phys_mem = (info->code_base != HL_DRIVER_ALLOCATE_DYNAMIC_MEM);
352 hl_dev->data_size = info->data_size;
353 hl_dev->data_is_phys_mem = (info->data_base != HL_DRIVER_ALLOCATE_DYNAMIC_MEM);
354
355 if ((hl_dev->code_is_phys_mem && !hl_dev->code) ||
356 (hl_dev->data_is_phys_mem && !hl_dev->data)) {
357 dev_err(hdcp->dev, "hdcp don't support phys mem\n");
358 return -ENOMEM;
359 }
360
361 hl_dev->code = dma_alloc_coherent(hdcp->dev, hl_dev->code_size,
362 &hl_dev->code_base, GFP_KERNEL);
363 if (!hl_dev->code)
364 return -ENOMEM;
365
366 hl_dev->data = dma_alloc_coherent(hdcp->dev, hl_dev->data_size,
367 &hl_dev->data_base, GFP_KERNEL);
368 if (!hl_dev->data) {
369 dw_hdcp_free_dma_areas(hl_dev);
370 return -ENOMEM;
371 }
372
373 return 0;
374 }
375
376 /* HL_DRV_IOC_INIT implementation */
dw_hdcp_init(struct hl_device * hl_dev,void __user * arg)377 static long dw_hdcp_init(struct hl_device *hl_dev, void __user *arg)
378 {
379 struct hl_drv_ioc_meminfo info;
380 int rc;
381
382 if (!arg)
383 return -EFAULT;
384
385 if (copy_from_user(&info, arg, sizeof(info)))
386 return -EFAULT;
387
388 rc = dw_hdcp_check_hl_dev_slot(&info, hl_dev);
389 if (rc)
390 return -EMFILE;
391
392 if (!hl_dev->initialized) {
393 rc = dw_hdcp_alloc_dma_areas(hl_dev, &info);
394 if (rc < 0)
395 goto err_free;
396
397 hl_dev->initialized = true;
398 }
399
400 return 0;
401
402 err_free:
403 dw_hdcp_free_dma_areas(hl_dev);
404 hl_dev->initialized = false;
405
406 return rc;
407 }
408
dw_hdcp_free_hl_dev_slot(struct hl_device * hl_dev)409 static void dw_hdcp_free_hl_dev_slot(struct hl_device *hl_dev)
410 {
411 if (hl_dev->initialized)
412 dw_hdcp_free_dma_areas(hl_dev);
413
414 hl_dev->initialized = false;
415 }
416
dw_hdcp_hld_ioctl(struct file * f,unsigned int cmd,unsigned long arg)417 static long dw_hdcp_hld_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
418 {
419 struct hl_device *hl_dev;
420 struct dw_hdcp *hdcp;
421 struct miscdevice *misc_dev;
422 void __user *data;
423
424 if (!f)
425 return -EFAULT;
426
427 misc_dev = f->private_data;
428 hdcp = container_of(misc_dev, struct dw_hdcp, misc_dev);
429 hl_dev = &hdcp->hl_dev;
430
431 data = (void __user *)arg;
432
433 switch (cmd) {
434 case HL_DRV_IOC_INIT:
435 return dw_hdcp_init(hl_dev, data);
436 case HL_DRV_IOC_MEMINFO:
437 return dw_hdcp_get_meminfo(hl_dev, data);
438 case HL_DRV_IOC_READ_HPI:
439 return dw_hdcp_hpi_read(hl_dev, data);
440 case HL_DRV_IOC_WRITE_HPI:
441 return dw_hdcp_hpi_write(hl_dev, data);
442 case HL_DRV_IOC_LOAD_CODE:
443 return dw_hdcp_load_code(hl_dev, data);
444 case HL_DRV_IOC_WRITE_DATA:
445 return dw_hdcp_write_data(hl_dev, data);
446 case HL_DRV_IOC_READ_DATA:
447 return dw_hdcp_read_data(hl_dev, data);
448 case HL_DRV_IOC_MEMSET_DATA:
449 return dw_hdcp_set_data(hl_dev, data);
450
451 case RK_DRV_IOC_GET_STATUS:
452 return dw_hdcp_get_status(hdcp, data);
453 case RK_DRV_IOC_RESET:
454 return dw_hdcp_set_reset(hdcp, data);
455 default:
456 return -EINVAL;
457 }
458
459 return -ENOTTY;
460 }
461
dw_hdcp_hld_open(struct inode * inode,struct file * f)462 static int dw_hdcp_hld_open(struct inode *inode, struct file *f)
463 {
464 struct dw_hdcp *hdcp;
465 struct miscdevice *misc_dev;
466
467 misc_dev = f->private_data;
468 hdcp = container_of(misc_dev, struct dw_hdcp, misc_dev);
469 pm_runtime_get_sync(hdcp->dev);
470
471 return 0;
472 }
473
dw_hdcp_hld_release(struct inode * inode,struct file * f)474 static int dw_hdcp_hld_release(struct inode *inode, struct file *f)
475 {
476 struct dw_hdcp *hdcp;
477 struct miscdevice *misc_dev;
478
479 misc_dev = f->private_data;
480 hdcp = container_of(misc_dev, struct dw_hdcp, misc_dev);
481 pm_runtime_put(hdcp->dev);
482
483 return 0;
484 }
485
486 static const struct file_operations dw_hdcp_hld_file_operations = {
487 #ifdef CONFIG_COMPAT
488 .compat_ioctl = dw_hdcp_hld_ioctl,
489 #else
490 .unlocked_ioctl = dw_hdcp_hld_ioctl,
491 #endif
492 .open = dw_hdcp_hld_open,
493 .release = dw_hdcp_hld_release,
494 .owner = THIS_MODULE,
495 };
496
dw_hdcp_hld_init(struct dw_hdcp * hdcp,struct resource * res,void __iomem * base)497 static int dw_hdcp_hld_init(struct dw_hdcp *hdcp, struct resource *res, void __iomem *base)
498 {
499 hdcp->hl_dev.allocated = false;
500 hdcp->hl_dev.initialized = false;
501 hdcp->hl_dev.code_loaded = false;
502 hdcp->hl_dev.code = NULL;
503 hdcp->hl_dev.data = NULL;
504 hdcp->hl_dev.hpi_resource = res;
505 hdcp->hl_dev.hpi = base;
506
507 hdcp->misc_dev.name = devm_kasprintf(hdcp->dev, GFP_KERNEL, "hl_dev%d", hdcp->id);
508 if (!hdcp->misc_dev.name)
509 return -ENOMEM;
510 hdcp->misc_dev.minor = MISC_DYNAMIC_MINOR;
511 hdcp->misc_dev.fops = &dw_hdcp_hld_file_operations;
512
513 return misc_register(&hdcp->misc_dev);
514 }
515
dw_hdcp_hld_exit(struct dw_hdcp * hdcp)516 static void dw_hdcp_hld_exit(struct dw_hdcp *hdcp)
517 {
518 dw_hdcp_free_hl_dev_slot(&hdcp->hl_dev);
519
520 misc_deregister(&hdcp->misc_dev);
521 }
522
dw_hdcp_probe(struct platform_device * pdev)523 static int dw_hdcp_probe(struct platform_device *pdev)
524 {
525 struct device *dev = &pdev->dev;
526 struct dw_hdcp *hdcp;
527 struct resource *res;
528 void __iomem *base;
529 int id, ret;
530
531 hdcp = devm_kzalloc(dev, sizeof(*hdcp), GFP_KERNEL);
532 if (!hdcp)
533 return -ENOMEM;
534
535 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
536 base = devm_ioremap_resource(dev, res);
537 if (IS_ERR(base))
538 return PTR_ERR(base);
539
540 id = of_alias_get_id(dev->of_node, "hdcp");
541 if (id < 0)
542 id = 0;
543
544 hdcp->id = id;
545 hdcp->dev = dev;
546
547 hdcp->vo_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo-grf");
548 if (IS_ERR(hdcp->vo_grf)) {
549 dev_err(hdcp->dev, "Get vo-grf failed\n");
550 return -ENODEV;
551 }
552
553 hdcp->rsts_bulk = devm_reset_control_array_get_exclusive(dev);
554 if (IS_ERR(hdcp->rsts_bulk)) {
555 dev_err(dev, "Get resets failed\n");
556 return -ENODEV;
557 }
558
559 hdcp->num_clks = devm_clk_bulk_get_all(dev, &hdcp->clks);
560 if (hdcp->num_clks < 1) {
561 dev_err(dev, "Get clks failed\n");
562 return -ENODEV;
563 }
564
565 ret = dw_hdcp_hld_init(hdcp, res, base);
566 if (ret) {
567 dev_err(dev, "hld init failed\n");
568 return -ENODEV;
569 }
570
571 platform_set_drvdata(pdev, hdcp);
572
573 pm_runtime_enable(hdcp->dev);
574
575 return 0;
576 }
577
dw_hdcp_remove(struct platform_device * pdev)578 static int dw_hdcp_remove(struct platform_device *pdev)
579 {
580 struct dw_hdcp *hdcp = platform_get_drvdata(pdev);
581
582 dw_hdcp_hld_exit(hdcp);
583
584 pm_runtime_disable(hdcp->dev);
585
586 return 0;
587 }
588
dw_hdcp_runtime_suspend(struct device * dev)589 static int dw_hdcp_runtime_suspend(struct device *dev)
590 {
591 struct dw_hdcp *hdcp = dev_get_drvdata(dev);
592
593 hdcp->is_suspend = true;
594 clk_bulk_disable_unprepare(hdcp->num_clks, hdcp->clks);
595
596 dw_hdcp_free_hl(hdcp);
597
598 return 0;
599 }
600
dw_hdcp_runtime_resume(struct device * dev)601 static int dw_hdcp_runtime_resume(struct device *dev)
602 {
603 struct dw_hdcp *hdcp = dev_get_drvdata(dev);
604 int ret;
605
606 ret = clk_bulk_prepare_enable(hdcp->num_clks, hdcp->clks);
607 if (ret)
608 dev_err(dev, "prepare enable clk bulk failed\n");
609
610 dw_hdcp_reset(hdcp);
611
612 hdcp->is_suspend = false;
613 return 0;
614 }
615
616 static const struct dev_pm_ops dw_hdcp_pm_ops = {
617 SET_RUNTIME_PM_OPS(dw_hdcp_runtime_suspend, dw_hdcp_runtime_resume, NULL)
618 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
619 };
620
621 static const struct of_device_id dw_hdcp_of_match[] = {
622 {.compatible = "rockchip,rk3588-hdcp",},
623 {}
624 };
625
626 MODULE_DEVICE_TABLE(of, dw_hdcp_of_match);
627
628 static struct platform_driver dw_hdcp_driver = {
629 .probe = dw_hdcp_probe,
630 .remove = dw_hdcp_remove,
631 .driver = {
632 .name = "dw-hdcp",
633 .of_match_table = dw_hdcp_of_match,
634 .pm = &dw_hdcp_pm_ops,
635 },
636 };
637
638 module_platform_driver(dw_hdcp_driver);
639
640 MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>");
641 MODULE_LICENSE("GPL");
642 MODULE_DESCRIPTION("Rockchip HDCP Host Library Driver");
643