1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31 #include <linux/hdmi.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/vga_switcheroo.h>
37
38 #include <drm/drm_displayid.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_encoder.h>
42 #include <drm/drm_print.h>
43 #include <drm/drm_scdc_helper.h>
44
45 #include "drm_crtc_internal.h"
46
47 #define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
50
51 #define EDID_EST_TIMINGS 16
52 #define EDID_STD_TIMINGS 8
53 #define EDID_DETAILED_TIMINGS 4
54
55 /*
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
60 */
61
62 /* First detailed mode wrong, use largest 60Hz mode */
63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64 /* Reported 135MHz pixel clock is too high, needs adjustment */
65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66 /* Prefer the largest mode at 75 Hz */
67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68 /* Detail timing is in cm not mm */
69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70 /* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
72 */
73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
74 /* use +hsync +vsync for detailed mode */
75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
76 /* Force reduced-blanking timings for detailed modes */
77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 /* Force 8bpc */
79 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 /* Force 12bpc */
81 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 /* Force 6bpc */
83 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 /* Force 10bpc */
85 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
86 /* Non desktop display (i.e. HMD) */
87 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
88
89 struct detailed_mode_closure {
90 struct drm_connector *connector;
91 struct edid *edid;
92 bool preferred;
93 u32 quirks;
94 int modes;
95 };
96
97 #define LEVEL_DMT 0
98 #define LEVEL_GTF 1
99 #define LEVEL_GTF2 2
100 #define LEVEL_CVT 3
101
102 static const struct edid_quirk {
103 char vendor[4];
104 int product_id;
105 u32 quirks;
106 } edid_quirk_list[] = {
107 /* Acer AL1706 */
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 /* Acer F51 */
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111
112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
114
115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
117
118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
120
121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
123
124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
126
127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
130
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
135
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
139
140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
142
143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146
147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
152
153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
155
156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
158
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
161
162 /* Lenovo G50 */
163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
164
165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
167
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
170
171 /* Valve Index Headset */
172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
189
190 /* HTC Vive and Vive Pro VR Headsets */
191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
193
194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
199
200 /* Windows Mixed Reality Headsets */
201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
209
210 /* Sony PlayStation VR Headset */
211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
212
213 /* Sensics VR Headsets */
214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
215
216 /* OSVR HDK and HDK2 VR Headsets */
217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
218 };
219
220 /*
221 * Autogenerated from the DMT spec.
222 * This table is copied from xfree86/modes/xf86EdidModes.c.
223 */
224 static const struct drm_display_mode drm_dmt_modes[] = {
225 /* 0x01 - 640x350@85Hz */
226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
227 736, 832, 0, 350, 382, 385, 445, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
229 /* 0x02 - 640x400@85Hz */
230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
231 736, 832, 0, 400, 401, 404, 445, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 0x03 - 720x400@85Hz */
234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
235 828, 936, 0, 400, 401, 404, 446, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
237 /* 0x04 - 640x480@60Hz */
238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
239 752, 800, 0, 480, 490, 492, 525, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
241 /* 0x05 - 640x480@72Hz */
242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
243 704, 832, 0, 480, 489, 492, 520, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x06 - 640x480@75Hz */
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
247 720, 840, 0, 480, 481, 484, 500, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x07 - 640x480@85Hz */
250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
251 752, 832, 0, 480, 481, 484, 509, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 0x08 - 800x600@56Hz */
254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
255 896, 1024, 0, 600, 601, 603, 625, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x09 - 800x600@60Hz */
258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
259 968, 1056, 0, 600, 601, 605, 628, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
261 /* 0x0a - 800x600@72Hz */
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
263 976, 1040, 0, 600, 637, 643, 666, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x0b - 800x600@75Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
267 896, 1056, 0, 600, 601, 604, 625, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x0c - 800x600@85Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
271 896, 1048, 0, 600, 601, 604, 631, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x0d - 800x600@120Hz RB */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
275 880, 960, 0, 600, 603, 607, 636, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
277 /* 0x0e - 848x480@60Hz */
278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
279 976, 1088, 0, 480, 486, 494, 517, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0f - 1024x768@43Hz, interlace */
282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
283 1208, 1264, 0, 768, 768, 776, 817, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
285 DRM_MODE_FLAG_INTERLACE) },
286 /* 0x10 - 1024x768@60Hz */
287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
288 1184, 1344, 0, 768, 771, 777, 806, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x11 - 1024x768@70Hz */
291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
292 1184, 1328, 0, 768, 771, 777, 806, 0,
293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
294 /* 0x12 - 1024x768@75Hz */
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
296 1136, 1312, 0, 768, 769, 772, 800, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x13 - 1024x768@85Hz */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
300 1168, 1376, 0, 768, 769, 772, 808, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
302 /* 0x14 - 1024x768@120Hz RB */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
304 1104, 1184, 0, 768, 771, 775, 813, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
306 /* 0x15 - 1152x864@75Hz */
307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
308 1344, 1600, 0, 864, 865, 868, 900, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x55 - 1280x720@60Hz */
311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
312 1430, 1650, 0, 720, 725, 730, 750, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x16 - 1280x768@60Hz RB */
315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
316 1360, 1440, 0, 768, 771, 778, 790, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
318 /* 0x17 - 1280x768@60Hz */
319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
320 1472, 1664, 0, 768, 771, 778, 798, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x18 - 1280x768@75Hz */
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
324 1488, 1696, 0, 768, 771, 778, 805, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x19 - 1280x768@85Hz */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
328 1496, 1712, 0, 768, 771, 778, 809, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x1a - 1280x768@120Hz RB */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
332 1360, 1440, 0, 768, 771, 778, 813, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x1b - 1280x800@60Hz RB */
335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
336 1360, 1440, 0, 800, 803, 809, 823, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
338 /* 0x1c - 1280x800@60Hz */
339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
340 1480, 1680, 0, 800, 803, 809, 831, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x1d - 1280x800@75Hz */
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
344 1488, 1696, 0, 800, 803, 809, 838, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x1e - 1280x800@85Hz */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
348 1496, 1712, 0, 800, 803, 809, 843, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x1f - 1280x800@120Hz RB */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
352 1360, 1440, 0, 800, 803, 809, 847, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x20 - 1280x960@60Hz */
355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
356 1488, 1800, 0, 960, 961, 964, 1000, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x21 - 1280x960@85Hz */
359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
360 1504, 1728, 0, 960, 961, 964, 1011, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x22 - 1280x960@120Hz RB */
363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
364 1360, 1440, 0, 960, 963, 967, 1017, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
366 /* 0x23 - 1280x1024@60Hz */
367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x24 - 1280x1024@75Hz */
371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x25 - 1280x1024@85Hz */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x26 - 1280x1024@120Hz RB */
379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
382 /* 0x27 - 1360x768@60Hz */
383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
384 1536, 1792, 0, 768, 771, 777, 795, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x28 - 1360x768@120Hz RB */
387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
388 1440, 1520, 0, 768, 771, 776, 813, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
390 /* 0x51 - 1366x768@60Hz */
391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
392 1579, 1792, 0, 768, 771, 774, 798, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x56 - 1366x768@60Hz */
395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
396 1436, 1500, 0, 768, 769, 772, 800, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x29 - 1400x1050@60Hz RB */
399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x2a - 1400x1050@60Hz */
403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x2b - 1400x1050@75Hz */
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x2c - 1400x1050@85Hz */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x2d - 1400x1050@120Hz RB */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 0x2e - 1440x900@60Hz RB */
419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
420 1520, 1600, 0, 900, 903, 909, 926, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 0x2f - 1440x900@60Hz */
423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
424 1672, 1904, 0, 900, 903, 909, 934, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x30 - 1440x900@75Hz */
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
428 1688, 1936, 0, 900, 903, 909, 942, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x31 - 1440x900@85Hz */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
432 1696, 1952, 0, 900, 903, 909, 948, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x32 - 1440x900@120Hz RB */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
436 1520, 1600, 0, 900, 903, 909, 953, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 0x53 - 1600x900@60Hz */
439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
440 1704, 1800, 0, 900, 901, 904, 1000, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x33 - 1600x1200@60Hz */
443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x34 - 1600x1200@65Hz */
447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x35 - 1600x1200@70Hz */
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x36 - 1600x1200@75Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x37 - 1600x1200@85Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x38 - 1600x1200@120Hz RB */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
466 /* 0x39 - 1680x1050@60Hz RB */
467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
470 /* 0x3a - 1680x1050@60Hz */
471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x3b - 1680x1050@75Hz */
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x3c - 1680x1050@85Hz */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x3d - 1680x1050@120Hz RB */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x3e - 1792x1344@60Hz */
487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3f - 1792x1344@75Hz */
491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x40 - 1792x1344@120Hz RB */
495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
498 /* 0x41 - 1856x1392@60Hz */
499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x42 - 1856x1392@75Hz */
503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 0x43 - 1856x1392@120Hz RB */
507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 /* 0x52 - 1920x1080@60Hz */
511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 /* 0x44 - 1920x1200@60Hz RB */
515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x45 - 1920x1200@60Hz */
519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x46 - 1920x1200@75Hz */
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 0x47 - 1920x1200@85Hz */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 0x48 - 1920x1200@120Hz RB */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
534 /* 0x49 - 1920x1440@60Hz */
535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x4a - 1920x1440@75Hz */
539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 0x4b - 1920x1440@120Hz RB */
543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
546 /* 0x54 - 2048x1152@60Hz */
547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x4c - 2560x1600@60Hz RB */
551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x4d - 2560x1600@60Hz */
555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4e - 2560x1600@75Hz */
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
562 /* 0x4f - 2560x1600@85Hz */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 0x50 - 2560x1600@120Hz RB */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
570 /* 0x57 - 4096x2160@60Hz RB */
571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
574 /* 0x58 - 4096x2160@59.94Hz RB */
575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
578 };
579
580 /*
581 * These more or less come from the DMT spec. The 720x400 modes are
582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
585 * mode.
586 *
587 * The DMT modes have been fact-checked; the rest are mild guesses.
588 */
589 static const struct drm_display_mode edid_est_modes[] = {
590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
591 968, 1056, 0, 600, 601, 605, 628, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
594 896, 1024, 0, 600, 601, 603, 625, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
597 720, 840, 0, 480, 481, 484, 500, 0,
598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
600 704, 832, 0, 480, 489, 492, 520, 0,
601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
603 768, 864, 0, 480, 483, 486, 525, 0,
604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
606 752, 800, 0, 480, 490, 492, 525, 0,
607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
609 846, 900, 0, 400, 421, 423, 449, 0,
610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
612 846, 900, 0, 400, 412, 414, 449, 0,
613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
618 1136, 1312, 0, 768, 769, 772, 800, 0,
619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
621 1184, 1328, 0, 768, 771, 777, 806, 0,
622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
624 1184, 1344, 0, 768, 771, 777, 806, 0,
625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
627 1208, 1264, 0, 768, 768, 776, 817, 0,
628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
630 928, 1152, 0, 624, 625, 628, 667, 0,
631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
633 896, 1056, 0, 600, 601, 604, 625, 0,
634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
636 976, 1040, 0, 600, 637, 643, 666, 0,
637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
639 1344, 1600, 0, 864, 865, 868, 900, 0,
640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
641 };
642
643 struct minimode {
644 short w;
645 short h;
646 short r;
647 short rb;
648 };
649
650 static const struct minimode est3_modes[] = {
651 /* byte 6 */
652 { 640, 350, 85, 0 },
653 { 640, 400, 85, 0 },
654 { 720, 400, 85, 0 },
655 { 640, 480, 85, 0 },
656 { 848, 480, 60, 0 },
657 { 800, 600, 85, 0 },
658 { 1024, 768, 85, 0 },
659 { 1152, 864, 75, 0 },
660 /* byte 7 */
661 { 1280, 768, 60, 1 },
662 { 1280, 768, 60, 0 },
663 { 1280, 768, 75, 0 },
664 { 1280, 768, 85, 0 },
665 { 1280, 960, 60, 0 },
666 { 1280, 960, 85, 0 },
667 { 1280, 1024, 60, 0 },
668 { 1280, 1024, 85, 0 },
669 /* byte 8 */
670 { 1360, 768, 60, 0 },
671 { 1440, 900, 60, 1 },
672 { 1440, 900, 60, 0 },
673 { 1440, 900, 75, 0 },
674 { 1440, 900, 85, 0 },
675 { 1400, 1050, 60, 1 },
676 { 1400, 1050, 60, 0 },
677 { 1400, 1050, 75, 0 },
678 /* byte 9 */
679 { 1400, 1050, 85, 0 },
680 { 1680, 1050, 60, 1 },
681 { 1680, 1050, 60, 0 },
682 { 1680, 1050, 75, 0 },
683 { 1680, 1050, 85, 0 },
684 { 1600, 1200, 60, 0 },
685 { 1600, 1200, 65, 0 },
686 { 1600, 1200, 70, 0 },
687 /* byte 10 */
688 { 1600, 1200, 75, 0 },
689 { 1600, 1200, 85, 0 },
690 { 1792, 1344, 60, 0 },
691 { 1792, 1344, 75, 0 },
692 { 1856, 1392, 60, 0 },
693 { 1856, 1392, 75, 0 },
694 { 1920, 1200, 60, 1 },
695 { 1920, 1200, 60, 0 },
696 /* byte 11 */
697 { 1920, 1200, 75, 0 },
698 { 1920, 1200, 85, 0 },
699 { 1920, 1440, 60, 0 },
700 { 1920, 1440, 75, 0 },
701 };
702
703 static const struct minimode extra_modes[] = {
704 { 1024, 576, 60, 0 },
705 { 1366, 768, 60, 0 },
706 { 1600, 900, 60, 0 },
707 { 1680, 945, 60, 0 },
708 { 1920, 1080, 60, 0 },
709 { 2048, 1152, 60, 0 },
710 { 2048, 1536, 60, 0 },
711 };
712
713 /*
714 * From CEA/CTA-861 spec.
715 *
716 * Do not access directly, instead always use cea_mode_for_vic().
717 */
718 static const struct drm_display_mode edid_cea_modes_1[] = {
719 /* 1 - 640x480@60Hz 4:3 */
720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
721 752, 800, 0, 480, 490, 492, 525, 0,
722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
723 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
724 /* 2 - 720x480@60Hz 4:3 */
725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
726 798, 858, 0, 480, 489, 495, 525, 0,
727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
728 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
729 /* 3 - 720x480@60Hz 16:9 */
730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
731 798, 858, 0, 480, 489, 495, 525, 0,
732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
733 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
734 /* 4 - 1280x720@60Hz 16:9 */
735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
736 1430, 1650, 0, 720, 725, 730, 750, 0,
737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
739 /* 5 - 1920x1080i@60Hz 16:9 */
740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
743 DRM_MODE_FLAG_INTERLACE),
744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
745 /* 6 - 720(1440)x480i@60Hz 4:3 */
746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
747 801, 858, 0, 480, 488, 494, 525, 0,
748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
751 /* 7 - 720(1440)x480i@60Hz 16:9 */
752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
753 801, 858, 0, 480, 488, 494, 525, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
757 /* 8 - 720(1440)x240@60Hz 4:3 */
758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
759 801, 858, 0, 240, 244, 247, 262, 0,
760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
761 DRM_MODE_FLAG_DBLCLK),
762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
763 /* 9 - 720(1440)x240@60Hz 16:9 */
764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
765 801, 858, 0, 240, 244, 247, 262, 0,
766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
767 DRM_MODE_FLAG_DBLCLK),
768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
769 /* 10 - 2880x480i@60Hz 4:3 */
770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
771 3204, 3432, 0, 480, 488, 494, 525, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
773 DRM_MODE_FLAG_INTERLACE),
774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
775 /* 11 - 2880x480i@60Hz 16:9 */
776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
777 3204, 3432, 0, 480, 488, 494, 525, 0,
778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
779 DRM_MODE_FLAG_INTERLACE),
780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
781 /* 12 - 2880x240@60Hz 4:3 */
782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
783 3204, 3432, 0, 240, 244, 247, 262, 0,
784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
786 /* 13 - 2880x240@60Hz 16:9 */
787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
788 3204, 3432, 0, 240, 244, 247, 262, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 14 - 1440x480@60Hz 4:3 */
792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
793 1596, 1716, 0, 480, 489, 495, 525, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
796 /* 15 - 1440x480@60Hz 16:9 */
797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
798 1596, 1716, 0, 480, 489, 495, 525, 0,
799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
801 /* 16 - 1920x1080@60Hz 16:9 */
802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
806 /* 17 - 720x576@50Hz 4:3 */
807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
808 796, 864, 0, 576, 581, 586, 625, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
811 /* 18 - 720x576@50Hz 16:9 */
812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
813 796, 864, 0, 576, 581, 586, 625, 0,
814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
816 /* 19 - 1280x720@50Hz 16:9 */
817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
818 1760, 1980, 0, 720, 725, 730, 750, 0,
819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
821 /* 20 - 1920x1080i@50Hz 16:9 */
822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
825 DRM_MODE_FLAG_INTERLACE),
826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
827 /* 21 - 720(1440)x576i@50Hz 4:3 */
828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
829 795, 864, 0, 576, 580, 586, 625, 0,
830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
833 /* 22 - 720(1440)x576i@50Hz 16:9 */
834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
835 795, 864, 0, 576, 580, 586, 625, 0,
836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
839 /* 23 - 720(1440)x288@50Hz 4:3 */
840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
841 795, 864, 0, 288, 290, 293, 312, 0,
842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
843 DRM_MODE_FLAG_DBLCLK),
844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
845 /* 24 - 720(1440)x288@50Hz 16:9 */
846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
847 795, 864, 0, 288, 290, 293, 312, 0,
848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
849 DRM_MODE_FLAG_DBLCLK),
850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
851 /* 25 - 2880x576i@50Hz 4:3 */
852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
853 3180, 3456, 0, 576, 580, 586, 625, 0,
854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
855 DRM_MODE_FLAG_INTERLACE),
856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
857 /* 26 - 2880x576i@50Hz 16:9 */
858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
859 3180, 3456, 0, 576, 580, 586, 625, 0,
860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
861 DRM_MODE_FLAG_INTERLACE),
862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 27 - 2880x288@50Hz 4:3 */
864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
865 3180, 3456, 0, 288, 290, 293, 312, 0,
866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
868 /* 28 - 2880x288@50Hz 16:9 */
869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
870 3180, 3456, 0, 288, 290, 293, 312, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 29 - 1440x576@50Hz 4:3 */
874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
875 1592, 1728, 0, 576, 581, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
878 /* 30 - 1440x576@50Hz 16:9 */
879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
880 1592, 1728, 0, 576, 581, 586, 625, 0,
881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
883 /* 31 - 1920x1080@50Hz 16:9 */
884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
888 /* 32 - 1920x1080@24Hz 16:9 */
889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
893 /* 33 - 1920x1080@25Hz 16:9 */
894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
898 /* 34 - 1920x1080@30Hz 16:9 */
899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 35 - 2880x480@60Hz 4:3 */
904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
905 3192, 3432, 0, 480, 489, 495, 525, 0,
906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
908 /* 36 - 2880x480@60Hz 16:9 */
909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
910 3192, 3432, 0, 480, 489, 495, 525, 0,
911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 37 - 2880x576@50Hz 4:3 */
914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
915 3184, 3456, 0, 576, 581, 586, 625, 0,
916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
918 /* 38 - 2880x576@50Hz 16:9 */
919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
920 3184, 3456, 0, 576, 581, 586, 625, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
923 /* 39 - 1920x1080i@50Hz 16:9 */
924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
927 DRM_MODE_FLAG_INTERLACE),
928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 40 - 1920x1080i@100Hz 16:9 */
930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
933 DRM_MODE_FLAG_INTERLACE),
934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 41 - 1280x720@100Hz 16:9 */
936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
937 1760, 1980, 0, 720, 725, 730, 750, 0,
938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
940 /* 42 - 720x576@100Hz 4:3 */
941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
942 796, 864, 0, 576, 581, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
945 /* 43 - 720x576@100Hz 16:9 */
946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
947 796, 864, 0, 576, 581, 586, 625, 0,
948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
950 /* 44 - 720(1440)x576i@100Hz 4:3 */
951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
952 795, 864, 0, 576, 580, 586, 625, 0,
953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
956 /* 45 - 720(1440)x576i@100Hz 16:9 */
957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
958 795, 864, 0, 576, 580, 586, 625, 0,
959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
962 /* 46 - 1920x1080i@120Hz 16:9 */
963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
966 DRM_MODE_FLAG_INTERLACE),
967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
968 /* 47 - 1280x720@120Hz 16:9 */
969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
970 1430, 1650, 0, 720, 725, 730, 750, 0,
971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
973 /* 48 - 720x480@120Hz 4:3 */
974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
975 798, 858, 0, 480, 489, 495, 525, 0,
976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
978 /* 49 - 720x480@120Hz 16:9 */
979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
980 798, 858, 0, 480, 489, 495, 525, 0,
981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
983 /* 50 - 720(1440)x480i@120Hz 4:3 */
984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
985 801, 858, 0, 480, 488, 494, 525, 0,
986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
989 /* 51 - 720(1440)x480i@120Hz 16:9 */
990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
991 801, 858, 0, 480, 488, 494, 525, 0,
992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 52 - 720x576@200Hz 4:3 */
996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
997 796, 864, 0, 576, 581, 586, 625, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1000 /* 53 - 720x576@200Hz 16:9 */
1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1002 796, 864, 0, 576, 581, 586, 625, 0,
1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1005 /* 54 - 720(1440)x576i@200Hz 4:3 */
1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1007 795, 864, 0, 576, 580, 586, 625, 0,
1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1011 /* 55 - 720(1440)x576i@200Hz 16:9 */
1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1013 795, 864, 0, 576, 580, 586, 625, 0,
1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 56 - 720x480@240Hz 4:3 */
1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1019 798, 858, 0, 480, 489, 495, 525, 0,
1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1022 /* 57 - 720x480@240Hz 16:9 */
1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1024 798, 858, 0, 480, 489, 495, 525, 0,
1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1027 /* 58 - 720(1440)x480i@240Hz 4:3 */
1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1029 801, 858, 0, 480, 488, 494, 525, 0,
1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1033 /* 59 - 720(1440)x480i@240Hz 16:9 */
1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1035 801, 858, 0, 480, 488, 494, 525, 0,
1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1039 /* 60 - 1280x720@24Hz 16:9 */
1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1041 3080, 3300, 0, 720, 725, 730, 750, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1044 /* 61 - 1280x720@25Hz 16:9 */
1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1046 3740, 3960, 0, 720, 725, 730, 750, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1049 /* 62 - 1280x720@30Hz 16:9 */
1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1051 3080, 3300, 0, 720, 725, 730, 750, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1054 /* 63 - 1920x1080@120Hz 16:9 */
1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1059 /* 64 - 1920x1080@100Hz 16:9 */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1064 /* 65 - 1280x720@24Hz 64:27 */
1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1066 3080, 3300, 0, 720, 725, 730, 750, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 66 - 1280x720@25Hz 64:27 */
1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1071 3740, 3960, 0, 720, 725, 730, 750, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 67 - 1280x720@30Hz 64:27 */
1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1076 3080, 3300, 0, 720, 725, 730, 750, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 68 - 1280x720@50Hz 64:27 */
1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1081 1760, 1980, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 69 - 1280x720@60Hz 64:27 */
1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1086 1430, 1650, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 70 - 1280x720@100Hz 64:27 */
1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1091 1760, 1980, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 71 - 1280x720@120Hz 64:27 */
1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1096 1430, 1650, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 72 - 1920x1080@24Hz 64:27 */
1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 73 - 1920x1080@25Hz 64:27 */
1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 74 - 1920x1080@30Hz 64:27 */
1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 75 - 1920x1080@50Hz 64:27 */
1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 76 - 1920x1080@60Hz 64:27 */
1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 77 - 1920x1080@100Hz 64:27 */
1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 78 - 1920x1080@120Hz 64:27 */
1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 79 - 1680x720@24Hz 64:27 */
1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1136 3080, 3300, 0, 720, 725, 730, 750, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 80 - 1680x720@25Hz 64:27 */
1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1141 2948, 3168, 0, 720, 725, 730, 750, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 81 - 1680x720@30Hz 64:27 */
1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1146 2420, 2640, 0, 720, 725, 730, 750, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 82 - 1680x720@50Hz 64:27 */
1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1151 1980, 2200, 0, 720, 725, 730, 750, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 83 - 1680x720@60Hz 64:27 */
1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1156 1980, 2200, 0, 720, 725, 730, 750, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159 /* 84 - 1680x720@100Hz 64:27 */
1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1161 1780, 2000, 0, 720, 725, 730, 825, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164 /* 85 - 1680x720@120Hz 64:27 */
1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1166 1780, 2000, 0, 720, 725, 730, 825, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1169 /* 86 - 2560x1080@24Hz 64:27 */
1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1174 /* 87 - 2560x1080@25Hz 64:27 */
1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1179 /* 88 - 2560x1080@30Hz 64:27 */
1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1184 /* 89 - 2560x1080@50Hz 64:27 */
1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1189 /* 90 - 2560x1080@60Hz 64:27 */
1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1194 /* 91 - 2560x1080@100Hz 64:27 */
1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1199 /* 92 - 2560x1080@120Hz 64:27 */
1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1204 /* 93 - 3840x2160@24Hz 16:9 */
1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1209 /* 94 - 3840x2160@25Hz 16:9 */
1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1214 /* 95 - 3840x2160@30Hz 16:9 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1219 /* 96 - 3840x2160@50Hz 16:9 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1224 /* 97 - 3840x2160@60Hz 16:9 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1229 /* 98 - 4096x2160@24Hz 256:135 */
1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1234 /* 99 - 4096x2160@25Hz 256:135 */
1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1239 /* 100 - 4096x2160@30Hz 256:135 */
1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1244 /* 101 - 4096x2160@50Hz 256:135 */
1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1249 /* 102 - 4096x2160@60Hz 256:135 */
1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1254 /* 103 - 3840x2160@24Hz 64:27 */
1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1259 /* 104 - 3840x2160@25Hz 64:27 */
1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1264 /* 105 - 3840x2160@30Hz 64:27 */
1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1269 /* 106 - 3840x2160@50Hz 64:27 */
1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1274 /* 107 - 3840x2160@60Hz 64:27 */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1279 /* 108 - 1280x720@48Hz 16:9 */
1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1281 2280, 2500, 0, 720, 725, 730, 750, 0,
1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1284 /* 109 - 1280x720@48Hz 64:27 */
1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1286 2280, 2500, 0, 720, 725, 730, 750, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1289 /* 110 - 1680x720@48Hz 64:27 */
1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1291 2530, 2750, 0, 720, 725, 730, 750, 0,
1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1294 /* 111 - 1920x1080@48Hz 16:9 */
1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1299 /* 112 - 1920x1080@48Hz 64:27 */
1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1304 /* 113 - 2560x1080@48Hz 64:27 */
1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1309 /* 114 - 3840x2160@48Hz 16:9 */
1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1314 /* 115 - 4096x2160@48Hz 256:135 */
1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1319 /* 116 - 3840x2160@48Hz 64:27 */
1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1324 /* 117 - 3840x2160@100Hz 16:9 */
1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1329 /* 118 - 3840x2160@120Hz 16:9 */
1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1334 /* 119 - 3840x2160@100Hz 64:27 */
1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1339 /* 120 - 3840x2160@120Hz 64:27 */
1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1344 /* 121 - 5120x2160@24Hz 64:27 */
1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1349 /* 122 - 5120x2160@25Hz 64:27 */
1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1354 /* 123 - 5120x2160@30Hz 64:27 */
1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1359 /* 124 - 5120x2160@48Hz 64:27 */
1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1364 /* 125 - 5120x2160@50Hz 64:27 */
1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1369 /* 126 - 5120x2160@60Hz 64:27 */
1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1374 /* 127 - 5120x2160@100Hz 64:27 */
1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1379 };
1380
1381 /*
1382 * From CEA/CTA-861 spec.
1383 *
1384 * Do not access directly, instead always use cea_mode_for_vic().
1385 */
1386 static const struct drm_display_mode edid_cea_modes_193[] = {
1387 /* 193 - 5120x2160@120Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1392 /* 194 - 7680x4320@24Hz 16:9 */
1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1397 /* 195 - 7680x4320@25Hz 16:9 */
1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1401 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1402 /* 196 - 7680x4320@30Hz 16:9 */
1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1407 /* 197 - 7680x4320@48Hz 16:9 */
1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1412 /* 198 - 7680x4320@50Hz 16:9 */
1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1417 /* 199 - 7680x4320@60Hz 16:9 */
1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1422 /* 200 - 7680x4320@100Hz 16:9 */
1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1427 /* 201 - 7680x4320@120Hz 16:9 */
1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1432 /* 202 - 7680x4320@24Hz 64:27 */
1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1437 /* 203 - 7680x4320@25Hz 64:27 */
1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1442 /* 204 - 7680x4320@30Hz 64:27 */
1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1447 /* 205 - 7680x4320@48Hz 64:27 */
1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1452 /* 206 - 7680x4320@50Hz 64:27 */
1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1457 /* 207 - 7680x4320@60Hz 64:27 */
1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1462 /* 208 - 7680x4320@100Hz 64:27 */
1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1467 /* 209 - 7680x4320@120Hz 64:27 */
1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1472 /* 210 - 10240x4320@24Hz 64:27 */
1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1477 /* 211 - 10240x4320@25Hz 64:27 */
1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1482 /* 212 - 10240x4320@30Hz 64:27 */
1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1487 /* 213 - 10240x4320@48Hz 64:27 */
1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1492 /* 214 - 10240x4320@50Hz 64:27 */
1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1497 /* 215 - 10240x4320@60Hz 64:27 */
1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1502 /* 216 - 10240x4320@100Hz 64:27 */
1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1507 /* 217 - 10240x4320@120Hz 64:27 */
1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1512 /* 218 - 4096x2160@100Hz 256:135 */
1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1517 /* 219 - 4096x2160@120Hz 256:135 */
1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1522 };
1523
1524 /*
1525 * HDMI 1.4 4k modes. Index using the VIC.
1526 */
1527 static const struct drm_display_mode edid_4k_modes[] = {
1528 /* 0 - dummy, VICs start at 1 */
1529 { },
1530 /* 1 - 3840x2160@30Hz */
1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1532 3840, 4016, 4104, 4400, 0,
1533 2160, 2168, 2178, 2250, 0,
1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1536 /* 2 - 3840x2160@25Hz */
1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1538 3840, 4896, 4984, 5280, 0,
1539 2160, 2168, 2178, 2250, 0,
1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1542 /* 3 - 3840x2160@24Hz */
1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1544 3840, 5116, 5204, 5500, 0,
1545 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1548 /* 4 - 4096x2160@24Hz (SMPTE) */
1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1550 4096, 5116, 5204, 5500, 0,
1551 2160, 2168, 2178, 2250, 0,
1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1554 };
1555
1556 /*** DDC fetch and block validation ***/
1557
1558 static const u8 edid_header[] = {
1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1560 };
1561
1562 /**
1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1564 * @raw_edid: pointer to raw base EDID block
1565 *
1566 * Sanity check the header of the base EDID block.
1567 *
1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1569 */
drm_edid_header_is_valid(const u8 * raw_edid)1570 int drm_edid_header_is_valid(const u8 *raw_edid)
1571 {
1572 int i, score = 0;
1573
1574 for (i = 0; i < sizeof(edid_header); i++)
1575 if (raw_edid[i] == edid_header[i])
1576 score++;
1577
1578 return score;
1579 }
1580 EXPORT_SYMBOL(drm_edid_header_is_valid);
1581
1582 static int edid_fixup __read_mostly = 6;
1583 module_param_named(edid_fixup, edid_fixup, int, 0400);
1584 MODULE_PARM_DESC(edid_fixup,
1585 "Minimum number of valid EDID header bytes (0-8, default 6)");
1586
1587 static int validate_displayid(u8 *displayid, int length, int idx);
1588
drm_edid_block_checksum(const u8 * raw_edid)1589 static int drm_edid_block_checksum(const u8 *raw_edid)
1590 {
1591 int i;
1592 u8 csum = 0, crc = 0;
1593
1594 for (i = 0; i < EDID_LENGTH - 1; i++)
1595 csum += raw_edid[i];
1596
1597 crc = 0x100 - csum;
1598
1599 return crc;
1600 }
1601
drm_edid_block_checksum_diff(const u8 * raw_edid,u8 real_checksum)1602 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1603 {
1604 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1605 return true;
1606 else
1607 return false;
1608 }
1609
drm_edid_is_zero(const u8 * in_edid,int length)1610 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1611 {
1612 if (memchr_inv(in_edid, 0, length))
1613 return false;
1614
1615 return true;
1616 }
1617
1618 /**
1619 * drm_edid_are_equal - compare two edid blobs.
1620 * @edid1: pointer to first blob
1621 * @edid2: pointer to second blob
1622 * This helper can be used during probing to determine if
1623 * edid had changed.
1624 */
drm_edid_are_equal(const struct edid * edid1,const struct edid * edid2)1625 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1626 {
1627 int edid1_len, edid2_len;
1628 bool edid1_present = edid1 != NULL;
1629 bool edid2_present = edid2 != NULL;
1630
1631 if (edid1_present != edid2_present)
1632 return false;
1633
1634 if (edid1) {
1635 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1636 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1637
1638 if (edid1_len != edid2_len)
1639 return false;
1640
1641 if (memcmp(edid1, edid2, edid1_len))
1642 return false;
1643 }
1644
1645 return true;
1646 }
1647 EXPORT_SYMBOL(drm_edid_are_equal);
1648
1649 /**
1650 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1651 * @raw_edid: pointer to raw EDID block
1652 * @block: type of block to validate (0 for base, extension otherwise)
1653 * @print_bad_edid: if true, dump bad EDID blocks to the console
1654 * @edid_corrupt: if true, the header or checksum is invalid
1655 *
1656 * Validate a base or extension EDID block and optionally dump bad blocks to
1657 * the console.
1658 *
1659 * Return: True if the block is valid, false otherwise.
1660 */
drm_edid_block_valid(u8 * raw_edid,int block,bool print_bad_edid,bool * edid_corrupt)1661 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1662 bool *edid_corrupt)
1663 {
1664 u8 csum;
1665 struct edid *edid = (struct edid *)raw_edid;
1666
1667 if (WARN_ON(!raw_edid))
1668 return false;
1669
1670 if (edid_fixup > 8 || edid_fixup < 0)
1671 edid_fixup = 6;
1672
1673 if (block == 0) {
1674 int score = drm_edid_header_is_valid(raw_edid);
1675
1676 if (score == 8) {
1677 if (edid_corrupt)
1678 *edid_corrupt = false;
1679 } else if (score >= edid_fixup) {
1680 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1681 * The corrupt flag needs to be set here otherwise, the
1682 * fix-up code here will correct the problem, the
1683 * checksum is correct and the test fails
1684 */
1685 if (edid_corrupt)
1686 *edid_corrupt = true;
1687 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1688 memcpy(raw_edid, edid_header, sizeof(edid_header));
1689 } else {
1690 if (edid_corrupt)
1691 *edid_corrupt = true;
1692 goto bad;
1693 }
1694 }
1695
1696 csum = drm_edid_block_checksum(raw_edid);
1697 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
1698 if (edid_corrupt)
1699 *edid_corrupt = true;
1700
1701 /* allow CEA to slide through, switches mangle this */
1702 if (raw_edid[0] == CEA_EXT) {
1703 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1704 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1705 } else {
1706 if (print_bad_edid)
1707 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1708
1709 goto bad;
1710 }
1711 }
1712
1713 /* per-block-type checks */
1714 switch (raw_edid[0]) {
1715 case 0: /* base */
1716 if (edid->version != 1) {
1717 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1718 goto bad;
1719 }
1720
1721 if (edid->revision > 4)
1722 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1723 break;
1724
1725 default:
1726 break;
1727 }
1728
1729 return true;
1730
1731 bad:
1732 if (print_bad_edid) {
1733 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1734 pr_notice("EDID block is all zeroes\n");
1735 } else {
1736 pr_notice("Raw EDID:\n");
1737 print_hex_dump(KERN_NOTICE,
1738 " \t", DUMP_PREFIX_NONE, 16, 1,
1739 raw_edid, EDID_LENGTH, false);
1740 }
1741 }
1742 return false;
1743 }
1744 EXPORT_SYMBOL(drm_edid_block_valid);
1745
1746 /**
1747 * drm_edid_is_valid - sanity check EDID data
1748 * @edid: EDID data
1749 *
1750 * Sanity-check an entire EDID record (including extensions)
1751 *
1752 * Return: True if the EDID data is valid, false otherwise.
1753 */
drm_edid_is_valid(struct edid * edid)1754 bool drm_edid_is_valid(struct edid *edid)
1755 {
1756 int i;
1757 u8 *raw = (u8 *)edid;
1758
1759 if (!edid)
1760 return false;
1761
1762 for (i = 0; i <= edid->extensions; i++)
1763 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1764 return false;
1765
1766 return true;
1767 }
1768 EXPORT_SYMBOL(drm_edid_is_valid);
1769
1770 #define DDC_SEGMENT_ADDR 0x30
1771 /**
1772 * drm_do_probe_ddc_edid() - get EDID information via I2C
1773 * @data: I2C device adapter
1774 * @buf: EDID data buffer to be filled
1775 * @block: 128 byte EDID block to start fetching from
1776 * @len: EDID data buffer length to fetch
1777 *
1778 * Try to fetch EDID information by calling I2C driver functions.
1779 *
1780 * Return: 0 on success or -1 on failure.
1781 */
1782 static int
drm_do_probe_ddc_edid(void * data,u8 * buf,unsigned int block,size_t len)1783 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1784 {
1785 struct i2c_adapter *adapter = data;
1786 unsigned char start = block * EDID_LENGTH;
1787 unsigned char segment = block >> 1;
1788 unsigned char xfers = segment ? 3 : 2;
1789 int ret, retries = 5;
1790
1791 /*
1792 * The core I2C driver will automatically retry the transfer if the
1793 * adapter reports EAGAIN. However, we find that bit-banging transfers
1794 * are susceptible to errors under a heavily loaded machine and
1795 * generate spurious NAKs and timeouts. Retrying the transfer
1796 * of the individual block a few times seems to overcome this.
1797 */
1798 do {
1799 struct i2c_msg msgs[] = {
1800 {
1801 .addr = DDC_SEGMENT_ADDR,
1802 .flags = 0,
1803 .len = 1,
1804 .buf = &segment,
1805 }, {
1806 .addr = DDC_ADDR,
1807 .flags = 0,
1808 .len = 1,
1809 .buf = &start,
1810 }, {
1811 .addr = DDC_ADDR,
1812 .flags = I2C_M_RD,
1813 .len = len,
1814 .buf = buf,
1815 }
1816 };
1817
1818 /*
1819 * Avoid sending the segment addr to not upset non-compliant
1820 * DDC monitors.
1821 */
1822 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1823
1824 if (ret == -ENXIO) {
1825 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1826 adapter->name);
1827 break;
1828 }
1829 } while (ret != xfers && --retries);
1830
1831 return ret == xfers ? 0 : -1;
1832 }
1833
connector_bad_edid(struct drm_connector * connector,u8 * edid,int num_blocks)1834 static void connector_bad_edid(struct drm_connector *connector,
1835 u8 *edid, int num_blocks)
1836 {
1837 int i;
1838 u8 last_block;
1839
1840 /*
1841 * 0x7e in the EDID is the number of extension blocks. The EDID
1842 * is 1 (base block) + num_ext_blocks big. That means we can think
1843 * of 0x7e in the EDID of the _index_ of the last block in the
1844 * combined chunk of memory.
1845 */
1846 last_block = edid[0x7e];
1847
1848 /* Calculate real checksum for the last edid extension block data */
1849 if (last_block < num_blocks)
1850 connector->real_edid_checksum =
1851 drm_edid_block_checksum(edid + last_block * EDID_LENGTH);
1852
1853 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1854 return;
1855
1856 drm_warn(connector->dev, "%s: EDID is invalid:\n", connector->name);
1857 for (i = 0; i < num_blocks; i++) {
1858 u8 *block = edid + i * EDID_LENGTH;
1859 char prefix[20];
1860
1861 if (drm_edid_is_zero(block, EDID_LENGTH))
1862 sprintf(prefix, "\t[%02x] ZERO ", i);
1863 else if (!drm_edid_block_valid(block, i, false, NULL))
1864 sprintf(prefix, "\t[%02x] BAD ", i);
1865 else
1866 sprintf(prefix, "\t[%02x] GOOD ", i);
1867
1868 print_hex_dump(KERN_WARNING,
1869 prefix, DUMP_PREFIX_NONE, 16, 1,
1870 block, EDID_LENGTH, false);
1871 }
1872 }
1873
1874 /* Get override or firmware EDID */
drm_get_override_edid(struct drm_connector * connector)1875 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1876 {
1877 struct edid *override = NULL;
1878
1879 if (connector->override_edid)
1880 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1881
1882 if (!override)
1883 override = drm_load_edid_firmware(connector);
1884
1885 return IS_ERR(override) ? NULL : override;
1886 }
1887
1888 /**
1889 * drm_add_override_edid_modes - add modes from override/firmware EDID
1890 * @connector: connector we're probing
1891 *
1892 * Add modes from the override/firmware EDID, if available. Only to be used from
1893 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1894 * failed during drm_get_edid() and caused the override/firmware EDID to be
1895 * skipped.
1896 *
1897 * Return: The number of modes added or 0 if we couldn't find any.
1898 */
drm_add_override_edid_modes(struct drm_connector * connector)1899 int drm_add_override_edid_modes(struct drm_connector *connector)
1900 {
1901 struct edid *override;
1902 int num_modes = 0;
1903
1904 override = drm_get_override_edid(connector);
1905 if (override) {
1906 drm_connector_update_edid_property(connector, override);
1907 num_modes = drm_add_edid_modes(connector, override);
1908 kfree(override);
1909
1910 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1911 connector->base.id, connector->name, num_modes);
1912 }
1913
1914 return num_modes;
1915 }
1916 EXPORT_SYMBOL(drm_add_override_edid_modes);
1917
1918 #ifdef CONFIG_NO_GKI
1919 /*
1920 * References:
1921 * - CTA-861-H section 7.3.3 CTA Extension Version 3
1922 */
cea_db_collection_size(const u8 * cta)1923 static int cea_db_collection_size(const u8 *cta)
1924 {
1925 u8 d = cta[2];
1926
1927 if (d < 4 || d > 127)
1928 return 0;
1929
1930 return d - 4;
1931 }
1932
1933 #define CTA_EXT_DB_HF_EEODB 0x78
1934 #define CTA_DB_EXTENDED_TAG 7
1935
1936 static int cea_db_tag(const u8 *db);
1937 static int cea_db_payload_len(const u8 *db);
1938 static int cea_db_extended_tag(const u8 *db);
1939
cea_db_is_extended_tag(const void * db,int tag)1940 static bool cea_db_is_extended_tag(const void *db, int tag)
1941 {
1942 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
1943 cea_db_payload_len(db) >= 1 &&
1944 cea_db_extended_tag(db) == tag;
1945 }
1946
cea_db_is_hdmi_forum_eeodb(const void * db)1947 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
1948 {
1949 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
1950 cea_db_payload_len(db) >= 2;
1951 }
1952
edid_hfeeodb_extension_block_count(const struct edid * edid)1953 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
1954 {
1955 const u8 *cta;
1956
1957 /* No extensions according to base block, no HF-EEODB. */
1958 if (!edid->extensions)
1959 return 0;
1960
1961 /* HF-EEODB is always in the first EDID extension block only */
1962 cta = (u8 *)edid + EDID_LENGTH * 1;
1963 if (cta[0] != CEA_EXT || cta[1] < 3)
1964 return 0;
1965
1966 /* Need to have the data block collection, and at least 3 bytes. */
1967 if (cea_db_collection_size(cta) < 3)
1968 return 0;
1969
1970 /*
1971 * Sinks that include the HF-EEODB in their E-EDID shall include one and
1972 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
1973 * through 6 of Block 1 of the E-EDID.
1974 */
1975 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
1976 return 0;
1977
1978 return cta[4 + 2];
1979 }
1980
edid_hfeeodb_block_count(const struct edid * edid)1981 static int edid_hfeeodb_block_count(const struct edid *edid)
1982 {
1983 int eeodb = edid_hfeeodb_extension_block_count(edid);
1984
1985 return eeodb ? eeodb + 1 : 0;
1986 }
1987
1988 /**
1989 * drm_do_get_edid - get EDID data using a custom EDID block read function
1990 * @connector: connector we're probing
1991 * @get_edid_block: EDID block read function
1992 * @data: private data passed to the block read function
1993 *
1994 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1995 * exposes a different interface to read EDID blocks this function can be used
1996 * to get EDID data using a custom block read function.
1997 *
1998 * As in the general case the DDC bus is accessible by the kernel at the I2C
1999 * level, drivers must make all reasonable efforts to expose it as an I2C
2000 * adapter and use drm_get_edid() instead of abusing this function.
2001 *
2002 * The EDID may be overridden using debugfs override_edid or firmare EDID
2003 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2004 * order. Having either of them bypasses actual EDID reads.
2005 *
2006 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2007 */
drm_do_get_edid(struct drm_connector * connector,int (* get_edid_block)(void * data,u8 * buf,unsigned int block,size_t len),void * data)2008 struct edid *drm_do_get_edid(struct drm_connector *connector,
2009 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
2010 size_t len),
2011 void *data)
2012 {
2013 int i, j = 0, valid_extensions = 0, num_blocks, invalid_blocks = 0;
2014 u8 *edid, *new;
2015 struct edid *override;
2016
2017 override = drm_get_override_edid(connector);
2018 if (override)
2019 return override;
2020
2021 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
2022 if (!edid)
2023 return NULL;
2024
2025 /* base block fetch */
2026 for (i = 0; i < 4; i++) {
2027 if (get_edid_block(data, edid, 0, EDID_LENGTH))
2028 goto out;
2029 if (drm_edid_block_valid(edid, 0, false,
2030 &connector->edid_corrupt))
2031 break;
2032 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
2033 connector->null_edid_counter++;
2034 goto out;
2035 }
2036 }
2037 if (i == 4)
2038 goto out;
2039
2040 /* if there's no extensions, we're done */
2041 valid_extensions = edid[0x7e];
2042 if (valid_extensions == 0)
2043 return (struct edid *)edid;
2044
2045 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2046 if (!new)
2047 goto out;
2048 edid = new;
2049
2050 num_blocks = edid[0x7e] + 1;
2051
2052 for (j = 1; j < num_blocks; j++) {
2053 u8 *block = edid + j * EDID_LENGTH;
2054
2055 for (i = 0; i < 4; i++) {
2056 if (get_edid_block(data, block, j, EDID_LENGTH))
2057 goto out;
2058 if (drm_edid_block_valid(block, j, false, NULL))
2059 break;
2060 }
2061
2062 if (i == 4)
2063 invalid_blocks++;
2064
2065 if (j == 1) {
2066 /*
2067 * If the first EDID extension is a CTA extension, and
2068 * the first Data Block is HF-EEODB, override the
2069 * extension block count.
2070 *
2071 * Note: HF-EEODB could specify a smaller extension
2072 * count too, but we can't risk allocating a smaller
2073 * amount.
2074 */
2075 int eeodb = edid_hfeeodb_block_count((const struct edid *)edid);
2076
2077 if (eeodb > num_blocks) {
2078 num_blocks = eeodb;
2079 new = krealloc(edid, num_blocks * EDID_LENGTH, GFP_KERNEL);
2080 if (!new)
2081 goto out;
2082 edid = new;
2083 }
2084 }
2085 }
2086
2087 if (invalid_blocks) {
2088 u8 *base;
2089
2090 connector_bad_edid(connector, edid, edid[0x7e] + 1);
2091
2092 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
2093 GFP_KERNEL);
2094 if (!new)
2095 goto out;
2096
2097 base = new;
2098 for (i = 0; i <= edid[0x7e]; i++) {
2099 u8 *block = edid + i * EDID_LENGTH;
2100
2101 if (!drm_edid_block_valid(block, i, false, NULL))
2102 continue;
2103
2104 memcpy(base, block, EDID_LENGTH);
2105 base += EDID_LENGTH;
2106 }
2107
2108 new[EDID_LENGTH - 1] += new[0x7e] - valid_extensions;
2109 new[0x7e] = valid_extensions;
2110
2111 kfree(edid);
2112 edid = new;
2113 }
2114
2115 return (struct edid *)edid;
2116
2117 out:
2118 kfree(edid);
2119 return NULL;
2120 }
2121 #else
drm_do_get_edid(struct drm_connector * connector,int (* get_edid_block)(void * data,u8 * buf,unsigned int block,size_t len),void * data)2122 struct edid *drm_do_get_edid(struct drm_connector *connector,
2123 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
2124 size_t len),
2125 void *data)
2126 {
2127 int i, j = 0, valid_extensions = 0;
2128 u8 *edid, *new;
2129 struct edid *override;
2130
2131 override = drm_get_override_edid(connector);
2132 if (override)
2133 return override;
2134
2135 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
2136 return NULL;
2137
2138 /* base block fetch */
2139 for (i = 0; i < 4; i++) {
2140 if (get_edid_block(data, edid, 0, EDID_LENGTH))
2141 goto out;
2142 if (drm_edid_block_valid(edid, 0, false,
2143 &connector->edid_corrupt))
2144 break;
2145 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
2146 connector->null_edid_counter++;
2147 goto carp;
2148 }
2149 }
2150 if (i == 4)
2151 goto carp;
2152
2153 /* if there's no extensions, we're done */
2154 valid_extensions = edid[0x7e];
2155 if (valid_extensions == 0)
2156 return (struct edid *)edid;
2157
2158 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2159 if (!new)
2160 goto out;
2161 edid = new;
2162
2163 for (j = 1; j <= edid[0x7e]; j++) {
2164 u8 *block = edid + j * EDID_LENGTH;
2165
2166 for (i = 0; i < 4; i++) {
2167 if (get_edid_block(data, block, j, EDID_LENGTH))
2168 goto out;
2169 if (drm_edid_block_valid(block, j, false, NULL))
2170 break;
2171 }
2172
2173 if (i == 4)
2174 valid_extensions--;
2175 }
2176
2177 if (valid_extensions != edid[0x7e]) {
2178 u8 *base;
2179
2180 connector_bad_edid(connector, edid, edid[0x7e] + 1);
2181
2182 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
2183 GFP_KERNEL);
2184 if (!new)
2185 goto out;
2186
2187 base = new;
2188 for (i = 0; i <= edid[0x7e]; i++) {
2189 u8 *block = edid + i * EDID_LENGTH;
2190
2191 if (!drm_edid_block_valid(block, i, false, NULL))
2192 continue;
2193
2194 memcpy(base, block, EDID_LENGTH);
2195 base += EDID_LENGTH;
2196 }
2197
2198 new[EDID_LENGTH - 1] += new[0x7e] - valid_extensions;
2199 new[0x7e] = valid_extensions;
2200
2201 kfree(edid);
2202 edid = new;
2203 }
2204
2205 return (struct edid *)edid;
2206
2207 carp:
2208 connector_bad_edid(connector, edid, 1);
2209 out:
2210 kfree(edid);
2211 return NULL;
2212 }
2213 #endif
2214 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2215
2216 /**
2217 * drm_probe_ddc() - probe DDC presence
2218 * @adapter: I2C adapter to probe
2219 *
2220 * Return: True on success, false on failure.
2221 */
2222 bool
drm_probe_ddc(struct i2c_adapter * adapter)2223 drm_probe_ddc(struct i2c_adapter *adapter)
2224 {
2225 unsigned char out;
2226
2227 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2228 }
2229 EXPORT_SYMBOL(drm_probe_ddc);
2230
2231 /**
2232 * drm_get_edid - get EDID data, if available
2233 * @connector: connector we're probing
2234 * @adapter: I2C adapter to use for DDC
2235 *
2236 * Poke the given I2C channel to grab EDID data if possible. If found,
2237 * attach it to the connector.
2238 *
2239 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2240 */
drm_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)2241 struct edid *drm_get_edid(struct drm_connector *connector,
2242 struct i2c_adapter *adapter)
2243 {
2244 struct edid *edid;
2245
2246 if (connector->force == DRM_FORCE_OFF)
2247 return NULL;
2248
2249 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2250 return NULL;
2251
2252 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2253 drm_connector_update_edid_property(connector, edid);
2254 return edid;
2255 }
2256 EXPORT_SYMBOL(drm_get_edid);
2257
2258 /**
2259 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2260 * @connector: connector we're probing
2261 * @adapter: I2C adapter to use for DDC
2262 *
2263 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2264 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2265 * switch DDC to the GPU which is retrieving EDID.
2266 *
2267 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2268 */
drm_get_edid_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2269 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2270 struct i2c_adapter *adapter)
2271 {
2272 struct pci_dev *pdev = connector->dev->pdev;
2273 struct edid *edid;
2274
2275 vga_switcheroo_lock_ddc(pdev);
2276 edid = drm_get_edid(connector, adapter);
2277 vga_switcheroo_unlock_ddc(pdev);
2278
2279 return edid;
2280 }
2281 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2282
2283 /**
2284 * drm_edid_duplicate - duplicate an EDID and the extensions
2285 * @edid: EDID to duplicate
2286 *
2287 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2288 */
drm_edid_duplicate(const struct edid * edid)2289 struct edid *drm_edid_duplicate(const struct edid *edid)
2290 {
2291 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2292 }
2293 EXPORT_SYMBOL(drm_edid_duplicate);
2294
2295 /*** EDID parsing ***/
2296
2297 /**
2298 * edid_vendor - match a string against EDID's obfuscated vendor field
2299 * @edid: EDID to match
2300 * @vendor: vendor string
2301 *
2302 * Returns true if @vendor is in @edid, false otherwise
2303 */
edid_vendor(const struct edid * edid,const char * vendor)2304 static bool edid_vendor(const struct edid *edid, const char *vendor)
2305 {
2306 char edid_vendor[3];
2307
2308 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2309 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2310 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
2311 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
2312
2313 return !strncmp(edid_vendor, vendor, 3);
2314 }
2315
2316 /**
2317 * edid_get_quirks - return quirk flags for a given EDID
2318 * @edid: EDID to process
2319 *
2320 * This tells subsequent routines what fixes they need to apply.
2321 */
edid_get_quirks(const struct edid * edid)2322 static u32 edid_get_quirks(const struct edid *edid)
2323 {
2324 const struct edid_quirk *quirk;
2325 int i;
2326
2327 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2328 quirk = &edid_quirk_list[i];
2329
2330 if (edid_vendor(edid, quirk->vendor) &&
2331 (EDID_PRODUCT_ID(edid) == quirk->product_id))
2332 return quirk->quirks;
2333 }
2334
2335 return 0;
2336 }
2337
2338 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2339 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2340
2341 /**
2342 * edid_fixup_preferred - set preferred modes based on quirk list
2343 * @connector: has mode list to fix up
2344 * @quirks: quirks list
2345 *
2346 * Walk the mode list for @connector, clearing the preferred status
2347 * on existing modes and setting it anew for the right mode ala @quirks.
2348 */
edid_fixup_preferred(struct drm_connector * connector,u32 quirks)2349 static void edid_fixup_preferred(struct drm_connector *connector,
2350 u32 quirks)
2351 {
2352 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2353 int target_refresh = 0;
2354 int cur_vrefresh, preferred_vrefresh;
2355
2356 if (list_empty(&connector->probed_modes))
2357 return;
2358
2359 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2360 target_refresh = 60;
2361 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2362 target_refresh = 75;
2363
2364 preferred_mode = list_first_entry(&connector->probed_modes,
2365 struct drm_display_mode, head);
2366
2367 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2368 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2369
2370 if (cur_mode == preferred_mode)
2371 continue;
2372
2373 /* Largest mode is preferred */
2374 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2375 preferred_mode = cur_mode;
2376
2377 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2378 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2379 /* At a given size, try to get closest to target refresh */
2380 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2381 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2382 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2383 preferred_mode = cur_mode;
2384 }
2385 }
2386
2387 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2388 }
2389
2390 static bool
mode_is_rb(const struct drm_display_mode * mode)2391 mode_is_rb(const struct drm_display_mode *mode)
2392 {
2393 return (mode->htotal - mode->hdisplay == 160) &&
2394 (mode->hsync_end - mode->hdisplay == 80) &&
2395 (mode->hsync_end - mode->hsync_start == 32) &&
2396 (mode->vsync_start - mode->vdisplay == 3);
2397 }
2398
2399 /*
2400 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2401 * @dev: Device to duplicate against
2402 * @hsize: Mode width
2403 * @vsize: Mode height
2404 * @fresh: Mode refresh rate
2405 * @rb: Mode reduced-blanking-ness
2406 *
2407 * Walk the DMT mode list looking for a match for the given parameters.
2408 *
2409 * Return: A newly allocated copy of the mode, or NULL if not found.
2410 */
drm_mode_find_dmt(struct drm_device * dev,int hsize,int vsize,int fresh,bool rb)2411 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2412 int hsize, int vsize, int fresh,
2413 bool rb)
2414 {
2415 int i;
2416
2417 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2418 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2419
2420 if (hsize != ptr->hdisplay)
2421 continue;
2422 if (vsize != ptr->vdisplay)
2423 continue;
2424 if (fresh != drm_mode_vrefresh(ptr))
2425 continue;
2426 if (rb != mode_is_rb(ptr))
2427 continue;
2428
2429 return drm_mode_duplicate(dev, ptr);
2430 }
2431
2432 return NULL;
2433 }
2434 EXPORT_SYMBOL(drm_mode_find_dmt);
2435
is_display_descriptor(const u8 d[18],u8 tag)2436 static bool is_display_descriptor(const u8 d[18], u8 tag)
2437 {
2438 return d[0] == 0x00 && d[1] == 0x00 &&
2439 d[2] == 0x00 && d[3] == tag;
2440 }
2441
is_detailed_timing_descriptor(const u8 d[18])2442 static bool is_detailed_timing_descriptor(const u8 d[18])
2443 {
2444 return d[0] != 0x00 || d[1] != 0x00;
2445 }
2446
2447 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2448
2449 static void
cea_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)2450 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2451 {
2452 int i, n;
2453 u8 d = ext[0x02];
2454 u8 *det_base = ext + d;
2455
2456 if (d < 4 || d > 127)
2457 return;
2458
2459 n = (127 - d) / 18;
2460 for (i = 0; i < n; i++)
2461 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2462 }
2463
2464 static void
vtb_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)2465 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2466 {
2467 unsigned int i, n = min((int)ext[0x02], 6);
2468 u8 *det_base = ext + 5;
2469
2470 if (ext[0x01] != 1)
2471 return; /* unknown version */
2472
2473 for (i = 0; i < n; i++)
2474 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2475 }
2476
2477 static void
drm_for_each_detailed_block(u8 * raw_edid,detailed_cb * cb,void * closure)2478 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2479 {
2480 int i;
2481 struct edid *edid = (struct edid *)raw_edid;
2482
2483 if (edid == NULL)
2484 return;
2485
2486 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2487 cb(&(edid->detailed_timings[i]), closure);
2488
2489 for (i = 1; i <= raw_edid[0x7e]; i++) {
2490 u8 *ext = raw_edid + (i * EDID_LENGTH);
2491
2492 switch (*ext) {
2493 case CEA_EXT:
2494 cea_for_each_detailed_block(ext, cb, closure);
2495 break;
2496 case VTB_EXT:
2497 vtb_for_each_detailed_block(ext, cb, closure);
2498 break;
2499 default:
2500 break;
2501 }
2502 }
2503 }
2504
2505 static void
is_rb(struct detailed_timing * t,void * data)2506 is_rb(struct detailed_timing *t, void *data)
2507 {
2508 u8 *r = (u8 *)t;
2509
2510 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2511 return;
2512
2513 if (r[15] & 0x10)
2514 *(bool *)data = true;
2515 }
2516
2517 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2518 static bool
drm_monitor_supports_rb(struct edid * edid)2519 drm_monitor_supports_rb(struct edid *edid)
2520 {
2521 if (edid->revision >= 4) {
2522 bool ret = false;
2523
2524 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2525 return ret;
2526 }
2527
2528 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2529 }
2530
2531 static void
find_gtf2(struct detailed_timing * t,void * data)2532 find_gtf2(struct detailed_timing *t, void *data)
2533 {
2534 u8 *r = (u8 *)t;
2535
2536 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2537 return;
2538
2539 if (r[10] == 0x02)
2540 *(u8 **)data = r;
2541 }
2542
2543 /* Secondary GTF curve kicks in above some break frequency */
2544 static int
drm_gtf2_hbreak(struct edid * edid)2545 drm_gtf2_hbreak(struct edid *edid)
2546 {
2547 u8 *r = NULL;
2548
2549 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2550 return r ? (r[12] * 2) : 0;
2551 }
2552
2553 static int
drm_gtf2_2c(struct edid * edid)2554 drm_gtf2_2c(struct edid *edid)
2555 {
2556 u8 *r = NULL;
2557
2558 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2559 return r ? r[13] : 0;
2560 }
2561
2562 static int
drm_gtf2_m(struct edid * edid)2563 drm_gtf2_m(struct edid *edid)
2564 {
2565 u8 *r = NULL;
2566
2567 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2568 return r ? (r[15] << 8) + r[14] : 0;
2569 }
2570
2571 static int
drm_gtf2_k(struct edid * edid)2572 drm_gtf2_k(struct edid *edid)
2573 {
2574 u8 *r = NULL;
2575
2576 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2577 return r ? r[16] : 0;
2578 }
2579
2580 static int
drm_gtf2_2j(struct edid * edid)2581 drm_gtf2_2j(struct edid *edid)
2582 {
2583 u8 *r = NULL;
2584
2585 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2586 return r ? r[17] : 0;
2587 }
2588
2589 /**
2590 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2591 * @edid: EDID block to scan
2592 */
standard_timing_level(struct edid * edid)2593 static int standard_timing_level(struct edid *edid)
2594 {
2595 if (edid->revision >= 2) {
2596 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2597 return LEVEL_CVT;
2598 if (drm_gtf2_hbreak(edid))
2599 return LEVEL_GTF2;
2600 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2601 return LEVEL_GTF;
2602 }
2603 return LEVEL_DMT;
2604 }
2605
2606 /*
2607 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2608 * monitors fill with ascii space (0x20) instead.
2609 */
2610 static int
bad_std_timing(u8 a,u8 b)2611 bad_std_timing(u8 a, u8 b)
2612 {
2613 return (a == 0x00 && b == 0x00) ||
2614 (a == 0x01 && b == 0x01) ||
2615 (a == 0x20 && b == 0x20);
2616 }
2617
drm_mode_hsync(const struct drm_display_mode * mode)2618 static int drm_mode_hsync(const struct drm_display_mode *mode)
2619 {
2620 if (mode->htotal <= 0)
2621 return 0;
2622
2623 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2624 }
2625
2626 /**
2627 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2628 * @connector: connector of for the EDID block
2629 * @edid: EDID block to scan
2630 * @t: standard timing params
2631 *
2632 * Take the standard timing params (in this case width, aspect, and refresh)
2633 * and convert them into a real mode using CVT/GTF/DMT.
2634 */
2635 static struct drm_display_mode *
drm_mode_std(struct drm_connector * connector,struct edid * edid,struct std_timing * t)2636 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2637 struct std_timing *t)
2638 {
2639 struct drm_device *dev = connector->dev;
2640 struct drm_display_mode *m, *mode = NULL;
2641 int hsize, vsize;
2642 int vrefresh_rate;
2643 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2644 >> EDID_TIMING_ASPECT_SHIFT;
2645 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2646 >> EDID_TIMING_VFREQ_SHIFT;
2647 int timing_level = standard_timing_level(edid);
2648
2649 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2650 return NULL;
2651
2652 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2653 hsize = t->hsize * 8 + 248;
2654 /* vrefresh_rate = vfreq + 60 */
2655 vrefresh_rate = vfreq + 60;
2656 /* the vdisplay is calculated based on the aspect ratio */
2657 if (aspect_ratio == 0) {
2658 if (edid->revision < 3)
2659 vsize = hsize;
2660 else
2661 vsize = (hsize * 10) / 16;
2662 } else if (aspect_ratio == 1)
2663 vsize = (hsize * 3) / 4;
2664 else if (aspect_ratio == 2)
2665 vsize = (hsize * 4) / 5;
2666 else
2667 vsize = (hsize * 9) / 16;
2668
2669 /* HDTV hack, part 1 */
2670 if (vrefresh_rate == 60 &&
2671 ((hsize == 1360 && vsize == 765) ||
2672 (hsize == 1368 && vsize == 769))) {
2673 hsize = 1366;
2674 vsize = 768;
2675 }
2676
2677 /*
2678 * If this connector already has a mode for this size and refresh
2679 * rate (because it came from detailed or CVT info), use that
2680 * instead. This way we don't have to guess at interlace or
2681 * reduced blanking.
2682 */
2683 list_for_each_entry(m, &connector->probed_modes, head)
2684 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2685 drm_mode_vrefresh(m) == vrefresh_rate)
2686 return NULL;
2687
2688 /* HDTV hack, part 2 */
2689 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2690 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2691 false);
2692 if (!mode)
2693 return NULL;
2694 mode->hdisplay = 1366;
2695 mode->hsync_start = mode->hsync_start - 1;
2696 mode->hsync_end = mode->hsync_end - 1;
2697 return mode;
2698 }
2699
2700 /* check whether it can be found in default mode table */
2701 if (drm_monitor_supports_rb(edid)) {
2702 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2703 true);
2704 if (mode)
2705 return mode;
2706 }
2707 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2708 if (mode)
2709 return mode;
2710
2711 /* okay, generate it */
2712 switch (timing_level) {
2713 case LEVEL_DMT:
2714 break;
2715 case LEVEL_GTF:
2716 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2717 break;
2718 case LEVEL_GTF2:
2719 /*
2720 * This is potentially wrong if there's ever a monitor with
2721 * more than one ranges section, each claiming a different
2722 * secondary GTF curve. Please don't do that.
2723 */
2724 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2725 if (!mode)
2726 return NULL;
2727 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2728 drm_mode_destroy(dev, mode);
2729 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2730 vrefresh_rate, 0, 0,
2731 drm_gtf2_m(edid),
2732 drm_gtf2_2c(edid),
2733 drm_gtf2_k(edid),
2734 drm_gtf2_2j(edid));
2735 }
2736 break;
2737 case LEVEL_CVT:
2738 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2739 false);
2740 break;
2741 }
2742 return mode;
2743 }
2744
2745 /*
2746 * EDID is delightfully ambiguous about how interlaced modes are to be
2747 * encoded. Our internal representation is of frame height, but some
2748 * HDTV detailed timings are encoded as field height.
2749 *
2750 * The format list here is from CEA, in frame size. Technically we
2751 * should be checking refresh rate too. Whatever.
2752 */
2753 static void
drm_mode_do_interlace_quirk(struct drm_display_mode * mode,struct detailed_pixel_timing * pt)2754 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2755 struct detailed_pixel_timing *pt)
2756 {
2757 int i;
2758 static const struct {
2759 int w, h;
2760 } cea_interlaced[] = {
2761 { 1920, 1080 },
2762 { 720, 480 },
2763 { 1440, 480 },
2764 { 2880, 480 },
2765 { 720, 576 },
2766 { 1440, 576 },
2767 { 2880, 576 },
2768 };
2769
2770 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2771 return;
2772
2773 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2774 if ((mode->hdisplay == cea_interlaced[i].w) &&
2775 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2776 mode->vdisplay *= 2;
2777 mode->vsync_start *= 2;
2778 mode->vsync_end *= 2;
2779 mode->vtotal *= 2;
2780 mode->vtotal |= 1;
2781 }
2782 }
2783
2784 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2785 }
2786
2787 /**
2788 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2789 * @dev: DRM device (needed to create new mode)
2790 * @edid: EDID block
2791 * @timing: EDID detailed timing info
2792 * @quirks: quirks to apply
2793 *
2794 * An EDID detailed timing block contains enough info for us to create and
2795 * return a new struct drm_display_mode.
2796 */
drm_mode_detailed(struct drm_device * dev,struct edid * edid,struct detailed_timing * timing,u32 quirks)2797 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2798 struct edid *edid,
2799 struct detailed_timing *timing,
2800 u32 quirks)
2801 {
2802 struct drm_display_mode *mode;
2803 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2804 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2805 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2806 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2807 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2808 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2809 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2810 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2811 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2812
2813 /* ignore tiny modes */
2814 if (hactive < 64 || vactive < 64)
2815 return NULL;
2816
2817 if (pt->misc & DRM_EDID_PT_STEREO) {
2818 DRM_DEBUG_KMS("stereo mode not supported\n");
2819 return NULL;
2820 }
2821 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2822 DRM_DEBUG_KMS("composite sync not supported\n");
2823 }
2824
2825 /* it is incorrect if hsync/vsync width is zero */
2826 if (!hsync_pulse_width || !vsync_pulse_width) {
2827 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2828 "Wrong Hsync/Vsync pulse width\n");
2829 return NULL;
2830 }
2831
2832 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2833 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2834 if (!mode)
2835 return NULL;
2836
2837 goto set_size;
2838 }
2839
2840 mode = drm_mode_create(dev);
2841 if (!mode)
2842 return NULL;
2843
2844 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2845 timing->pixel_clock = cpu_to_le16(1088);
2846
2847 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2848
2849 mode->hdisplay = hactive;
2850 mode->hsync_start = mode->hdisplay + hsync_offset;
2851 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2852 mode->htotal = mode->hdisplay + hblank;
2853
2854 mode->vdisplay = vactive;
2855 mode->vsync_start = mode->vdisplay + vsync_offset;
2856 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2857 mode->vtotal = mode->vdisplay + vblank;
2858
2859 /* Some EDIDs have bogus h/vtotal values */
2860 if (mode->hsync_end > mode->htotal)
2861 mode->htotal = mode->hsync_end + 1;
2862 if (mode->vsync_end > mode->vtotal)
2863 mode->vtotal = mode->vsync_end + 1;
2864
2865 drm_mode_do_interlace_quirk(mode, pt);
2866
2867 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2868 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2869 }
2870
2871 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2872 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2873 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2874 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2875
2876 set_size:
2877 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2878 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2879
2880 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2881 mode->width_mm *= 10;
2882 mode->height_mm *= 10;
2883 }
2884
2885 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2886 mode->width_mm = edid->width_cm * 10;
2887 mode->height_mm = edid->height_cm * 10;
2888 }
2889
2890 mode->type = DRM_MODE_TYPE_DRIVER;
2891 drm_mode_set_name(mode);
2892
2893 return mode;
2894 }
2895
2896 static bool
mode_in_hsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)2897 mode_in_hsync_range(const struct drm_display_mode *mode,
2898 struct edid *edid, u8 *t)
2899 {
2900 int hsync, hmin, hmax;
2901
2902 hmin = t[7];
2903 if (edid->revision >= 4)
2904 hmin += ((t[4] & 0x04) ? 255 : 0);
2905 hmax = t[8];
2906 if (edid->revision >= 4)
2907 hmax += ((t[4] & 0x08) ? 255 : 0);
2908 hsync = drm_mode_hsync(mode);
2909
2910 return (hsync <= hmax && hsync >= hmin);
2911 }
2912
2913 static bool
mode_in_vsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)2914 mode_in_vsync_range(const struct drm_display_mode *mode,
2915 struct edid *edid, u8 *t)
2916 {
2917 int vsync, vmin, vmax;
2918
2919 vmin = t[5];
2920 if (edid->revision >= 4)
2921 vmin += ((t[4] & 0x01) ? 255 : 0);
2922 vmax = t[6];
2923 if (edid->revision >= 4)
2924 vmax += ((t[4] & 0x02) ? 255 : 0);
2925 vsync = drm_mode_vrefresh(mode);
2926
2927 return (vsync <= vmax && vsync >= vmin);
2928 }
2929
2930 static u32
range_pixel_clock(struct edid * edid,u8 * t)2931 range_pixel_clock(struct edid *edid, u8 *t)
2932 {
2933 /* unspecified */
2934 if (t[9] == 0 || t[9] == 255)
2935 return 0;
2936
2937 /* 1.4 with CVT support gives us real precision, yay */
2938 if (edid->revision >= 4 && t[10] == 0x04)
2939 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2940
2941 /* 1.3 is pathetic, so fuzz up a bit */
2942 return t[9] * 10000 + 5001;
2943 }
2944
2945 static bool
mode_in_range(const struct drm_display_mode * mode,struct edid * edid,struct detailed_timing * timing)2946 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2947 struct detailed_timing *timing)
2948 {
2949 u32 max_clock;
2950 u8 *t = (u8 *)timing;
2951
2952 if (!mode_in_hsync_range(mode, edid, t))
2953 return false;
2954
2955 if (!mode_in_vsync_range(mode, edid, t))
2956 return false;
2957
2958 if ((max_clock = range_pixel_clock(edid, t)))
2959 if (mode->clock > max_clock)
2960 return false;
2961
2962 /* 1.4 max horizontal check */
2963 if (edid->revision >= 4 && t[10] == 0x04)
2964 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2965 return false;
2966
2967 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2968 return false;
2969
2970 return true;
2971 }
2972
valid_inferred_mode(const struct drm_connector * connector,const struct drm_display_mode * mode)2973 static bool valid_inferred_mode(const struct drm_connector *connector,
2974 const struct drm_display_mode *mode)
2975 {
2976 const struct drm_display_mode *m;
2977 bool ok = false;
2978
2979 list_for_each_entry(m, &connector->probed_modes, head) {
2980 if (mode->hdisplay == m->hdisplay &&
2981 mode->vdisplay == m->vdisplay &&
2982 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2983 return false; /* duplicated */
2984 if (mode->hdisplay <= m->hdisplay &&
2985 mode->vdisplay <= m->vdisplay)
2986 ok = true;
2987 }
2988 return ok;
2989 }
2990
2991 static int
drm_dmt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2992 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2993 struct detailed_timing *timing)
2994 {
2995 int i, modes = 0;
2996 struct drm_display_mode *newmode;
2997 struct drm_device *dev = connector->dev;
2998
2999 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3000 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
3001 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3002 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3003 if (newmode) {
3004 drm_mode_probed_add(connector, newmode);
3005 modes++;
3006 }
3007 }
3008 }
3009
3010 return modes;
3011 }
3012
3013 /* fix up 1366x768 mode from 1368x768;
3014 * GFT/CVT can't express 1366 width which isn't dividable by 8
3015 */
drm_mode_fixup_1366x768(struct drm_display_mode * mode)3016 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3017 {
3018 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3019 mode->hdisplay = 1366;
3020 mode->hsync_start--;
3021 mode->hsync_end--;
3022 drm_mode_set_name(mode);
3023 }
3024 }
3025
3026 static int
drm_gtf_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)3027 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
3028 struct detailed_timing *timing)
3029 {
3030 int i, modes = 0;
3031 struct drm_display_mode *newmode;
3032 struct drm_device *dev = connector->dev;
3033
3034 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3035 const struct minimode *m = &extra_modes[i];
3036
3037 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3038 if (!newmode)
3039 return modes;
3040
3041 drm_mode_fixup_1366x768(newmode);
3042 if (!mode_in_range(newmode, edid, timing) ||
3043 !valid_inferred_mode(connector, newmode)) {
3044 drm_mode_destroy(dev, newmode);
3045 continue;
3046 }
3047
3048 drm_mode_probed_add(connector, newmode);
3049 modes++;
3050 }
3051
3052 return modes;
3053 }
3054
3055 static int
drm_cvt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)3056 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
3057 struct detailed_timing *timing)
3058 {
3059 int i, modes = 0;
3060 struct drm_display_mode *newmode;
3061 struct drm_device *dev = connector->dev;
3062 bool rb = drm_monitor_supports_rb(edid);
3063
3064 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3065 const struct minimode *m = &extra_modes[i];
3066
3067 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3068 if (!newmode)
3069 return modes;
3070
3071 drm_mode_fixup_1366x768(newmode);
3072 if (!mode_in_range(newmode, edid, timing) ||
3073 !valid_inferred_mode(connector, newmode)) {
3074 drm_mode_destroy(dev, newmode);
3075 continue;
3076 }
3077
3078 drm_mode_probed_add(connector, newmode);
3079 modes++;
3080 }
3081
3082 return modes;
3083 }
3084
3085 static void
do_inferred_modes(struct detailed_timing * timing,void * c)3086 do_inferred_modes(struct detailed_timing *timing, void *c)
3087 {
3088 struct detailed_mode_closure *closure = c;
3089 struct detailed_non_pixel *data = &timing->data.other_data;
3090 struct detailed_data_monitor_range *range = &data->data.range;
3091
3092 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
3093 return;
3094
3095 closure->modes += drm_dmt_modes_for_range(closure->connector,
3096 closure->edid,
3097 timing);
3098
3099 if (!version_greater(closure->edid, 1, 1))
3100 return; /* GTF not defined yet */
3101
3102 switch (range->flags) {
3103 case 0x02: /* secondary gtf, XXX could do more */
3104 case 0x00: /* default gtf */
3105 closure->modes += drm_gtf_modes_for_range(closure->connector,
3106 closure->edid,
3107 timing);
3108 break;
3109 case 0x04: /* cvt, only in 1.4+ */
3110 if (!version_greater(closure->edid, 1, 3))
3111 break;
3112
3113 closure->modes += drm_cvt_modes_for_range(closure->connector,
3114 closure->edid,
3115 timing);
3116 break;
3117 case 0x01: /* just the ranges, no formula */
3118 default:
3119 break;
3120 }
3121 }
3122
3123 static int
add_inferred_modes(struct drm_connector * connector,struct edid * edid)3124 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
3125 {
3126 struct detailed_mode_closure closure = {
3127 .connector = connector,
3128 .edid = edid,
3129 };
3130
3131 if (version_greater(edid, 1, 0))
3132 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
3133 &closure);
3134
3135 return closure.modes;
3136 }
3137
3138 static int
drm_est3_modes(struct drm_connector * connector,struct detailed_timing * timing)3139 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
3140 {
3141 int i, j, m, modes = 0;
3142 struct drm_display_mode *mode;
3143 u8 *est = ((u8 *)timing) + 6;
3144
3145 for (i = 0; i < 6; i++) {
3146 for (j = 7; j >= 0; j--) {
3147 m = (i * 8) + (7 - j);
3148 if (m >= ARRAY_SIZE(est3_modes))
3149 break;
3150 if (est[i] & (1 << j)) {
3151 mode = drm_mode_find_dmt(connector->dev,
3152 est3_modes[m].w,
3153 est3_modes[m].h,
3154 est3_modes[m].r,
3155 est3_modes[m].rb);
3156 if (mode) {
3157 drm_mode_probed_add(connector, mode);
3158 modes++;
3159 }
3160 }
3161 }
3162 }
3163
3164 return modes;
3165 }
3166
3167 static void
do_established_modes(struct detailed_timing * timing,void * c)3168 do_established_modes(struct detailed_timing *timing, void *c)
3169 {
3170 struct detailed_mode_closure *closure = c;
3171
3172 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
3173 return;
3174
3175 closure->modes += drm_est3_modes(closure->connector, timing);
3176 }
3177
3178 /**
3179 * add_established_modes - get est. modes from EDID and add them
3180 * @connector: connector to add mode(s) to
3181 * @edid: EDID block to scan
3182 *
3183 * Each EDID block contains a bitmap of the supported "established modes" list
3184 * (defined above). Tease them out and add them to the global modes list.
3185 */
3186 static int
add_established_modes(struct drm_connector * connector,struct edid * edid)3187 add_established_modes(struct drm_connector *connector, struct edid *edid)
3188 {
3189 struct drm_device *dev = connector->dev;
3190 unsigned long est_bits = edid->established_timings.t1 |
3191 (edid->established_timings.t2 << 8) |
3192 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3193 int i, modes = 0;
3194 struct detailed_mode_closure closure = {
3195 .connector = connector,
3196 .edid = edid,
3197 };
3198
3199 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3200 if (est_bits & (1<<i)) {
3201 struct drm_display_mode *newmode;
3202
3203 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3204 if (newmode) {
3205 drm_mode_probed_add(connector, newmode);
3206 modes++;
3207 }
3208 }
3209 }
3210
3211 if (version_greater(edid, 1, 0))
3212 drm_for_each_detailed_block((u8 *)edid,
3213 do_established_modes, &closure);
3214
3215 return modes + closure.modes;
3216 }
3217
3218 static void
do_standard_modes(struct detailed_timing * timing,void * c)3219 do_standard_modes(struct detailed_timing *timing, void *c)
3220 {
3221 struct detailed_mode_closure *closure = c;
3222 struct detailed_non_pixel *data = &timing->data.other_data;
3223 struct drm_connector *connector = closure->connector;
3224 struct edid *edid = closure->edid;
3225 int i;
3226
3227 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
3228 return;
3229
3230 for (i = 0; i < 6; i++) {
3231 struct std_timing *std = &data->data.timings[i];
3232 struct drm_display_mode *newmode;
3233
3234 newmode = drm_mode_std(connector, edid, std);
3235 if (newmode) {
3236 drm_mode_probed_add(connector, newmode);
3237 closure->modes++;
3238 }
3239 }
3240 }
3241
3242 /**
3243 * add_standard_modes - get std. modes from EDID and add them
3244 * @connector: connector to add mode(s) to
3245 * @edid: EDID block to scan
3246 *
3247 * Standard modes can be calculated using the appropriate standard (DMT,
3248 * GTF or CVT. Grab them from @edid and add them to the list.
3249 */
3250 static int
add_standard_modes(struct drm_connector * connector,struct edid * edid)3251 add_standard_modes(struct drm_connector *connector, struct edid *edid)
3252 {
3253 int i, modes = 0;
3254 struct detailed_mode_closure closure = {
3255 .connector = connector,
3256 .edid = edid,
3257 };
3258
3259 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3260 struct drm_display_mode *newmode;
3261
3262 newmode = drm_mode_std(connector, edid,
3263 &edid->standard_timings[i]);
3264 if (newmode) {
3265 drm_mode_probed_add(connector, newmode);
3266 modes++;
3267 }
3268 }
3269
3270 if (version_greater(edid, 1, 0))
3271 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3272 &closure);
3273
3274 /* XXX should also look for standard codes in VTB blocks */
3275
3276 return modes + closure.modes;
3277 }
3278
drm_cvt_modes(struct drm_connector * connector,struct detailed_timing * timing)3279 static int drm_cvt_modes(struct drm_connector *connector,
3280 struct detailed_timing *timing)
3281 {
3282 int i, j, modes = 0;
3283 struct drm_display_mode *newmode;
3284 struct drm_device *dev = connector->dev;
3285 struct cvt_timing *cvt;
3286 const int rates[] = { 60, 85, 75, 60, 50 };
3287 const u8 empty[3] = { 0, 0, 0 };
3288
3289 for (i = 0; i < 4; i++) {
3290 int width, height;
3291
3292 cvt = &(timing->data.other_data.data.cvt[i]);
3293
3294 if (!memcmp(cvt->code, empty, 3))
3295 continue;
3296
3297 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3298 switch (cvt->code[1] & 0x0c) {
3299 /* default - because compiler doesn't see that we've enumerated all cases */
3300 default:
3301 case 0x00:
3302 width = height * 4 / 3;
3303 break;
3304 case 0x04:
3305 width = height * 16 / 9;
3306 break;
3307 case 0x08:
3308 width = height * 16 / 10;
3309 break;
3310 case 0x0c:
3311 width = height * 15 / 9;
3312 break;
3313 }
3314
3315 for (j = 1; j < 5; j++) {
3316 if (cvt->code[2] & (1 << j)) {
3317 newmode = drm_cvt_mode(dev, width, height,
3318 rates[j], j == 0,
3319 false, false);
3320 if (newmode) {
3321 drm_mode_probed_add(connector, newmode);
3322 modes++;
3323 }
3324 }
3325 }
3326 }
3327
3328 return modes;
3329 }
3330
3331 static void
do_cvt_mode(struct detailed_timing * timing,void * c)3332 do_cvt_mode(struct detailed_timing *timing, void *c)
3333 {
3334 struct detailed_mode_closure *closure = c;
3335
3336 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3337 return;
3338
3339 closure->modes += drm_cvt_modes(closure->connector, timing);
3340 }
3341
3342 static int
add_cvt_modes(struct drm_connector * connector,struct edid * edid)3343 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
3344 {
3345 struct detailed_mode_closure closure = {
3346 .connector = connector,
3347 .edid = edid,
3348 };
3349
3350 if (version_greater(edid, 1, 2))
3351 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
3352
3353 /* XXX should also look for CVT codes in VTB blocks */
3354
3355 return closure.modes;
3356 }
3357
3358 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3359
3360 static void
do_detailed_mode(struct detailed_timing * timing,void * c)3361 do_detailed_mode(struct detailed_timing *timing, void *c)
3362 {
3363 struct detailed_mode_closure *closure = c;
3364 struct drm_display_mode *newmode;
3365
3366 if (!is_detailed_timing_descriptor((const u8 *)timing))
3367 return;
3368
3369 newmode = drm_mode_detailed(closure->connector->dev,
3370 closure->edid, timing,
3371 closure->quirks);
3372 if (!newmode)
3373 return;
3374
3375 if (closure->preferred)
3376 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3377
3378 /*
3379 * Detailed modes are limited to 10kHz pixel clock resolution,
3380 * so fix up anything that looks like CEA/HDMI mode, but the clock
3381 * is just slightly off.
3382 */
3383 fixup_detailed_cea_mode_clock(newmode);
3384
3385 drm_mode_probed_add(closure->connector, newmode);
3386 closure->modes++;
3387 closure->preferred = false;
3388 }
3389
3390 /*
3391 * add_detailed_modes - Add modes from detailed timings
3392 * @connector: attached connector
3393 * @edid: EDID block to scan
3394 * @quirks: quirks to apply
3395 */
3396 static int
add_detailed_modes(struct drm_connector * connector,struct edid * edid,u32 quirks)3397 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3398 u32 quirks)
3399 {
3400 struct detailed_mode_closure closure = {
3401 .connector = connector,
3402 .edid = edid,
3403 .preferred = true,
3404 .quirks = quirks,
3405 };
3406
3407 if (closure.preferred && !version_greater(edid, 1, 3))
3408 closure.preferred =
3409 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3410
3411 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3412
3413 return closure.modes;
3414 }
3415
3416 #define AUDIO_BLOCK 0x01
3417 #define VIDEO_BLOCK 0x02
3418 #define VENDOR_BLOCK 0x03
3419 #define SPEAKER_BLOCK 0x04
3420 #define HDR_STATIC_METADATA_BLOCK 0x6
3421 #define USE_EXTENDED_TAG 0x07
3422 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3423 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
3424 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3425 #define EDID_BASIC_AUDIO (1 << 6)
3426 #define EDID_CEA_YCRCB444 (1 << 5)
3427 #define EDID_CEA_YCRCB422 (1 << 4)
3428 #define EDID_CEA_VCDB_QS (1 << 6)
3429
3430 /*
3431 * Search EDID for CEA extension block.
3432 */
3433 #ifdef CONFIG_NO_GKI
drm_find_edid_extension(const struct edid * edid,int ext_id,int * ext_index)3434 static u8 *drm_find_edid_extension(const struct edid *edid,
3435 int ext_id, int *ext_index)
3436 {
3437 u8 *edid_ext = NULL;
3438 int i;
3439 int len;
3440
3441 /* No EDID or EDID extensions */
3442 if (edid == NULL || edid->extensions == 0)
3443 return NULL;
3444
3445 if (edid_hfeeodb_extension_block_count(edid))
3446 len = edid_hfeeodb_extension_block_count(edid);
3447 else
3448 len = edid->extensions;
3449
3450 /* Find CEA extension */
3451 for (i = *ext_index; i < len; i++) {
3452 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
3453
3454 if (edid_ext[0] == ext_id)
3455 break;
3456 }
3457
3458 if (i >= len)
3459 return NULL;
3460
3461 *ext_index = i + 1;
3462
3463 return edid_ext;
3464 }
3465 #else
drm_find_edid_extension(const struct edid * edid,int ext_id,int * ext_index)3466 static u8 *drm_find_edid_extension(const struct edid *edid,
3467 int ext_id, int *ext_index)
3468 {
3469 u8 *edid_ext = NULL;
3470 int i;
3471
3472 /* No EDID or EDID extensions */
3473 if (edid == NULL || edid->extensions == 0)
3474 return NULL;
3475
3476 /* Find CEA extension */
3477 for (i = *ext_index; i < edid->extensions; i++) {
3478 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
3479 if (edid_ext[0] == ext_id)
3480 break;
3481 }
3482
3483 if (i >= edid->extensions)
3484 return NULL;
3485
3486 *ext_index = i + 1;
3487
3488 return edid_ext;
3489 }
3490 #endif
3491
drm_find_displayid_extension(const struct edid * edid,int * length,int * idx,int * ext_index)3492 static u8 *drm_find_displayid_extension(const struct edid *edid,
3493 int *length, int *idx,
3494 int *ext_index)
3495 {
3496 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index);
3497 struct displayid_hdr *base;
3498 int ret;
3499
3500 if (!displayid)
3501 return NULL;
3502
3503 /* EDID extensions block checksum isn't for us */
3504 *length = EDID_LENGTH - 1;
3505 *idx = 1;
3506
3507 ret = validate_displayid(displayid, *length, *idx);
3508 if (ret)
3509 return NULL;
3510
3511 base = (struct displayid_hdr *)&displayid[*idx];
3512 *length = *idx + sizeof(*base) + base->bytes;
3513
3514 return displayid;
3515 }
3516
drm_find_cea_extension(const struct edid * edid)3517 static u8 *drm_find_cea_extension(const struct edid *edid)
3518 {
3519 int length, idx;
3520 struct displayid_block *block;
3521 u8 *cea;
3522 u8 *displayid;
3523 int ext_index;
3524
3525 /* Look for a top level CEA extension block */
3526 /* FIXME: make callers iterate through multiple CEA ext blocks? */
3527 ext_index = 0;
3528 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
3529 if (cea)
3530 return cea;
3531
3532 /* CEA blocks can also be found embedded in a DisplayID block */
3533 ext_index = 0;
3534 for (;;) {
3535 displayid = drm_find_displayid_extension(edid, &length, &idx,
3536 &ext_index);
3537 if (!displayid)
3538 return NULL;
3539
3540 idx += sizeof(struct displayid_hdr);
3541 for_each_displayid_db(displayid, block, idx, length) {
3542 if (block->tag == DATA_BLOCK_CTA)
3543 return (u8 *)block;
3544 }
3545 }
3546
3547 return NULL;
3548 }
3549
cea_mode_for_vic(u8 vic)3550 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3551 {
3552 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3553 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3554
3555 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3556 return &edid_cea_modes_1[vic - 1];
3557 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3558 return &edid_cea_modes_193[vic - 193];
3559 return NULL;
3560 }
3561
cea_num_vics(void)3562 static u8 cea_num_vics(void)
3563 {
3564 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3565 }
3566
cea_next_vic(u8 vic)3567 static u8 cea_next_vic(u8 vic)
3568 {
3569 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3570 vic = 193;
3571 return vic;
3572 }
3573
3574 /*
3575 * Calculate the alternate clock for the CEA mode
3576 * (60Hz vs. 59.94Hz etc.)
3577 */
3578 static unsigned int
cea_mode_alternate_clock(const struct drm_display_mode * cea_mode)3579 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3580 {
3581 unsigned int clock = cea_mode->clock;
3582
3583 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3584 return clock;
3585
3586 /*
3587 * edid_cea_modes contains the 59.94Hz
3588 * variant for 240 and 480 line modes,
3589 * and the 60Hz variant otherwise.
3590 */
3591 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3592 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3593 else
3594 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3595
3596 return clock;
3597 }
3598
3599 static bool
cea_mode_alternate_timings(u8 vic,struct drm_display_mode * mode)3600 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3601 {
3602 /*
3603 * For certain VICs the spec allows the vertical
3604 * front porch to vary by one or two lines.
3605 *
3606 * cea_modes[] stores the variant with the shortest
3607 * vertical front porch. We can adjust the mode to
3608 * get the other variants by simply increasing the
3609 * vertical front porch length.
3610 */
3611 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3612 cea_mode_for_vic(9)->vtotal != 262 ||
3613 cea_mode_for_vic(12)->vtotal != 262 ||
3614 cea_mode_for_vic(13)->vtotal != 262 ||
3615 cea_mode_for_vic(23)->vtotal != 312 ||
3616 cea_mode_for_vic(24)->vtotal != 312 ||
3617 cea_mode_for_vic(27)->vtotal != 312 ||
3618 cea_mode_for_vic(28)->vtotal != 312);
3619
3620 if (((vic == 8 || vic == 9 ||
3621 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3622 ((vic == 23 || vic == 24 ||
3623 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3624 mode->vsync_start++;
3625 mode->vsync_end++;
3626 mode->vtotal++;
3627
3628 return true;
3629 }
3630
3631 return false;
3632 }
3633
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3634 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3635 unsigned int clock_tolerance)
3636 {
3637 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3638 u8 vic;
3639
3640 if (!to_match->clock)
3641 return 0;
3642
3643 if (to_match->picture_aspect_ratio)
3644 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3645
3646 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3647 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3648 unsigned int clock1, clock2;
3649
3650 /* Check both 60Hz and 59.94Hz */
3651 clock1 = cea_mode.clock;
3652 clock2 = cea_mode_alternate_clock(&cea_mode);
3653
3654 if (abs(to_match->clock - clock1) > clock_tolerance &&
3655 abs(to_match->clock - clock2) > clock_tolerance)
3656 continue;
3657
3658 do {
3659 if (drm_mode_match(to_match, &cea_mode, match_flags))
3660 return vic;
3661 } while (cea_mode_alternate_timings(vic, &cea_mode));
3662 }
3663
3664 return 0;
3665 }
3666
3667 /**
3668 * drm_match_cea_mode - look for a CEA mode matching given mode
3669 * @to_match: display mode
3670 *
3671 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3672 * mode.
3673 */
drm_match_cea_mode(const struct drm_display_mode * to_match)3674 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3675 {
3676 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3677 u8 vic;
3678
3679 if (!to_match->clock)
3680 return 0;
3681
3682 if (to_match->picture_aspect_ratio)
3683 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3684
3685 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3686 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3687 unsigned int clock1, clock2;
3688
3689 /* Check both 60Hz and 59.94Hz */
3690 clock1 = cea_mode.clock;
3691 clock2 = cea_mode_alternate_clock(&cea_mode);
3692
3693 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3694 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3695 continue;
3696
3697 do {
3698 if (drm_mode_match(to_match, &cea_mode, match_flags))
3699 return vic;
3700 } while (cea_mode_alternate_timings(vic, &cea_mode));
3701 }
3702
3703 return 0;
3704 }
3705 EXPORT_SYMBOL(drm_match_cea_mode);
3706
drm_valid_cea_vic(u8 vic)3707 static bool drm_valid_cea_vic(u8 vic)
3708 {
3709 return cea_mode_for_vic(vic) != NULL;
3710 }
3711
drm_get_cea_aspect_ratio(const u8 video_code)3712 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3713 {
3714 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3715
3716 if (mode)
3717 return mode->picture_aspect_ratio;
3718
3719 return HDMI_PICTURE_ASPECT_NONE;
3720 }
3721
drm_get_hdmi_aspect_ratio(const u8 video_code)3722 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3723 {
3724 return edid_4k_modes[video_code].picture_aspect_ratio;
3725 }
3726
3727 /*
3728 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3729 * specific block).
3730 */
3731 static unsigned int
hdmi_mode_alternate_clock(const struct drm_display_mode * hdmi_mode)3732 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3733 {
3734 return cea_mode_alternate_clock(hdmi_mode);
3735 }
3736
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3737 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3738 unsigned int clock_tolerance)
3739 {
3740 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3741 u8 vic;
3742
3743 if (!to_match->clock)
3744 return 0;
3745
3746 if (to_match->picture_aspect_ratio)
3747 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3748
3749 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3750 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3751 unsigned int clock1, clock2;
3752
3753 /* Make sure to also match alternate clocks */
3754 clock1 = hdmi_mode->clock;
3755 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3756
3757 if (abs(to_match->clock - clock1) > clock_tolerance &&
3758 abs(to_match->clock - clock2) > clock_tolerance)
3759 continue;
3760
3761 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3762 return vic;
3763 }
3764
3765 return 0;
3766 }
3767
3768 /*
3769 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3770 * @to_match: display mode
3771 *
3772 * An HDMI mode is one defined in the HDMI vendor specific block.
3773 *
3774 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3775 */
drm_match_hdmi_mode(const struct drm_display_mode * to_match)3776 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3777 {
3778 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3779 u8 vic;
3780
3781 if (!to_match->clock)
3782 return 0;
3783
3784 if (to_match->picture_aspect_ratio)
3785 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3786
3787 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3788 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3789 unsigned int clock1, clock2;
3790
3791 /* Make sure to also match alternate clocks */
3792 clock1 = hdmi_mode->clock;
3793 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3794
3795 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3796 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3797 drm_mode_match(to_match, hdmi_mode, match_flags))
3798 return vic;
3799 }
3800 return 0;
3801 }
3802
drm_valid_hdmi_vic(u8 vic)3803 static bool drm_valid_hdmi_vic(u8 vic)
3804 {
3805 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3806 }
3807
3808 static int
add_alternate_cea_modes(struct drm_connector * connector,struct edid * edid)3809 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3810 {
3811 struct drm_device *dev = connector->dev;
3812 struct drm_display_mode *mode, *tmp;
3813 LIST_HEAD(list);
3814 int modes = 0;
3815
3816 /* Don't add CEA modes if the CEA extension block is missing */
3817 if (!drm_find_cea_extension(edid))
3818 return 0;
3819
3820 /*
3821 * Go through all probed modes and create a new mode
3822 * with the alternate clock for certain CEA modes.
3823 */
3824 list_for_each_entry(mode, &connector->probed_modes, head) {
3825 const struct drm_display_mode *cea_mode = NULL;
3826 struct drm_display_mode *newmode;
3827 u8 vic = drm_match_cea_mode(mode);
3828 unsigned int clock1, clock2;
3829
3830 if (drm_valid_cea_vic(vic)) {
3831 cea_mode = cea_mode_for_vic(vic);
3832 clock2 = cea_mode_alternate_clock(cea_mode);
3833 } else {
3834 vic = drm_match_hdmi_mode(mode);
3835 if (drm_valid_hdmi_vic(vic)) {
3836 cea_mode = &edid_4k_modes[vic];
3837 clock2 = hdmi_mode_alternate_clock(cea_mode);
3838 }
3839 }
3840
3841 if (!cea_mode)
3842 continue;
3843
3844 clock1 = cea_mode->clock;
3845
3846 if (clock1 == clock2)
3847 continue;
3848
3849 if (mode->clock != clock1 && mode->clock != clock2)
3850 continue;
3851
3852 newmode = drm_mode_duplicate(dev, cea_mode);
3853 if (!newmode)
3854 continue;
3855
3856 /* Carry over the stereo flags */
3857 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3858
3859 /*
3860 * The current mode could be either variant. Make
3861 * sure to pick the "other" clock for the new mode.
3862 */
3863 if (mode->clock != clock1)
3864 newmode->clock = clock1;
3865 else
3866 newmode->clock = clock2;
3867
3868 list_add_tail(&newmode->head, &list);
3869 }
3870
3871 list_for_each_entry_safe(mode, tmp, &list, head) {
3872 list_del(&mode->head);
3873 drm_mode_probed_add(connector, mode);
3874 modes++;
3875 }
3876
3877 return modes;
3878 }
3879
svd_to_vic(u8 svd)3880 static u8 svd_to_vic(u8 svd)
3881 {
3882 /* 0-6 bit vic, 7th bit native mode indicator */
3883 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3884 return svd & 127;
3885
3886 return svd;
3887 }
3888
3889 static struct drm_display_mode *
drm_display_mode_from_vic_index(struct drm_connector * connector,const u8 * video_db,u8 video_len,u8 video_index)3890 drm_display_mode_from_vic_index(struct drm_connector *connector,
3891 const u8 *video_db, u8 video_len,
3892 u8 video_index)
3893 {
3894 struct drm_device *dev = connector->dev;
3895 struct drm_display_mode *newmode;
3896 u8 vic;
3897
3898 if (video_db == NULL || video_index >= video_len)
3899 return NULL;
3900
3901 /* CEA modes are numbered 1..127 */
3902 vic = svd_to_vic(video_db[video_index]);
3903 if (!drm_valid_cea_vic(vic))
3904 return NULL;
3905
3906 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3907 if (!newmode)
3908 return NULL;
3909
3910 return newmode;
3911 }
3912
3913 /*
3914 * do_y420vdb_modes - Parse YCBCR 420 only modes
3915 * @connector: connector corresponding to the HDMI sink
3916 * @svds: start of the data block of CEA YCBCR 420 VDB
3917 * @len: length of the CEA YCBCR 420 VDB
3918 *
3919 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3920 * which contains modes which can be supported in YCBCR 420
3921 * output format only.
3922 */
do_y420vdb_modes(struct drm_connector * connector,const u8 * svds,u8 svds_len)3923 static int do_y420vdb_modes(struct drm_connector *connector,
3924 const u8 *svds, u8 svds_len)
3925 {
3926 int modes = 0, i;
3927 struct drm_device *dev = connector->dev;
3928 struct drm_display_info *info = &connector->display_info;
3929 struct drm_hdmi_info *hdmi = &info->hdmi;
3930
3931 for (i = 0; i < svds_len; i++) {
3932 u8 vic = svd_to_vic(svds[i]);
3933 struct drm_display_mode *newmode;
3934
3935 if (!drm_valid_cea_vic(vic))
3936 continue;
3937
3938 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3939 if (!newmode)
3940 break;
3941 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3942 drm_mode_probed_add(connector, newmode);
3943 modes++;
3944 }
3945
3946 if (modes > 0)
3947 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3948 return modes;
3949 }
3950
3951 /*
3952 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3953 * @connector: connector corresponding to the HDMI sink
3954 * @vic: CEA vic for the video mode to be added in the map
3955 *
3956 * Makes an entry for a videomode in the YCBCR 420 bitmap
3957 */
3958 static void
drm_add_cmdb_modes(struct drm_connector * connector,u8 svd)3959 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3960 {
3961 u8 vic = svd_to_vic(svd);
3962 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3963
3964 if (!drm_valid_cea_vic(vic))
3965 return;
3966
3967 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3968 }
3969
3970 /**
3971 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3972 * @dev: DRM device
3973 * @video_code: CEA VIC of the mode
3974 *
3975 * Creates a new mode matching the specified CEA VIC.
3976 *
3977 * Returns: A new drm_display_mode on success or NULL on failure
3978 */
3979 struct drm_display_mode *
drm_display_mode_from_cea_vic(struct drm_device * dev,u8 video_code)3980 drm_display_mode_from_cea_vic(struct drm_device *dev,
3981 u8 video_code)
3982 {
3983 const struct drm_display_mode *cea_mode;
3984 struct drm_display_mode *newmode;
3985
3986 cea_mode = cea_mode_for_vic(video_code);
3987 if (!cea_mode)
3988 return NULL;
3989
3990 newmode = drm_mode_duplicate(dev, cea_mode);
3991 if (!newmode)
3992 return NULL;
3993
3994 return newmode;
3995 }
3996 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3997
3998 static int
do_cea_modes(struct drm_connector * connector,const u8 * db,u8 len)3999 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4000 {
4001 int i, modes = 0;
4002 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4003
4004 for (i = 0; i < len; i++) {
4005 struct drm_display_mode *mode;
4006
4007 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4008 if (mode) {
4009 /*
4010 * YCBCR420 capability block contains a bitmap which
4011 * gives the index of CEA modes from CEA VDB, which
4012 * can support YCBCR 420 sampling output also (apart
4013 * from RGB/YCBCR444 etc).
4014 * For example, if the bit 0 in bitmap is set,
4015 * first mode in VDB can support YCBCR420 output too.
4016 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4017 */
4018 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4019 drm_add_cmdb_modes(connector, db[i]);
4020
4021 drm_mode_probed_add(connector, mode);
4022 modes++;
4023 }
4024 }
4025
4026 return modes;
4027 }
4028
4029 struct stereo_mandatory_mode {
4030 int width, height, vrefresh;
4031 unsigned int flags;
4032 };
4033
4034 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4035 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4036 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4037 { 1920, 1080, 50,
4038 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4039 { 1920, 1080, 60,
4040 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4041 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4042 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4043 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4044 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4045 };
4046
4047 static bool
stereo_match_mandatory(const struct drm_display_mode * mode,const struct stereo_mandatory_mode * stereo_mode)4048 stereo_match_mandatory(const struct drm_display_mode *mode,
4049 const struct stereo_mandatory_mode *stereo_mode)
4050 {
4051 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4052
4053 return mode->hdisplay == stereo_mode->width &&
4054 mode->vdisplay == stereo_mode->height &&
4055 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4056 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4057 }
4058
add_hdmi_mandatory_stereo_modes(struct drm_connector * connector)4059 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4060 {
4061 struct drm_device *dev = connector->dev;
4062 const struct drm_display_mode *mode;
4063 struct list_head stereo_modes;
4064 int modes = 0, i;
4065
4066 INIT_LIST_HEAD(&stereo_modes);
4067
4068 list_for_each_entry(mode, &connector->probed_modes, head) {
4069 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4070 const struct stereo_mandatory_mode *mandatory;
4071 struct drm_display_mode *new_mode;
4072
4073 if (!stereo_match_mandatory(mode,
4074 &stereo_mandatory_modes[i]))
4075 continue;
4076
4077 mandatory = &stereo_mandatory_modes[i];
4078 new_mode = drm_mode_duplicate(dev, mode);
4079 if (!new_mode)
4080 continue;
4081
4082 new_mode->flags |= mandatory->flags;
4083 list_add_tail(&new_mode->head, &stereo_modes);
4084 modes++;
4085 }
4086 }
4087
4088 list_splice_tail(&stereo_modes, &connector->probed_modes);
4089
4090 return modes;
4091 }
4092
add_hdmi_mode(struct drm_connector * connector,u8 vic)4093 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4094 {
4095 struct drm_device *dev = connector->dev;
4096 struct drm_display_mode *newmode;
4097
4098 if (!drm_valid_hdmi_vic(vic)) {
4099 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4100 return 0;
4101 }
4102
4103 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4104 if (!newmode)
4105 return 0;
4106
4107 drm_mode_probed_add(connector, newmode);
4108
4109 return 1;
4110 }
4111
add_3d_struct_modes(struct drm_connector * connector,u16 structure,const u8 * video_db,u8 video_len,u8 video_index)4112 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4113 const u8 *video_db, u8 video_len, u8 video_index)
4114 {
4115 struct drm_display_mode *newmode;
4116 int modes = 0;
4117
4118 if (structure & (1 << 0)) {
4119 newmode = drm_display_mode_from_vic_index(connector, video_db,
4120 video_len,
4121 video_index);
4122 if (newmode) {
4123 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4124 drm_mode_probed_add(connector, newmode);
4125 modes++;
4126 }
4127 }
4128 if (structure & (1 << 6)) {
4129 newmode = drm_display_mode_from_vic_index(connector, video_db,
4130 video_len,
4131 video_index);
4132 if (newmode) {
4133 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4134 drm_mode_probed_add(connector, newmode);
4135 modes++;
4136 }
4137 }
4138 if (structure & (1 << 8)) {
4139 newmode = drm_display_mode_from_vic_index(connector, video_db,
4140 video_len,
4141 video_index);
4142 if (newmode) {
4143 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4144 drm_mode_probed_add(connector, newmode);
4145 modes++;
4146 }
4147 }
4148
4149 return modes;
4150 }
4151
4152 /*
4153 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4154 * @connector: connector corresponding to the HDMI sink
4155 * @db: start of the CEA vendor specific block
4156 * @len: length of the CEA block payload, ie. one can access up to db[len]
4157 *
4158 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4159 * also adds the stereo 3d modes when applicable.
4160 */
4161 static int
do_hdmi_vsdb_modes(struct drm_connector * connector,const u8 * db,u8 len,const u8 * video_db,u8 video_len)4162 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4163 const u8 *video_db, u8 video_len)
4164 {
4165 struct drm_display_info *info = &connector->display_info;
4166 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4167 u8 vic_len, hdmi_3d_len = 0;
4168 u16 mask;
4169 u16 structure_all;
4170
4171 if (len < 8)
4172 goto out;
4173
4174 /* no HDMI_Video_Present */
4175 if (!(db[8] & (1 << 5)))
4176 goto out;
4177
4178 /* Latency_Fields_Present */
4179 if (db[8] & (1 << 7))
4180 offset += 2;
4181
4182 /* I_Latency_Fields_Present */
4183 if (db[8] & (1 << 6))
4184 offset += 2;
4185
4186 /* the declared length is not long enough for the 2 first bytes
4187 * of additional video format capabilities */
4188 if (len < (8 + offset + 2))
4189 goto out;
4190
4191 /* 3D_Present */
4192 offset++;
4193 if (db[8 + offset] & (1 << 7)) {
4194 modes += add_hdmi_mandatory_stereo_modes(connector);
4195
4196 /* 3D_Multi_present */
4197 multi_present = (db[8 + offset] & 0x60) >> 5;
4198 }
4199
4200 offset++;
4201 vic_len = db[8 + offset] >> 5;
4202 hdmi_3d_len = db[8 + offset] & 0x1f;
4203
4204 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4205 u8 vic;
4206
4207 vic = db[9 + offset + i];
4208 modes += add_hdmi_mode(connector, vic);
4209 }
4210 offset += 1 + vic_len;
4211
4212 if (multi_present == 1)
4213 multi_len = 2;
4214 else if (multi_present == 2)
4215 multi_len = 4;
4216 else
4217 multi_len = 0;
4218
4219 if (len < (8 + offset + hdmi_3d_len - 1))
4220 goto out;
4221
4222 if (hdmi_3d_len < multi_len)
4223 goto out;
4224
4225 if (multi_present == 1 || multi_present == 2) {
4226 /* 3D_Structure_ALL */
4227 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4228
4229 /* check if 3D_MASK is present */
4230 if (multi_present == 2)
4231 mask = (db[10 + offset] << 8) | db[11 + offset];
4232 else
4233 mask = 0xffff;
4234
4235 for (i = 0; i < 16; i++) {
4236 if (mask & (1 << i))
4237 modes += add_3d_struct_modes(connector,
4238 structure_all,
4239 video_db,
4240 video_len, i);
4241 }
4242 }
4243
4244 offset += multi_len;
4245
4246 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4247 int vic_index;
4248 struct drm_display_mode *newmode = NULL;
4249 unsigned int newflag = 0;
4250 bool detail_present;
4251
4252 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4253
4254 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4255 break;
4256
4257 /* 2D_VIC_order_X */
4258 vic_index = db[8 + offset + i] >> 4;
4259
4260 /* 3D_Structure_X */
4261 switch (db[8 + offset + i] & 0x0f) {
4262 case 0:
4263 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4264 break;
4265 case 6:
4266 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4267 break;
4268 case 8:
4269 /* 3D_Detail_X */
4270 if ((db[9 + offset + i] >> 4) == 1)
4271 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4272 break;
4273 }
4274
4275 if (newflag != 0) {
4276 newmode = drm_display_mode_from_vic_index(connector,
4277 video_db,
4278 video_len,
4279 vic_index);
4280
4281 if (newmode) {
4282 newmode->flags |= newflag;
4283 drm_mode_probed_add(connector, newmode);
4284 modes++;
4285 }
4286 }
4287
4288 if (detail_present)
4289 i++;
4290 }
4291
4292 out:
4293 if (modes > 0)
4294 info->has_hdmi_infoframe = true;
4295 return modes;
4296 }
4297
4298 static int
cea_db_payload_len(const u8 * db)4299 cea_db_payload_len(const u8 *db)
4300 {
4301 return db[0] & 0x1f;
4302 }
4303
4304 static int
cea_db_extended_tag(const u8 * db)4305 cea_db_extended_tag(const u8 *db)
4306 {
4307 return db[1];
4308 }
4309
4310 static int
cea_db_tag(const u8 * db)4311 cea_db_tag(const u8 *db)
4312 {
4313 return db[0] >> 5;
4314 }
4315
4316 static int
cea_revision(const u8 * cea)4317 cea_revision(const u8 *cea)
4318 {
4319 /*
4320 * FIXME is this correct for the DispID variant?
4321 * The DispID spec doesn't really specify whether
4322 * this is the revision of the CEA extension or
4323 * the DispID CEA data block. And the only value
4324 * given as an example is 0.
4325 */
4326 return cea[1];
4327 }
4328
4329 static int
cea_db_offsets(const u8 * cea,int * start,int * end)4330 cea_db_offsets(const u8 *cea, int *start, int *end)
4331 {
4332 /* DisplayID CTA extension blocks and top-level CEA EDID
4333 * block header definitions differ in the following bytes:
4334 * 1) Byte 2 of the header specifies length differently,
4335 * 2) Byte 3 is only present in the CEA top level block.
4336 *
4337 * The different definitions for byte 2 follow.
4338 *
4339 * DisplayID CTA extension block defines byte 2 as:
4340 * Number of payload bytes
4341 *
4342 * CEA EDID block defines byte 2 as:
4343 * Byte number (decimal) within this block where the 18-byte
4344 * DTDs begin. If no non-DTD data is present in this extension
4345 * block, the value should be set to 04h (the byte after next).
4346 * If set to 00h, there are no DTDs present in this block and
4347 * no non-DTD data.
4348 */
4349 if (cea[0] == DATA_BLOCK_CTA) {
4350 /*
4351 * for_each_displayid_db() has already verified
4352 * that these stay within expected bounds.
4353 */
4354 *start = 3;
4355 *end = *start + cea[2];
4356 } else if (cea[0] == CEA_EXT) {
4357 /* Data block offset in CEA extension block */
4358 *start = 4;
4359 *end = cea[2];
4360 if (*end == 0)
4361 *end = 127;
4362 if (*end < 4 || *end > 127)
4363 return -ERANGE;
4364 } else {
4365 return -EOPNOTSUPP;
4366 }
4367
4368 return 0;
4369 }
4370
cea_db_is_hdmi_vsdb(const u8 * db)4371 static bool cea_db_is_hdmi_vsdb(const u8 *db)
4372 {
4373 int hdmi_id;
4374
4375 if (cea_db_tag(db) != VENDOR_BLOCK)
4376 return false;
4377
4378 if (cea_db_payload_len(db) < 5)
4379 return false;
4380
4381 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4382
4383 return hdmi_id == HDMI_IEEE_OUI;
4384 }
4385
cea_db_is_hdmi_forum_vsdb(const u8 * db)4386 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4387 {
4388 unsigned int oui;
4389
4390 if (cea_db_tag(db) != VENDOR_BLOCK)
4391 return false;
4392
4393 if (cea_db_payload_len(db) < 7)
4394 return false;
4395
4396 oui = db[3] << 16 | db[2] << 8 | db[1];
4397
4398 return oui == HDMI_FORUM_IEEE_OUI;
4399 }
4400
cea_db_is_vcdb(const u8 * db)4401 static bool cea_db_is_vcdb(const u8 *db)
4402 {
4403 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4404 return false;
4405
4406 if (cea_db_payload_len(db) != 2)
4407 return false;
4408
4409 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4410 return false;
4411
4412 return true;
4413 }
4414
cea_db_is_y420cmdb(const u8 * db)4415 static bool cea_db_is_y420cmdb(const u8 *db)
4416 {
4417 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4418 return false;
4419
4420 if (!cea_db_payload_len(db))
4421 return false;
4422
4423 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4424 return false;
4425
4426 return true;
4427 }
4428
cea_db_is_y420vdb(const u8 * db)4429 static bool cea_db_is_y420vdb(const u8 *db)
4430 {
4431 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4432 return false;
4433
4434 if (!cea_db_payload_len(db))
4435 return false;
4436
4437 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4438 return false;
4439
4440 return true;
4441 }
4442
4443 #define for_each_cea_db(cea, i, start, end) \
4444 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4445
drm_parse_y420cmdb_bitmap(struct drm_connector * connector,const u8 * db)4446 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4447 const u8 *db)
4448 {
4449 struct drm_display_info *info = &connector->display_info;
4450 struct drm_hdmi_info *hdmi = &info->hdmi;
4451 u8 map_len = cea_db_payload_len(db) - 1;
4452 u8 count;
4453 u64 map = 0;
4454
4455 if (map_len == 0) {
4456 /* All CEA modes support ycbcr420 sampling also.*/
4457 hdmi->y420_cmdb_map = U64_MAX;
4458 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4459 return;
4460 }
4461
4462 /*
4463 * This map indicates which of the existing CEA block modes
4464 * from VDB can support YCBCR420 output too. So if bit=0 is
4465 * set, first mode from VDB can support YCBCR420 output too.
4466 * We will parse and keep this map, before parsing VDB itself
4467 * to avoid going through the same block again and again.
4468 *
4469 * Spec is not clear about max possible size of this block.
4470 * Clamping max bitmap block size at 8 bytes. Every byte can
4471 * address 8 CEA modes, in this way this map can address
4472 * 8*8 = first 64 SVDs.
4473 */
4474 if (WARN_ON_ONCE(map_len > 8))
4475 map_len = 8;
4476
4477 for (count = 0; count < map_len; count++)
4478 map |= (u64)db[2 + count] << (8 * count);
4479
4480 if (map)
4481 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4482
4483 hdmi->y420_cmdb_map = map;
4484 }
4485
4486 #ifdef CONFIG_NO_GKI
4487
4488 static int
add_cea_modes(struct drm_connector * connector,struct edid * edid)4489 add_cea_modes(struct drm_connector *connector, struct edid *edid)
4490 {
4491 const u8 *cea;
4492 const u8 *db, *hdmi = NULL, *video = NULL;
4493 u8 dbl, hdmi_len, video_len = 0;
4494 int i, count = 0, modes = 0;
4495 int ext_index = 0;
4496
4497 if (edid_hfeeodb_extension_block_count(edid))
4498 count = edid_hfeeodb_extension_block_count(edid);
4499 else
4500 count = edid->extensions;
4501
4502 for (i = 0; i < count; i++) {
4503 ext_index = i;
4504
4505 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
4506 if (cea && cea_revision(cea) >= 3) {
4507 int i, start, end;
4508
4509 if (cea_db_offsets(cea, &start, &end))
4510 return 0;
4511
4512 for_each_cea_db(cea, i, start, end) {
4513 db = &cea[i];
4514 dbl = cea_db_payload_len(db);
4515
4516 if (cea_db_tag(db) == VIDEO_BLOCK) {
4517 video = db + 1;
4518 video_len = dbl;
4519 modes += do_cea_modes(connector, video, dbl);
4520 } else if (cea_db_is_hdmi_vsdb(db)) {
4521 hdmi = db;
4522 hdmi_len = dbl;
4523 } else if (cea_db_is_y420vdb(db)) {
4524 const u8 *vdb420 = &db[2];
4525
4526 /* Add 4:2:0(only) modes present in EDID */
4527 modes += do_y420vdb_modes(connector,
4528 vdb420,
4529 dbl - 1);
4530 }
4531 }
4532 }
4533
4534 /*
4535 * We parse the HDMI VSDB after having added the cea modes as we will
4536 * be patching their flags when the sink supports stereo 3D.
4537 */
4538 if (hdmi)
4539 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4540 video_len);
4541 }
4542
4543 return modes;
4544 }
4545
4546 #else
4547
4548 static int
add_cea_modes(struct drm_connector * connector,struct edid * edid)4549 add_cea_modes(struct drm_connector *connector, struct edid *edid)
4550 {
4551 const u8 *cea = drm_find_cea_extension(edid);
4552 const u8 *db, *hdmi = NULL, *video = NULL;
4553 u8 dbl, hdmi_len, video_len = 0;
4554 int modes = 0;
4555
4556 if (cea && cea_revision(cea) >= 3) {
4557 int i, start, end;
4558
4559 if (cea_db_offsets(cea, &start, &end))
4560 return 0;
4561
4562 for_each_cea_db(cea, i, start, end) {
4563 db = &cea[i];
4564 dbl = cea_db_payload_len(db);
4565
4566 if (cea_db_tag(db) == VIDEO_BLOCK) {
4567 video = db + 1;
4568 video_len = dbl;
4569 modes += do_cea_modes(connector, video, dbl);
4570 } else if (cea_db_is_hdmi_vsdb(db)) {
4571 hdmi = db;
4572 hdmi_len = dbl;
4573 } else if (cea_db_is_y420vdb(db)) {
4574 const u8 *vdb420 = &db[2];
4575
4576 /* Add 4:2:0(only) modes present in EDID */
4577 modes += do_y420vdb_modes(connector,
4578 vdb420,
4579 dbl - 1);
4580 }
4581 }
4582 }
4583
4584 /*
4585 * We parse the HDMI VSDB after having added the cea modes as we will
4586 * be patching their flags when the sink supports stereo 3D.
4587 */
4588 if (hdmi)
4589 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4590 video_len);
4591
4592 return modes;
4593 }
4594 #endif
4595
fixup_detailed_cea_mode_clock(struct drm_display_mode * mode)4596 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4597 {
4598 const struct drm_display_mode *cea_mode;
4599 int clock1, clock2, clock;
4600 u8 vic;
4601 const char *type;
4602
4603 /*
4604 * allow 5kHz clock difference either way to account for
4605 * the 10kHz clock resolution limit of detailed timings.
4606 */
4607 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4608 if (drm_valid_cea_vic(vic)) {
4609 type = "CEA";
4610 cea_mode = cea_mode_for_vic(vic);
4611 clock1 = cea_mode->clock;
4612 clock2 = cea_mode_alternate_clock(cea_mode);
4613 } else {
4614 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4615 if (drm_valid_hdmi_vic(vic)) {
4616 type = "HDMI";
4617 cea_mode = &edid_4k_modes[vic];
4618 clock1 = cea_mode->clock;
4619 clock2 = hdmi_mode_alternate_clock(cea_mode);
4620 } else {
4621 return;
4622 }
4623 }
4624
4625 /* pick whichever is closest */
4626 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4627 clock = clock1;
4628 else
4629 clock = clock2;
4630
4631 if (mode->clock == clock)
4632 return;
4633
4634 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4635 type, vic, mode->clock, clock);
4636 mode->clock = clock;
4637 }
4638
cea_db_is_hdmi_hdr_metadata_block(const u8 * db)4639 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4640 {
4641 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4642 return false;
4643
4644 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4645 return false;
4646
4647 if (cea_db_payload_len(db) < 3)
4648 return false;
4649
4650 return true;
4651 }
4652
eotf_supported(const u8 * edid_ext)4653 static uint8_t eotf_supported(const u8 *edid_ext)
4654 {
4655 return edid_ext[2] &
4656 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4657 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4658 BIT(HDMI_EOTF_SMPTE_ST2084) |
4659 BIT(HDMI_EOTF_BT_2100_HLG));
4660 }
4661
hdr_metadata_type(const u8 * edid_ext)4662 static uint8_t hdr_metadata_type(const u8 *edid_ext)
4663 {
4664 return edid_ext[3] &
4665 BIT(HDMI_STATIC_METADATA_TYPE1);
4666 }
4667
4668 static void
drm_parse_hdr_metadata_block(struct drm_connector * connector,const u8 * db)4669 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4670 {
4671 u16 len;
4672
4673 len = cea_db_payload_len(db);
4674
4675 connector->hdr_sink_metadata.hdmi_type1.eotf =
4676 eotf_supported(db);
4677 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4678 hdr_metadata_type(db);
4679
4680 if (len >= 4)
4681 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4682 if (len >= 5)
4683 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4684 if (len >= 6)
4685 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4686 }
4687
4688 static void
drm_parse_hdmi_vsdb_audio(struct drm_connector * connector,const u8 * db)4689 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4690 {
4691 u8 len = cea_db_payload_len(db);
4692
4693 if (len >= 6 && (db[6] & (1 << 7)))
4694 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4695 if (len >= 8) {
4696 connector->latency_present[0] = db[8] >> 7;
4697 connector->latency_present[1] = (db[8] >> 6) & 1;
4698 }
4699 if (len >= 9)
4700 connector->video_latency[0] = db[9];
4701 if (len >= 10)
4702 connector->audio_latency[0] = db[10];
4703 if (len >= 11)
4704 connector->video_latency[1] = db[11];
4705 if (len >= 12)
4706 connector->audio_latency[1] = db[12];
4707
4708 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4709 "video latency %d %d, "
4710 "audio latency %d %d\n",
4711 connector->latency_present[0],
4712 connector->latency_present[1],
4713 connector->video_latency[0],
4714 connector->video_latency[1],
4715 connector->audio_latency[0],
4716 connector->audio_latency[1]);
4717 }
4718
4719 static void
monitor_name(struct detailed_timing * t,void * data)4720 monitor_name(struct detailed_timing *t, void *data)
4721 {
4722 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4723 return;
4724
4725 *(u8 **)data = t->data.other_data.data.str.str;
4726 }
4727
get_monitor_name(struct edid * edid,char name[13])4728 static int get_monitor_name(struct edid *edid, char name[13])
4729 {
4730 char *edid_name = NULL;
4731 int mnl;
4732
4733 if (!edid || !name)
4734 return 0;
4735
4736 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4737 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4738 if (edid_name[mnl] == 0x0a)
4739 break;
4740
4741 name[mnl] = edid_name[mnl];
4742 }
4743
4744 return mnl;
4745 }
4746
4747 /**
4748 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4749 * @edid: monitor EDID information
4750 * @name: pointer to a character array to hold the name of the monitor
4751 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4752 *
4753 */
drm_edid_get_monitor_name(struct edid * edid,char * name,int bufsize)4754 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4755 {
4756 int name_length;
4757 char buf[13];
4758
4759 if (bufsize <= 0)
4760 return;
4761
4762 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4763 memcpy(name, buf, name_length);
4764 name[name_length] = '\0';
4765 }
4766 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4767
clear_eld(struct drm_connector * connector)4768 static void clear_eld(struct drm_connector *connector)
4769 {
4770 memset(connector->eld, 0, sizeof(connector->eld));
4771
4772 connector->latency_present[0] = false;
4773 connector->latency_present[1] = false;
4774 connector->video_latency[0] = 0;
4775 connector->audio_latency[0] = 0;
4776 connector->video_latency[1] = 0;
4777 connector->audio_latency[1] = 0;
4778 }
4779
4780 /*
4781 * drm_edid_to_eld - build ELD from EDID
4782 * @connector: connector corresponding to the HDMI/DP sink
4783 * @edid: EDID to parse
4784 *
4785 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4786 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4787 */
drm_edid_to_eld(struct drm_connector * connector,struct edid * edid)4788 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4789 {
4790 uint8_t *eld = connector->eld;
4791 u8 *cea;
4792 u8 *db;
4793 int total_sad_count = 0;
4794 int mnl;
4795 int dbl;
4796
4797 clear_eld(connector);
4798
4799 if (!edid)
4800 return;
4801
4802 cea = drm_find_cea_extension(edid);
4803 if (!cea) {
4804 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4805 return;
4806 }
4807
4808 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4809 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4810
4811 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4812 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4813
4814 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4815
4816 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4817 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4818 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4819 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4820
4821 if (cea_revision(cea) >= 3) {
4822 int i, start, end;
4823 int sad_count;
4824
4825 if (cea_db_offsets(cea, &start, &end)) {
4826 start = 0;
4827 end = 0;
4828 }
4829
4830 for_each_cea_db(cea, i, start, end) {
4831 db = &cea[i];
4832 dbl = cea_db_payload_len(db);
4833
4834 switch (cea_db_tag(db)) {
4835 case AUDIO_BLOCK:
4836 /* Audio Data Block, contains SADs */
4837 sad_count = min(dbl / 3, 15 - total_sad_count);
4838 if (sad_count >= 1)
4839 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4840 &db[1], sad_count * 3);
4841 total_sad_count += sad_count;
4842 break;
4843 case SPEAKER_BLOCK:
4844 /* Speaker Allocation Data Block */
4845 if (dbl >= 1)
4846 eld[DRM_ELD_SPEAKER] = db[1];
4847 break;
4848 case VENDOR_BLOCK:
4849 /* HDMI Vendor-Specific Data Block */
4850 if (cea_db_is_hdmi_vsdb(db))
4851 drm_parse_hdmi_vsdb_audio(connector, db);
4852 break;
4853 default:
4854 break;
4855 }
4856 }
4857 }
4858 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4859
4860 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4861 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4862 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4863 else
4864 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4865
4866 eld[DRM_ELD_BASELINE_ELD_LEN] =
4867 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4868
4869 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4870 drm_eld_size(eld), total_sad_count);
4871 }
4872
4873 /**
4874 * drm_edid_to_sad - extracts SADs from EDID
4875 * @edid: EDID to parse
4876 * @sads: pointer that will be set to the extracted SADs
4877 *
4878 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4879 *
4880 * Note: The returned pointer needs to be freed using kfree().
4881 *
4882 * Return: The number of found SADs or negative number on error.
4883 */
drm_edid_to_sad(struct edid * edid,struct cea_sad ** sads)4884 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4885 {
4886 int count = 0;
4887 int i, start, end, dbl;
4888 u8 *cea;
4889
4890 cea = drm_find_cea_extension(edid);
4891 if (!cea) {
4892 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4893 return 0;
4894 }
4895
4896 if (cea_revision(cea) < 3) {
4897 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4898 return 0;
4899 }
4900
4901 if (cea_db_offsets(cea, &start, &end)) {
4902 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4903 return -EPROTO;
4904 }
4905
4906 for_each_cea_db(cea, i, start, end) {
4907 u8 *db = &cea[i];
4908
4909 if (cea_db_tag(db) == AUDIO_BLOCK) {
4910 int j;
4911
4912 dbl = cea_db_payload_len(db);
4913
4914 count = dbl / 3; /* SAD is 3B */
4915 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4916 if (!*sads)
4917 return -ENOMEM;
4918 for (j = 0; j < count; j++) {
4919 u8 *sad = &db[1 + j * 3];
4920
4921 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4922 (*sads)[j].channels = sad[0] & 0x7;
4923 (*sads)[j].freq = sad[1] & 0x7F;
4924 (*sads)[j].byte2 = sad[2];
4925 }
4926 break;
4927 }
4928 }
4929
4930 return count;
4931 }
4932 EXPORT_SYMBOL(drm_edid_to_sad);
4933
4934 /**
4935 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4936 * @edid: EDID to parse
4937 * @sadb: pointer to the speaker block
4938 *
4939 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4940 *
4941 * Note: The returned pointer needs to be freed using kfree().
4942 *
4943 * Return: The number of found Speaker Allocation Blocks or negative number on
4944 * error.
4945 */
drm_edid_to_speaker_allocation(struct edid * edid,u8 ** sadb)4946 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4947 {
4948 int count = 0;
4949 int i, start, end, dbl;
4950 const u8 *cea;
4951
4952 cea = drm_find_cea_extension(edid);
4953 if (!cea) {
4954 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4955 return 0;
4956 }
4957
4958 if (cea_revision(cea) < 3) {
4959 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4960 return 0;
4961 }
4962
4963 if (cea_db_offsets(cea, &start, &end)) {
4964 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4965 return -EPROTO;
4966 }
4967
4968 for_each_cea_db(cea, i, start, end) {
4969 const u8 *db = &cea[i];
4970
4971 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4972 dbl = cea_db_payload_len(db);
4973
4974 /* Speaker Allocation Data Block */
4975 if (dbl == 3) {
4976 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4977 if (!*sadb)
4978 return -ENOMEM;
4979 count = dbl;
4980 break;
4981 }
4982 }
4983 }
4984
4985 return count;
4986 }
4987 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4988
4989 /**
4990 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4991 * @connector: connector associated with the HDMI/DP sink
4992 * @mode: the display mode
4993 *
4994 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4995 * the sink doesn't support audio or video.
4996 */
drm_av_sync_delay(struct drm_connector * connector,const struct drm_display_mode * mode)4997 int drm_av_sync_delay(struct drm_connector *connector,
4998 const struct drm_display_mode *mode)
4999 {
5000 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5001 int a, v;
5002
5003 if (!connector->latency_present[0])
5004 return 0;
5005 if (!connector->latency_present[1])
5006 i = 0;
5007
5008 a = connector->audio_latency[i];
5009 v = connector->video_latency[i];
5010
5011 /*
5012 * HDMI/DP sink doesn't support audio or video?
5013 */
5014 if (a == 255 || v == 255)
5015 return 0;
5016
5017 /*
5018 * Convert raw EDID values to millisecond.
5019 * Treat unknown latency as 0ms.
5020 */
5021 if (a)
5022 a = min(2 * (a - 1), 500);
5023 if (v)
5024 v = min(2 * (v - 1), 500);
5025
5026 return max(v - a, 0);
5027 }
5028 EXPORT_SYMBOL(drm_av_sync_delay);
5029
5030 /**
5031 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5032 * @edid: monitor EDID information
5033 *
5034 * Parse the CEA extension according to CEA-861-B.
5035 *
5036 * Drivers that have added the modes parsed from EDID to drm_display_info
5037 * should use &drm_display_info.is_hdmi instead of calling this function.
5038 *
5039 * Return: True if the monitor is HDMI, false if not or unknown.
5040 */
drm_detect_hdmi_monitor(struct edid * edid)5041 bool drm_detect_hdmi_monitor(struct edid *edid)
5042 {
5043 u8 *edid_ext;
5044 int i;
5045 int start_offset, end_offset;
5046
5047 edid_ext = drm_find_cea_extension(edid);
5048 if (!edid_ext)
5049 return false;
5050
5051 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
5052 return false;
5053
5054 /*
5055 * Because HDMI identifier is in Vendor Specific Block,
5056 * search it from all data blocks of CEA extension.
5057 */
5058 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
5059 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
5060 return true;
5061 }
5062
5063 return false;
5064 }
5065 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5066
5067 /**
5068 * drm_detect_monitor_audio - check monitor audio capability
5069 * @edid: EDID block to scan
5070 *
5071 * Monitor should have CEA extension block.
5072 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5073 * audio' only. If there is any audio extension block and supported
5074 * audio format, assume at least 'basic audio' support, even if 'basic
5075 * audio' is not defined in EDID.
5076 *
5077 * Return: True if the monitor supports audio, false otherwise.
5078 */
drm_detect_monitor_audio(struct edid * edid)5079 bool drm_detect_monitor_audio(struct edid *edid)
5080 {
5081 u8 *edid_ext;
5082 int i, j;
5083 bool has_audio = false;
5084 int start_offset, end_offset;
5085
5086 edid_ext = drm_find_cea_extension(edid);
5087 if (!edid_ext)
5088 goto end;
5089
5090 has_audio = (edid_ext[0] == CEA_EXT &&
5091 (edid_ext[3] & EDID_BASIC_AUDIO) != 0);
5092
5093 if (has_audio) {
5094 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5095 goto end;
5096 }
5097
5098 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
5099 goto end;
5100
5101 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
5102 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
5103 has_audio = true;
5104 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
5105 DRM_DEBUG_KMS("CEA audio format %d\n",
5106 (edid_ext[i + j] >> 3) & 0xf);
5107 goto end;
5108 }
5109 }
5110 end:
5111 return has_audio;
5112 }
5113 EXPORT_SYMBOL(drm_detect_monitor_audio);
5114
5115
5116 /**
5117 * drm_default_rgb_quant_range - default RGB quantization range
5118 * @mode: display mode
5119 *
5120 * Determine the default RGB quantization range for the mode,
5121 * as specified in CEA-861.
5122 *
5123 * Return: The default RGB quantization range for the mode
5124 */
5125 enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode * mode)5126 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5127 {
5128 /* All CEA modes other than VIC 1 use limited quantization range. */
5129 return drm_match_cea_mode(mode) > 1 ?
5130 HDMI_QUANTIZATION_RANGE_LIMITED :
5131 HDMI_QUANTIZATION_RANGE_FULL;
5132 }
5133 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5134
drm_parse_vcdb(struct drm_connector * connector,const u8 * db)5135 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5136 {
5137 struct drm_display_info *info = &connector->display_info;
5138
5139 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
5140
5141 if (db[2] & EDID_CEA_VCDB_QS)
5142 info->rgb_quant_range_selectable = true;
5143 }
5144
5145 #ifdef CONFIG_NO_GKI
5146 static
drm_get_max_frl_rate(int max_frl_rate,u8 * max_lanes,u8 * max_rate_per_lane)5147 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5148 {
5149 switch (max_frl_rate) {
5150 case 1:
5151 *max_lanes = 3;
5152 *max_rate_per_lane = 3;
5153 break;
5154 case 2:
5155 *max_lanes = 3;
5156 *max_rate_per_lane = 6;
5157 break;
5158 case 3:
5159 *max_lanes = 4;
5160 *max_rate_per_lane = 6;
5161 break;
5162 case 4:
5163 *max_lanes = 4;
5164 *max_rate_per_lane = 8;
5165 break;
5166 case 5:
5167 *max_lanes = 4;
5168 *max_rate_per_lane = 10;
5169 break;
5170 case 6:
5171 *max_lanes = 4;
5172 *max_rate_per_lane = 12;
5173 break;
5174 case 0:
5175 default:
5176 *max_lanes = 0;
5177 *max_rate_per_lane = 0;
5178 }
5179 }
5180 #endif
5181
drm_parse_ycbcr420_deep_color_info(struct drm_connector * connector,const u8 * db)5182 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5183 const u8 *db)
5184 {
5185 u8 dc_mask;
5186 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5187
5188 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5189 hdmi->y420_dc_modes = dc_mask;
5190 }
5191
drm_parse_hdmi_forum_vsdb(struct drm_connector * connector,const u8 * hf_vsdb)5192 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
5193 const u8 *hf_vsdb)
5194 {
5195 struct drm_display_info *display = &connector->display_info;
5196 struct drm_hdmi_info *hdmi = &display->hdmi;
5197
5198 display->has_hdmi_infoframe = true;
5199
5200 if (hf_vsdb[6] & 0x80) {
5201 hdmi->scdc.supported = true;
5202 if (hf_vsdb[6] & 0x40)
5203 hdmi->scdc.read_request = true;
5204 }
5205
5206 /*
5207 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5208 * And as per the spec, three factors confirm this:
5209 * * Availability of a HF-VSDB block in EDID (check)
5210 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5211 * * SCDC support available (let's check)
5212 * Lets check it out.
5213 */
5214
5215 if (hf_vsdb[5]) {
5216 /* max clock is 5000 KHz times block value */
5217 u32 max_tmds_clock = hf_vsdb[5] * 5000;
5218 struct drm_scdc *scdc = &hdmi->scdc;
5219
5220 if (max_tmds_clock > 340000) {
5221 display->max_tmds_clock = max_tmds_clock;
5222 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5223 display->max_tmds_clock);
5224 }
5225
5226 if (scdc->supported) {
5227 scdc->scrambling.supported = true;
5228
5229 /* Few sinks support scrambling for clocks < 340M */
5230 if ((hf_vsdb[6] & 0x8))
5231 scdc->scrambling.low_rates = true;
5232 }
5233 }
5234
5235 #ifdef CONFIG_NO_GKI
5236 if (hf_vsdb[7]) {
5237 u8 max_frl_rate;
5238 u8 dsc_max_frl_rate;
5239 u8 dsc_max_slices;
5240 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5241
5242 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5243 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5244 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5245 &hdmi->max_frl_rate_per_lane);
5246 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2;
5247
5248 if (hdmi_dsc->v_1p2) {
5249 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420;
5250 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP;
5251
5252 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC)
5253 hdmi_dsc->bpc_supported = 16;
5254 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC)
5255 hdmi_dsc->bpc_supported = 12;
5256 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC)
5257 hdmi_dsc->bpc_supported = 10;
5258 else
5259 hdmi_dsc->bpc_supported = 0;
5260
5261 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5262 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5263 &hdmi_dsc->max_frl_rate_per_lane);
5264 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5265
5266 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES;
5267 switch (dsc_max_slices) {
5268 case 1:
5269 hdmi_dsc->max_slices = 1;
5270 hdmi_dsc->clk_per_slice = 340;
5271 break;
5272 case 2:
5273 hdmi_dsc->max_slices = 2;
5274 hdmi_dsc->clk_per_slice = 340;
5275 break;
5276 case 3:
5277 hdmi_dsc->max_slices = 4;
5278 hdmi_dsc->clk_per_slice = 340;
5279 break;
5280 case 4:
5281 hdmi_dsc->max_slices = 8;
5282 hdmi_dsc->clk_per_slice = 340;
5283 break;
5284 case 5:
5285 hdmi_dsc->max_slices = 8;
5286 hdmi_dsc->clk_per_slice = 400;
5287 break;
5288 case 6:
5289 hdmi_dsc->max_slices = 12;
5290 hdmi_dsc->clk_per_slice = 400;
5291 break;
5292 case 7:
5293 hdmi_dsc->max_slices = 16;
5294 hdmi_dsc->clk_per_slice = 400;
5295 break;
5296 case 0:
5297 default:
5298 hdmi_dsc->max_slices = 0;
5299 hdmi_dsc->clk_per_slice = 0;
5300 }
5301 }
5302 }
5303 #endif
5304
5305 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
5306 }
5307
drm_parse_hdmi_deep_color_info(struct drm_connector * connector,const u8 * hdmi)5308 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5309 const u8 *hdmi)
5310 {
5311 struct drm_display_info *info = &connector->display_info;
5312 unsigned int dc_bpc = 0;
5313
5314 /* HDMI supports at least 8 bpc */
5315 info->bpc = 8;
5316
5317 if (cea_db_payload_len(hdmi) < 6)
5318 return;
5319
5320 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5321 dc_bpc = 10;
5322 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
5323 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5324 connector->name);
5325 }
5326
5327 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5328 dc_bpc = 12;
5329 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
5330 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5331 connector->name);
5332 }
5333
5334 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5335 dc_bpc = 16;
5336 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
5337 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5338 connector->name);
5339 }
5340
5341 if (dc_bpc == 0) {
5342 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5343 connector->name);
5344 return;
5345 }
5346
5347 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5348 connector->name, dc_bpc);
5349 info->bpc = dc_bpc;
5350
5351 /* YCRCB444 is optional according to spec. */
5352 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
5353 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5354 connector->name);
5355 }
5356
5357 /*
5358 * Spec says that if any deep color mode is supported at all,
5359 * then deep color 36 bit must be supported.
5360 */
5361 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5362 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5363 connector->name);
5364 }
5365 }
5366
5367 static void
drm_parse_hdmi_vsdb_video(struct drm_connector * connector,const u8 * db)5368 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5369 {
5370 struct drm_display_info *info = &connector->display_info;
5371 u8 len = cea_db_payload_len(db);
5372
5373 info->is_hdmi = true;
5374
5375 if (len >= 6)
5376 info->dvi_dual = db[6] & 1;
5377 if (len >= 7)
5378 info->max_tmds_clock = db[7] * 5000;
5379
5380 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5381 "max TMDS clock %d kHz\n",
5382 info->dvi_dual,
5383 info->max_tmds_clock);
5384
5385 drm_parse_hdmi_deep_color_info(connector, db);
5386 }
5387
drm_parse_cea_ext(struct drm_connector * connector,const struct edid * edid)5388 static void drm_parse_cea_ext(struct drm_connector *connector,
5389 const struct edid *edid)
5390 {
5391 struct drm_display_info *info = &connector->display_info;
5392 const u8 *edid_ext;
5393 int i, start, end;
5394
5395 edid_ext = drm_find_cea_extension(edid);
5396 if (!edid_ext)
5397 return;
5398
5399 info->cea_rev = edid_ext[1];
5400
5401 /* The existence of a CEA block should imply RGB support */
5402 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5403 if (edid_ext[3] & EDID_CEA_YCRCB444)
5404 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5405 if (edid_ext[3] & EDID_CEA_YCRCB422)
5406 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5407
5408 if (cea_db_offsets(edid_ext, &start, &end))
5409 return;
5410
5411 for_each_cea_db(edid_ext, i, start, end) {
5412 const u8 *db = &edid_ext[i];
5413
5414 if (cea_db_is_hdmi_vsdb(db))
5415 drm_parse_hdmi_vsdb_video(connector, db);
5416 if (cea_db_is_hdmi_forum_vsdb(db))
5417 drm_parse_hdmi_forum_vsdb(connector, db);
5418 if (cea_db_is_y420cmdb(db))
5419 drm_parse_y420cmdb_bitmap(connector, db);
5420 if (cea_db_is_vcdb(db))
5421 drm_parse_vcdb(connector, db);
5422 if (cea_db_is_hdmi_hdr_metadata_block(db))
5423 drm_parse_hdr_metadata_block(connector, db);
5424 }
5425 }
5426
5427 static
get_monitor_range(struct detailed_timing * timing,void * info_monitor_range)5428 void get_monitor_range(struct detailed_timing *timing,
5429 void *info_monitor_range)
5430 {
5431 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5432 const struct detailed_non_pixel *data = &timing->data.other_data;
5433 const struct detailed_data_monitor_range *range = &data->data.range;
5434
5435 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
5436 return;
5437
5438 /*
5439 * Check for flag range limits only. If flag == 1 then
5440 * no additional timing information provided.
5441 * Default GTF, GTF Secondary curve and CVT are not
5442 * supported
5443 */
5444 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5445 return;
5446
5447 monitor_range->min_vfreq = range->min_vfreq;
5448 monitor_range->max_vfreq = range->max_vfreq;
5449 }
5450
5451 static
drm_get_monitor_range(struct drm_connector * connector,const struct edid * edid)5452 void drm_get_monitor_range(struct drm_connector *connector,
5453 const struct edid *edid)
5454 {
5455 struct drm_display_info *info = &connector->display_info;
5456
5457 if (!version_greater(edid, 1, 1))
5458 return;
5459
5460 drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
5461 &info->monitor_range);
5462
5463 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5464 info->monitor_range.min_vfreq,
5465 info->monitor_range.max_vfreq);
5466 }
5467
5468 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5469 * all of the values which would have been set from EDID
5470 */
5471 void
drm_reset_display_info(struct drm_connector * connector)5472 drm_reset_display_info(struct drm_connector *connector)
5473 {
5474 struct drm_display_info *info = &connector->display_info;
5475
5476 info->width_mm = 0;
5477 info->height_mm = 0;
5478
5479 info->bpc = 0;
5480 info->color_formats = 0;
5481 info->cea_rev = 0;
5482 info->max_tmds_clock = 0;
5483 info->dvi_dual = false;
5484 info->is_hdmi = false;
5485 info->has_hdmi_infoframe = false;
5486 info->rgb_quant_range_selectable = false;
5487 memset(&info->hdmi, 0, sizeof(info->hdmi));
5488
5489 info->non_desktop = 0;
5490 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5491 }
5492
drm_add_display_info(struct drm_connector * connector,const struct edid * edid)5493 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
5494 {
5495 struct drm_display_info *info = &connector->display_info;
5496
5497 u32 quirks = edid_get_quirks(edid);
5498
5499 drm_reset_display_info(connector);
5500
5501 info->width_mm = edid->width_cm * 10;
5502 info->height_mm = edid->height_cm * 10;
5503
5504 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
5505
5506 drm_get_monitor_range(connector, edid);
5507
5508 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
5509
5510 if (edid->revision < 3)
5511 return quirks;
5512
5513 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
5514 return quirks;
5515
5516 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5517 drm_parse_cea_ext(connector, edid);
5518
5519 /*
5520 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5521 *
5522 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5523 * tells us to assume 8 bpc color depth if the EDID doesn't have
5524 * extensions which tell otherwise.
5525 */
5526 if (info->bpc == 0 && edid->revision == 3 &&
5527 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
5528 info->bpc = 8;
5529 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5530 connector->name, info->bpc);
5531 }
5532
5533 /* Only defined for 1.4 with digital displays */
5534 if (edid->revision < 4)
5535 return quirks;
5536
5537 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5538 case DRM_EDID_DIGITAL_DEPTH_6:
5539 info->bpc = 6;
5540 break;
5541 case DRM_EDID_DIGITAL_DEPTH_8:
5542 info->bpc = 8;
5543 break;
5544 case DRM_EDID_DIGITAL_DEPTH_10:
5545 info->bpc = 10;
5546 break;
5547 case DRM_EDID_DIGITAL_DEPTH_12:
5548 info->bpc = 12;
5549 break;
5550 case DRM_EDID_DIGITAL_DEPTH_14:
5551 info->bpc = 14;
5552 break;
5553 case DRM_EDID_DIGITAL_DEPTH_16:
5554 info->bpc = 16;
5555 break;
5556 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5557 default:
5558 info->bpc = 0;
5559 break;
5560 }
5561
5562 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
5563 connector->name, info->bpc);
5564
5565 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5566 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5567 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5568 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5569 return quirks;
5570 }
5571
validate_displayid(u8 * displayid,int length,int idx)5572 static int validate_displayid(u8 *displayid, int length, int idx)
5573 {
5574 int i, dispid_length;
5575 u8 csum = 0;
5576 struct displayid_hdr *base;
5577
5578 base = (struct displayid_hdr *)&displayid[idx];
5579
5580 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
5581 base->rev, base->bytes, base->prod_id, base->ext_count);
5582
5583 /* +1 for DispID checksum */
5584 dispid_length = sizeof(*base) + base->bytes + 1;
5585 if (dispid_length > length - idx)
5586 return -EINVAL;
5587
5588 for (i = 0; i < dispid_length; i++)
5589 csum += displayid[idx + i];
5590 if (csum) {
5591 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
5592 return -EINVAL;
5593 }
5594
5595 return 0;
5596 }
5597
drm_mode_displayid_detailed(struct drm_device * dev,struct displayid_detailed_timings_1 * timings)5598 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5599 struct displayid_detailed_timings_1 *timings)
5600 {
5601 struct drm_display_mode *mode;
5602 unsigned pixel_clock = (timings->pixel_clock[0] |
5603 (timings->pixel_clock[1] << 8) |
5604 (timings->pixel_clock[2] << 16)) + 1;
5605 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5606 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5607 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5608 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5609 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5610 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5611 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5612 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5613 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5614 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5615
5616 mode = drm_mode_create(dev);
5617 if (!mode)
5618 return NULL;
5619
5620 mode->clock = pixel_clock * 10;
5621 mode->hdisplay = hactive;
5622 mode->hsync_start = mode->hdisplay + hsync;
5623 mode->hsync_end = mode->hsync_start + hsync_width;
5624 mode->htotal = mode->hdisplay + hblank;
5625
5626 mode->vdisplay = vactive;
5627 mode->vsync_start = mode->vdisplay + vsync;
5628 mode->vsync_end = mode->vsync_start + vsync_width;
5629 mode->vtotal = mode->vdisplay + vblank;
5630
5631 mode->flags = 0;
5632 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5633 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5634 mode->type = DRM_MODE_TYPE_DRIVER;
5635
5636 if (timings->flags & 0x80)
5637 mode->type |= DRM_MODE_TYPE_PREFERRED;
5638 drm_mode_set_name(mode);
5639
5640 return mode;
5641 }
5642
add_displayid_detailed_1_modes(struct drm_connector * connector,struct displayid_block * block)5643 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5644 struct displayid_block *block)
5645 {
5646 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5647 int i;
5648 int num_timings;
5649 struct drm_display_mode *newmode;
5650 int num_modes = 0;
5651 /* blocks must be multiple of 20 bytes length */
5652 if (block->num_bytes % 20)
5653 return 0;
5654
5655 num_timings = block->num_bytes / 20;
5656 for (i = 0; i < num_timings; i++) {
5657 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5658
5659 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5660 if (!newmode)
5661 continue;
5662
5663 drm_mode_probed_add(connector, newmode);
5664 num_modes++;
5665 }
5666 return num_modes;
5667 }
5668
add_displayid_detailed_modes(struct drm_connector * connector,struct edid * edid)5669 static int add_displayid_detailed_modes(struct drm_connector *connector,
5670 struct edid *edid)
5671 {
5672 u8 *displayid;
5673 int length, idx;
5674 struct displayid_block *block;
5675 int num_modes = 0;
5676 int ext_index = 0;
5677
5678 for (;;) {
5679 displayid = drm_find_displayid_extension(edid, &length, &idx,
5680 &ext_index);
5681 if (!displayid)
5682 break;
5683
5684 idx += sizeof(struct displayid_hdr);
5685 for_each_displayid_db(displayid, block, idx, length) {
5686 switch (block->tag) {
5687 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5688 num_modes += add_displayid_detailed_1_modes(connector, block);
5689 break;
5690 }
5691 }
5692 }
5693
5694 return num_modes;
5695 }
5696
5697 /**
5698 * drm_add_edid_modes - add modes from EDID data, if available
5699 * @connector: connector we're probing
5700 * @edid: EDID data
5701 *
5702 * Add the specified modes to the connector's mode list. Also fills out the
5703 * &drm_display_info structure and ELD in @connector with any information which
5704 * can be derived from the edid.
5705 *
5706 * Return: The number of modes added or 0 if we couldn't find any.
5707 */
drm_add_edid_modes(struct drm_connector * connector,struct edid * edid)5708 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5709 {
5710 int num_modes = 0;
5711 u32 quirks;
5712
5713 if (edid == NULL) {
5714 clear_eld(connector);
5715 return 0;
5716 }
5717 if (!drm_edid_is_valid(edid)) {
5718 clear_eld(connector);
5719 drm_warn(connector->dev, "%s: EDID invalid.\n",
5720 connector->name);
5721 return 0;
5722 }
5723
5724 drm_edid_to_eld(connector, edid);
5725
5726 /*
5727 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5728 * To avoid multiple parsing of same block, lets parse that map
5729 * from sink info, before parsing CEA modes.
5730 */
5731 quirks = drm_add_display_info(connector, edid);
5732
5733 /*
5734 * EDID spec says modes should be preferred in this order:
5735 * - preferred detailed mode
5736 * - other detailed modes from base block
5737 * - detailed modes from extension blocks
5738 * - CVT 3-byte code modes
5739 * - standard timing codes
5740 * - established timing codes
5741 * - modes inferred from GTF or CVT range information
5742 *
5743 * We get this pretty much right.
5744 *
5745 * XXX order for additional mode types in extension blocks?
5746 */
5747 num_modes += add_detailed_modes(connector, edid, quirks);
5748 num_modes += add_cvt_modes(connector, edid);
5749 num_modes += add_standard_modes(connector, edid);
5750 num_modes += add_established_modes(connector, edid);
5751 num_modes += add_cea_modes(connector, edid);
5752 num_modes += add_alternate_cea_modes(connector, edid);
5753 num_modes += add_displayid_detailed_modes(connector, edid);
5754 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5755 num_modes += add_inferred_modes(connector, edid);
5756
5757 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5758 edid_fixup_preferred(connector, quirks);
5759
5760 if (quirks & EDID_QUIRK_FORCE_6BPC)
5761 connector->display_info.bpc = 6;
5762
5763 if (quirks & EDID_QUIRK_FORCE_8BPC)
5764 connector->display_info.bpc = 8;
5765
5766 if (quirks & EDID_QUIRK_FORCE_10BPC)
5767 connector->display_info.bpc = 10;
5768
5769 if (quirks & EDID_QUIRK_FORCE_12BPC)
5770 connector->display_info.bpc = 12;
5771
5772 return num_modes;
5773 }
5774 EXPORT_SYMBOL(drm_add_edid_modes);
5775
5776 /**
5777 * drm_add_modes_noedid - add modes for the connectors without EDID
5778 * @connector: connector we're probing
5779 * @hdisplay: the horizontal display limit
5780 * @vdisplay: the vertical display limit
5781 *
5782 * Add the specified modes to the connector's mode list. Only when the
5783 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5784 *
5785 * Return: The number of modes added or 0 if we couldn't find any.
5786 */
drm_add_modes_noedid(struct drm_connector * connector,int hdisplay,int vdisplay)5787 int drm_add_modes_noedid(struct drm_connector *connector,
5788 int hdisplay, int vdisplay)
5789 {
5790 int i, count, num_modes = 0;
5791 struct drm_display_mode *mode;
5792 struct drm_device *dev = connector->dev;
5793
5794 count = ARRAY_SIZE(drm_dmt_modes);
5795 if (hdisplay < 0)
5796 hdisplay = 0;
5797 if (vdisplay < 0)
5798 vdisplay = 0;
5799
5800 for (i = 0; i < count; i++) {
5801 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5802
5803 if (hdisplay && vdisplay) {
5804 /*
5805 * Only when two are valid, they will be used to check
5806 * whether the mode should be added to the mode list of
5807 * the connector.
5808 */
5809 if (ptr->hdisplay > hdisplay ||
5810 ptr->vdisplay > vdisplay)
5811 continue;
5812 }
5813 if (drm_mode_vrefresh(ptr) > 61)
5814 continue;
5815 mode = drm_mode_duplicate(dev, ptr);
5816 if (mode) {
5817 drm_mode_probed_add(connector, mode);
5818 num_modes++;
5819 }
5820 }
5821 return num_modes;
5822 }
5823 EXPORT_SYMBOL(drm_add_modes_noedid);
5824
5825 /**
5826 * drm_set_preferred_mode - Sets the preferred mode of a connector
5827 * @connector: connector whose mode list should be processed
5828 * @hpref: horizontal resolution of preferred mode
5829 * @vpref: vertical resolution of preferred mode
5830 *
5831 * Marks a mode as preferred if it matches the resolution specified by @hpref
5832 * and @vpref.
5833 */
drm_set_preferred_mode(struct drm_connector * connector,int hpref,int vpref)5834 void drm_set_preferred_mode(struct drm_connector *connector,
5835 int hpref, int vpref)
5836 {
5837 struct drm_display_mode *mode;
5838
5839 list_for_each_entry(mode, &connector->probed_modes, head) {
5840 if (mode->hdisplay == hpref &&
5841 mode->vdisplay == vpref)
5842 mode->type |= DRM_MODE_TYPE_PREFERRED;
5843 }
5844 }
5845 EXPORT_SYMBOL(drm_set_preferred_mode);
5846
is_hdmi2_sink(const struct drm_connector * connector)5847 static bool is_hdmi2_sink(const struct drm_connector *connector)
5848 {
5849 /*
5850 * FIXME: sil-sii8620 doesn't have a connector around when
5851 * we need one, so we have to be prepared for a NULL connector.
5852 */
5853 if (!connector)
5854 return true;
5855
5856 return connector->display_info.hdmi.scdc.supported ||
5857 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5858 }
5859
is_eotf_supported(u8 output_eotf,u8 sink_eotf)5860 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5861 {
5862 return sink_eotf & BIT(output_eotf);
5863 }
5864
5865 /**
5866 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5867 * HDR metadata from userspace
5868 * @frame: HDMI DRM infoframe
5869 * @conn_state: Connector state containing HDR metadata
5870 *
5871 * Return: 0 on success or a negative error code on failure.
5872 */
5873 int
drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe * frame,const struct drm_connector_state * conn_state)5874 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5875 const struct drm_connector_state *conn_state)
5876 {
5877 struct drm_connector *connector;
5878 struct hdr_output_metadata *hdr_metadata;
5879 int err;
5880
5881 if (!frame || !conn_state)
5882 return -EINVAL;
5883
5884 connector = conn_state->connector;
5885
5886 if (!conn_state->hdr_output_metadata)
5887 return -EINVAL;
5888
5889 hdr_metadata = conn_state->hdr_output_metadata->data;
5890
5891 if (!hdr_metadata || !connector)
5892 return -EINVAL;
5893
5894 /* Sink EOTF is Bit map while infoframe is absolute values */
5895 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5896 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5897 DRM_DEBUG_KMS("EOTF Not Supported\n");
5898 return -EINVAL;
5899 }
5900
5901 err = hdmi_drm_infoframe_init(frame);
5902 if (err < 0)
5903 return err;
5904
5905 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5906 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5907
5908 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5909 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5910 BUILD_BUG_ON(sizeof(frame->white_point) !=
5911 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5912
5913 memcpy(&frame->display_primaries,
5914 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5915 sizeof(frame->display_primaries));
5916
5917 memcpy(&frame->white_point,
5918 &hdr_metadata->hdmi_metadata_type1.white_point,
5919 sizeof(frame->white_point));
5920
5921 frame->max_display_mastering_luminance =
5922 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5923 frame->min_display_mastering_luminance =
5924 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5925 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5926 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5927
5928 return 0;
5929 }
5930 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5931
drm_mode_hdmi_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)5932 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
5933 const struct drm_display_mode *mode)
5934 {
5935 bool has_hdmi_infoframe = connector ?
5936 connector->display_info.has_hdmi_infoframe : false;
5937
5938 if (!has_hdmi_infoframe)
5939 return 0;
5940
5941 /* No HDMI VIC when signalling 3D video format */
5942 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5943 return 0;
5944
5945 return drm_match_hdmi_mode(mode);
5946 }
5947
drm_mode_cea_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)5948 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
5949 const struct drm_display_mode *mode)
5950 {
5951 u8 vic;
5952
5953 /*
5954 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5955 * we should send its VIC in vendor infoframes, else send the
5956 * VIC in AVI infoframes. Lets check if this mode is present in
5957 * HDMI 1.4b 4K modes
5958 */
5959 if (drm_mode_hdmi_vic(connector, mode))
5960 return 0;
5961
5962 vic = drm_match_cea_mode(mode);
5963
5964 /*
5965 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5966 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5967 * have to make sure we dont break HDMI 1.4 sinks.
5968 */
5969 if (!is_hdmi2_sink(connector) && vic > 64)
5970 return 0;
5971
5972 return vic;
5973 }
5974
5975 /**
5976 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5977 * data from a DRM display mode
5978 * @frame: HDMI AVI infoframe
5979 * @connector: the connector
5980 * @mode: DRM display mode
5981 *
5982 * Return: 0 on success or a negative error code on failure.
5983 */
5984 int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)5985 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5986 const struct drm_connector *connector,
5987 const struct drm_display_mode *mode)
5988 {
5989 enum hdmi_picture_aspect picture_aspect;
5990 u8 vic, hdmi_vic;
5991
5992 if (!frame || !mode)
5993 return -EINVAL;
5994
5995 hdmi_avi_infoframe_init(frame);
5996
5997 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5998 frame->pixel_repeat = 1;
5999
6000 vic = drm_mode_cea_vic(connector, mode);
6001 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
6002
6003 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6004
6005 /*
6006 * As some drivers don't support atomic, we can't use connector state.
6007 * So just initialize the frame with default values, just the same way
6008 * as it's done with other properties here.
6009 */
6010 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6011 frame->itc = 0;
6012
6013 /*
6014 * Populate picture aspect ratio from either
6015 * user input (if specified) or from the CEA/HDMI mode lists.
6016 */
6017 picture_aspect = mode->picture_aspect_ratio;
6018 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6019 if (vic)
6020 picture_aspect = drm_get_cea_aspect_ratio(vic);
6021 else if (hdmi_vic)
6022 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6023 }
6024
6025 /*
6026 * The infoframe can't convey anything but none, 4:3
6027 * and 16:9, so if the user has asked for anything else
6028 * we can only satisfy it by specifying the right VIC.
6029 */
6030 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
6031 if (vic) {
6032 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6033 return -EINVAL;
6034 } else if (hdmi_vic) {
6035 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6036 return -EINVAL;
6037 } else {
6038 return -EINVAL;
6039 }
6040
6041 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6042 }
6043
6044 frame->video_code = vic;
6045 frame->picture_aspect = picture_aspect;
6046 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
6047 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
6048
6049 return 0;
6050 }
6051 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
6052
6053 /* HDMI Colorspace Spec Definitions */
6054 #define FULL_COLORIMETRY_MASK 0x1FF
6055 #define NORMAL_COLORIMETRY_MASK 0x3
6056 #define EXTENDED_COLORIMETRY_MASK 0x7
6057 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
6058
6059 #define C(x) ((x) << 0)
6060 #define EC(x) ((x) << 2)
6061 #define ACE(x) ((x) << 5)
6062
6063 #define HDMI_COLORIMETRY_NO_DATA 0x0
6064 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
6065 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
6066 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
6067 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
6068 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
6069 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
6070 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
6071 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
6072 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
6073 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
6074 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
6075 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
6076
6077 static const u32 hdmi_colorimetry_val[] = {
6078 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
6079 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
6080 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
6081 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
6082 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
6083 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
6084 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
6085 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
6086 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
6087 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
6088 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
6089 };
6090
6091 #undef C
6092 #undef EC
6093 #undef ACE
6094
6095 /**
6096 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
6097 * colorspace information
6098 * @frame: HDMI AVI infoframe
6099 * @conn_state: connector state
6100 */
6101 void
drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe * frame,const struct drm_connector_state * conn_state)6102 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
6103 const struct drm_connector_state *conn_state)
6104 {
6105 u32 colorimetry_val;
6106 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
6107
6108 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
6109 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
6110 else
6111 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
6112
6113 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
6114 /*
6115 * ToDo: Extend it for ACE formats as well. Modify the infoframe
6116 * structure and extend it in drivers/video/hdmi
6117 */
6118 frame->extended_colorimetry = (colorimetry_val >> 2) &
6119 EXTENDED_COLORIMETRY_MASK;
6120 }
6121 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
6122
6123 /**
6124 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6125 * quantization range information
6126 * @frame: HDMI AVI infoframe
6127 * @connector: the connector
6128 * @mode: DRM display mode
6129 * @rgb_quant_range: RGB quantization range (Q)
6130 */
6131 void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode,enum hdmi_quantization_range rgb_quant_range)6132 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
6133 const struct drm_connector *connector,
6134 const struct drm_display_mode *mode,
6135 enum hdmi_quantization_range rgb_quant_range)
6136 {
6137 const struct drm_display_info *info = &connector->display_info;
6138
6139 /*
6140 * CEA-861:
6141 * "A Source shall not send a non-zero Q value that does not correspond
6142 * to the default RGB Quantization Range for the transmitted Picture
6143 * unless the Sink indicates support for the Q bit in a Video
6144 * Capabilities Data Block."
6145 *
6146 * HDMI 2.0 recommends sending non-zero Q when it does match the
6147 * default RGB quantization range for the mode, even when QS=0.
6148 */
6149 if (info->rgb_quant_range_selectable ||
6150 rgb_quant_range == drm_default_rgb_quant_range(mode))
6151 frame->quantization_range = rgb_quant_range;
6152 else
6153 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
6154
6155 /*
6156 * CEA-861-F:
6157 * "When transmitting any RGB colorimetry, the Source should set the
6158 * YQ-field to match the RGB Quantization Range being transmitted
6159 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6160 * set YQ=1) and the Sink shall ignore the YQ-field."
6161 *
6162 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6163 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6164 * good way to tell which version of CEA-861 the sink supports, so
6165 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6166 * on on CEA-861-F.
6167 */
6168 if (!is_hdmi2_sink(connector) ||
6169 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
6170 frame->ycc_quantization_range =
6171 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6172 else
6173 frame->ycc_quantization_range =
6174 HDMI_YCC_QUANTIZATION_RANGE_FULL;
6175 }
6176 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6177
6178 /**
6179 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
6180 * bar information
6181 * @frame: HDMI AVI infoframe
6182 * @conn_state: connector state
6183 */
6184 void
drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe * frame,const struct drm_connector_state * conn_state)6185 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
6186 const struct drm_connector_state *conn_state)
6187 {
6188 frame->right_bar = conn_state->tv.margins.right;
6189 frame->left_bar = conn_state->tv.margins.left;
6190 frame->top_bar = conn_state->tv.margins.top;
6191 frame->bottom_bar = conn_state->tv.margins.bottom;
6192 }
6193 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
6194
6195 static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode * mode)6196 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6197 {
6198 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6199
6200 switch (layout) {
6201 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6202 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6203 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6204 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6205 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6206 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6207 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6208 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6209 case DRM_MODE_FLAG_3D_L_DEPTH:
6210 return HDMI_3D_STRUCTURE_L_DEPTH;
6211 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6212 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6213 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6214 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6215 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6216 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6217 default:
6218 return HDMI_3D_STRUCTURE_INVALID;
6219 }
6220 }
6221
6222 /**
6223 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6224 * data from a DRM display mode
6225 * @frame: HDMI vendor infoframe
6226 * @connector: the connector
6227 * @mode: DRM display mode
6228 *
6229 * Note that there's is a need to send HDMI vendor infoframes only when using a
6230 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6231 * function will return -EINVAL, error that can be safely ignored.
6232 *
6233 * Return: 0 on success or a negative error code on failure.
6234 */
6235 int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)6236 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
6237 const struct drm_connector *connector,
6238 const struct drm_display_mode *mode)
6239 {
6240 /*
6241 * FIXME: sil-sii8620 doesn't have a connector around when
6242 * we need one, so we have to be prepared for a NULL connector.
6243 */
6244 bool has_hdmi_infoframe = connector ?
6245 connector->display_info.has_hdmi_infoframe : false;
6246 int err;
6247
6248 if (!frame || !mode)
6249 return -EINVAL;
6250
6251 if (!has_hdmi_infoframe)
6252 return -EINVAL;
6253
6254 err = hdmi_vendor_infoframe_init(frame);
6255 if (err < 0)
6256 return err;
6257
6258 /*
6259 * Even if it's not absolutely necessary to send the infoframe
6260 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6261 * know that the sink can handle it. This is based on a
6262 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
6263 * have trouble realizing that they shuld switch from 3D to 2D
6264 * mode if the source simply stops sending the infoframe when
6265 * it wants to switch from 3D to 2D.
6266 */
6267 frame->vic = drm_mode_hdmi_vic(connector, mode);
6268 frame->s3d_struct = s3d_structure_from_display_mode(mode);
6269
6270 return 0;
6271 }
6272 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
6273
drm_parse_tiled_block(struct drm_connector * connector,const struct displayid_block * block)6274 static void drm_parse_tiled_block(struct drm_connector *connector,
6275 const struct displayid_block *block)
6276 {
6277 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
6278 u16 w, h;
6279 u8 tile_v_loc, tile_h_loc;
6280 u8 num_v_tile, num_h_tile;
6281 struct drm_tile_group *tg;
6282
6283 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6284 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6285
6286 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6287 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6288 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6289 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6290
6291 connector->has_tile = true;
6292 if (tile->tile_cap & 0x80)
6293 connector->tile_is_single_monitor = true;
6294
6295 connector->num_h_tile = num_h_tile + 1;
6296 connector->num_v_tile = num_v_tile + 1;
6297 connector->tile_h_loc = tile_h_loc;
6298 connector->tile_v_loc = tile_v_loc;
6299 connector->tile_h_size = w + 1;
6300 connector->tile_v_size = h + 1;
6301
6302 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6303 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6304 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6305 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6306 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6307
6308 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
6309 if (!tg)
6310 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
6311 if (!tg)
6312 return;
6313
6314 if (connector->tile_group != tg) {
6315 /* if we haven't got a pointer,
6316 take the reference, drop ref to old tile group */
6317 if (connector->tile_group)
6318 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6319 connector->tile_group = tg;
6320 } else {
6321 /* if same tile group, then release the ref we just took. */
6322 drm_mode_put_tile_group(connector->dev, tg);
6323 }
6324 }
6325
drm_displayid_parse_tiled(struct drm_connector * connector,const u8 * displayid,int length,int idx)6326 static void drm_displayid_parse_tiled(struct drm_connector *connector,
6327 const u8 *displayid, int length, int idx)
6328 {
6329 const struct displayid_block *block;
6330
6331 idx += sizeof(struct displayid_hdr);
6332 for_each_displayid_db(displayid, block, idx, length) {
6333 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
6334 block->tag, block->rev, block->num_bytes);
6335
6336 switch (block->tag) {
6337 case DATA_BLOCK_TILED_DISPLAY:
6338 drm_parse_tiled_block(connector, block);
6339 break;
6340 default:
6341 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
6342 break;
6343 }
6344 }
6345 }
6346
drm_update_tile_info(struct drm_connector * connector,const struct edid * edid)6347 void drm_update_tile_info(struct drm_connector *connector,
6348 const struct edid *edid)
6349 {
6350 const void *displayid = NULL;
6351 int ext_index = 0;
6352 int length, idx;
6353
6354 connector->has_tile = false;
6355 for (;;) {
6356 displayid = drm_find_displayid_extension(edid, &length, &idx,
6357 &ext_index);
6358 if (!displayid)
6359 break;
6360
6361 drm_displayid_parse_tiled(connector, displayid, length, idx);
6362 }
6363
6364 if (!connector->has_tile && connector->tile_group) {
6365 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6366 connector->tile_group = NULL;
6367 }
6368 }
6369