1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * dw-hdmi-qp-i2s-audio.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
6*4882a593Smuzhiyun * Author: Sugar Zhang <sugar.zhang@rock-chips.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/dma-mapping.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <drm/bridge/dw_hdmi.h>
13*4882a593Smuzhiyun #include <drm/drm_crtc.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <sound/hdmi-codec.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "dw-hdmi-qp.h"
18*4882a593Smuzhiyun #include "dw-hdmi-qp-audio.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define DRIVER_NAME "dw-hdmi-qp-i2s-audio"
21*4882a593Smuzhiyun
hdmi_write(struct dw_hdmi_qp_i2s_audio_data * audio,u32 val,int offset)22*4882a593Smuzhiyun static inline void hdmi_write(struct dw_hdmi_qp_i2s_audio_data *audio,
23*4882a593Smuzhiyun u32 val, int offset)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct dw_hdmi_qp *hdmi = audio->hdmi;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun audio->write(hdmi, val, offset);
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
hdmi_read(struct dw_hdmi_qp_i2s_audio_data * audio,int offset)30*4882a593Smuzhiyun static inline u32 hdmi_read(struct dw_hdmi_qp_i2s_audio_data *audio, int offset)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct dw_hdmi_qp *hdmi = audio->hdmi;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return audio->read(hdmi, offset);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
hdmi_mod(struct dw_hdmi_qp_i2s_audio_data * audio,u32 data,u32 mask,u32 reg)37*4882a593Smuzhiyun static inline void hdmi_mod(struct dw_hdmi_qp_i2s_audio_data *audio,
38*4882a593Smuzhiyun u32 data, u32 mask, u32 reg)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct dw_hdmi_qp *hdmi = audio->hdmi;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return audio->mod(hdmi, data, mask, reg);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
dw_hdmi_qp_i2s_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * fmt,struct hdmi_codec_params * hparms)45*4882a593Smuzhiyun static int dw_hdmi_qp_i2s_hw_params(struct device *dev, void *data,
46*4882a593Smuzhiyun struct hdmi_codec_daifmt *fmt,
47*4882a593Smuzhiyun struct hdmi_codec_params *hparms)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct dw_hdmi_qp_i2s_audio_data *audio = data;
50*4882a593Smuzhiyun struct dw_hdmi_qp *hdmi = audio->hdmi;
51*4882a593Smuzhiyun bool ref2stream = false;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if (fmt->bit_clk_master | fmt->frame_clk_master) {
54*4882a593Smuzhiyun dev_err(dev, "unsupported clock settings\n");
55*4882a593Smuzhiyun return -EINVAL;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (fmt->bit_fmt == SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE)
59*4882a593Smuzhiyun ref2stream = true;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun dw_hdmi_qp_set_audio_interface(hdmi, fmt, hparms);
62*4882a593Smuzhiyun dw_hdmi_qp_set_sample_rate(hdmi, hparms->sample_rate);
63*4882a593Smuzhiyun dw_hdmi_qp_set_channel_status(hdmi, hparms->iec.status, ref2stream);
64*4882a593Smuzhiyun dw_hdmi_qp_set_channel_count(hdmi, hparms->channels);
65*4882a593Smuzhiyun dw_hdmi_qp_set_channel_allocation(hdmi, hparms->cea.channel_allocation);
66*4882a593Smuzhiyun dw_hdmi_qp_set_audio_infoframe(hdmi, hparms);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
dw_hdmi_qp_i2s_audio_startup(struct device * dev,void * data)71*4882a593Smuzhiyun static int dw_hdmi_qp_i2s_audio_startup(struct device *dev, void *data)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct dw_hdmi_qp_i2s_audio_data *audio = data;
74*4882a593Smuzhiyun struct dw_hdmi_qp *hdmi = audio->hdmi;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun dw_hdmi_qp_audio_enable(hdmi);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
dw_hdmi_qp_i2s_audio_shutdown(struct device * dev,void * data)81*4882a593Smuzhiyun static void dw_hdmi_qp_i2s_audio_shutdown(struct device *dev, void *data)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct dw_hdmi_qp_i2s_audio_data *audio = data;
84*4882a593Smuzhiyun struct dw_hdmi_qp *hdmi = audio->hdmi;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun dw_hdmi_qp_audio_disable(hdmi);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
dw_hdmi_qp_i2s_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)89*4882a593Smuzhiyun static int dw_hdmi_qp_i2s_get_eld(struct device *dev, void *data, uint8_t *buf,
90*4882a593Smuzhiyun size_t len)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct dw_hdmi_qp_i2s_audio_data *audio = data;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun memcpy(buf, audio->eld, min_t(size_t, MAX_ELD_BYTES, len));
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
dw_hdmi_qp_i2s_get_dai_id(struct snd_soc_component * component,struct device_node * endpoint)99*4882a593Smuzhiyun static int dw_hdmi_qp_i2s_get_dai_id(struct snd_soc_component *component,
100*4882a593Smuzhiyun struct device_node *endpoint)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun struct of_endpoint of_ep;
103*4882a593Smuzhiyun int ret;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun ret = of_graph_parse_endpoint(endpoint, &of_ep);
106*4882a593Smuzhiyun if (ret < 0)
107*4882a593Smuzhiyun return ret;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun * HDMI sound should be located as reg = <2>
111*4882a593Smuzhiyun * Then, it is sound port 0
112*4882a593Smuzhiyun */
113*4882a593Smuzhiyun if (of_ep.port == 2)
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun return -EINVAL;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
dw_hdmi_qp_i2s_hook_plugged_cb(struct device * dev,void * data,hdmi_codec_plugged_cb fn,struct device * codec_dev)119*4882a593Smuzhiyun static int dw_hdmi_qp_i2s_hook_plugged_cb(struct device *dev, void *data,
120*4882a593Smuzhiyun hdmi_codec_plugged_cb fn,
121*4882a593Smuzhiyun struct device *codec_dev)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct dw_hdmi_qp_i2s_audio_data *audio = data;
124*4882a593Smuzhiyun struct dw_hdmi_qp *hdmi = audio->hdmi;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return dw_hdmi_qp_set_plugged_cb(hdmi, fn, codec_dev);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static struct hdmi_codec_ops dw_hdmi_qp_i2s_ops = {
130*4882a593Smuzhiyun .hw_params = dw_hdmi_qp_i2s_hw_params,
131*4882a593Smuzhiyun .audio_startup = dw_hdmi_qp_i2s_audio_startup,
132*4882a593Smuzhiyun .audio_shutdown = dw_hdmi_qp_i2s_audio_shutdown,
133*4882a593Smuzhiyun .get_eld = dw_hdmi_qp_i2s_get_eld,
134*4882a593Smuzhiyun .get_dai_id = dw_hdmi_qp_i2s_get_dai_id,
135*4882a593Smuzhiyun .hook_plugged_cb = dw_hdmi_qp_i2s_hook_plugged_cb,
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
snd_dw_hdmi_qp_probe(struct platform_device * pdev)138*4882a593Smuzhiyun static int snd_dw_hdmi_qp_probe(struct platform_device *pdev)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun struct dw_hdmi_qp_i2s_audio_data *audio = pdev->dev.platform_data;
141*4882a593Smuzhiyun struct platform_device_info pdevinfo;
142*4882a593Smuzhiyun struct hdmi_codec_pdata pdata;
143*4882a593Smuzhiyun struct platform_device *platform;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun pdata.ops = &dw_hdmi_qp_i2s_ops;
146*4882a593Smuzhiyun pdata.i2s = 1;
147*4882a593Smuzhiyun pdata.max_i2s_channels = 8;
148*4882a593Smuzhiyun pdata.data = audio;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun memset(&pdevinfo, 0, sizeof(pdevinfo));
151*4882a593Smuzhiyun pdevinfo.parent = pdev->dev.parent;
152*4882a593Smuzhiyun pdevinfo.id = PLATFORM_DEVID_AUTO;
153*4882a593Smuzhiyun pdevinfo.name = HDMI_CODEC_DRV_NAME;
154*4882a593Smuzhiyun pdevinfo.data = &pdata;
155*4882a593Smuzhiyun pdevinfo.size_data = sizeof(pdata);
156*4882a593Smuzhiyun pdevinfo.dma_mask = DMA_BIT_MASK(32);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun platform = platform_device_register_full(&pdevinfo);
159*4882a593Smuzhiyun if (IS_ERR(platform))
160*4882a593Smuzhiyun return PTR_ERR(platform);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun dev_set_drvdata(&pdev->dev, platform);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun return 0;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
snd_dw_hdmi_qp_remove(struct platform_device * pdev)167*4882a593Smuzhiyun static int snd_dw_hdmi_qp_remove(struct platform_device *pdev)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun struct platform_device *platform = dev_get_drvdata(&pdev->dev);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun platform_device_unregister(platform);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return 0;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun static struct platform_driver snd_dw_hdmi_qp_driver = {
177*4882a593Smuzhiyun .probe = snd_dw_hdmi_qp_probe,
178*4882a593Smuzhiyun .remove = snd_dw_hdmi_qp_remove,
179*4882a593Smuzhiyun .driver = {
180*4882a593Smuzhiyun .name = DRIVER_NAME,
181*4882a593Smuzhiyun },
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun module_platform_driver(snd_dw_hdmi_qp_driver);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
186*4882a593Smuzhiyun MODULE_DESCRIPTION("Synopsis Designware HDMI QP I2S ALSA SoC interface");
187*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
188*4882a593Smuzhiyun MODULE_ALIAS("platform:" DRIVER_NAME);
189