1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2018 Renesas Electronics
4 *
5 * Copyright (C) 2016 Atmel
6 * Bo Shen <voice.shen@atmel.com>
7 *
8 * Authors: Bo Shen <voice.shen@atmel.com>
9 * Boris Brezillon <boris.brezillon@free-electrons.com>
10 * Wu, Songjun <Songjun.Wu@atmel.com>
11 *
12 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
13 */
14
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c-mux.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/clk.h>
22
23 #include <drm/drm_atomic_helper.h>
24 #include <drm/drm_bridge.h>
25 #include <drm/drm_drv.h>
26 #include <drm/drm_edid.h>
27 #include <drm/drm_modes.h>
28 #include <drm/drm_print.h>
29 #include <drm/drm_probe_helper.h>
30
31 #include <sound/hdmi-codec.h>
32 #include <video/videomode.h>
33
34 #define SII902X_TPI_VIDEO_DATA 0x0
35
36 #define SII902X_TPI_PIXEL_REPETITION 0x8
37 #define SII902X_TPI_AVI_PIXEL_REP_BUS_24BIT BIT(5)
38 #define SII902X_TPI_AVI_PIXEL_REP_RISING_EDGE BIT(4)
39 #define SII902X_TPI_AVI_PIXEL_REP_4X 3
40 #define SII902X_TPI_AVI_PIXEL_REP_2X 1
41 #define SII902X_TPI_AVI_PIXEL_REP_NONE 0
42 #define SII902X_TPI_CLK_RATIO_HALF (0 << 6)
43 #define SII902X_TPI_CLK_RATIO_1X (1 << 6)
44 #define SII902X_TPI_CLK_RATIO_2X (2 << 6)
45 #define SII902X_TPI_CLK_RATIO_4X (3 << 6)
46
47 #define SII902X_TPI_AVI_IN_FORMAT 0x9
48 #define SII902X_TPI_AVI_INPUT_BITMODE_12BIT BIT(7)
49 #define SII902X_TPI_AVI_INPUT_DITHER BIT(6)
50 #define SII902X_TPI_AVI_INPUT_RANGE_LIMITED (2 << 2)
51 #define SII902X_TPI_AVI_INPUT_RANGE_FULL (1 << 2)
52 #define SII902X_TPI_AVI_INPUT_RANGE_AUTO (0 << 2)
53 #define SII902X_TPI_AVI_INPUT_COLORSPACE_BLACK (3 << 0)
54 #define SII902X_TPI_AVI_INPUT_COLORSPACE_YUV422 (2 << 0)
55 #define SII902X_TPI_AVI_INPUT_COLORSPACE_YUV444 (1 << 0)
56 #define SII902X_TPI_AVI_INPUT_COLORSPACE_RGB (0 << 0)
57
58 #define SII902X_TPI_AVI_INFOFRAME 0x0c
59
60 #define SII902X_SYS_CTRL_DATA 0x1a
61 #define SII902X_SYS_CTRL_PWR_DWN BIT(4)
62 #define SII902X_SYS_CTRL_AV_MUTE BIT(3)
63 #define SII902X_SYS_CTRL_DDC_BUS_REQ BIT(2)
64 #define SII902X_SYS_CTRL_DDC_BUS_GRTD BIT(1)
65 #define SII902X_SYS_CTRL_OUTPUT_MODE BIT(0)
66 #define SII902X_SYS_CTRL_OUTPUT_HDMI 1
67 #define SII902X_SYS_CTRL_OUTPUT_DVI 0
68
69 #define SII902X_REG_CHIPID(n) (0x1b + (n))
70
71 #define SII902X_PWR_STATE_CTRL 0x1e
72 #define SII902X_AVI_POWER_STATE_MSK GENMASK(1, 0)
73 #define SII902X_AVI_POWER_STATE_D(l) ((l) & SII902X_AVI_POWER_STATE_MSK)
74
75 /* Audio */
76 #define SII902X_TPI_I2S_ENABLE_MAPPING_REG 0x1f
77 #define SII902X_TPI_I2S_CONFIG_FIFO0 (0 << 0)
78 #define SII902X_TPI_I2S_CONFIG_FIFO1 (1 << 0)
79 #define SII902X_TPI_I2S_CONFIG_FIFO2 (2 << 0)
80 #define SII902X_TPI_I2S_CONFIG_FIFO3 (3 << 0)
81 #define SII902X_TPI_I2S_LEFT_RIGHT_SWAP (1 << 2)
82 #define SII902X_TPI_I2S_AUTO_DOWNSAMPLE (1 << 3)
83 #define SII902X_TPI_I2S_SELECT_SD0 (0 << 4)
84 #define SII902X_TPI_I2S_SELECT_SD1 (1 << 4)
85 #define SII902X_TPI_I2S_SELECT_SD2 (2 << 4)
86 #define SII902X_TPI_I2S_SELECT_SD3 (3 << 4)
87 #define SII902X_TPI_I2S_FIFO_ENABLE (1 << 7)
88
89 #define SII902X_TPI_I2S_INPUT_CONFIG_REG 0x20
90 #define SII902X_TPI_I2S_FIRST_BIT_SHIFT_YES (0 << 0)
91 #define SII902X_TPI_I2S_FIRST_BIT_SHIFT_NO (1 << 0)
92 #define SII902X_TPI_I2S_SD_DIRECTION_MSB_FIRST (0 << 1)
93 #define SII902X_TPI_I2S_SD_DIRECTION_LSB_FIRST (1 << 1)
94 #define SII902X_TPI_I2S_SD_JUSTIFY_LEFT (0 << 2)
95 #define SII902X_TPI_I2S_SD_JUSTIFY_RIGHT (1 << 2)
96 #define SII902X_TPI_I2S_WS_POLARITY_LOW (0 << 3)
97 #define SII902X_TPI_I2S_WS_POLARITY_HIGH (1 << 3)
98 #define SII902X_TPI_I2S_MCLK_MULTIPLIER_128 (0 << 4)
99 #define SII902X_TPI_I2S_MCLK_MULTIPLIER_256 (1 << 4)
100 #define SII902X_TPI_I2S_MCLK_MULTIPLIER_384 (2 << 4)
101 #define SII902X_TPI_I2S_MCLK_MULTIPLIER_512 (3 << 4)
102 #define SII902X_TPI_I2S_MCLK_MULTIPLIER_768 (4 << 4)
103 #define SII902X_TPI_I2S_MCLK_MULTIPLIER_1024 (5 << 4)
104 #define SII902X_TPI_I2S_MCLK_MULTIPLIER_1152 (6 << 4)
105 #define SII902X_TPI_I2S_MCLK_MULTIPLIER_192 (7 << 4)
106 #define SII902X_TPI_I2S_SCK_EDGE_FALLING (0 << 7)
107 #define SII902X_TPI_I2S_SCK_EDGE_RISING (1 << 7)
108
109 #define SII902X_TPI_I2S_STRM_HDR_BASE 0x21
110 #define SII902X_TPI_I2S_STRM_HDR_SIZE 5
111
112 #define SII902X_TPI_AUDIO_CONFIG_BYTE2_REG 0x26
113 #define SII902X_TPI_AUDIO_CODING_STREAM_HEADER (0 << 0)
114 #define SII902X_TPI_AUDIO_CODING_PCM (1 << 0)
115 #define SII902X_TPI_AUDIO_CODING_AC3 (2 << 0)
116 #define SII902X_TPI_AUDIO_CODING_MPEG1 (3 << 0)
117 #define SII902X_TPI_AUDIO_CODING_MP3 (4 << 0)
118 #define SII902X_TPI_AUDIO_CODING_MPEG2 (5 << 0)
119 #define SII902X_TPI_AUDIO_CODING_AAC (6 << 0)
120 #define SII902X_TPI_AUDIO_CODING_DTS (7 << 0)
121 #define SII902X_TPI_AUDIO_CODING_ATRAC (8 << 0)
122 #define SII902X_TPI_AUDIO_MUTE_DISABLE (0 << 4)
123 #define SII902X_TPI_AUDIO_MUTE_ENABLE (1 << 4)
124 #define SII902X_TPI_AUDIO_LAYOUT_2_CHANNELS (0 << 5)
125 #define SII902X_TPI_AUDIO_LAYOUT_8_CHANNELS (1 << 5)
126 #define SII902X_TPI_AUDIO_INTERFACE_DISABLE (0 << 6)
127 #define SII902X_TPI_AUDIO_INTERFACE_SPDIF (1 << 6)
128 #define SII902X_TPI_AUDIO_INTERFACE_I2S (2 << 6)
129
130 #define SII902X_TPI_AUDIO_CONFIG_BYTE3_REG 0x27
131 #define SII902X_TPI_AUDIO_FREQ_STREAM (0 << 3)
132 #define SII902X_TPI_AUDIO_FREQ_32KHZ (1 << 3)
133 #define SII902X_TPI_AUDIO_FREQ_44KHZ (2 << 3)
134 #define SII902X_TPI_AUDIO_FREQ_48KHZ (3 << 3)
135 #define SII902X_TPI_AUDIO_FREQ_88KHZ (4 << 3)
136 #define SII902X_TPI_AUDIO_FREQ_96KHZ (5 << 3)
137 #define SII902X_TPI_AUDIO_FREQ_176KHZ (6 << 3)
138 #define SII902X_TPI_AUDIO_FREQ_192KHZ (7 << 3)
139 #define SII902X_TPI_AUDIO_SAMPLE_SIZE_STREAM (0 << 6)
140 #define SII902X_TPI_AUDIO_SAMPLE_SIZE_16 (1 << 6)
141 #define SII902X_TPI_AUDIO_SAMPLE_SIZE_20 (2 << 6)
142 #define SII902X_TPI_AUDIO_SAMPLE_SIZE_24 (3 << 6)
143
144 #define SII902X_TPI_AUDIO_CONFIG_BYTE4_REG 0x28
145
146 #define SII902X_INT_ENABLE 0x3c
147 #define SII902X_INT_STATUS 0x3d
148 #define SII902X_HOTPLUG_EVENT BIT(0)
149 #define SII902X_PLUGGED_STATUS BIT(2)
150
151 #define SII902X_TPI_SYNC_GEN_CTRL 0x60
152 #define SII902X_TPI_SYNC_POLAR_DETECT 0x61
153 #define SII902X_TPI_HBIT_TO_HSYNC 0x62
154 #define SII902X_EMBEDDED_SYNC_EXTRACTION_REG 0x63
155 #define SII902X_EMBEDDED_SYNC_EXTRACTION BIT(6)
156
157 #define SII902X_REG_TPI_RQB 0xc7
158
159 /* Indirect internal register access */
160 #define SII902X_IND_SET_PAGE 0xbc
161 #define SII902X_IND_OFFSET 0xbd
162 #define SII902X_IND_VALUE 0xbe
163
164 #define SII902X_TPI_MISC_INFOFRAME_BASE 0xbf
165 #define SII902X_TPI_MISC_INFOFRAME_END 0xde
166 #define SII902X_TPI_MISC_INFOFRAME_SIZE \
167 (SII902X_TPI_MISC_INFOFRAME_END - SII902X_TPI_MISC_INFOFRAME_BASE)
168
169 #define SII902X_I2C_BUS_ACQUISITION_TIMEOUT_MS 500
170
171 #define SII902X_AUDIO_PORT_INDEX 3
172
173 struct sii902x {
174 struct i2c_client *i2c;
175 struct regmap *regmap;
176 struct drm_bridge bridge;
177 struct drm_connector connector;
178 struct gpio_desc *reset_gpio;
179 struct gpio_desc *enable_gpio;
180 struct i2c_mux_core *i2cmux;
181 struct regulator_bulk_data supplies[2];
182 /*
183 * Mutex protects audio and video functions from interfering
184 * each other, by keeping their i2c command sequences atomic.
185 */
186 struct mutex mutex;
187 struct sii902x_audio {
188 struct platform_device *pdev;
189 struct clk *mclk;
190 u32 i2s_fifo_sequence[4];
191 } audio;
192 struct drm_display_mode mode;
193 int bus_format;
194 };
195
196 enum sii902x_bus_format {
197 FORMAT_RGB_INPUT,
198 FORMAT_YCBCR422_INPUT,
199 FORMAT_YCBCR444_INPUT,
200 };
201
sii902x_read_unlocked(struct i2c_client * i2c,u8 reg,u8 * val)202 static int sii902x_read_unlocked(struct i2c_client *i2c, u8 reg, u8 *val)
203 {
204 union i2c_smbus_data data;
205 int ret;
206
207 ret = __i2c_smbus_xfer(i2c->adapter, i2c->addr, i2c->flags,
208 I2C_SMBUS_READ, reg, I2C_SMBUS_BYTE_DATA, &data);
209
210 if (ret < 0)
211 return ret;
212
213 *val = data.byte;
214 return 0;
215 }
216
sii902x_write_unlocked(struct i2c_client * i2c,u8 reg,u8 val)217 static int sii902x_write_unlocked(struct i2c_client *i2c, u8 reg, u8 val)
218 {
219 union i2c_smbus_data data;
220
221 data.byte = val;
222
223 return __i2c_smbus_xfer(i2c->adapter, i2c->addr, i2c->flags,
224 I2C_SMBUS_WRITE, reg, I2C_SMBUS_BYTE_DATA,
225 &data);
226 }
227
sii902x_update_bits_unlocked(struct i2c_client * i2c,u8 reg,u8 mask,u8 val)228 static int sii902x_update_bits_unlocked(struct i2c_client *i2c, u8 reg, u8 mask,
229 u8 val)
230 {
231 int ret;
232 u8 status;
233
234 ret = sii902x_read_unlocked(i2c, reg, &status);
235 if (ret)
236 return ret;
237 status &= ~mask;
238 status |= val & mask;
239 return sii902x_write_unlocked(i2c, reg, status);
240 }
241
bridge_to_sii902x(struct drm_bridge * bridge)242 static inline struct sii902x *bridge_to_sii902x(struct drm_bridge *bridge)
243 {
244 return container_of(bridge, struct sii902x, bridge);
245 }
246
connector_to_sii902x(struct drm_connector * con)247 static inline struct sii902x *connector_to_sii902x(struct drm_connector *con)
248 {
249 return container_of(con, struct sii902x, connector);
250 }
251
sii902x_reset(struct sii902x * sii902x)252 static void sii902x_reset(struct sii902x *sii902x)
253 {
254 if (!sii902x->reset_gpio)
255 return;
256
257 gpiod_set_value(sii902x->reset_gpio, 1);
258
259 /* The datasheet says treset-min = 100us. Make it 150us to be sure. */
260 usleep_range(150, 200);
261
262 gpiod_set_value(sii902x->reset_gpio, 0);
263 }
264
265 static enum drm_connector_status
sii902x_connector_detect(struct drm_connector * connector,bool force)266 sii902x_connector_detect(struct drm_connector *connector, bool force)
267 {
268 struct sii902x *sii902x = connector_to_sii902x(connector);
269 unsigned int status;
270
271 mutex_lock(&sii902x->mutex);
272
273 regmap_read(sii902x->regmap, SII902X_INT_STATUS, &status);
274
275 mutex_unlock(&sii902x->mutex);
276
277 return (status & SII902X_PLUGGED_STATUS) ?
278 connector_status_connected : connector_status_disconnected;
279 }
280
281 static const struct drm_connector_funcs sii902x_connector_funcs = {
282 .detect = sii902x_connector_detect,
283 .fill_modes = drm_helper_probe_single_connector_modes,
284 .destroy = drm_connector_cleanup,
285 .reset = drm_atomic_helper_connector_reset,
286 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
287 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
288 };
289
290 static const struct drm_display_mode sii902x_default_modes[] = {
291 /* 4 - 1280x720@60Hz 16:9 */
292 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
293 1430, 1650, 0, 720, 725, 730, 750, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
296 /* 16 - 1920x1080@60Hz 16:9 */
297 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
298 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
301 /* 5 - 1920x1080i@60Hz 16:9 */
302 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
303 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
305 DRM_MODE_FLAG_INTERLACE),
306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
307 /* 31 - 1920x1080@50Hz 16:9 */
308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
309 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
312 /* 19 - 1280x720@50Hz 16:9 */
313 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
314 1760, 1980, 0, 720, 725, 730, 750, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
317 /* 0x10 - 1024x768@60Hz */
318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
319 1184, 1344, 0, 768, 771, 777, 806, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
321 /* 17 - 720x576@50Hz 4:3 */
322 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
323 796, 864, 0, 576, 581, 586, 625, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
326 /* 2 - 720x480@60Hz 4:3 */
327 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
328 798, 858, 0, 480, 489, 495, 525, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
331 };
332
sii902x_get_modes(struct drm_connector * connector)333 static int sii902x_get_modes(struct drm_connector *connector)
334 {
335 struct sii902x *sii902x = connector_to_sii902x(connector);
336 u8 output_mode = SII902X_SYS_CTRL_OUTPUT_DVI;
337 struct edid *edid;
338 int num = 0, ret = 0, i;
339 struct drm_display_mode *mode;
340
341 mutex_lock(&sii902x->mutex);
342
343 edid = drm_get_edid(connector, sii902x->i2cmux->adapter[0]);
344 drm_connector_update_edid_property(connector, edid);
345 if (edid) {
346 if (drm_detect_hdmi_monitor(edid))
347 output_mode = SII902X_SYS_CTRL_OUTPUT_HDMI;
348
349 num = drm_add_edid_modes(connector, edid);
350 kfree(edid);
351 } else {
352 for (i = 0; i < ARRAY_SIZE(sii902x_default_modes); i++) {
353 const struct drm_display_mode *ptr =
354 &sii902x_default_modes[i];
355
356 mode = drm_mode_duplicate(connector->dev, ptr);
357 if (mode) {
358 if (!i)
359 mode->type = DRM_MODE_TYPE_PREFERRED;
360 drm_mode_probed_add(connector, mode);
361 ret++;
362 }
363 }
364 output_mode = SII902X_SYS_CTRL_OUTPUT_HDMI;
365 }
366
367 ret = drm_display_info_set_bus_formats(&connector->display_info,
368 &sii902x->bus_format, 1);
369 if (ret)
370 goto error_out;
371
372 ret = regmap_update_bits(sii902x->regmap, SII902X_SYS_CTRL_DATA,
373 SII902X_SYS_CTRL_OUTPUT_MODE, output_mode);
374 if (ret)
375 goto error_out;
376
377 ret = num;
378
379 error_out:
380 mutex_unlock(&sii902x->mutex);
381
382 return ret;
383 }
384
sii902x_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)385 static enum drm_mode_status sii902x_mode_valid(struct drm_connector *connector,
386 struct drm_display_mode *mode)
387 {
388 if (mode->hdisplay > 1920 || mode->vdisplay > 1080)
389 return MODE_BAD;
390 if (mode->clock > 165000)
391 return MODE_BAD;
392
393 return MODE_OK;
394 }
395
396 static const struct drm_connector_helper_funcs sii902x_connector_helper_funcs = {
397 .get_modes = sii902x_get_modes,
398 .mode_valid = sii902x_mode_valid,
399 };
400
sii902x_bridge_disable(struct drm_bridge * bridge)401 static void sii902x_bridge_disable(struct drm_bridge *bridge)
402 {
403 struct sii902x *sii902x = bridge_to_sii902x(bridge);
404
405 mutex_lock(&sii902x->mutex);
406
407 regmap_update_bits(sii902x->regmap, SII902X_SYS_CTRL_DATA,
408 SII902X_SYS_CTRL_PWR_DWN,
409 SII902X_SYS_CTRL_PWR_DWN);
410
411 mutex_unlock(&sii902x->mutex);
412 }
413
sii902x_bridge_enable(struct drm_bridge * bridge)414 static void sii902x_bridge_enable(struct drm_bridge *bridge)
415 {
416 struct sii902x *sii902x = bridge_to_sii902x(bridge);
417
418 mutex_lock(&sii902x->mutex);
419
420 regmap_update_bits(sii902x->regmap, SII902X_PWR_STATE_CTRL,
421 SII902X_AVI_POWER_STATE_MSK,
422 SII902X_AVI_POWER_STATE_D(0));
423 regmap_update_bits(sii902x->regmap, SII902X_SYS_CTRL_DATA,
424 SII902X_SYS_CTRL_PWR_DWN, 0);
425
426 mutex_unlock(&sii902x->mutex);
427 }
428
sii902x_check_embedded_format(uint32_t bus_format)429 static bool sii902x_check_embedded_format(uint32_t bus_format)
430 {
431 switch (bus_format) {
432 case MEDIA_BUS_FMT_YUYV8_2X8:
433 case MEDIA_BUS_FMT_YVYU8_2X8:
434 case MEDIA_BUS_FMT_UYVY8_2X8:
435 case MEDIA_BUS_FMT_VYUY8_2X8:
436 case MEDIA_BUS_FMT_YUYV8_1X16:
437 case MEDIA_BUS_FMT_YVYU8_1X16:
438 case MEDIA_BUS_FMT_UYVY8_1X16:
439 case MEDIA_BUS_FMT_VYUY8_1X16:
440 return true;
441 default:
442 return false;
443 }
444 }
445
sii902x_set_embedded_sync(struct sii902x * sii902x)446 static void sii902x_set_embedded_sync(struct sii902x *sii902x)
447 {
448 unsigned char data[8];
449 struct videomode vm;
450
451 if (!sii902x_check_embedded_format(sii902x->bus_format))
452 return;
453
454 switch (sii902x->bus_format) {
455 case MEDIA_BUS_FMT_YUYV8_2X8:
456 case MEDIA_BUS_FMT_YVYU8_2X8:
457 case MEDIA_BUS_FMT_UYVY8_2X8:
458 case MEDIA_BUS_FMT_VYUY8_2X8:
459 sii902x_update_bits_unlocked(sii902x->i2c, SII902X_TPI_SYNC_GEN_CTRL,
460 0x20, 0x20);
461 break;
462 default:
463 break;
464 }
465
466 sii902x_update_bits_unlocked(sii902x->i2c, SII902X_TPI_SYNC_GEN_CTRL,
467 0x80, 0x00);
468 regmap_write(sii902x->regmap,
469 SII902X_EMBEDDED_SYNC_EXTRACTION_REG, 0x00);
470 sii902x_update_bits_unlocked(sii902x->i2c, SII902X_TPI_SYNC_GEN_CTRL,
471 0x80, 0x80);
472
473 drm_display_mode_to_videomode(&sii902x->mode, &vm);
474 data[0] = vm.hfront_porch & 0xff;
475 data[1] = (vm.hfront_porch >> 8) & 0x03;
476 if (sii902x->mode.flags & DRM_MODE_FLAG_INTERLACE) {
477 data[2] = (sii902x->mode.vtotal >> 1) & 0xff;
478 data[3] = ((sii902x->mode.vtotal >> 1) >> 8) & 0x1f;
479 } else {
480 data[2] = 0;
481 data[3] = 0;
482 }
483 data[4] = vm.hsync_len & 0xff;
484 data[5] = (vm.hsync_len >> 8) & 0x03;
485 data[6] = vm.vfront_porch;
486 data[7] = vm.vsync_len;
487 regmap_bulk_write(sii902x->regmap, SII902X_TPI_HBIT_TO_HSYNC, data, 8);
488
489 sii902x_update_bits_unlocked(sii902x->i2c, SII902X_TPI_SYNC_GEN_CTRL,
490 0x80, 0x80);
491 sii902x_update_bits_unlocked(sii902x->i2c,
492 SII902X_EMBEDDED_SYNC_EXTRACTION_REG,
493 0x40, 0x40);
494
495 regmap_update_bits(sii902x->regmap,
496 SII902X_EMBEDDED_SYNC_EXTRACTION_REG,
497 SII902X_EMBEDDED_SYNC_EXTRACTION,
498 SII902X_EMBEDDED_SYNC_EXTRACTION);
499 }
500
sii902x_set_format(struct sii902x * sii902x)501 static void sii902x_set_format(struct sii902x *sii902x)
502 {
503 u8 val;
504
505 switch (sii902x->bus_format) {
506 case MEDIA_BUS_FMT_YUYV8_1X16:
507 case MEDIA_BUS_FMT_YVYU8_1X16:
508 case MEDIA_BUS_FMT_UYVY8_1X16:
509 case MEDIA_BUS_FMT_VYUY8_1X16:
510 case MEDIA_BUS_FMT_YUYV8_2X8:
511 case MEDIA_BUS_FMT_YVYU8_2X8:
512 case MEDIA_BUS_FMT_UYVY8_2X8:
513 case MEDIA_BUS_FMT_VYUY8_2X8:
514 val = SII902X_TPI_AVI_INPUT_COLORSPACE_YUV422;
515 break;
516 case MEDIA_BUS_FMT_YUV8_1X24:
517 case MEDIA_BUS_FMT_VUY8_1X24:
518 val = SII902X_TPI_AVI_INPUT_COLORSPACE_YUV444;
519 break;
520 case MEDIA_BUS_FMT_RGB888_1X24:
521 default:
522 val = SII902X_TPI_AVI_INPUT_COLORSPACE_RGB;
523 break;
524 }
525
526 val |= SII902X_TPI_AVI_INPUT_RANGE_AUTO;
527 val &= ~(SII902X_TPI_AVI_INPUT_DITHER |
528 SII902X_TPI_AVI_INPUT_BITMODE_12BIT);
529 regmap_write(sii902x->regmap, SII902X_TPI_AVI_IN_FORMAT, val);
530
531 sii902x_set_embedded_sync(sii902x);
532 }
533
sii902x_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adj)534 static void sii902x_bridge_mode_set(struct drm_bridge *bridge,
535 const struct drm_display_mode *mode,
536 const struct drm_display_mode *adj)
537 {
538 struct sii902x *sii902x = bridge_to_sii902x(bridge);
539 struct regmap *regmap = sii902x->regmap;
540 u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
541 struct hdmi_avi_infoframe frame;
542 u16 pixel_clock_10kHz = adj->clock / 10;
543 int ret, vrefresh;
544
545 drm_mode_copy(&sii902x->mode, adj);
546 vrefresh = drm_mode_vrefresh(mode) * 100;
547 buf[0] = pixel_clock_10kHz & 0xff;
548 buf[1] = pixel_clock_10kHz >> 8;
549 buf[2] = vrefresh & 0xff;
550 buf[3] = vrefresh >> 8;
551 buf[4] = adj->crtc_htotal;
552 buf[5] = adj->crtc_htotal >> 8;
553 buf[6] = adj->crtc_vtotal;
554 buf[7] = adj->crtc_vtotal >> 8;
555 buf[8] = SII902X_TPI_CLK_RATIO_1X | SII902X_TPI_AVI_PIXEL_REP_NONE |
556 SII902X_TPI_AVI_PIXEL_REP_BUS_24BIT;
557 switch (sii902x->bus_format) {
558 case MEDIA_BUS_FMT_YUYV8_1X16:
559 case MEDIA_BUS_FMT_YVYU8_1X16:
560 case MEDIA_BUS_FMT_UYVY8_1X16:
561 case MEDIA_BUS_FMT_VYUY8_1X16:
562 case MEDIA_BUS_FMT_YUYV8_2X8:
563 case MEDIA_BUS_FMT_YVYU8_2X8:
564 case MEDIA_BUS_FMT_UYVY8_2X8:
565 case MEDIA_BUS_FMT_VYUY8_2X8:
566 buf[8] |= SII902X_TPI_AVI_PIXEL_REP_RISING_EDGE;
567 break;
568 default:
569 break;
570 }
571
572 buf[9] = SII902X_TPI_AVI_INPUT_RANGE_AUTO;
573 switch (sii902x->bus_format) {
574 case MEDIA_BUS_FMT_YUYV8_1X16:
575 case MEDIA_BUS_FMT_YVYU8_1X16:
576 case MEDIA_BUS_FMT_UYVY8_1X16:
577 case MEDIA_BUS_FMT_VYUY8_1X16:
578 case MEDIA_BUS_FMT_YUYV8_2X8:
579 case MEDIA_BUS_FMT_YVYU8_2X8:
580 case MEDIA_BUS_FMT_UYVY8_2X8:
581 case MEDIA_BUS_FMT_VYUY8_2X8:
582 buf[9] |= SII902X_TPI_AVI_INPUT_COLORSPACE_YUV422;
583 break;
584 case MEDIA_BUS_FMT_YUV8_1X24:
585 case MEDIA_BUS_FMT_VUY8_1X24:
586 buf[9] |= SII902X_TPI_AVI_INPUT_COLORSPACE_YUV444;
587 break;
588 case MEDIA_BUS_FMT_RGB888_1X24:
589 default:
590 buf[9] |= SII902X_TPI_AVI_INPUT_COLORSPACE_RGB;
591 break;
592 }
593
594 mutex_lock(&sii902x->mutex);
595
596 ret = regmap_bulk_write(regmap, SII902X_TPI_VIDEO_DATA, buf, 10);
597 if (ret)
598 goto out;
599
600 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
601 &sii902x->connector, adj);
602 if (ret < 0) {
603 DRM_ERROR("couldn't fill AVI infoframe\n");
604 goto out;
605 }
606
607 ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
608 if (ret < 0) {
609 DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
610 goto out;
611 }
612
613 /* Do not send the infoframe header, but keep the CRC field. */
614 regmap_bulk_write(regmap, SII902X_TPI_AVI_INFOFRAME,
615 buf + HDMI_INFOFRAME_HEADER_SIZE - 1,
616 HDMI_AVI_INFOFRAME_SIZE + 1);
617 sii902x_set_format(sii902x);
618 out:
619 mutex_unlock(&sii902x->mutex);
620 }
621
sii902x_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)622 static int sii902x_bridge_attach(struct drm_bridge *bridge,
623 enum drm_bridge_attach_flags flags)
624 {
625 struct sii902x *sii902x = bridge_to_sii902x(bridge);
626 struct drm_device *drm = bridge->dev;
627 int ret;
628
629 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
630 DRM_ERROR("Fix bridge driver to make connector optional!");
631 return -EINVAL;
632 }
633
634 sii902x->connector.interlace_allowed = true;
635 drm_connector_helper_add(&sii902x->connector,
636 &sii902x_connector_helper_funcs);
637
638 if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) {
639 dev_err(&sii902x->i2c->dev,
640 "sii902x driver is only compatible with DRM devices supporting atomic updates\n");
641 return -ENOTSUPP;
642 }
643
644 ret = drm_connector_init(drm, &sii902x->connector,
645 &sii902x_connector_funcs,
646 DRM_MODE_CONNECTOR_HDMIA);
647 if (ret)
648 return ret;
649
650 if (sii902x->i2c->irq > 0)
651 sii902x->connector.polled = DRM_CONNECTOR_POLL_HPD;
652 else
653 sii902x->connector.polled = DRM_CONNECTOR_POLL_CONNECT;
654
655 drm_connector_attach_encoder(&sii902x->connector, bridge->encoder);
656
657 return 0;
658 }
659
660 static const struct drm_bridge_funcs sii902x_bridge_funcs = {
661 .attach = sii902x_bridge_attach,
662 .mode_set = sii902x_bridge_mode_set,
663 .disable = sii902x_bridge_disable,
664 .enable = sii902x_bridge_enable,
665 };
666
sii902x_mute(struct sii902x * sii902x,bool mute)667 static int sii902x_mute(struct sii902x *sii902x, bool mute)
668 {
669 struct device *dev = &sii902x->i2c->dev;
670 unsigned int val = mute ? SII902X_TPI_AUDIO_MUTE_ENABLE :
671 SII902X_TPI_AUDIO_MUTE_DISABLE;
672
673 dev_dbg(dev, "%s: %s\n", __func__, mute ? "Muted" : "Unmuted");
674
675 return regmap_update_bits(sii902x->regmap,
676 SII902X_TPI_AUDIO_CONFIG_BYTE2_REG,
677 SII902X_TPI_AUDIO_MUTE_ENABLE, val);
678 }
679
680 static const int sii902x_mclk_div_table[] = {
681 128, 256, 384, 512, 768, 1024, 1152, 192 };
682
sii902x_select_mclk_div(u8 * i2s_config_reg,unsigned int rate,unsigned int mclk)683 static int sii902x_select_mclk_div(u8 *i2s_config_reg, unsigned int rate,
684 unsigned int mclk)
685 {
686 int div = mclk / rate;
687 int distance = 100000;
688 u8 i, nearest = 0;
689
690 for (i = 0; i < ARRAY_SIZE(sii902x_mclk_div_table); i++) {
691 unsigned int d = abs(div - sii902x_mclk_div_table[i]);
692
693 if (d >= distance)
694 continue;
695
696 nearest = i;
697 distance = d;
698 if (d == 0)
699 break;
700 }
701
702 *i2s_config_reg |= nearest << 4;
703
704 return sii902x_mclk_div_table[nearest];
705 }
706
707 static const struct sii902x_sample_freq {
708 u32 freq;
709 u8 val;
710 } sii902x_sample_freq[] = {
711 { .freq = 32000, .val = SII902X_TPI_AUDIO_FREQ_32KHZ },
712 { .freq = 44000, .val = SII902X_TPI_AUDIO_FREQ_44KHZ },
713 { .freq = 48000, .val = SII902X_TPI_AUDIO_FREQ_48KHZ },
714 { .freq = 88000, .val = SII902X_TPI_AUDIO_FREQ_88KHZ },
715 { .freq = 96000, .val = SII902X_TPI_AUDIO_FREQ_96KHZ },
716 { .freq = 176000, .val = SII902X_TPI_AUDIO_FREQ_176KHZ },
717 { .freq = 192000, .val = SII902X_TPI_AUDIO_FREQ_192KHZ },
718 };
719
sii902x_audio_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)720 static int sii902x_audio_hw_params(struct device *dev, void *data,
721 struct hdmi_codec_daifmt *daifmt,
722 struct hdmi_codec_params *params)
723 {
724 struct sii902x *sii902x = dev_get_drvdata(dev);
725 u8 i2s_config_reg = SII902X_TPI_I2S_SD_DIRECTION_MSB_FIRST;
726 u8 config_byte2_reg = (SII902X_TPI_AUDIO_INTERFACE_I2S |
727 SII902X_TPI_AUDIO_MUTE_ENABLE |
728 SII902X_TPI_AUDIO_CODING_PCM);
729 u8 config_byte3_reg = 0;
730 u8 infoframe_buf[HDMI_INFOFRAME_SIZE(AUDIO)];
731 unsigned long mclk_rate;
732 int i, ret;
733
734 if (daifmt->bit_clk_master || daifmt->frame_clk_master) {
735 dev_dbg(dev, "%s: I2S master mode not supported\n", __func__);
736 return -EINVAL;
737 }
738
739 switch (daifmt->fmt) {
740 case HDMI_I2S:
741 i2s_config_reg |= SII902X_TPI_I2S_FIRST_BIT_SHIFT_YES |
742 SII902X_TPI_I2S_SD_JUSTIFY_LEFT;
743 break;
744 case HDMI_RIGHT_J:
745 i2s_config_reg |= SII902X_TPI_I2S_SD_JUSTIFY_RIGHT;
746 break;
747 case HDMI_LEFT_J:
748 i2s_config_reg |= SII902X_TPI_I2S_SD_JUSTIFY_LEFT;
749 break;
750 default:
751 dev_dbg(dev, "%s: Unsupported i2s format %u\n", __func__,
752 daifmt->fmt);
753 return -EINVAL;
754 }
755
756 if (daifmt->bit_clk_inv)
757 i2s_config_reg |= SII902X_TPI_I2S_SCK_EDGE_FALLING;
758 else
759 i2s_config_reg |= SII902X_TPI_I2S_SCK_EDGE_RISING;
760
761 if (daifmt->frame_clk_inv)
762 i2s_config_reg |= SII902X_TPI_I2S_WS_POLARITY_LOW;
763 else
764 i2s_config_reg |= SII902X_TPI_I2S_WS_POLARITY_HIGH;
765
766 if (params->channels > 2)
767 config_byte2_reg |= SII902X_TPI_AUDIO_LAYOUT_8_CHANNELS;
768 else
769 config_byte2_reg |= SII902X_TPI_AUDIO_LAYOUT_2_CHANNELS;
770
771 switch (params->sample_width) {
772 case 16:
773 config_byte3_reg |= SII902X_TPI_AUDIO_SAMPLE_SIZE_16;
774 break;
775 case 20:
776 config_byte3_reg |= SII902X_TPI_AUDIO_SAMPLE_SIZE_20;
777 break;
778 case 24:
779 case 32:
780 config_byte3_reg |= SII902X_TPI_AUDIO_SAMPLE_SIZE_24;
781 break;
782 default:
783 dev_err(dev, "%s: Unsupported sample width %u\n", __func__,
784 params->sample_width);
785 return -EINVAL;
786 }
787
788 for (i = 0; i < ARRAY_SIZE(sii902x_sample_freq); i++) {
789 if (params->sample_rate == sii902x_sample_freq[i].freq) {
790 config_byte3_reg |= sii902x_sample_freq[i].val;
791 break;
792 }
793 }
794
795 ret = clk_prepare_enable(sii902x->audio.mclk);
796 if (ret) {
797 dev_err(dev, "Enabling mclk failed: %d\n", ret);
798 return ret;
799 }
800
801 if (sii902x->audio.mclk) {
802 mclk_rate = clk_get_rate(sii902x->audio.mclk);
803 ret = sii902x_select_mclk_div(&i2s_config_reg,
804 params->sample_rate, mclk_rate);
805 if (mclk_rate != ret * params->sample_rate)
806 dev_dbg(dev, "Inaccurate reference clock (%ld/%d != %u)\n",
807 mclk_rate, ret, params->sample_rate);
808 }
809
810 mutex_lock(&sii902x->mutex);
811
812 ret = regmap_write(sii902x->regmap,
813 SII902X_TPI_AUDIO_CONFIG_BYTE2_REG,
814 config_byte2_reg);
815 if (ret < 0)
816 goto out;
817
818 ret = regmap_write(sii902x->regmap, SII902X_TPI_I2S_INPUT_CONFIG_REG,
819 i2s_config_reg);
820 if (ret)
821 goto out;
822
823 for (i = 0; i < ARRAY_SIZE(sii902x->audio.i2s_fifo_sequence) &&
824 sii902x->audio.i2s_fifo_sequence[i]; i++)
825 regmap_write(sii902x->regmap,
826 SII902X_TPI_I2S_ENABLE_MAPPING_REG,
827 sii902x->audio.i2s_fifo_sequence[i]);
828
829 ret = regmap_write(sii902x->regmap, SII902X_TPI_AUDIO_CONFIG_BYTE3_REG,
830 config_byte3_reg);
831 if (ret)
832 goto out;
833
834 ret = regmap_bulk_write(sii902x->regmap, SII902X_TPI_I2S_STRM_HDR_BASE,
835 params->iec.status,
836 min((size_t) SII902X_TPI_I2S_STRM_HDR_SIZE,
837 sizeof(params->iec.status)));
838 if (ret)
839 goto out;
840
841 ret = hdmi_audio_infoframe_pack(¶ms->cea, infoframe_buf,
842 sizeof(infoframe_buf));
843 if (ret < 0) {
844 dev_err(dev, "%s: Failed to pack audio infoframe: %d\n",
845 __func__, ret);
846 goto out;
847 }
848
849 ret = regmap_bulk_write(sii902x->regmap,
850 SII902X_TPI_MISC_INFOFRAME_BASE,
851 infoframe_buf,
852 min(ret, SII902X_TPI_MISC_INFOFRAME_SIZE));
853 if (ret)
854 goto out;
855
856 /* Decode Level 0 Packets */
857 ret = regmap_write(sii902x->regmap, SII902X_IND_SET_PAGE, 0x02);
858 if (ret)
859 goto out;
860
861 ret = regmap_write(sii902x->regmap, SII902X_IND_OFFSET, 0x24);
862 if (ret)
863 goto out;
864
865 ret = regmap_write(sii902x->regmap, SII902X_IND_VALUE, 0x02);
866 if (ret)
867 goto out;
868
869 dev_dbg(dev, "%s: hdmi audio enabled\n", __func__);
870 out:
871 mutex_unlock(&sii902x->mutex);
872
873 if (ret) {
874 clk_disable_unprepare(sii902x->audio.mclk);
875 dev_err(dev, "%s: hdmi audio enable failed: %d\n", __func__,
876 ret);
877 }
878
879 return ret;
880 }
881
sii902x_audio_shutdown(struct device * dev,void * data)882 static void sii902x_audio_shutdown(struct device *dev, void *data)
883 {
884 struct sii902x *sii902x = dev_get_drvdata(dev);
885
886 mutex_lock(&sii902x->mutex);
887
888 regmap_write(sii902x->regmap, SII902X_TPI_AUDIO_CONFIG_BYTE2_REG,
889 SII902X_TPI_AUDIO_INTERFACE_DISABLE);
890
891 mutex_unlock(&sii902x->mutex);
892
893 clk_disable_unprepare(sii902x->audio.mclk);
894 }
895
sii902x_audio_mute(struct device * dev,void * data,bool enable,int direction)896 static int sii902x_audio_mute(struct device *dev, void *data,
897 bool enable, int direction)
898 {
899 struct sii902x *sii902x = dev_get_drvdata(dev);
900
901 mutex_lock(&sii902x->mutex);
902
903 sii902x_mute(sii902x, enable);
904
905 mutex_unlock(&sii902x->mutex);
906
907 return 0;
908 }
909
sii902x_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)910 static int sii902x_audio_get_eld(struct device *dev, void *data,
911 uint8_t *buf, size_t len)
912 {
913 struct sii902x *sii902x = dev_get_drvdata(dev);
914
915 mutex_lock(&sii902x->mutex);
916
917 memcpy(buf, sii902x->connector.eld,
918 min(sizeof(sii902x->connector.eld), len));
919
920 mutex_unlock(&sii902x->mutex);
921
922 return 0;
923 }
924
sii902x_audio_get_dai_id(struct snd_soc_component * component,struct device_node * endpoint)925 static int sii902x_audio_get_dai_id(struct snd_soc_component *component,
926 struct device_node *endpoint)
927 {
928 struct of_endpoint of_ep;
929 int ret;
930
931 ret = of_graph_parse_endpoint(endpoint, &of_ep);
932 if (ret < 0)
933 return ret;
934
935 /*
936 * HDMI sound should be located at reg = <3>
937 * Return expected DAI index 0.
938 */
939 if (of_ep.port == SII902X_AUDIO_PORT_INDEX)
940 return 0;
941
942 return -EINVAL;
943 }
944
945 static const struct hdmi_codec_ops sii902x_audio_codec_ops = {
946 .hw_params = sii902x_audio_hw_params,
947 .audio_shutdown = sii902x_audio_shutdown,
948 .mute_stream = sii902x_audio_mute,
949 .get_eld = sii902x_audio_get_eld,
950 .get_dai_id = sii902x_audio_get_dai_id,
951 .no_capture_mute = 1,
952 };
953
sii902x_audio_codec_init(struct sii902x * sii902x,struct device * dev)954 static int sii902x_audio_codec_init(struct sii902x *sii902x,
955 struct device *dev)
956 {
957 static const u8 audio_fifo_id[] = {
958 SII902X_TPI_I2S_CONFIG_FIFO0,
959 SII902X_TPI_I2S_CONFIG_FIFO1,
960 SII902X_TPI_I2S_CONFIG_FIFO2,
961 SII902X_TPI_I2S_CONFIG_FIFO3,
962 };
963 static const u8 i2s_lane_id[] = {
964 SII902X_TPI_I2S_SELECT_SD0,
965 SII902X_TPI_I2S_SELECT_SD1,
966 SII902X_TPI_I2S_SELECT_SD2,
967 SII902X_TPI_I2S_SELECT_SD3,
968 };
969 struct hdmi_codec_pdata codec_data = {
970 .ops = &sii902x_audio_codec_ops,
971 .i2s = 1, /* Only i2s support for now. */
972 .spdif = 0,
973 .max_i2s_channels = 0,
974 };
975 u8 lanes[4];
976 int num_lanes, i;
977
978 if (!of_property_read_bool(dev->of_node, "#sound-dai-cells")) {
979 dev_dbg(dev, "%s: No \"#sound-dai-cells\", no audio\n",
980 __func__);
981 return 0;
982 }
983
984 num_lanes = of_property_read_variable_u8_array(dev->of_node,
985 "sil,i2s-data-lanes",
986 lanes, 1,
987 ARRAY_SIZE(lanes));
988
989 if (num_lanes == -EINVAL) {
990 dev_dbg(dev,
991 "%s: No \"sil,i2s-data-lanes\", use default <0>\n",
992 __func__);
993 num_lanes = 1;
994 lanes[0] = 0;
995 } else if (num_lanes < 0) {
996 dev_err(dev,
997 "%s: Error gettin \"sil,i2s-data-lanes\": %d\n",
998 __func__, num_lanes);
999 return num_lanes;
1000 }
1001 codec_data.max_i2s_channels = 2 * num_lanes;
1002
1003 for (i = 0; i < num_lanes; i++)
1004 sii902x->audio.i2s_fifo_sequence[i] |= audio_fifo_id[i] |
1005 i2s_lane_id[lanes[i]] | SII902X_TPI_I2S_FIFO_ENABLE;
1006
1007 sii902x->audio.mclk = devm_clk_get_optional(dev, "mclk");
1008 if (IS_ERR(sii902x->audio.mclk)) {
1009 dev_err(dev, "%s: No clock (audio mclk) found: %ld\n",
1010 __func__, PTR_ERR(sii902x->audio.mclk));
1011 return PTR_ERR(sii902x->audio.mclk);
1012 }
1013
1014 sii902x->audio.pdev = platform_device_register_data(
1015 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1016 &codec_data, sizeof(codec_data));
1017
1018 return PTR_ERR_OR_ZERO(sii902x->audio.pdev);
1019 }
1020
1021 static const struct regmap_range sii902x_volatile_ranges[] = {
1022 { .range_min = 0, .range_max = 0xff },
1023 };
1024
1025 static const struct regmap_access_table sii902x_volatile_table = {
1026 .yes_ranges = sii902x_volatile_ranges,
1027 .n_yes_ranges = ARRAY_SIZE(sii902x_volatile_ranges),
1028 };
1029
1030 static const struct regmap_config sii902x_regmap_config = {
1031 .reg_bits = 8,
1032 .val_bits = 8,
1033 .disable_locking = true, /* struct sii902x mutex should be enough */
1034 .max_register = SII902X_TPI_MISC_INFOFRAME_END,
1035 .volatile_table = &sii902x_volatile_table,
1036 .cache_type = REGCACHE_NONE,
1037 };
1038
sii902x_interrupt(int irq,void * data)1039 static irqreturn_t sii902x_interrupt(int irq, void *data)
1040 {
1041 struct sii902x *sii902x = data;
1042 unsigned int status = 0;
1043
1044 mutex_lock(&sii902x->mutex);
1045
1046 regmap_read(sii902x->regmap, SII902X_INT_STATUS, &status);
1047 regmap_write(sii902x->regmap, SII902X_INT_STATUS, status);
1048
1049 mutex_unlock(&sii902x->mutex);
1050
1051 if ((status & SII902X_HOTPLUG_EVENT) && sii902x->bridge.dev)
1052 drm_helper_hpd_irq_event(sii902x->bridge.dev);
1053
1054 return IRQ_HANDLED;
1055 }
1056
1057 /*
1058 * The purpose of sii902x_i2c_bypass_select is to enable the pass through
1059 * mode of the HDMI transmitter. Do not use regmap from within this function,
1060 * only use sii902x_*_unlocked functions to read/modify/write registers.
1061 * We are holding the parent adapter lock here, keep this in mind before
1062 * adding more i2c transactions.
1063 *
1064 * Also, since SII902X_SYS_CTRL_DATA is used with regmap_update_bits elsewhere
1065 * in this driver, we need to make sure that we only touch 0x1A[2:1] from
1066 * within sii902x_i2c_bypass_select and sii902x_i2c_bypass_deselect, and that
1067 * we leave the remaining bits as we have found them.
1068 */
sii902x_i2c_bypass_select(struct i2c_mux_core * mux,u32 chan_id)1069 static int sii902x_i2c_bypass_select(struct i2c_mux_core *mux, u32 chan_id)
1070 {
1071 struct sii902x *sii902x = i2c_mux_priv(mux);
1072 struct device *dev = &sii902x->i2c->dev;
1073 unsigned long timeout;
1074 u8 status;
1075 int ret;
1076
1077 ret = sii902x_update_bits_unlocked(sii902x->i2c, SII902X_SYS_CTRL_DATA,
1078 SII902X_SYS_CTRL_DDC_BUS_REQ,
1079 SII902X_SYS_CTRL_DDC_BUS_REQ);
1080 if (ret)
1081 return ret;
1082
1083 timeout = jiffies +
1084 msecs_to_jiffies(SII902X_I2C_BUS_ACQUISITION_TIMEOUT_MS);
1085 do {
1086 ret = sii902x_read_unlocked(sii902x->i2c, SII902X_SYS_CTRL_DATA,
1087 &status);
1088 if (ret)
1089 return ret;
1090 } while (!(status & SII902X_SYS_CTRL_DDC_BUS_GRTD) &&
1091 time_before(jiffies, timeout));
1092
1093 if (!(status & SII902X_SYS_CTRL_DDC_BUS_GRTD)) {
1094 dev_err(dev, "Failed to acquire the i2c bus\n");
1095 return -ETIMEDOUT;
1096 }
1097
1098 return sii902x_write_unlocked(sii902x->i2c, SII902X_SYS_CTRL_DATA,
1099 status);
1100 }
1101
1102 /*
1103 * The purpose of sii902x_i2c_bypass_deselect is to disable the pass through
1104 * mode of the HDMI transmitter. Do not use regmap from within this function,
1105 * only use sii902x_*_unlocked functions to read/modify/write registers.
1106 * We are holding the parent adapter lock here, keep this in mind before
1107 * adding more i2c transactions.
1108 *
1109 * Also, since SII902X_SYS_CTRL_DATA is used with regmap_update_bits elsewhere
1110 * in this driver, we need to make sure that we only touch 0x1A[2:1] from
1111 * within sii902x_i2c_bypass_select and sii902x_i2c_bypass_deselect, and that
1112 * we leave the remaining bits as we have found them.
1113 */
sii902x_i2c_bypass_deselect(struct i2c_mux_core * mux,u32 chan_id)1114 static int sii902x_i2c_bypass_deselect(struct i2c_mux_core *mux, u32 chan_id)
1115 {
1116 struct sii902x *sii902x = i2c_mux_priv(mux);
1117 struct device *dev = &sii902x->i2c->dev;
1118 unsigned long timeout;
1119 unsigned int retries;
1120 u8 status;
1121 int ret;
1122
1123 /*
1124 * When the HDMI transmitter is in pass through mode, we need an
1125 * (undocumented) additional delay between STOP and START conditions
1126 * to guarantee the bus won't get stuck.
1127 */
1128 udelay(30);
1129
1130 /*
1131 * Sometimes the I2C bus can stall after failure to use the
1132 * EDID channel. Retry a few times to see if things clear
1133 * up, else continue anyway.
1134 */
1135 retries = 5;
1136 do {
1137 ret = sii902x_read_unlocked(sii902x->i2c, SII902X_SYS_CTRL_DATA,
1138 &status);
1139 retries--;
1140 } while (ret && retries);
1141 if (ret) {
1142 dev_err(dev, "failed to read status (%d)\n", ret);
1143 return ret;
1144 }
1145
1146 ret = sii902x_update_bits_unlocked(sii902x->i2c, SII902X_SYS_CTRL_DATA,
1147 SII902X_SYS_CTRL_DDC_BUS_REQ |
1148 SII902X_SYS_CTRL_DDC_BUS_GRTD, 0);
1149 if (ret)
1150 return ret;
1151
1152 timeout = jiffies +
1153 msecs_to_jiffies(SII902X_I2C_BUS_ACQUISITION_TIMEOUT_MS);
1154 do {
1155 ret = sii902x_read_unlocked(sii902x->i2c, SII902X_SYS_CTRL_DATA,
1156 &status);
1157 if (ret)
1158 return ret;
1159 } while (status & (SII902X_SYS_CTRL_DDC_BUS_REQ |
1160 SII902X_SYS_CTRL_DDC_BUS_GRTD) &&
1161 time_before(jiffies, timeout));
1162
1163 if (status & (SII902X_SYS_CTRL_DDC_BUS_REQ |
1164 SII902X_SYS_CTRL_DDC_BUS_GRTD)) {
1165 dev_err(dev, "failed to release the i2c bus\n");
1166 return -ETIMEDOUT;
1167 }
1168
1169 return 0;
1170 }
1171
1172 static const struct drm_bridge_timings default_sii902x_timings = {
1173 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE
1174 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
1175 | DRM_BUS_FLAG_DE_HIGH,
1176 };
1177
sii902x_init(struct sii902x * sii902x)1178 static int sii902x_init(struct sii902x *sii902x)
1179 {
1180 struct device *dev = &sii902x->i2c->dev;
1181 unsigned int status = 0;
1182 u8 chipid[4];
1183 int ret;
1184
1185 sii902x_reset(sii902x);
1186
1187 ret = regmap_write(sii902x->regmap, SII902X_REG_TPI_RQB, 0x0);
1188 if (ret) {
1189 dev_err(dev, "enable TPI mode failed %d\n", ret);
1190 return ret;
1191 }
1192
1193 ret = regmap_bulk_read(sii902x->regmap, SII902X_REG_CHIPID(0),
1194 &chipid, 4);
1195 if (ret) {
1196 dev_err(dev, "regmap_read failed %d\n", ret);
1197 return ret;
1198 }
1199
1200 if (chipid[0] != 0xb0) {
1201 dev_err(dev, "Invalid chipid: %02x (expecting 0xb0)\n",
1202 chipid[0]);
1203 return -EINVAL;
1204 }
1205
1206 /* Clear all pending interrupts */
1207 regmap_read(sii902x->regmap, SII902X_INT_STATUS, &status);
1208 regmap_write(sii902x->regmap, SII902X_INT_STATUS, status);
1209
1210 if (sii902x->i2c->irq > 0) {
1211 regmap_write(sii902x->regmap, SII902X_INT_ENABLE,
1212 SII902X_HOTPLUG_EVENT);
1213
1214 ret = devm_request_threaded_irq(dev, sii902x->i2c->irq, NULL,
1215 sii902x_interrupt,
1216 IRQF_TRIGGER_FALLING |
1217 IRQF_ONESHOT, dev_name(dev),
1218 sii902x);
1219 if (ret)
1220 return ret;
1221 }
1222
1223 sii902x->bridge.funcs = &sii902x_bridge_funcs;
1224 sii902x->bridge.of_node = dev->of_node;
1225 sii902x->bridge.timings = &default_sii902x_timings;
1226 drm_bridge_add(&sii902x->bridge);
1227
1228 sii902x_audio_codec_init(sii902x, dev);
1229
1230 i2c_set_clientdata(sii902x->i2c, sii902x);
1231
1232 sii902x->i2cmux = i2c_mux_alloc(sii902x->i2c->adapter, dev,
1233 1, 0, I2C_MUX_GATE,
1234 sii902x_i2c_bypass_select,
1235 sii902x_i2c_bypass_deselect);
1236 if (!sii902x->i2cmux)
1237 return -ENOMEM;
1238
1239 sii902x->i2cmux->priv = sii902x;
1240 return i2c_mux_add_adapter(sii902x->i2cmux, 0, 0, 0);
1241 }
1242
sii902x_probe(struct i2c_client * client,const struct i2c_device_id * id)1243 static int sii902x_probe(struct i2c_client *client,
1244 const struct i2c_device_id *id)
1245 {
1246 struct device *dev = &client->dev;
1247 struct sii902x *sii902x;
1248 int ret;
1249 u32 val;
1250
1251 ret = i2c_check_functionality(client->adapter,
1252 I2C_FUNC_SMBUS_BYTE_DATA);
1253 if (!ret) {
1254 dev_err(dev, "I2C adapter not suitable\n");
1255 return -EIO;
1256 }
1257
1258 sii902x = devm_kzalloc(dev, sizeof(*sii902x), GFP_KERNEL);
1259 if (!sii902x)
1260 return -ENOMEM;
1261
1262 sii902x->i2c = client;
1263 sii902x->regmap = devm_regmap_init_i2c(client, &sii902x_regmap_config);
1264 if (IS_ERR(sii902x->regmap))
1265 return PTR_ERR(sii902x->regmap);
1266
1267 sii902x->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1268 GPIOD_OUT_LOW);
1269 if (IS_ERR(sii902x->reset_gpio)) {
1270 dev_err(dev, "Failed to retrieve/request reset gpio: %ld\n",
1271 PTR_ERR(sii902x->reset_gpio));
1272 return PTR_ERR(sii902x->reset_gpio);
1273 }
1274
1275 sii902x->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1276 GPIOD_OUT_LOW);
1277 if (IS_ERR(sii902x->enable_gpio)) {
1278 dev_err(dev, "Failed to retrieve/request enable gpio: %ld\n",
1279 PTR_ERR(sii902x->enable_gpio));
1280 return PTR_ERR(sii902x->enable_gpio);
1281 } else if (sii902x->enable_gpio) {
1282 gpiod_direction_output(sii902x->enable_gpio, 1);
1283 usleep_range(1500, 2000);
1284 }
1285
1286 ret = of_property_read_u32(dev->of_node, "bus-format", &val);
1287 if (ret < 0) {
1288 sii902x->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1289 } else {
1290 switch (val) {
1291 case FORMAT_RGB_INPUT:
1292 sii902x->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1293 break;
1294 case FORMAT_YCBCR422_INPUT:
1295 sii902x->bus_format = MEDIA_BUS_FMT_YUYV8_1X16;
1296 break;
1297 case FORMAT_YCBCR444_INPUT:
1298 sii902x->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
1299 break;
1300 default:
1301 sii902x->bus_format = val;
1302 break;
1303 }
1304 }
1305
1306 mutex_init(&sii902x->mutex);
1307
1308 sii902x->supplies[0].supply = "iovcc";
1309 sii902x->supplies[1].supply = "cvcc12";
1310 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(sii902x->supplies),
1311 sii902x->supplies);
1312 if (ret < 0)
1313 return ret;
1314
1315 ret = regulator_bulk_enable(ARRAY_SIZE(sii902x->supplies),
1316 sii902x->supplies);
1317 if (ret < 0) {
1318 dev_err_probe(dev, ret, "Failed to enable supplies");
1319 return ret;
1320 }
1321
1322 ret = sii902x_init(sii902x);
1323 if (ret < 0) {
1324 dev_err(dev, "Failed to init sii902x %d\n", ret);
1325 regulator_bulk_disable(ARRAY_SIZE(sii902x->supplies),
1326 sii902x->supplies);
1327 }
1328
1329 return ret;
1330 }
1331
sii902x_remove(struct i2c_client * client)1332 static int sii902x_remove(struct i2c_client *client)
1333
1334 {
1335 struct sii902x *sii902x = i2c_get_clientdata(client);
1336
1337 i2c_mux_del_adapters(sii902x->i2cmux);
1338 drm_bridge_remove(&sii902x->bridge);
1339 regulator_bulk_disable(ARRAY_SIZE(sii902x->supplies),
1340 sii902x->supplies);
1341
1342 return 0;
1343 }
1344
1345 static const struct of_device_id sii902x_dt_ids[] = {
1346 { .compatible = "sil,sii9022", },
1347 { }
1348 };
1349 MODULE_DEVICE_TABLE(of, sii902x_dt_ids);
1350
1351 static const struct i2c_device_id sii902x_i2c_ids[] = {
1352 { "sii9022", 0 },
1353 { },
1354 };
1355 MODULE_DEVICE_TABLE(i2c, sii902x_i2c_ids);
1356
1357 static struct i2c_driver sii902x_driver = {
1358 .probe = sii902x_probe,
1359 .remove = sii902x_remove,
1360 .driver = {
1361 .name = "sii902x",
1362 .of_match_table = sii902x_dt_ids,
1363 },
1364 .id_table = sii902x_i2c_ids,
1365 };
1366 module_i2c_driver(sii902x_driver);
1367
1368 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
1369 MODULE_DESCRIPTION("SII902x RGB -> HDMI bridges");
1370 MODULE_LICENSE("GPL");
1371