1 // SPDX-License-Identifier: GPL-2.0 2 ///***************************************** 3 // Copyright (C) 2009-2019 4 // ITE Tech. Inc. All Rights Reserved 5 ///***************************************** 6 // @file <hdmitx_sys.h> 7 // @author Jau-Chih.Tseng@ite.com.tw 8 // @date 2019/02/15 9 // @fileversion: IT6161_SAMPLE_0.50 10 //******************************************/ 11 12 typedef enum _SYS_STATUS { 13 ER_SUCCESS = 0, 14 ER_FAIL, 15 ER_RESERVED 16 } SYS_STATUS ; 17 18 //#define FALSE 0 19 //#define TRUE 1 20 #ifndef NULL 21 #define NULL ((void *) 0) 22 #endif 23 24 struct register_load_table 25 { 26 unsigned char offset; 27 unsigned char mask; 28 unsigned char value; 29 }; 30 31 /////////////////////////////////////////////////////////////////////// 32 // Video Data Type 33 /////////////////////////////////////////////////////////////////////// 34 35 #define F_MODE_RGB444 0 36 #define F_MODE_YUV422 1 37 #define F_MODE_YUV444 2 38 #define F_MODE_CLRMOD_MASK 3 39 40 41 #define F_MODE_INTERLACE 1 42 43 #define F_VIDMODE_ITU709 (1<<4) 44 #define F_VIDMODE_ITU601 0 45 46 #define F_VIDMODE_0_255 0 47 #define F_VIDMODE_16_235 (1<<5) 48 49 #define F_VIDMODE_EN_UDFILT (1<<6) 50 #define F_VIDMODE_EN_DITHER (1<<7) 51 52 #define T_MODE_CCIR656 (1<<0) 53 #define T_MODE_SYNCEMB (1<<1) 54 #define T_MODE_INDDR (1<<2) 55 #define T_MODE_PCLKDIV2 (1<<3) 56 #define T_MODE_DEGEN (1<<4) 57 #define T_MODE_SYNCGEN (1<<5) 58 ///////////////////////////////////////////////////////////////////// 59 // Packet and Info Frame definition and datastructure. 60 ///////////////////////////////////////////////////////////////////// 61 62 63 #define VENDORSPEC_INFOFRAME_TYPE 0x81 64 #define AVI_INFOFRAME_TYPE 0x82 65 #define SPD_INFOFRAME_TYPE 0x83 66 #define AUDIO_INFOFRAME_TYPE 0x84 67 #define MPEG_INFOFRAME_TYPE 0x85 68 69 #define VENDORSPEC_INFOFRAME_VER 0x01 70 #define AVI_INFOFRAME_VER 0x02 71 #define SPD_INFOFRAME_VER 0x01 72 #define AUDIO_INFOFRAME_VER 0x01 73 #define MPEG_INFOFRAME_VER 0x01 74 75 #define VENDORSPEC_INFOFRAME_LEN 5 76 #define AVI_INFOFRAME_LEN 13 77 #define SPD_INFOFRAME_LEN 25 78 #define AUDIO_INFOFRAME_LEN 10 79 #define MPEG_INFOFRAME_LEN 10 80 81 #define ACP_PKT_LEN 9 82 #define ISRC1_PKT_LEN 16 83 #define ISRC2_PKT_LEN 16 84 85 typedef union _VendorSpecific_InfoFrame 86 { 87 struct { 88 u8 Type ; 89 u8 Ver ; 90 u8 Len ; 91 92 u8 CheckSum; 93 94 u8 IEEE_0;//PB1 95 u8 IEEE_1;//PB2 96 u8 IEEE_2;//PB3 97 98 u8 Rsvd:5 ;//PB4 99 u8 HDMI_Video_Format:3 ; 100 101 u8 Reserved_PB5:4 ;//PB5 102 u8 _3D_Structure:4 ; 103 104 u8 Reserved_PB6:4 ;//PB6 105 u8 _3D_Ext_Data:4 ; 106 } info ; 107 struct { 108 u8 VS_HB[3] ; 109 u8 CheckSum; 110 u8 VS_DB[28] ; 111 } pktbyte ; 112 } VendorSpecific_InfoFrame ; 113 114 115 typedef union _AVI_InfoFrame 116 { 117 struct { 118 u8 Type; 119 u8 Ver; 120 u8 Len; 121 122 u8 checksum ; 123 124 u8 Scan:2; 125 u8 BarInfo:2; 126 u8 ActiveFmtInfoPresent:1; 127 u8 ColorMode:2; 128 u8 FU1:1; 129 130 u8 ActiveFormatAspectRatio:4; 131 u8 PictureAspectRatio:2; 132 u8 Colorimetry:2; 133 134 u8 Scaling:2; 135 u8 FU2:6; 136 137 u8 VIC:7; 138 u8 FU3:1; 139 140 u8 PixelRepetition:4; 141 u8 FU4:4; 142 143 u16 Ln_End_Top; 144 u16 Ln_Start_Bottom; 145 u16 Pix_End_Left; 146 u16 Pix_Start_Right; 147 } info; 148 149 struct { 150 u8 AVI_HB[3]; 151 u8 checksum ; 152 u8 AVI_DB[AVI_INFOFRAME_LEN]; 153 } pktbyte; 154 } AVI_InfoFrame; 155 156 typedef union _Audio_InfoFrame { 157 158 struct { 159 u8 Type; 160 u8 Ver; 161 u8 Len; 162 u8 checksum ; 163 164 u8 AudioChannelCount:3; 165 u8 RSVD1:1; 166 u8 AudioCodingType:4; 167 168 u8 SampleSize:2; 169 u8 SampleFreq:3; 170 u8 Rsvd2:3; 171 172 u8 FmtCoding; 173 174 u8 SpeakerPlacement; 175 176 u8 Rsvd3:3; 177 u8 LevelShiftValue:4; 178 u8 DM_INH:1; 179 } info; 180 181 struct { 182 u8 AUD_HB[3]; 183 u8 checksum ; 184 u8 AUD_DB[10]; 185 } pktbyte; 186 187 } Audio_InfoFrame; 188 189 typedef union _MPEG_InfoFrame { 190 struct { 191 u8 Type; 192 u8 Ver; 193 u8 Len; 194 u8 checksum ; 195 196 u32 MpegBitRate; 197 198 u8 MpegFrame:2; 199 u8 Rvsd1:2; 200 u8 FieldRepeat:1; 201 u8 Rvsd2:3; 202 } info; 203 struct { 204 u8 MPG_HB[3]; 205 u8 checksum ; 206 u8 MPG_DB[MPEG_INFOFRAME_LEN]; 207 } pktbyte; 208 } MPEG_InfoFrame; 209 210 typedef union _SPD_InfoFrame { 211 struct { 212 u8 Type; 213 u8 Ver; 214 u8 Len; 215 u8 checksum ; 216 217 char VN[8]; 218 char PD[16]; 219 u8 SourceDeviceInfomation; 220 } info; 221 struct { 222 u8 SPD_HB[3]; 223 u8 checksum ; 224 u8 SPD_DB[SPD_INFOFRAME_LEN]; 225 } pktbyte; 226 } SPD_InfoFrame; 227 228 229 /////////////////////////////////////////////////////////////////////////// 230 // Using for interface. 231 /////////////////////////////////////////////////////////////////////////// 232 233 #define PROG 1 234 #define INTERLACE 0 235 #define Vneg 0 236 #define Hneg 0 237 #define Vpos 1 238 #define Hpos 1 239 240 typedef struct { 241 u32 H_ActiveStart; 242 u32 H_ActiveEnd; 243 u32 H_SyncStart; 244 u32 H_SyncEnd; 245 u32 V_ActiveStart; 246 u32 V_ActiveEnd; 247 u32 V_SyncStart; 248 u32 V_SyncEnd; 249 u32 V2_ActiveStart; 250 u32 V2_ActiveEnd; 251 u32 HTotal; 252 u32 VTotal; 253 } CEAVTiming; 254 255 typedef struct { 256 u8 VIC ; 257 u8 PixelRep ; 258 u32 HActive; 259 u32 VActive; 260 u32 HTotal; 261 u32 VTotal; 262 u32 PCLK; 263 u16 xCnt; 264 u32 HFrontPorch; 265 u32 HSyncWidth; 266 u32 HBackPorch; 267 u8 VFrontPorch; 268 u8 VSyncWidth; 269 u8 VBackPorch; 270 u8 ScanMode:1; 271 u8 VPolarity:1; 272 u8 HPolarity:1; 273 } HDMI_VTiming; 274 275 ////////////////////////////////////////////////////////////////// 276 // Audio relate definition and macro. 277 ////////////////////////////////////////////////////////////////// 278 279 // 2008/08/15 added by jj_tseng@chipadvanced 280 #define F_AUDIO_ON (1<<7) 281 #define F_AUDIO_HBR (1<<6) 282 #define F_AUDIO_DSD (1<<5) 283 #define F_AUDIO_NLPCM (1<<4) 284 #define F_AUDIO_LAYOUT_1 (1<<3) 285 #define F_AUDIO_LAYOUT_0 (0<<3) 286 287 // HBR - 1100 288 // DSD - 1010 289 // NLPCM - 1001 290 // LPCM - 1000 291 292 #define T_AUDIO_MASK 0xF0 293 #define T_AUDIO_OFF 0 294 #define T_AUDIO_HBR (F_AUDIO_ON|F_AUDIO_HBR) 295 #define T_AUDIO_DSD (F_AUDIO_ON|F_AUDIO_DSD) 296 #define T_AUDIO_NLPCM (F_AUDIO_ON|F_AUDIO_NLPCM) 297 #define T_AUDIO_LPCM (F_AUDIO_ON) 298 299 // for sample clock 300 #define AUDFS_22p05KHz 4 301 #define AUDFS_44p1KHz 0 302 #define AUDFS_88p2KHz 8 303 #define AUDFS_176p4KHz 12 304 305 #define AUDFS_24KHz 6 306 #define AUDFS_48KHz 2 307 #define AUDFS_96KHz 10 308 #define AUDFS_192KHz 14 309 310 #define AUDFS_768KHz 9 311 312 #define AUDFS_32KHz 3 313 #define AUDFS_OTHER 1 314 315 // Audio Enable 316 #define ENABLE_SPDIF (1<<4) 317 #define ENABLE_I2S_SRC3 (1<<3) 318 #define ENABLE_I2S_SRC2 (1<<2) 319 #define ENABLE_I2S_SRC1 (1<<1) 320 #define ENABLE_I2S_SRC0 (1<<0) 321 322 #define AUD_SWL_NOINDICATE 0x0 323 #define AUD_SWL_16 0x2 324 #define AUD_SWL_17 0xC 325 #define AUD_SWL_18 0x4 326 #define AUD_SWL_20 0xA // for maximum 20 bit 327 #define AUD_SWL_21 0xD 328 #define AUD_SWL_22 0x5 329 #define AUD_SWL_23 0x9 330 #define AUD_SWL_24 0xB 331 332 333 334 335 336 #ifndef _IT6161_CONFIG_H_ 337 #define _IT6161_CONFIG_H_ 338 339 340 #define IC_VERSION (0xC0) 341 #if (IC_VERSION == 0xC0) 342 #pragma message("Defined IC_VERSION C0") 343 #endif // EXTERN_HDCPROM 344 345 /*************************************************************************************************/ 346 //HDMITX 347 /*************************************************************************************************/ 348 #pragma message("config.h") 349 350 #ifdef EXTERN_HDCPROM 351 #pragma message("Defined EXTERN_HDCPROM") 352 #endif // EXTERN_HDCPROM 353 354 #define SUPPORT_EDID 355 #define SUPPORT_HDCP 356 #define SUPPORT_SHA 357 //#define SUPPORT_AUDIO_MONITOR 358 #define AudioOutDelayCnt 250 359 360 // #define SUPPORT_CEC 361 362 363 ////////////////////////////////////////////////////////////////////////////////////////// 364 // Video Configuration 365 ////////////////////////////////////////////////////////////////////////////////////////// 366 // 2010/01/26 added a option to disable HDCP. 367 #define SUPPORT_OUTPUTYUV 368 #define SUPPORT_OUTPUTRGB 369 // #define DISABLE_HDMITX_CSC 370 371 #define SUPPORT_INPUTRGB 372 #define SUPPORT_INPUTYUV444 373 #define SUPPORT_INPUTYUV422 374 // #define SUPPORT_SYNCEMBEDDED 375 // #define SUPPORT_DEGEN 376 #define NON_SEQUENTIAL_YCBCR422 377 378 379 380 #define INPUT_COLOR_MODE F_MODE_RGB444 381 //#define INPUT_COLOR_MODE F_MODE_YUV422 382 //#define INPUT_COLOR_MODE F_MODE_YUV444 383 384 #define INPUT_COLOR_DEPTH 24 385 // #define INPUT_COLOR_DEPTH 30 386 // #define INPUT_COLOR_DEPTH 36 387 388 //#define OUTPUT_3D_MODE Frame_Pcaking 389 //#define OUTPUT_3D_MODE Top_and_Botton 390 //#define OUTPUT_3D_MODE Side_by_Side 391 392 // #define INV_INPUT_ACLK 393 // #define INV_INPUT_PCLK 394 #ifdef USING_IT66120 395 #pragma message("Defined Using IT66120") 396 #define SUPPORT_SYNCEMBEDDED 397 #endif 398 399 #ifdef SUPPORT_SYNCEMBEDDED 400 #ifndef USING_IT66120 401 // #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB) // 16 bit sync embedded 402 // #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB | T_MODE_CCIR656) // 8 bit sync embedded 403 #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB|T_MODE_INDDR|T_MODE_PCLKDIV2) // 16 bit sync embedded DDR 404 // #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB|T_MODE_INDDR) // 8 bit sync embedded DDR 405 #else 406 #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB | T_MODE_CCIR656) // 8 bit sync embedded 407 #endif 408 409 #define SUPPORT_INPUTYUV422 410 #ifdef INPUT_COLOR_MODE 411 #undef INPUT_COLOR_MODE 412 #endif // INPUT_COLOR_MODE 413 #define INPUT_COLOR_MODE F_MODE_YUV422 414 #else 415 #pragma message ("Defined seperated sync.") 416 #define INPUT_SIGNAL_TYPE 0 // 24 bit sync seperate 417 //#define INPUT_SIGNAL_TYPE ( T_MODE_DEGEN ) 418 //#define INPUT_SIGNAL_TYPE ( T_MODE_INDDR) 419 //#define INPUT_SIGNAL_TYPE ( T_MODE_SYNCEMB) 420 //#define INPUT_SIGNAL_TYPE ( T_MODE_CCIR656 | T_MODE_SYNCEMB ) 421 #endif 422 423 424 #if defined(SUPPORT_INPUTYUV444) || defined(SUPPORT_INPUTYUV422) 425 #define SUPPORT_INPUTYUV 426 #endif 427 428 #ifdef SUPPORT_SYNCEMBEDDED 429 #pragma message("defined SUPPORT_SYNCEMBEDDED for Sync Embedded timing input or CCIR656 input.") 430 #endif 431 432 433 ////////////////////////////////////////////////////////////////////////////////////////// 434 // Audio Configuration 435 ////////////////////////////////////////////////////////////////////////////////////////// 436 437 // #define SUPPORT_HBR_AUDIO 438 #define USE_SPDIF_CHSTAT 439 #ifndef SUPPORT_HBR_AUDIO 440 #define INPUT_SAMPLE_FREQ AUDFS_48KHz 441 #define INPUT_SAMPLE_FREQ_HZ 48000L 442 #define OUTPUT_CHANNEL 2 // 3 // 4 // 5//6 //7 //8 443 444 #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_LPCM 445 // #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_NLPCM 446 #define CONFIG_INPUT_AUDIO_INTERFACE I2S 447 // #define CONFIG_INPUT_AUDIO_INTERFACE SPDIF 448 // #define CONFIG_INPUT_AUDIO_INTERFACE TDM 449 450 // #define I2S_FORMAT 0x00 // 24bit I2S audio 451 #define I2S_FORMAT 0x01 // 32bit I2S audio 452 // #define I2S_FORMAT 0x02 // 24bit I2S audio, right justify 453 // #define I2S_FORMAT 0x03 // 32bit I2S audio, right justify 454 455 #else // SUPPORT_HBR_AUDIO 456 457 #define INPUT_SAMPLE_FREQ AUDFS_768KHz 458 #define INPUT_SAMPLE_FREQ_HZ 768000L 459 #define OUTPUT_CHANNEL 8 460 #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_HBR 461 #define CONFIG_INPUT_AUDIO_INTERFACE FALSE // I2S 462 // #define CONFIG_INPUT_AUDIO_INTERFACE TRUE // SPDIF 463 #define I2S_FORMAT 0x47 // 32bit audio 464 #endif 465 466 467 468 ////////////////////////////////////////////////////////////////////////////////////////// 469 // Audio Monitor Configuration 470 ////////////////////////////////////////////////////////////////////////////////////////// 471 472 //#define HDMITX_AUTO_MONITOR_INPUT 473 #define HDMITX_INPUT_INFO 474 475 #ifdef HDMITX_AUTO_MONITOR_INPUT 476 #define HDMITX_INPUT_INFO 477 #endif 478 479 ////////////////////////////////////////////////////////////////////////////////////////// 480 // Reduce Source Clock Jitter 481 ////////////////////////////////////////////////////////////////////////////////////////// 482 //#define REDUCE_HDMITX_SRC_JITTER 483 484 ////////////////////////////////////////////////////////////////////////////////////////// 485 // MIPI Rx Configuration 486 ////////////////////////////////////////////////////////////////////////////////////////// 487 #define MIPIRX_LANE_NUM 4 //1~4 488 489 #endif 490 491 492 493 494 #ifndef _HDMITX_H_ 495 #define _HDMITX_H_ 496 497 #define HDMITX_MAX_DEV_COUNT 1 498 499 500 /////////////////////////////////////////////////////////////////////// 501 // Output Mode Type 502 /////////////////////////////////////////////////////////////////////// 503 504 #define RES_ASPEC_4x3 0 505 #define RES_ASPEC_16x9 1 506 #define F_MODE_REPT_NO 0 507 #define F_MODE_REPT_TWICE 1 508 #define F_MODE_REPT_QUATRO 3 509 #define F_MODE_CSC_ITU601 0 510 #define F_MODE_CSC_ITU709 1 511 512 513 #define TIMER_LOOP_LEN 10 514 #define MS(x) (((x)+(TIMER_LOOP_LEN-1))/TIMER_LOOP_LEN); // for timer loop 515 516 // #define SUPPORT_AUDI_AudSWL 16 // Jeilin case. 517 #define SUPPORT_AUDI_AudSWL 24 // Jeilin case. 518 519 #if(SUPPORT_AUDI_AudSWL==16) 520 #define CHTSTS_SWCODE 0x02 521 #elif(SUPPORT_AUDI_AudSWL==18) 522 #define CHTSTS_SWCODE 0x04 523 #elif(SUPPORT_AUDI_AudSWL==20) 524 #define CHTSTS_SWCODE 0x03 525 #else 526 #define CHTSTS_SWCODE 0x0B 527 #endif 528 529 #endif // _HDMITX_H_ 530 531 532 ///***************************************** 533 // Copyright (C) 2009-2019 534 // ITE Tech. Inc. All Rights Reserved 535 // Proprietary and Confidential 536 ///***************************************** 537 // @file <hdmitx_drv.h> 538 // @author Jau-Chih.Tseng@ite.com.tw 539 // @date 2019/02/15 540 // @fileversion: IT6161_SAMPLE_0.50 541 //******************************************/ 542 543 #ifndef _HDMITX_DRV_H_ 544 #define _HDMITX_DRV_H_ 545 546 //#define EXTERN_HDCPROM 547 ///////////////////////////////////////// 548 // DDC Address 549 ///////////////////////////////////////// 550 #define DDC_HDCP_ADDRESS 0x74 551 #define DDC_EDID_ADDRESS 0xA0 552 #define DDC_FIFO_MAXREQ 0x20 553 554 // I2C address 555 556 #define _80MHz 80000000 557 #define HDMI_TX_I2C_SLAVE_ADDR 0x98 558 #define CEC_I2C_SLAVE_ADDR 0x9C 559 /////////////////////////////////////////////////////////////////////// 560 // Register offset 561 /////////////////////////////////////////////////////////////////////// 562 563 #define REG_TX_VENDOR_ID0 0x00 564 #define REG_TX_VENDOR_ID1 0x01 565 #define REG_TX_DEVICE_ID0 0x02 566 #define REG_TX_DEVICE_ID1 0x03 567 568 #define O_TX_DEVID 0 569 #define M_TX_DEVID 0xF 570 #define O_TX_REVID 4 571 #define M_TX_REVID 0xF 572 573 #define REG_TX_SW_RST 0x04 574 #define B_TX_ENTEST (1<<7) 575 #define B_TX_REF_RST_HDMITX (1<<5) 576 #define B_TX_AREF_RST (1<<4) 577 #define B_HDMITX_VID_RST (1<<3) 578 #define B_HDMITX_AUD_RST (1<<2) 579 #define B_TX_HDMI_RST (1<<1) 580 #define B_TX_HDCP_RST_HDMITX (1<<0) 581 582 #define REG_TX_INT_CTRL 0x05 583 #define B_TX_INTPOL_ACTL 0 584 #define B_TX_INTPOL_ACTH (1<<7) 585 #define B_TX_INT_PUSHPULL 0 586 #define B_TX_INT_OPENDRAIN (1<<6) 587 588 #define REG_TX_INT_STAT1 0x06 589 #define B_TX_INT_AUD_OVERFLOW (1<<7) 590 #define B_TX_INT_ROMACQ_NOACK (1<<6) 591 #define B_TX_INT_RDDC_NOACK (1<<5) 592 #define B_TX_INT_DDCFIFO_ERR (1<<4) 593 #define B_TX_INT_ROMACQ_BUS_HANG (1<<3) 594 #define B_TX_INT_DDC_BUS_HANG (1<<2) 595 #define B_TX_INT_RX_SENSE (1<<1) 596 #define B_TX_INT_HPD_PLUG (1<<0) 597 598 #define REG_TX_INT_STAT2 0x07 599 #define B_TX_INT_HDCP_SYNC_DET_FAIL (1<<7) 600 #define B_TX_INT_VID_UNSTABLE (1<<6) 601 #define B_TX_INT_PKTACP (1<<5) 602 #define B_TX_INT_PKTNULL (1<<4) 603 #define B_TX_INT_PKTGENERAL (1<<3) 604 #define B_TX_INT_KSVLIST_CHK (1<<2) 605 #define B_TX_INT_AUTH_DONE (1<<1) 606 #define B_TX_INT_AUTH_FAIL (1<<0) 607 608 #define REG_TX_INT_STAT3 0x08 609 #define B_TX_INT_AUD_CTS (1<<6) 610 #define B_TX_INT_VSYNC (1<<5) 611 #define B_TX_INT_VIDSTABLE (1<<4) 612 #define B_TX_INT_PKTMPG (1<<3) 613 #define B_TX_INT_PKTSPD (1<<2) 614 #define B_TX_INT_PKTAUD (1<<1) 615 #define B_TX_INT_PKTAVI (1<<0) 616 617 #define REG_TX_INT_MASK1 0x09 618 #define B_TX_AUDIO_OVFLW_MASK (1<<7) 619 #define B_TX_DDC_NOACK_MASK (1<<5) 620 #define B_TX_DDC_FIFO_ERR_MASK (1<<4) 621 #define B_TX_DDC_BUS_HANG_MASK (1<<2) 622 #define B_TX_RXSEN_MASK (1<<1) 623 #define B_TX_HPD_MASK (1<<0) 624 625 #define REG_TX_INT_MASK2 0x0A 626 #define B_TX_PKT_AVI_MASK (1<<7) 627 #define B_TX_PKT_VID_UNSTABLE_MASK (1<<6) 628 #define B_TX_PKT_ACP_MASK (1<<5) 629 #define B_TX_PKT_NULL_MASK (1<<4) 630 #define B_TX_PKT_GEN_MASK (1<<3) 631 #define B_TX_KSVLISTCHK_MASK (1<<2) 632 #define B_TX_AUTH_DONE_MASK (1<<1) 633 #define B_TX_AUTH_FAIL_MASK (1<<0) 634 635 #define REG_TX_INT_MASK3 0x0B 636 #define B_TX_HDCP_SYNC_DET_FAIL_MASK (1<<6) 637 #define B_TX_AUDCTS_MASK (1<<5) 638 #define B_TX_VSYNC_MASK (1<<4) 639 #define B_TX_VIDSTABLE_MASK (1<<3) 640 #define B_TX_PKT_MPG_MASK (1<<2) 641 #define B_TX_PKT_SPD_MASK (1<<1) 642 #define B_TX_PKT_AUD_MASK (1<<0) 643 644 #define REG_TX_INT_CLR0 0x0C 645 #define B_TX_CLR_PKTACP (1<<7) 646 #define B_TX_CLR_PKTNULL (1<<6) 647 #define B_TX_CLR_PKTGENERAL (1<<5) 648 #define B_TX_CLR_KSVLISTCHK (1<<4) 649 #define B_TX_CLR_AUTH_DONE (1<<3) 650 #define B_TX_CLR_AUTH_FAIL (1<<2) 651 #define B_TX_CLR_RXSENSE (1<<1) 652 #define B_TX_CLR_HPD (1<<0) 653 654 #define REG_TX_INT_CLR1 0x0D 655 #define B_TX_CLR_VSYNC (1<<7) 656 #define B_TX_CLR_VIDSTABLE (1<<6) 657 #define B_TX_CLR_PKTMPG (1<<5) 658 #define B_TX_CLR_PKTSPD (1<<4) 659 #define B_TX_CLR_PKTAUD (1<<3) 660 #define B_TX_CLR_PKTAVI (1<<2) 661 #define B_TX_CLR_HDCP_SYNC_DET_FAIL (1<<1) 662 #define B_TX_CLR_VID_UNSTABLE (1<<0) 663 664 #define REG_TX_SYS_STATUS 0x0E 665 // readonly 666 #define B_TX_INT_ACTIVE (1<<7) 667 #define B_TX_HPDETECT (1<<6) 668 #define B_TX_RXSENDETECT (1<<5) 669 #define B_TXVIDSTABLE (1<<4) 670 // read/write 671 #define O_TX_CTSINTSTEP 2 672 #define M_TX_CTSINTSTEP (3<<2) 673 #define B_TX_CLR_AUD_CTS (1<<1) 674 #define B_TX_INTACTDONE (1<<0) 675 676 #define REG_TX_BANK_CTRL 0x0F 677 #define B_TX_BANK0 0 678 #define B_TX_BANK1 1 679 680 // DDC 681 682 #define REG_TX_DDC_MASTER_CTRL 0x10 683 #define B_TX_MASTERROM (1<<1) 684 #define B_TX_MASTERDDC (0<<1) 685 #define B_TX_MASTERHOST (1<<0) 686 #define B_TX_MASTERHDCP (0<<0) 687 688 #define REG_TX_DDC_HEADER 0x11 689 #define REG_TX_DDC_REQOFF 0x12 690 #define REG_TX_DDC_REQCOUNT 0x13 691 #define REG_TX_DDC_EDIDSEG 0x14 692 #define REG_TX_DDC_CMD 0x15 693 #define CMD_DDC_SEQ_BURSTREAD 0 694 #define CMD_LINK_CHKREAD 2 695 #define CMD_EDID_READ 3 696 #define CMD_FIFO_CLR 9 697 #define CMD_GEN_SCLCLK 0xA 698 #define CMD_DDC_ABORT 0xF 699 700 #define REG_TX_DDC_STATUS 0x16 701 #define B_TX_DDC_DONE (1<<7) 702 #define B_TX_DDC_ACT (1<<6) 703 #define B_TX_DDC_NOACK (1<<5) 704 #define B_TX_DDC_WAITBUS (1<<4) 705 #define B_TX_DDC_ARBILOSE (1<<3) 706 #define B_TX_DDC_ERROR (B_TX_DDC_NOACK|B_TX_DDC_WAITBUS|B_TX_DDC_ARBILOSE) 707 #define B_TX_DDC_FIFOFULL (1<<2) 708 #define B_TX_DDC_FIFOEMPTY (1<<1) 709 710 #define REG_TX_DDC_READFIFO 0x17 711 #define REG_TX_ROM_STARTADDR 0x18 712 #define REG_TX_HDCP_HEADER 0x19 713 #define REG_TX_ROM_HEADER 0x1A 714 #define REG_TX_BUSHOLD_T 0x1B 715 #define REG_TX_ROM_STAT 0x1C 716 #define B_TX_ROM_DONE (1<<7) 717 #define B_TX_ROM_ACTIVE (1<<6) 718 #define B_TX_ROM_NOACK (1<<5) 719 #define B_TX_ROM_WAITBUS (1<<4) 720 #define B_TX_ROM_ARBILOSE (1<<3) 721 #define B_TX_ROM_BUSHANG (1<<2) 722 723 // HDCP 724 #define REG_TX_AN_GENERATE 0x1F 725 #define B_TX_START_CIPHER_GEN 1 726 #define B_TX_STOP_CIPHER_GEN 0 727 728 #define REG_TX_CLK_CTRL0 0x58 729 #define O_TX_OSCLK_SEL 5 730 #define M_TX_OSCLK_SEL 3 731 #define B_TX_AUTO_OVER_SAMPLING_CLOCK (1<<4) 732 #define O_TX_EXT_MCLK_SEL 2 733 #define M_TX_EXT_MCLK_SEL (3<<O_TX_EXT_MCLK_SEL) 734 #define B_TX_EXT_128FS (0<<O_TX_EXT_MCLK_SEL) 735 #define B_TX_EXT_256FS (1<<O_TX_EXT_MCLK_SEL) 736 #define B_TX_EXT_512FS (2<<O_TX_EXT_MCLK_SEL) 737 #define B_TX_EXT_1024FS (3<<O_TX_EXT_MCLK_SEL) 738 739 #define REG_TX_SHA_SEL 0x50 740 #define REG_TX_SHA_RD_BYTE1 0x51 741 #define REG_TX_SHA_RD_BYTE2 0x52 742 #define REG_TX_SHA_RD_BYTE3 0x53 743 #define REG_TX_SHA_RD_BYTE4 0x54 744 #define REG_TX_AKSV_RD_BYTE5 0x55 745 746 747 #define REG_TX_CLK_CTRL1 0x59 748 #define B_TX_EN_TXCLK_COUNT (1<<5) 749 #define B_TX_VDO_LATCH_EDGE (1<<3) 750 751 #define REG_TX_CLK_STATUS1 0x5E 752 #define REG_TX_CLK_STATUS2 0x5F 753 #define B_TX_IP_LOCK (1<<7) 754 #define B_TX_XP_LOCK (1<<6) 755 #define B_TX_OSF_LOCK (1<<5) 756 757 #define REG_TX_AUD_COUNT 0x60 758 #define REG_TX_AFE_DRV_CTRL 0x61 759 760 #define B_TX_AFE_DRV_PWD (1<<5) 761 #define B_TX_AFE_DRV_RST (1<<4) 762 763 // Input Data Format Register 764 #define REG_TX_INPUT_MODE 0x70 765 #define O_TX_INCLKDLY 0 766 #define M_TX_INCLKDLY 3 767 #define B_TX_INDDR (1<<2) 768 #define B_TX_SYNCEMB (1<<3) 769 #define B_TX_2X656CLK (1<<4) 770 #define B_TX_PCLKDIV2 (1<<5) 771 #define M_TX_INCOLMOD (3<<6) 772 #define B_TX_IN_RGB 0 773 #define B_TX_IN_YUV422 (1<<6) 774 #define B_TX_IN_YUV444 (2<<6) 775 776 #define REG_TX_TXFIFO_RST 0x71 777 #define B_TX_ENAVMUTERST 1 778 #define B_TXFFRST (1<<1) 779 780 #define REG_TX_CSC_CTRL 0x72 781 #define B_HDMITX_CSC_BYPASS 0 782 #define B_HDMITX_CSC_RGB2YUV 2 783 #define B_HDMITX_CSC_YUV2RGB 3 784 #define M_TX_CSC_SEL 3 785 #define B_TX_EN_DITHER (1<<7) 786 #define B_TX_EN_UDFILTER (1<<6) 787 #define B_TX_DNFREE_GO (1<<5) 788 789 #define SIZEOF_CSCMTX 21 790 #define SIZEOF_CSCGAIN 6 791 #define SIZEOF_CSCOFFSET 3 792 793 794 #define REG_TX_CSC_YOFF 0x73 795 #define REG_TX_CSC_COFF 0x74 796 #define REG_TX_CSC_RGBOFF 0x75 797 798 #define REG_TX_CSC_MTX11_L 0x76 799 #define REG_TX_CSC_MTX11_H 0x77 800 #define REG_TX_CSC_MTX12_L 0x78 801 #define REG_TX_CSC_MTX12_H 0x79 802 #define REG_TX_CSC_MTX13_L 0x7A 803 #define REG_TX_CSC_MTX13_H 0x7B 804 #define REG_TX_CSC_MTX21_L 0x7C 805 #define REG_TX_CSC_MTX21_H 0x7D 806 #define REG_TX_CSC_MTX22_L 0x7E 807 #define REG_TX_CSC_MTX22_H 0x7F 808 #define REG_TX_CSC_MTX23_L 0x80 809 #define REG_TX_CSC_MTX23_H 0x81 810 #define REG_TX_CSC_MTX31_L 0x82 811 #define REG_TX_CSC_MTX31_H 0x83 812 #define REG_TX_CSC_MTX32_L 0x84 813 #define REG_TX_CSC_MTX32_H 0x85 814 #define REG_TX_CSC_MTX33_L 0x86 815 #define REG_TX_CSC_MTX33_H 0x87 816 817 #define REG_TX_CSC_GAIN1V_L 0x88 818 #define REG_TX_CSC_GAIN1V_H 0x89 819 #define REG_TX_CSC_GAIN2V_L 0x8A 820 #define REG_TX_CSC_GAIN2V_H 0x8B 821 #define REG_TX_CSC_GAIN3V_L 0x8C 822 #define REG_TX_CSC_GAIN3V_H 0x8D 823 824 #define REG_TX_HVPol 0x90 825 #define REG_TX_HfPixel 0x91 826 #define REG_TX_HSSL 0x95 827 #define REG_TX_HSEL 0x96 828 #define REG_TX_HSH 0x97 829 #define REG_TX_VSS1 0xA0 830 #define REG_TX_VSE1 0xA1 831 #define REG_TX_VSS2 0xA2 832 #define REG_TX_VSE2 0xA3 833 834 // HDMI General Control Registers 835 836 #define REG_TX_HDMI_MODE 0xC0 837 #define B_TX_HDMI_MODE 1 838 #define B_TX_DVI_MODE 0 839 #define REG_TX_AV_MUTE 0xC1 840 #define REG_TX_GCP 0xC1 841 #define B_TX_CLR_AVMUTE 0 842 #define B_TX_SET_AVMUTE 1 843 #define B_TX_SETAVMUTE (1<<0) 844 #define B_TX_BLUE_SCR_MUTE (1<<1) 845 #define B_TX_NODEF_PHASE (1<<2) 846 #define B_TX_PHASE_RESYNC (1<<3) 847 848 #define O_TX_COLOR_DEPTH 4 849 #define M_TX_COLOR_DEPTH 7 850 #define B_TX_COLOR_DEPTH_MASK (M_TX_COLOR_DEPTH<<O_TX_COLOR_DEPTH) 851 #define B_TX_CD_NODEF 0 852 #define B_TX_CD_24 (4<<4) 853 #define B_TX_CD_30 (5<<4) 854 #define B_TX_CD_36 (6<<4) 855 #define B_TX_CD_48 (7<<4) 856 #define REG_TX_PKT_GENERAL_CTRL 0xC6 857 858 #define REG_TX_OESS_CYCLE 0xC3 859 860 ///////////////////////////////////////////////////////////////////// 861 // data structure 862 ///////////////////////////////////////////////////////////////////// 863 #ifdef _SUPPORT_HDCP_REPEATER_ 864 typedef enum { 865 TxHDCP_Off=0,//0 866 TxHDCP_AuthRestart,//1 867 TxHDCP_AuthStart,//2 868 TxHDCP_Receiver,//3 869 TxHDCP_Repeater,//4 870 TxHDCP_CheckFIFORDY,//5 871 TxHDCP_VerifyRevocationList,//6 872 TxHDCP_CheckSHA,//7 873 TxHDCP_Authenticated,//8 874 TxHDCP_AuthFail,//9 875 TxHDCP_RepeaterFail,//10 876 TxHDCP_RepeaterSuccess,//11 877 TxHDCP_Reserved //12 878 } HDMITX_HDCP_State ; 879 #endif 880 881 typedef struct _HDMITXDEV_STRUCT { 882 883 u8 I2C_DEV ; 884 u8 I2C_ADDR ; 885 886 ///////////////////////////////////////////////// 887 // Interrupt Type 888 ///////////////////////////////////////////////// 889 u8 bIntType ; // = 0 ; 890 ///////////////////////////////////////////////// 891 // Video Property 892 ///////////////////////////////////////////////// 893 u8 bInputVideoSignalType ; // for Sync Embedded,CCIR656,InputDDR 894 ///////////////////////////////////////////////// 895 // Audio Property 896 ///////////////////////////////////////////////// 897 u8 bOutputAudioMode ; // = 0 ; 898 u8 bAudioChannelSwap ; // = 0 ; 899 u8 bAudioChannelEnable ; 900 u8 bAudFs ; 901 u32 TMDSClock ; 902 u32 RCLK ; 903 #ifdef _SUPPORT_HDCP_REPEATER_ 904 HDMITX_HDCP_State TxHDCP_State ; 905 u16 usHDCPTimeOut ; 906 u16 Tx_BStatus ; 907 #endif 908 u8 bAuthenticated:1 ; 909 u8 bHDMIMode: 1; 910 u8 bIntPOL:1 ; // 0 = Low Active 911 u8 bHPD:1 ; 912 // 2009/11/11 added by jj_tseng@ite.com.tw 913 u8 bAudInterface; 914 u8 TxEMEMStatus:1 ; 915 //~jau-chih.tseng@ite.com.tw 2009/11/11 916 } HDMITXDEV ; 917 918 // 2008/02/27 added by jj_tseng@chipadvanced.com 919 typedef enum _mode_id { 920 UNKNOWN_MODE=0, 921 CEA_640x480p60, 922 CEA_720x480p60, 923 CEA_1280x720p60, 924 CEA_1920x1080i60, 925 CEA_720x480i60, 926 CEA_720x240p60, 927 CEA_1440x480i60, 928 CEA_1440x240p60, 929 CEA_2880x480i60, 930 CEA_2880x240p60, 931 CEA_1440x480p60, 932 CEA_1920x1080p60, 933 CEA_720x576p50, 934 CEA_1280x720p50, 935 CEA_1920x1080i50, 936 CEA_720x576i50, 937 CEA_1440x576i50, 938 CEA_720x288p50, 939 CEA_1440x288p50, 940 CEA_2880x576i50, 941 CEA_2880x288p50, 942 CEA_1440x576p50, 943 CEA_1920x1080p50, 944 CEA_1920x1080p24, 945 CEA_1920x1080p25, 946 CEA_1920x1080p30, 947 VESA_640x350p85, 948 VESA_640x400p85, 949 VESA_720x400p85, 950 VESA_640x480p60, 951 VESA_640x480p72, 952 VESA_640x480p75, 953 VESA_640x480p85, 954 VESA_800x600p56, 955 VESA_800x600p60, 956 VESA_800x600p72, 957 VESA_800x600p75, 958 VESA_800X600p85, 959 VESA_840X480p60, 960 VESA_1024x768p60, 961 VESA_1024x768p70, 962 VESA_1024x768p75, 963 VESA_1024x768p85, 964 VESA_1152x864p75, 965 VESA_1280x768p60R, 966 VESA_1280x768p60, 967 VESA_1280x768p75, 968 VESA_1280x768p85, 969 VESA_1280x960p60, 970 VESA_1280x960p85, 971 VESA_1280x1024p60, 972 VESA_1280x1024p75, 973 VESA_1280X1024p85, 974 VESA_1360X768p60, 975 VESA_1400x768p60R, 976 VESA_1400x768p60, 977 VESA_1400x1050p75, 978 VESA_1400x1050p85, 979 VESA_1440x900p60R, 980 VESA_1440x900p60, 981 VESA_1440x900p75, 982 VESA_1440x900p85, 983 VESA_1600x1200p60, 984 VESA_1600x1200p65, 985 VESA_1600x1200p70, 986 VESA_1600x1200p75, 987 VESA_1600x1200p85, 988 VESA_1680x1050p60R, 989 VESA_1680x1050p60, 990 VESA_1680x1050p75, 991 VESA_1680x1050p85, 992 VESA_1792x1344p60, 993 VESA_1792x1344p75, 994 VESA_1856x1392p60, 995 VESA_1856x1392p75, 996 VESA_1920x1200p60R, 997 VESA_1920x1200p60, 998 VESA_1920x1200p75, 999 VESA_1920x1200p85, 1000 VESA_1920x1440p60, 1001 VESA_1920x1440p75, 1002 } MODE_ID ; 1003 1004 //~jj_tseng@chipadvanced.com 1005 1006 typedef struct structRegSetEntry { 1007 u8 offset; 1008 u8 mask; 1009 u8 value; 1010 } RegSetEntry; 1011 1012 // Audio Channel Control 1013 #define REG_TX_AUDIO_CTRL0 0xE0 1014 #define M_TX_AUD_SWL (3<<6) 1015 #define M_TX_AUD_16BIT (0<<6) 1016 #define M_TX_AUD_18BIT (1<<6) 1017 #define M_TX_AUD_20BIT (2<<6) 1018 #define M_TX_AUD_24BIT (3<<6) 1019 1020 #define B_TX_SPDIFTC (1<<5) 1021 1022 #define B_TX_AUD_SPDIF (1<<4) 1023 #define B_TX_AUD_I2S (0<<4) 1024 #define B_TX_AUD_EN_I2S3 (1<<3) 1025 #define B_TX_AUD_EN_I2S2 (1<<2) 1026 #define B_TX_AUD_EN_I2S1 (1<<1) 1027 #define B_TX_AUD_EN_I2S0 (1<<0) 1028 #define B_TX_AUD_EN_SPDIF 1 1029 1030 #define REG_TX_AUDIO_CTRL1 0xE1 1031 #define B_TX_AUD_FULLPKT (1<<6) 1032 1033 #define B_TX_AUDFMT_STD_I2S (0<<0) 1034 #define B_TX_AUDFMT_32BIT_I2S (1<<0) 1035 #define B_TX_AUDFMT_LEFT_JUSTIFY (0<<1) 1036 #define B_TX_AUDFMT_RIGHT_JUSTIFY (1<<1) 1037 #define B_TX_AUDFMT_DELAY_1T_TO_WS (0<<2) 1038 #define B_TX_AUDFMT_NO_DELAY_TO_WS (1<<2) 1039 #define B_TX_AUDFMT_WS0_LEFT (0<<3) 1040 #define B_TX_AUDFMT_WS0_RIGHT (1<<3) 1041 #define B_TX_AUDFMT_MSB_SHIFT_FIRST (0<<4) 1042 #define B_TX_AUDFMT_LSB_SHIFT_FIRST (1<<4) 1043 #define B_TX_AUDFMT_RISE_EDGE_SAMPLE_WS (0<<5) 1044 #define B_TX_AUDFMT_FALL_EDGE_SAMPLE_WS (1<<5) 1045 1046 #define REG_TX_AUDIO_FIFOMAP 0xE2 1047 #define O_TX_FIFO3SEL 6 1048 #define O_TX_FIFO2SEL 4 1049 #define O_TX_FIFO1SEL 2 1050 #define O_TX_FIFO0SEL 0 1051 #define B_TX_SELSRC3 3 1052 #define B_TX_SELSRC2 2 1053 #define B_TX_SELSRC1 1 1054 #define B_TX_SELSRC0 0 1055 1056 #define REG_TX_AUDIO_CTRL3 0xE3 1057 #define B_TX_AUD_MULCH (1<<7) 1058 #define B_TX_EN_ZERO_CTS (1<<6) 1059 #define B_TX_CHSTSEL (1<<4) 1060 #define B_TX_S3RLCHG (1<<3) 1061 #define B_TX_S2RLCHG (1<<2) 1062 #define B_TX_S1RLCHG (1<<1) 1063 #define B_TX_S0RLCHG (1<<0) 1064 1065 #define REG_TX_AUD_SRCVALID_FLAT 0xE4 1066 #define B_TX_AUD_SPXFLAT_SRC3 (1<<7) 1067 #define B_TX_AUD_SPXFLAT_SRC2 (1<<6) 1068 #define B_TX_AUD_SPXFLAT_SRC1 (1<<5) 1069 #define B_TX_AUD_SPXFLAT_SRC0 (1<<4) 1070 #define B_TX_AUD_ERR2FLAT (1<<3) 1071 #define B_TX_AUD_S3VALID (1<<2) 1072 #define B_TX_AUD_S2VALID (1<<1) 1073 #define B_TX_AUD_S1VALID (1<<0) 1074 1075 #define REG_TX_AUD_HDAUDIO 0xE5 1076 #define B_TX_HBR (1<<3) 1077 #define B_TX_DSD (1<<1) 1078 #define B_TX_TDM (1<<0) 1079 1080 ////////////////////////////////////////// 1081 // Bank 1 1082 ////////////////////////////////////////// 1083 1084 #define REGPktAudCTS0 0x30 // 7:0 1085 #define REGPktAudCTS1 0x31 // 15:8 1086 #define REGPktAudCTS2 0x32 // 19:16 1087 #define REGPktAudN0 0x33 // 7:0 1088 #define REGPktAudN1 0x34 // 15:8 1089 #define REGPktAudN2 0x35 // 19:16 1090 #define REGPktAudCTSCnt0 0x35 // 3:0 1091 #define REGPktAudCTSCnt1 0x36 // 11:4 1092 #define REGPktAudCTSCnt2 0x37 // 19:12 1093 1094 1095 #define REG_TX_AUDCHST_MODE 0x91 // 191 REG_TX_AUD_CHSTD[2:0] 6:4 1096 // REG_TX_AUD_CHSTC 3 1097 // REG_TX_AUD_NLPCM 2 1098 // REG_TX_AUD_MONO 0 1099 #define REG_TX_AUDCHST_CAT 0x92 // 192 REG_TX_AUD_CHSTCAT 7:0 1100 #define REG_TX_AUDCHST_SRCNUM 0x93 // 193 REG_TX_AUD_CHSTSRC 3:0 1101 #define REG_TX_AUD0CHST_CHTNUM 0x94 // 194 REG_TX_AUD0_CHSTCHR 7:4 1102 // REG_TX_AUD0_CHSTCHL 3:0 1103 #define REG_TX_AUD1CHST_CHTNUM 0x95 // 195 REG_TX_AUD1_CHSTCHR 7:4 1104 // REG_TX_AUD1_CHSTCHL 3:0 1105 #define REG_TX_AUD2CHST_CHTNUM 0x96 // 196 REG_TX_AUD2_CHSTCHR 7:4 1106 // REG_TX_AUD2_CHSTCHL 3:0 1107 #define REG_TX_AUD3CHST_CHTNUM 0x97 // 197 REG_TX_AUD3_CHSTCHR 7:4 1108 // REG_TX_AUD3_CHSTCHL 3:0 1109 #define REG_TX_AUDCHST_CA_FS 0x98 // 198 REG_TX_AUD_CHSTCA 5:4 1110 // REG_TX_AUD_CHSTFS 3:0 1111 #define REG_TX_AUDCHST_OFS_WL 0x99 // 199 REG_TX_AUD_CHSTOFS 7:4 1112 // REG_TX_AUD_CHSTWL 3:0 1113 1114 #define REG_TX_PKT_SINGLE_CTRL 0xC5 1115 #define B_TX_SINGLE_PKT 1 1116 #define B_TX_BURST_PKT 1117 #define B_TX_SW_CTS (1<<1) 1118 1119 #define REG_TX_NULL_CTRL 0xC9 1120 #define REG_TX_ACP_CTRL 0xCA 1121 #define REG_TX_ISRC1_CTRL 0xCB 1122 #define REG_TX_ISRC2_CTRL 0xCC 1123 #define REG_TX_AVI_INFOFRM_CTRL 0xCD 1124 #define REG_TX_AUD_INFOFRM_CTRL 0xCE 1125 #define REG_TX_SPD_INFOFRM_CTRL 0xCF 1126 #define REG_TX_MPG_INFOFRM_CTRL 0xD0 1127 #define B_TX_ENABLE_PKT 1 1128 #define B_TX_REPEAT_PKT (1<<1) 1129 1130 #define REG_TX_3D_INFO_CTRL 0xD2 1131 1132 ////////////////////////////////////////// 1133 // COMMON PACKET for NULL,ISRC1,ISRC2,SPD 1134 ////////////////////////////////////////// 1135 1136 #define REG_TX_PKT_HB00 0x38 1137 #define REG_TX_PKT_HB01 0x39 1138 #define REG_TX_PKT_HB02 0x3A 1139 1140 #define REG_TX_PKT_PB00 0x3B 1141 #define REG_TX_PKT_PB01 0x3C 1142 #define REG_TX_PKT_PB02 0x3D 1143 #define REG_TX_PKT_PB03 0x3E 1144 #define REG_TX_PKT_PB04 0x3F 1145 #define REG_TX_PKT_PB05 0x40 1146 #define REG_TX_PKT_PB06 0x41 1147 #define REG_TX_PKT_PB07 0x42 1148 #define REG_TX_PKT_PB08 0x43 1149 #define REG_TX_PKT_PB09 0x44 1150 #define REG_TX_PKT_PB10 0x45 1151 #define REG_TX_PKT_PB11 0x46 1152 #define REG_TX_PKT_PB12 0x47 1153 #define REG_TX_PKT_PB13 0x48 1154 #define REG_TX_PKT_PB14 0x49 1155 #define REG_TX_PKT_PB15 0x4A 1156 #define REG_TX_PKT_PB16 0x4B 1157 #define REG_TX_PKT_PB17 0x4C 1158 #define REG_TX_PKT_PB18 0x4D 1159 #define REG_TX_PKT_PB19 0x4E 1160 #define REG_TX_PKT_PB20 0x4F 1161 #define REG_TX_PKT_PB21 0x50 1162 #define REG_TX_PKT_PB22 0x51 1163 #define REG_TX_PKT_PB23 0x52 1164 #define REG_TX_PKT_PB24 0x53 1165 #define REG_TX_PKT_PB25 0x54 1166 #define REG_TX_PKT_PB26 0x55 1167 #define REG_TX_PKT_PB27 0x56 1168 1169 #define REG_TX_AVIINFO_DB1 0x58 1170 #define REG_TX_AVIINFO_DB2 0x59 1171 #define REG_TX_AVIINFO_DB3 0x5A 1172 #define REG_TX_AVIINFO_DB4 0x5B 1173 #define REG_TX_AVIINFO_DB5 0x5C 1174 #define REG_TX_AVIINFO_DB6 0x5E 1175 #define REG_TX_AVIINFO_DB7 0x5F 1176 #define REG_TX_AVIINFO_DB8 0x60 1177 #define REG_TX_AVIINFO_DB9 0x61 1178 #define REG_TX_AVIINFO_DB10 0x62 1179 #define REG_TX_AVIINFO_DB11 0x63 1180 #define REG_TX_AVIINFO_DB12 0x64 1181 #define REG_TX_AVIINFO_DB13 0x65 1182 #define REG_TX_AVIINFO_SUM 0x5D 1183 1184 #define REG_TX_PKT_AUDINFO_CC 0x68 // [2:0] 1185 #define REG_TX_PKT_AUDINFO_SF 0x69 // [4:2] 1186 #define REG_TX_PKT_AUDINFO_CA 0x6B // [7:0] 1187 1188 #define REG_TX_PKT_AUDINFO_DM_LSV 0x6C // [7][6:3] 1189 #define REG_TX_PKT_AUDINFO_SUM 0x6D // [7:0] 1190 1191 // Source Product Description Info Frame 1192 #define REG_TX_PKT_SPDINFO_SUM 0x70 1193 #define REG_TX_PKT_SPDINFO_PB1 0x71 1194 #define REG_TX_PKT_SPDINFO_PB2 0x72 1195 #define REG_TX_PKT_SPDINFO_PB3 0x73 1196 #define REG_TX_PKT_SPDINFO_PB4 0x74 1197 #define REG_TX_PKT_SPDINFO_PB5 0x75 1198 #define REG_TX_PKT_SPDINFO_PB6 0x76 1199 #define REG_TX_PKT_SPDINFO_PB7 0x77 1200 #define REG_TX_PKT_SPDINFO_PB8 0x78 1201 #define REG_TX_PKT_SPDINFO_PB9 0x79 1202 #define REG_TX_PKT_SPDINFO_PB10 0x7A 1203 #define REG_TX_PKT_SPDINFO_PB11 0x7B 1204 #define REG_TX_PKT_SPDINFO_PB12 0x7C 1205 #define REG_TX_PKT_SPDINFO_PB13 0x7D 1206 #define REG_TX_PKT_SPDINFO_PB14 0x7E 1207 #define REG_TX_PKT_SPDINFO_PB15 0x7F 1208 #define REG_TX_PKT_SPDINFO_PB16 0x80 1209 #define REG_TX_PKT_SPDINFO_PB17 0x81 1210 #define REG_TX_PKT_SPDINFO_PB18 0x82 1211 #define REG_TX_PKT_SPDINFO_PB19 0x83 1212 #define REG_TX_PKT_SPDINFO_PB20 0x84 1213 #define REG_TX_PKT_SPDINFO_PB21 0x85 1214 #define REG_TX_PKT_SPDINFO_PB22 0x86 1215 #define REG_TX_PKT_SPDINFO_PB23 0x87 1216 #define REG_TX_PKT_SPDINFO_PB24 0x88 1217 #define REG_TX_PKT_SPDINFO_PB25 0x89 1218 1219 #define REG_TX_PKT_MPGINFO_FMT 0x8A 1220 #define B_TX_MPG_FR 1 1221 #define B_TX_MPG_MF_I (1<<1) 1222 #define B_TX_MPG_MF_B (2<<1) 1223 #define B_TX_MPG_MF_P (3<<1) 1224 #define B_TX_MPG_MF_MASK (3<<1) 1225 #define REG_TX_PKG_MPGINFO_DB0 0x8B 1226 #define REG_TX_PKG_MPGINFO_DB1 0x8C 1227 #define REG_TX_PKG_MPGINFO_DB2 0x8D 1228 #define REG_TX_PKG_MPGINFO_DB3 0x8E 1229 #define REG_TX_PKG_MPGINFO_SUM 0x8F 1230 1231 #define Frame_Pcaking 0 1232 #define Top_and_Botton 6 1233 #define Side_by_Side 8 1234 1235 //////////////////////////////////////////////////// 1236 // Function Prototype 1237 //////////////////////////////////////////////////// 1238 #define hdmitx_ENABLE_NULL_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_NULL_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); } 1239 #define hdmitx_ENABLE_ACP_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_ACP_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); } 1240 #define hdmitx_ENABLE_ISRC1_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_ISRC1_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); } 1241 #define hdmitx_ENABLE_ISRC2_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_ISRC2_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); } 1242 #define hdmitx_ENABLE_AVI_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_AVI_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); } 1243 #define hdmitx_ENABLE_AUD_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_AUD_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); } 1244 #define hdmitx_ENABLE_SPD_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_SPD_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); } 1245 #define hdmitx_ENABLE_MPG_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_MPG_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); } 1246 #define hdmitx_ENABLE_GeneralPurpose_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_NULL_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); } 1247 #define hdmitx_DISABLE_VSDB_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_3D_INFO_CTRL,0); } 1248 #define hdmitx_DISABLE_NULL_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_NULL_CTRL,0); } 1249 #define hdmitx_DISABLE_ACP_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_ACP_CTRL,0); } 1250 #define hdmitx_DISABLE_ISRC1_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_ISRC1_CTRL,0); } 1251 #define hdmitx_DISABLE_ISRC2_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_ISRC2_CTRL,0); } 1252 #define hdmitx_DISABLE_AVI_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_AVI_INFOFRM_CTRL,0); } 1253 #define hdmitx_DISABLE_AUD_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_AUD_INFOFRM_CTRL,0); } 1254 #define hdmitx_DISABLE_SPD_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_SPD_INFOFRM_CTRL,0); } 1255 #define hdmitx_DISABLE_MPG_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_MPG_INFOFRM_CTRL,0); } 1256 #define hdmitx_DISABLE_GeneralPurpose_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_NULL_CTRL,0); } 1257 1258 ////////////////////////////////////////////////////////////////////// 1259 // External Interface 1260 ////////////////////////////////////////////////////////////////////// 1261 1262 typedef enum { 1263 PCLK_LOW = 0 , 1264 PCLK_MEDIUM, 1265 PCLK_HIGH 1266 } VIDEOPCLKLEVEL ; 1267 1268 u8 CheckHDMITX(u8 *pHPD,u8 *pHPDChange); 1269 static bool getHDMITX_LinkStatus(void); 1270 void HDMITX_PowerDown(void); 1271 bool HDMITX_EnableVideoOutput(VIDEOPCLKLEVEL level,u8 inputColorMode,u8 outputColorMode,u8 bHDMI); 1272 bool setHDMITX_VideoSignalType(u8 inputSignalType); 1273 void setHDMITX_ColorDepthPhase(u8 ColorDepth,u8 bPhase); 1274 1275 // TBD ... 1276 // #ifdef SUPPORT_DEGEN 1277 // bool ProgramDEGenModeByID(MODE_ID id,u8 bInputSignalType); 1278 // #endif // SUPPORT_DEGEN 1279 1280 #ifdef SUPPORT_SYNCEMBEDDED 1281 bool setHDMITX_SyncEmbeddedByVIC(u8 VIC,u8 bInputSignalType); 1282 #endif 1283 1284 ///////////////////////////////////////////////////////////////////////////////////// 1285 // HDMITX audio function prototype 1286 ///////////////////////////////////////////////////////////////////////////////////// 1287 #ifdef SUPPORT_AUDIO_MONITOR 1288 //void setHDMITX_AudioChannelEnable(bool EnableAudio_b); 1289 #endif //#ifdef SUPPORT_AUDIO_MONITOR 1290 static void setHDMITX_DSDAudio(void); 1291 static void setHDMITX_HBRAudio(u8 bAudInterface /*I2S/SPDIF/TDM*/); 1292 static void setHDMITX_LPCMAudio(u8 AudioSrcNum, u8 AudSWL, u8 bAudInterface /*I2S/SPDIF/TDM*/); 1293 static void setHDMITX_NCTS(u8 Fs); 1294 static void setHDMITX_NLPCMAudio(u8 bAudInterface /*I2S/SPDIF/TDM*/); 1295 //void setHDMITX_UpdateChStatFs(u32 Fs); 1296 #ifdef SUPPORT_AUDIO_MONITOR 1297 bool hdmitx_IsAudioChang(void); 1298 void hdmitx_AutoAdjustAudio(void); 1299 #endif //#ifdef SUPPORT_AUDIO_MONITOR 1300 1301 ///////////////////////////////////////////////////////////////////////////////////// 1302 // HDMITX pkt/infoframe function prototype 1303 ///////////////////////////////////////////////////////////////////////////////////// 1304 1305 //SYS_STATUS hdmitx_SetSPDInfoFrame(SPD_InfoFrame *pSPDInfoFrame); 1306 //SYS_STATUS hdmitx_SetMPEGInfoFrame(MPEG_InfoFrame *pMPGInfoFrame); 1307 //SYS_STATUS hdmitx_Set_GeneralPurpose_PKT(u8 *pData); 1308 1309 //////////////////////////////////////////////////////////////////// 1310 // Required Interfance 1311 //////////////////////////////////////////////////////////////////// 1312 /*u8 HDMITX_ReadI2C_Byte(u8 RegAddr); 1313 SYS_STATUS it6161_hdmi_tx_write(it6161, u8 RegAddr,u8 d); 1314 SYS_STATUS HDMITX_ReadI2C_ByteN(u8 RegAddr,u8 *pData,int N); 1315 SYS_STATUS HDMITX_WriteI2C_ByteN(u8 RegAddr,u8 *pData,int N); 1316 SYS_STATUS HDMITX_SetI2C_Byte(u8 Reg,u8 Mask,u8 Value); 1317 SYS_STATUS HDMITX_ToggleBit(u8 Reg,u8 n);*/ 1318 1319 1320 #endif // _HDMITX_DRV_H_ 1321 1322 #ifndef _HDMITX_SYS_H_ 1323 #define _HDMITX_SYS_H_ 1324 1325 #define I2S 0 1326 #define SPDIF 1 1327 #define TDM 2 1328 1329 #ifndef I2S_FORMAT 1330 #define I2S_FORMAT 0x01 // 32bit audio 1331 #endif 1332 1333 #ifndef INPUT_SAMPLE_FREQ 1334 #define INPUT_SAMPLE_FREQ AUDFS_48KHz 1335 #endif //INPUT_SAMPLE_FREQ 1336 1337 #ifndef INPUT_SAMPLE_FREQ_HZ 1338 #define INPUT_SAMPLE_FREQ_HZ 48000L 1339 #endif //INPUT_SAMPLE_FREQ_HZ 1340 1341 #ifndef OUTPUT_CHANNEL 1342 #define OUTPUT_CHANNEL 2 1343 #endif //OUTPUT_CHANNEL 1344 1345 #ifndef CNOFIG_INPUT_AUDIO_TYPE 1346 #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_LPCM 1347 // #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_NLPCM 1348 // #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_HBR 1349 #endif //CNOFIG_INPUT_AUDIO_TYPE 1350 1351 #ifndef CONFIG_INPUT_AUDIO_INTERFACE 1352 #define CONFIG_INPUT_AUDIO_INTERFACE I2S 1353 // #define CONFIG_INPUT_AUDIO_INTERFACE SPDIF 1354 #endif //CONFIG_INPUT_AUDIO_INTERFACE 1355 1356 #ifndef INPUT_SIGNAL_TYPE 1357 #define INPUT_SIGNAL_TYPE 0 // 24 bit sync seperate 1358 #endif 1359 1360 //////////////////////////////////////////////////////////////////////////////// 1361 // Internal Data Type 1362 //////////////////////////////////////////////////////////////////////////////// 1363 1364 typedef enum tagHDMI_Video_Type { 1365 HDMI_Unkown = 0 , 1366 HDMI_640x480p60 = 1 , 1367 HDMI_480p60, 1368 HDMI_480p60_16x9, 1369 HDMI_720p60, 1370 HDMI_1080i60, 1371 HDMI_480i60, 1372 HDMI_480i60_16x9, 1373 HDMI_1080p60 = 16, 1374 HDMI_576p50, 1375 HDMI_576p50_16x9, 1376 HDMI_720p50, 1377 HDMI_1080i50, 1378 HDMI_576i50, 1379 HDMI_576i50_16x9, 1380 HDMI_1080p50 = 31, 1381 HDMI_1080p24, 1382 HDMI_1080p25, 1383 HDMI_1080p30, 1384 HDMI_720p30 = 61, 1385 } HDMI_Video_Type ; 1386 1387 typedef enum tagHDMI_Aspec { 1388 HDMI_4x3 , 1389 HDMI_16x9 1390 } HDMI_Aspec; 1391 1392 typedef enum tagHDMI_OutputColorMode { 1393 HDMI_RGB444, 1394 HDMI_YUV444, 1395 HDMI_YUV422 1396 } HDMI_OutputColorMode ; 1397 1398 typedef enum tagHDMI_Colorimetry { 1399 HDMI_ITU601, 1400 HDMI_ITU709 1401 } HDMI_Colorimetry ; 1402 1403 struct VideoTiming { 1404 u32 VideoPixelClock ; 1405 u8 VIC ; 1406 u8 pixelrep ; 1407 u8 outputVideoMode ; 1408 } ; 1409 1410 1411 1412 typedef enum _TXVideo_State_Type { 1413 TXVSTATE_Unplug = 0, 1414 TXVSTATE_HPD, 1415 TXVSTATE_WaitForMode, 1416 TXVSTATE_WaitForVStable, 1417 TXVSTATE_VideoInit, 1418 TXVSTATE_VideoSetup, 1419 TXVSTATE_VideoOn, 1420 TXVSTATE_Reserved 1421 } TXVideo_State_Type ; 1422 1423 1424 typedef enum _TXAudio_State_Type { 1425 TXASTATE_AudioOff = 0, 1426 TXASTATE_AudioPrepare, 1427 TXASTATE_AudioOn, 1428 TXASTATE_AudioFIFOFail, 1429 TXASTATE_Reserved 1430 } TXAudio_State_Type ; 1431 ///////////////////////////////////////// 1432 // RX Capability. 1433 ///////////////////////////////////////// 1434 typedef struct { 1435 u8 b16bit:1 ; 1436 u8 b20bit:1 ; 1437 u8 b24bit:1 ; 1438 u8 Rsrv:5 ; 1439 } LPCM_BitWidth ; 1440 1441 typedef enum { 1442 AUD_RESERVED_0 = 0 , 1443 AUD_LPCM, 1444 AUD_AC3, 1445 AUD_MPEG1, 1446 AUD_MP3, 1447 AUD_MPEG2, 1448 AUD_AAC, 1449 AUD_DTS, 1450 AUD_ATRAC, 1451 AUD_ONE_BIT_AUDIO, 1452 AUD_DOLBY_DIGITAL_PLUS, 1453 AUD_DTS_HD, 1454 AUD_MAT_MLP, 1455 AUD_DST, 1456 AUD_WMA_PRO, 1457 AUD_RESERVED_15 1458 } AUDIO_FORMAT_CODE ; 1459 1460 typedef union { 1461 struct { 1462 u8 channel:3 ; 1463 u8 AudioFormatCode:4 ; 1464 u8 Rsrv1:1 ; 1465 1466 u8 b32KHz:1 ; 1467 u8 b44_1KHz:1 ; 1468 u8 b48KHz:1 ; 1469 u8 b88_2KHz:1 ; 1470 u8 b96KHz:1 ; 1471 u8 b176_4KHz:1 ; 1472 u8 b192KHz:1 ; 1473 u8 Rsrv2:1 ; 1474 u8 ucCode ; 1475 } s ; 1476 u8 uc[3] ; 1477 } AUDDESCRIPTOR ; 1478 1479 typedef union { 1480 struct { 1481 u8 FL_FR:1 ; 1482 u8 LFE:1 ; 1483 u8 FC:1 ; 1484 u8 RL_RR:1 ; 1485 u8 RC:1 ; 1486 u8 FLC_FRC:1 ; 1487 u8 RLC_RRC:1 ; 1488 u8 Reserve:1 ; 1489 u8 Unuse[2] ; 1490 } s ; 1491 u8 uc[3] ; 1492 } SPK_ALLOC ; 1493 1494 #define CEA_SUPPORT_UNDERSCAN (1<<7) 1495 #define CEA_SUPPORT_AUDIO (1<<6) 1496 #define CEA_SUPPORT_YUV444 (1<<5) 1497 #define CEA_SUPPORT_YUV422 (1<<4) 1498 #define CEA_NATIVE_MASK 0xF 1499 1500 1501 #define HDMI_DC_SUPPORT_AI (1<<7) 1502 #define HDMI_DC_SUPPORT_48 (1<<6) 1503 #define HDMI_DC_SUPPORT_36 (1<<5) 1504 #define HDMI_DC_SUPPORT_30 (1<<4) 1505 #define HDMI_DC_SUPPORT_Y444 (1<<3) 1506 #define HDMI_DC_SUPPORT_DVI_DUAL 1 1507 1508 typedef union _tag_DCSUPPORT { 1509 struct { 1510 u8 DVI_Dual:1 ; 1511 u8 Rsvd:2 ; 1512 u8 DC_Y444:1 ; 1513 u8 DC_30Bit:1 ; 1514 u8 DC_36Bit:1 ; 1515 u8 DC_48Bit:1 ; 1516 u8 SUPPORT_AI:1 ; 1517 } info ; 1518 u8 uc ; 1519 } DCSUPPORT ; 1520 1521 typedef union _LATENCY_SUPPORT{ 1522 struct { 1523 u8 Rsvd:6 ; 1524 u8 I_Latency_Present:1 ; 1525 u8 Latency_Present:1 ; 1526 } info ; 1527 u8 uc ; 1528 } LATENCY_SUPPORT ; 1529 1530 #define HDMI_IEEEOUI 0x0c03 1531 #define MAX_VODMODE_COUNT 32 1532 #define MAX_AUDDES_COUNT 4 1533 1534 typedef struct _RX_CAP{ 1535 u8 VideoMode ; 1536 u8 NativeVDOMode ; 1537 u8 VDOMode[8] ; 1538 u8 AUDDesCount ; 1539 AUDDESCRIPTOR AUDDes[MAX_AUDDES_COUNT] ; 1540 u8 PA[2] ; 1541 u32 IEEEOUI ; 1542 DCSUPPORT dc ; 1543 u8 MaxTMDSClock ; 1544 LATENCY_SUPPORT lsupport ; 1545 SPK_ALLOC SpeakerAllocBlk ; 1546 u8 ValidCEA:1 ; 1547 u8 ValidHDMI:1 ; 1548 u8 Valid3D:1 ; 1549 } RX_CAP ; 1550 1551 /////////////////////////////////////////////////////////////////////// 1552 // Output Mode Type 1553 /////////////////////////////////////////////////////////////////////// 1554 1555 #define RES_ASPEC_4x3 0 1556 #define RES_ASPEC_16x9 1 1557 #define F_MODE_REPT_NO 0 1558 #define F_MODE_REPT_TWICE 1 1559 #define F_MODE_REPT_QUATRO 3 1560 #define F_MODE_CSC_ITU601 0 1561 #define F_MODE_CSC_ITU709 1 1562 1563 void HDMITX_DevLoopProc(void); 1564 //void HDMITX_ChangeAudioOption(u8 Option, u8 channelNum, u8 AudioFs); 1565 //void HDMITX_ChangeColorDepth(u8 colorDepth); 1566 1567 #endif // _HDMITX_SYS_H_ 1568 1569 #ifndef _HDMITX_HDCP_H_ 1570 #define _HDMITX_HDCP_H_ 1571 1572 #define REG_TX_HDCP_DESIRE 0x20 1573 #define B_TX_ENABLE_HDPC11 (1<<1) 1574 #define B_TX_CPDESIRE (1<<0) 1575 1576 #define REG_TX_AUTHFIRE 0x21 1577 #define REG_TX_LISTCTRL 0x22 1578 #define B_TX_LISTFAIL (1<<1) 1579 #define B_TX_LISTDONE (1<<0) 1580 1581 #define REG_TX_AKSV 0x23 1582 #define REG_TX_AKSV0 0x23 1583 #define REG_TX_AKSV1 0x24 1584 #define REG_TX_AKSV2 0x25 1585 #define REG_TX_AKSV3 0x26 1586 #define REG_TX_AKSV4 0x27 1587 1588 #define REG_TX_AN 0x28 1589 #define REG_TX_AN_GEN 0x30 1590 #define REG_TX_ARI 0x38 1591 #define REG_TX_ARI0 0x38 1592 #define REG_TX_ARI1 0x39 1593 #define REG_TX_APJ 0x3A 1594 1595 #define REG_TX_BKSV 0x3B 1596 #define REG_TX_BRI 0x40 1597 #define REG_TX_BRI0 0x40 1598 #define REG_TX_BRI1 0x41 1599 #define REG_TX_BPJ 0x42 1600 #define REG_TX_BCAP 0x43 1601 #define B_TX_CAP_HDMI_REPEATER (1<<6) 1602 #define B_TX_CAP_KSV_FIFO_RDY (1<<5) 1603 #define B_TX_CAP_HDMI_FAST_MODE (1<<4) 1604 #define B_CAP_HDCP_1p1 (1<<1) 1605 #define B_TX_CAP_FAST_REAUTH (1<<0) 1606 #define REG_TX_BSTAT 0x44 1607 #define REG_TX_BSTAT0 0x44 1608 #define REG_TX_BSTAT1 0x45 1609 #define B_TX_CAP_HDMI_MODE (1<<12) 1610 #define B_TX_CAP_DVI_MODE (0<<12) 1611 #define B_TX_MAX_CASCADE_EXCEEDED (1<<11) 1612 #define M_TX_REPEATER_DEPTH (0x7<<8) 1613 #define O_TX_REPEATER_DEPTH 8 1614 #define B_TX_DOWNSTREAM_OVER (1<<7) 1615 #define M_TX_DOWNSTREAM_COUNT 0x7F 1616 1617 #define REG_TX_AUTH_STAT 0x46 1618 #define B_TX_AUTH_DONE (1<<7) 1619 //////////////////////////////////////////////////// 1620 // Function Prototype 1621 //////////////////////////////////////////////////// 1622 1623 //SYS_STATUS hdmitx_hdcp_VerifyIntegration(); 1624 //static SYS_STATUS hdmitx_hdcp_CheckSHA(u8 pM0[],u16 BStatus,u8 pKSVList[],int cDownStream,u8 Vr[]); 1625 #endif // _HDMITX_HDCP_H_ 1626 1627 1628 #if (defined (SUPPORT_OUTPUTYUV)) && (defined (SUPPORT_INPUTRGB)) 1629 1630 static u8 bCSCMtx_RGB2YUV_ITU601_16_235[] = 1631 { 1632 0x00,0x80,0x00, 1633 0xB2,0x04,0x65,0x02,0xE9,0x00, 1634 0x93,0x3C,0x18,0x04,0x55,0x3F, 1635 0x49,0x3D,0x9F,0x3E,0x18,0x04 1636 } ; 1637 1638 static u8 bCSCMtx_RGB2YUV_ITU601_0_255[] = 1639 { 1640 0x10,0x80,0x10, 1641 0x09,0x04,0x0E,0x02,0xC9,0x00, 1642 0x0F,0x3D,0x84,0x03,0x6D,0x3F, 1643 0xAB,0x3D,0xD1,0x3E,0x84,0x03 1644 } ; 1645 1646 static u8 bCSCMtx_RGB2YUV_ITU709_16_235[] = 1647 { 1648 0x00,0x80,0x00, 1649 0xB8,0x05,0xB4,0x01,0x94,0x00, 1650 0x4a,0x3C,0x17,0x04,0x9F,0x3F, 1651 0xD9,0x3C,0x10,0x3F,0x17,0x04 1652 } ; 1653 1654 static u8 bCSCMtx_RGB2YUV_ITU709_0_255[] = 1655 { 1656 0x10,0x80,0x10, 1657 0xEa,0x04,0x77,0x01,0x7F,0x00, 1658 0xD0,0x3C,0x83,0x03,0xAD,0x3F, 1659 0x4B,0x3D,0x32,0x3F,0x83,0x03 1660 } ; 1661 #endif 1662 1663 #if (defined (SUPPORT_OUTPUTRGB)) && (defined (SUPPORT_INPUTYUV)) 1664 1665 static u8 bCSCMtx_YUV2RGB_ITU601_16_235[] = 1666 { 1667 0x00,0x00,0x00, 1668 0x00,0x08,0x6B,0x3A,0x50,0x3D, 1669 0x00,0x08,0xF5,0x0A,0x02,0x00, 1670 0x00,0x08,0xFD,0x3F,0xDA,0x0D 1671 } ; 1672 1673 static u8 bCSCMtx_YUV2RGB_ITU601_0_255[] = 1674 { 1675 0x04,0x00,0xA7, 1676 0x4F,0x09,0x81,0x39,0xDD,0x3C, 1677 0x4F,0x09,0xC4,0x0C,0x01,0x00, 1678 0x4F,0x09,0xFD,0x3F,0x1F,0x10 1679 } ; 1680 1681 static u8 bCSCMtx_YUV2RGB_ITU709_16_235[] = 1682 { 1683 0x00,0x00,0x00, 1684 0x00,0x08,0x55,0x3C,0x88,0x3E, 1685 0x00,0x08,0x51,0x0C,0x00,0x00, 1686 0x00,0x08,0x00,0x00,0x84,0x0E 1687 } ; 1688 1689 static u8 bCSCMtx_YUV2RGB_ITU709_0_255[] = 1690 { 1691 0x04,0x00,0xA7, 1692 0x4F,0x09,0xBA,0x3B,0x4B,0x3E, 1693 0x4F,0x09,0x57,0x0E,0x02,0x00, 1694 0x4F,0x09,0xFE,0x3F,0xE8,0x10 1695 } ; 1696 #endif 1697