1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Register definition file for Analogix DP core driver 4 * 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 */ 8 9 #ifndef _ANALOGIX_DP_REG_H 10 #define _ANALOGIX_DP_REG_H 11 12 #define ANALOGIX_DP_TX_SW_RESET 0x14 13 #define ANALOGIX_DP_FUNC_EN_1 0x18 14 #define ANALOGIX_DP_FUNC_EN_2 0x1C 15 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 16 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 17 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 18 #define ANALOGIX_DP_VIDEO_CTL_4 0x2C 19 20 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 21 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 22 #define ANALOGIX_DP_TOTAL_LINE_CFG_L 0x48 23 #define ANALOGIX_DP_TOTAL_LINE_CFG_H 0x4C 24 #define ANALOGIX_DP_ACTIVE_LINE_CFG_L 0x50 25 #define ANALOGIX_DP_ACTIVE_LINE_CFG_H 0x54 26 #define ANALOGIX_DP_V_F_PORCH_CFG 0x58 27 #define ANALOGIX_DP_V_SYNC_WIDTH_CFG 0x5C 28 #define ANALOGIX_DP_V_B_PORCH_CFG 0x60 29 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_L 0x64 30 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_H 0x68 31 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_L 0x6C 32 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_H 0x70 33 #define ANALOGIX_DP_H_F_PORCH_CFG_L 0x74 34 #define ANALOGIX_DP_H_F_PORCH_CFG_H 0x78 35 #define ANALOGIX_DP_H_SYNC_CFG_L 0x7C 36 #define ANALOGIX_DP_H_SYNC_CFG_H 0x80 37 #define ANALOGIX_DP_H_B_PORCH_CFG_L 0x84 38 #define ANALOGIX_DP_H_B_PORCH_CFG_H 0x88 39 40 #define ANALOGIX_DP_SPDIF_AUDIO_CTL_0 0xD8 41 42 #define ANALOGIX_DP_PLL_REG_1 0xfc 43 #define ANALOGIX_DP_PLL_REG_2 0x9e4 44 #define ANALOGIX_DP_PLL_REG_3 0x9e8 45 #define ANALOGIX_DP_PLL_REG_4 0x9ec 46 #define ANALOGIX_DP_PLL_REG_5 0xa00 47 48 #define ANALOIGX_DP_SSC_REG 0x104 49 #define ANALOGIX_DP_BIAS 0x124 50 #define ANALOGIX_DP_PD 0x12c 51 52 #define ANALOGIX_DP_IF_TYPE 0x244 53 #define ANALOGIX_DP_IF_PKT_DB1 0x254 54 #define ANALOGIX_DP_IF_PKT_DB2 0x258 55 #define ANALOGIX_DP_SPD_HB0 0x2F8 56 #define ANALOGIX_DP_SPD_HB1 0x2FC 57 #define ANALOGIX_DP_SPD_HB2 0x300 58 #define ANALOGIX_DP_SPD_HB3 0x304 59 #define ANALOGIX_DP_SPD_PB0 0x308 60 #define ANALOGIX_DP_SPD_PB1 0x30C 61 #define ANALOGIX_DP_SPD_PB2 0x310 62 #define ANALOGIX_DP_SPD_PB3 0x314 63 #define ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL 0x318 64 #define ANALOGIX_DP_VSC_SHADOW_DB0 0x31C 65 #define ANALOGIX_DP_VSC_SHADOW_DB1 0x320 66 #define ANALOGIX_DP_VSC_SHADOW_PB0 0x33C 67 #define ANALOGIX_DP_VSC_SHADOW_PB1 0x340 68 69 #define ANALOGIX_DP_LANE_MAP 0x35C 70 71 #define ANALOGIX_DP_ANALOG_CTL_1 0x370 72 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 73 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 74 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 75 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 76 77 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 78 79 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 80 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 81 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 82 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 83 #define ANALOGIX_DP_INT_STA 0x3DC 84 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 85 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 86 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 87 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 88 #define ANALOGIX_DP_INT_STA_MASK 0x3F8 89 #define ANALOGIX_DP_INT_CTL 0x3FC 90 91 #define ANALOGIX_DP_SYS_CTL_1 0x600 92 #define ANALOGIX_DP_SYS_CTL_2 0x604 93 #define ANALOGIX_DP_SYS_CTL_3 0x608 94 #define ANALOGIX_DP_SYS_CTL_4 0x60C 95 #define ANALOGIX_DP_AUD_CTL 0x618 96 #define ANALOGIX_DP_PKT_SEND_CTL 0x640 97 #define ANALOGIX_DP_HDCP_CTL 0x648 98 99 #define ANALOGIX_DP_LINK_BW_SET 0x680 100 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 101 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 102 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 103 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 104 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 105 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 106 107 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 108 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 109 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 110 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 111 112 #define ANALOGIX_DP_M_VID_0 0x700 113 #define ANALOGIX_DP_M_VID_1 0x704 114 #define ANALOGIX_DP_M_VID_2 0x708 115 #define ANALOGIX_DP_N_VID_0 0x70C 116 #define ANALOGIX_DP_N_VID_1 0x710 117 #define ANALOGIX_DP_N_VID_2 0x714 118 119 #define ANALOGIX_DP_PLL_CTL 0x71C 120 #define ANALOGIX_DP_PHY_PD 0x720 121 #define ANALOGIX_DP_PHY_TEST 0x724 122 123 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 124 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C 125 126 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 127 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 128 #define ANALOGIX_DP_AUX_CH_STA 0x780 129 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 130 #define ANALOGIX_DP_AUX_RX_COMM 0x78C 131 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 132 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 133 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 134 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 135 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 136 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 137 138 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 139 140 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 141 #define ANALOGIX_DP_TEST_80B_PATTERN0 0x81C 142 #define ANALOGIX_DP_TEST_80B_PATTERN1 0x820 143 #define ANALOGIX_DP_TEST_80B_PATTERN2 0x824 144 #define ANALOGIX_DP_TEST_HBR2_PATTERN 0x828 145 #define ANALOGIX_DP_AUD_CHANNEL_CTL 0x834 146 #define ANALOGIX_DP_CRC_CON 0x890 147 #define ANALOGIX_DP_I2S_CTRL 0x9C8 148 149 /* ANALOGIX_DP_TX_SW_RESET */ 150 #define RESET_DP_TX (0x1 << 0) 151 152 /* ANALOGIX_DP_FUNC_EN_1 */ 153 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 154 #define RK_VID_CAP_FUNC_EN_N (0x1 << 6) 155 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 156 #define RK_VID_FIFO_FUNC_EN_N (0x1 << 5) 157 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 158 #define AUD_FUNC_EN_N (0x1 << 3) 159 #define HDCP_FUNC_EN_N (0x1 << 2) 160 #define CRC_FUNC_EN_N (0x1 << 1) 161 #define SW_FUNC_EN_N (0x1 << 0) 162 163 /* ANALOGIX_DP_FUNC_EN_2 */ 164 #define SSC_FUNC_EN_N (0x1 << 7) 165 #define AUX_FUNC_EN_N (0x1 << 2) 166 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 167 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 168 169 /* ANALOGIX_DP_VIDEO_CTL_1 */ 170 #define VIDEO_EN (0x1 << 7) 171 #define HDCP_VIDEO_MUTE (0x1 << 6) 172 173 /* ANALOGIX_DP_VIDEO_CTL_1 */ 174 #define IN_D_RANGE_MASK (0x1 << 7) 175 #define IN_D_RANGE_SHIFT (7) 176 #define IN_D_RANGE_CEA (0x1 << 7) 177 #define IN_D_RANGE_VESA (0x0 << 7) 178 #define IN_BPC_MASK (0x7 << 4) 179 #define IN_BPC_SHIFT (4) 180 #define IN_BPC_12_BITS (0x3 << 4) 181 #define IN_BPC_10_BITS (0x2 << 4) 182 #define IN_BPC_8_BITS (0x1 << 4) 183 #define IN_BPC_6_BITS (0x0 << 4) 184 #define IN_COLOR_F_MASK (0x3 << 0) 185 #define IN_COLOR_F_SHIFT (0) 186 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 187 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 188 #define IN_COLOR_F_RGB (0x0 << 0) 189 190 /* ANALOGIX_DP_VIDEO_CTL_3 */ 191 #define IN_YC_COEFFI_MASK (0x1 << 7) 192 #define IN_YC_COEFFI_SHIFT (7) 193 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 194 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 195 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 196 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 197 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 198 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 199 #define REUSE_SPD_EN (0x1 << 3) 200 201 /* ANALOGIX_DP_VIDEO_CTL_4 */ 202 #define BIST_EN (0x1 << 3) 203 #define BIST_WIDTH(x) (((x) & 0x1) << 2) 204 #define BIST_TYPE(x) (((x) & 0x3) << 0) 205 206 /* ANALOGIX_DP_VIDEO_CTL_8 */ 207 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 208 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 209 210 /* ANALOGIX_DP_VIDEO_CTL_10 */ 211 #define FORMAT_SEL (0x1 << 4) 212 #define INTERACE_SCAN_CFG (0x1 << 2) 213 #define VSYNC_POLARITY_CFG (0x1 << 1) 214 #define HSYNC_POLARITY_CFG (0x1 << 0) 215 216 /* ANALOGIX_DP_TOTAL_LINE_CFG_L */ 217 #define TOTAL_LINE_CFG_L(x) (((x) & 0xff) << 0) 218 219 /* ANALOGIX_DP_TOTAL_LINE_CFG_H */ 220 #define TOTAL_LINE_CFG_H(x) (((x) & 0xf) << 0) 221 222 /* ANALOGIX_DP_ACTIVE_LINE_CFG_L */ 223 #define ACTIVE_LINE_CFG_L(x) (((x) & 0xff) << 0) 224 225 /* ANALOGIX_DP_ACTIVE_LINE_CFG_H */ 226 #define ACTIVE_LINE_CFG_H(x) (((x) & 0xf) << 0) 227 228 /* ANALOGIX_DP_V_F_PORCH_CFG */ 229 #define V_F_PORCH_CFG(x) (((x) & 0xff) << 0) 230 231 /* ANALOGIX_DP_V_SYNC_WIDTH_CFG */ 232 #define V_SYNC_WIDTH_CFG(x) (((x) & 0xff) << 0) 233 234 /* ANALOGIX_DP_V_B_PORCH_CFG */ 235 #define V_B_PORCH_CFG(x) (((x) & 0xff) << 0) 236 237 /* ANALOGIX_DP_TOTAL_PIXEL_CFG_L */ 238 #define TOTAL_PIXEL_CFG_L(x) (((x) & 0xff) << 0) 239 240 /* ANALOGIX_DP_TOTAL_PIXEL_CFG_H */ 241 #define TOTAL_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) 242 243 /* ANALOGIX_DP_ACTIVE_PIXEL_CFG_L */ 244 #define ACTIVE_PIXEL_CFG_L(x) (((x) & 0xff) << 0) 245 246 /* ANALOGIX_DP_ACTIVE_PIXEL_CFG_H */ 247 #define ACTIVE_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) 248 249 /* ANALOGIX_DP_H_F_PORCH_CFG_L */ 250 #define H_F_PORCH_CFG_L(x) (((x) & 0xff) << 0) 251 252 /* ANALOGIX_DP_H_F_PORCH_CFG_H */ 253 #define H_F_PORCH_CFG_H(x) (((x) & 0xf) << 0) 254 255 /* ANALOGIX_DP_H_SYNC_CFG_L */ 256 #define H_SYNC_CFG_L(x) (((x) & 0xff) << 0) 257 258 /* ANALOGIX_DP_H_SYNC_CFG_H */ 259 #define H_SYNC_CFG_H(x) (((x) & 0xf) << 0) 260 261 /* ANALOGIX_DP_H_B_PORCH_CFG_L */ 262 #define H_B_PORCH_CFG_L(x) (((x) & 0xff) << 0) 263 264 /* ANALOGIX_DP_H_B_PORCH_CFG_H */ 265 #define H_B_PORCH_CFG_H(x) (((x) & 0xf) << 0) 266 267 /* ANALOGIX_DP_SPDIF_AUDIO_CTL_0 */ 268 #define AUD_SPDIF_EN (0x1 << 7) 269 270 /* ANALOGIX_DP_PLL_REG_1 */ 271 #define REF_CLK_24M (0x1 << 0) 272 #define REF_CLK_27M (0x0 << 0) 273 #define REF_CLK_MASK (0x1 << 0) 274 275 /* ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL */ 276 #define PSR_FRAME_UP_TYPE_BURST (0x1 << 0) 277 #define PSR_FRAME_UP_TYPE_SINGLE (0x0 << 0) 278 #define PSR_CRC_SEL_HARDWARE (0x1 << 1) 279 #define PSR_CRC_SEL_MANUALLY (0x0 << 1) 280 281 /* ANALOGIX_DP_LANE_MAP */ 282 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 283 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 284 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 285 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 286 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 287 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 288 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 289 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 290 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 291 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 292 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 293 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 294 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 295 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 296 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 297 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 298 299 /* ANALOGIX_DP_ANALOG_CTL_1 */ 300 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 301 302 /* ANALOGIX_DP_ANALOG_CTL_2 */ 303 #define SEL_24M (0x1 << 3) 304 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 305 306 /* ANALOGIX_DP_ANALOG_CTL_3 */ 307 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 308 #define VCO_BIT_600_MICRO (0x5 << 0) 309 310 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 311 #define PD_RING_OSC (0x1 << 6) 312 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 313 #define TX_CUR1_2X (0x1 << 2) 314 #define TX_CUR_16_MA (0x3 << 0) 315 316 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 317 #define CH3_AMP_400_MV (0x0 << 24) 318 #define CH2_AMP_400_MV (0x0 << 16) 319 #define CH1_AMP_400_MV (0x0 << 8) 320 #define CH0_AMP_400_MV (0x0 << 0) 321 322 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 323 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 324 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 325 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 326 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 327 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 328 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 329 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 330 331 /* ANALOGIX_DP_COMMON_INT_STA_1 */ 332 #define VSYNC_DET (0x1 << 7) 333 #define PLL_LOCK_CHG (0x1 << 6) 334 #define SPDIF_ERR (0x1 << 5) 335 #define SPDIF_UNSTBL (0x1 << 4) 336 #define VID_FORMAT_CHG (0x1 << 3) 337 #define AUD_CLK_CHG (0x1 << 2) 338 #define VID_CLK_CHG (0x1 << 1) 339 #define SW_INT (0x1 << 0) 340 341 /* ANALOGIX_DP_COMMON_INT_STA_2 */ 342 #define ENC_EN_CHG (0x1 << 6) 343 #define HW_BKSV_RDY (0x1 << 3) 344 #define HW_SHA_DONE (0x1 << 2) 345 #define HW_AUTH_STATE_CHG (0x1 << 1) 346 #define HW_AUTH_DONE (0x1 << 0) 347 348 /* ANALOGIX_DP_COMMON_INT_STA_3 */ 349 #define AFIFO_UNDER (0x1 << 7) 350 #define AFIFO_OVER (0x1 << 6) 351 #define R0_CHK_FLAG (0x1 << 5) 352 353 /* ANALOGIX_DP_COMMON_INT_STA_4 */ 354 #define PSR_ACTIVE (0x1 << 7) 355 #define PSR_INACTIVE (0x1 << 6) 356 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 357 #define HOTPLUG_CHG (0x1 << 2) 358 #define HPD_LOST (0x1 << 1) 359 #define PLUG (0x1 << 0) 360 361 /* ANALOGIX_DP_INT_STA */ 362 #define INT_HPD (0x1 << 6) 363 #define HW_TRAINING_FINISH (0x1 << 5) 364 #define RPLY_RECEIV (0x1 << 1) 365 #define AUX_ERR (0x1 << 0) 366 367 /* ANALOGIX_DP_INT_CTL */ 368 #define SOFT_INT_CTRL (0x1 << 2) 369 #define INT_POL1 (0x1 << 1) 370 #define INT_POL0 (0x1 << 0) 371 372 /* ANALOGIX_DP_SYS_CTL_1 */ 373 #define DET_STA (0x1 << 2) 374 #define FORCE_DET (0x1 << 1) 375 #define DET_CTRL (0x1 << 0) 376 377 /* ANALOGIX_DP_SYS_CTL_2 */ 378 #define CHA_CRI(x) (((x) & 0xf) << 4) 379 #define CHA_STA (0x1 << 2) 380 #define FORCE_CHA (0x1 << 1) 381 #define CHA_CTRL (0x1 << 0) 382 383 /* ANALOGIX_DP_SYS_CTL_3 */ 384 #define HPD_STATUS (0x1 << 6) 385 #define F_HPD (0x1 << 5) 386 #define HPD_CTRL (0x1 << 4) 387 #define HDCP_RDY (0x1 << 3) 388 #define STRM_VALID (0x1 << 2) 389 #define F_VALID (0x1 << 1) 390 #define VALID_CTRL (0x1 << 0) 391 392 /* ANALOGIX_DP_SYS_CTL_4 */ 393 #define FIX_M_AUD (0x1 << 4) 394 #define ENHANCED (0x1 << 3) 395 #define FIX_M_VID (0x1 << 2) 396 #define M_VID_UPDATE_CTRL (0x3 << 0) 397 398 /* ANALOGIX_DP_AUD_CTL */ 399 #define MISC_CTRL_RESET (0x1 << 4) 400 #define DP_AUDIO_EN (0x1 << 0) 401 402 /* ANALOGIX_DP_TRAINING_PTN_SET */ 403 #define SCRAMBLER_TYPE (0x1 << 9) 404 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 405 #define SCRAMBLING_DISABLE (0x1 << 5) 406 #define SCRAMBLING_ENABLE (0x0 << 5) 407 #define LINK_QUAL_PATTERN_SET_MASK (0x7 << 2) 408 #define LINK_QUAL_PATTERN_SET_HBR2 (0x5 << 2) 409 #define LINK_QUAL_PATTERN_SET_80BIT (0x4 << 2) 410 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 411 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 412 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 413 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 414 #define SW_TRAINING_PATTERN_SET_PTN3 (0x3 << 0) 415 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 416 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 417 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 418 419 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 420 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 421 #define PRE_EMPHASIS_SET_SHIFT (3) 422 423 /* ANALOGIX_DP_DEBUG_CTL */ 424 #define PLL_LOCK (0x1 << 4) 425 #define F_PLL_LOCK (0x1 << 3) 426 #define PLL_LOCK_CTRL (0x1 << 2) 427 #define PN_INV (0x1 << 0) 428 429 /* ANALOGIX_DP_PLL_CTL */ 430 #define DP_PLL_PD (0x1 << 7) 431 #define DP_PLL_RESET (0x1 << 6) 432 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 433 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 434 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 435 436 /* ANALOGIX_DP_PHY_PD */ 437 #define DP_INC_BG (0x1 << 7) 438 #define DP_EXP_BG (0x1 << 6) 439 #define DP_PHY_PD (0x1 << 5) 440 #define RK_AUX_PD (0x1 << 5) 441 #define AUX_PD (0x1 << 4) 442 #define RK_PLL_PD (0x1 << 4) 443 #define CH3_PD (0x1 << 3) 444 #define CH2_PD (0x1 << 2) 445 #define CH1_PD (0x1 << 1) 446 #define CH0_PD (0x1 << 0) 447 #define DP_ALL_PD (0xff) 448 449 /* ANALOGIX_DP_PHY_TEST */ 450 #define MACRO_RST (0x1 << 5) 451 #define CH1_TEST (0x1 << 1) 452 #define CH0_TEST (0x1 << 0) 453 454 /* ANALOGIX_DP_AUX_CH_STA */ 455 #define AUX_BUSY (0x1 << 4) 456 #define AUX_STATUS_MASK (0xf << 0) 457 458 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 459 #define DEFER_CTRL_EN (0x1 << 7) 460 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 461 462 /* ANALOGIX_DP_AUX_RX_COMM */ 463 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 464 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 465 466 /* ANALOGIX_DP_BUFFER_DATA_CTL */ 467 #define BUF_CLR (0x1 << 7) 468 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 469 470 /* ANALOGIX_DP_AUX_CH_CTL_1 */ 471 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 472 #define AUX_TX_COMM_MASK (0xf << 0) 473 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 474 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 475 #define AUX_TX_COMM_MOT (0x1 << 2) 476 #define AUX_TX_COMM_WRITE (0x0 << 0) 477 #define AUX_TX_COMM_READ (0x1 << 0) 478 479 /* ANALOGIX_DP_AUX_ADDR_7_0 */ 480 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 481 482 /* ANALOGIX_DP_AUX_ADDR_15_8 */ 483 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 484 485 /* ANALOGIX_DP_AUX_ADDR_19_16 */ 486 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 487 488 /* ANALOGIX_DP_AUX_CH_CTL_2 */ 489 #define ADDR_ONLY (0x1 << 1) 490 #define AUX_EN (0x1 << 0) 491 492 /* ANALOGIX_DP_SOC_GENERAL_CTL */ 493 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 494 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 495 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 496 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 497 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 498 #define VIDEO_MODE_MASK (0x1 << 0) 499 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 500 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 501 502 /* ANALOGIX_DP_AUD_CHANNEL_CTL */ 503 #define AUD_CHANNEL_COUNT_6 (0x5 << 0) 504 #define AUD_CHANNEL_COUNT_4 (0x3 << 0) 505 #define AUD_CHANNEL_COUNT_2 (0x1 << 0) 506 507 /* ANALOGIX_DP_PKT_SEND_CTL */ 508 #define IF_UP (0x1 << 4) 509 #define IF_EN (0x1 << 0) 510 511 /* ANALOGIX_DP_CRC_CON */ 512 #define PSR_VID_CRC_FLUSH (0x1 << 2) 513 #define PSR_VID_CRC_ENABLE (0x1 << 0) 514 515 /* ANALOGIX_DP_I2S_CTRL */ 516 #define I2S_EN (0x1 << 4) 517 518 #endif /* _ANALOGIX_DP_REG_H */ 519