1 /*
2 * Copyright (C) 2010, 2012-2017 ARM Limited. All rights reserved.
3 *
4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2
5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
6 *
7 * A copy of the licence is included with the program, and can also be obtained from Free Software
8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
9 */
10
11 /**
12 * @file mali_platform.c
13 * Platform specific Mali driver functions for:
14 * - Realview Versatile platforms with ARM11 Mpcore and virtex 5.
15 * - Versatile Express platforms with ARM Cortex-A9 and virtex 6.
16 */
17 #include <linux/platform_device.h>
18 #include <linux/version.h>
19 #include <linux/pm.h>
20 #include "mali_kernel_linux.h"
21 #ifdef CONFIG_PM_RUNTIME
22 #include <linux/pm_runtime.h>
23 #endif
24 #include <asm/io.h>
25 #include <linux/mali/mali_utgard.h>
26 #include "mali_kernel_common.h"
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29
30 #include "arm_core_scaling.h"
31 #include "mali_executor.h"
32
33 #if defined(CONFIG_MALI_DEVFREQ) && defined(CONFIG_DEVFREQ_THERMAL)
34 #include <linux/devfreq_cooling.h>
35 #include <linux/thermal.h>
36 #endif
37
38 static int mali_core_scaling_enable = 0;
39
40 void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
41 static u32 mali_read_phys(u32 phys_addr);
42 #if defined(CONFIG_ARCH_REALVIEW)
43 static void mali_write_phys(u32 phys_addr, u32 value);
44 #endif
45
46 #if defined(CONFIG_ARCH_VEXPRESS) && defined(CONFIG_ARM64)
47
48 #define SECURE_MODE_CONTROL_HANDLER 0x6F02006C
49 void *secure_mode_mapped_addr = NULL;
50 /**
51 * Reset GPU and enable/disable Mali secure mode.
52 * @Return value:
53 * 0: success
54 * non-0: failure.
55 */
56
mali_gpu_reset_and_secure_mode_enable_juno(void)57 static int mali_gpu_reset_and_secure_mode_enable_juno(void)
58 {
59 u32 phys_offset = SECURE_MODE_CONTROL_HANDLER & 0x00001FFF;
60 MALI_DEBUG_ASSERT(NULL != secure_mode_mapped_addr);
61
62 iowrite32(1, ((u8 *)secure_mode_mapped_addr) + phys_offset);
63
64 if (1 == (u32)ioread32(((u8 *)secure_mode_mapped_addr) + phys_offset)) {
65 MALI_DEBUG_PRINT(3, ("Mali reset GPU and enable secured mode successfully! \n"));
66 return 0;
67 }
68
69 MALI_PRINT_ERROR(("Failed to reset GPU and enable Mali secured mode !!! \n"));
70
71 return -1;
72
73 }
74
mali_gpu_reset_and_secure_mode_disable_juno(void)75 static int mali_gpu_reset_and_secure_mode_disable_juno(void)
76 {
77 u32 phys_offset = SECURE_MODE_CONTROL_HANDLER & 0x00001FFF;
78 MALI_DEBUG_ASSERT(NULL != secure_mode_mapped_addr);
79
80 iowrite32(0, ((u8 *)secure_mode_mapped_addr) + phys_offset);
81
82 if (0 == (u32)ioread32(((u8 *)secure_mode_mapped_addr) + phys_offset)) {
83 MALI_DEBUG_PRINT(3, ("Mali reset GPU and disable secured mode successfully! \n"));
84 return 0;
85 }
86
87 MALI_PRINT_ERROR(("Failed to reset GPU and disable mali secured mode !!! \n"));
88 return -1;
89 }
90
mali_secure_mode_init_juno(void)91 static int mali_secure_mode_init_juno(void)
92 {
93 u32 phys_addr_page = SECURE_MODE_CONTROL_HANDLER & 0xFFFFE000;
94 u32 phys_offset = SECURE_MODE_CONTROL_HANDLER & 0x00001FFF;
95 u32 map_size = phys_offset + sizeof(u32);
96
97 MALI_DEBUG_ASSERT(NULL == secure_mode_mapped_addr);
98
99 secure_mode_mapped_addr = ioremap(phys_addr_page, map_size);
100 if (NULL != secure_mode_mapped_addr) {
101 return mali_gpu_reset_and_secure_mode_disable_juno();
102 }
103 MALI_DEBUG_PRINT(2, ("Failed to ioremap for Mali secured mode! \n"));
104 return -1;
105 }
106
mali_secure_mode_deinit_juno(void)107 static void mali_secure_mode_deinit_juno(void)
108 {
109 if (NULL != secure_mode_mapped_addr) {
110 mali_gpu_reset_and_secure_mode_disable_juno();
111 iounmap(secure_mode_mapped_addr);
112 secure_mode_mapped_addr = NULL;
113 }
114 }
115 #endif
116
117 #ifndef CONFIG_MALI_DT
118 static void mali_platform_device_release(struct device *device);
119
120 #if defined(CONFIG_ARCH_VEXPRESS)
121
122 #if defined(CONFIG_ARM64)
123 /* Juno + Mali-450 MP6 in V7 FPGA */
124 static struct resource mali_gpu_resources_m450_mp6[] = {
125 MALI_GPU_RESOURCES_MALI450_MP6_PMU(0x6F040000, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200)
126 };
127
128 static struct resource mali_gpu_resources_m470_mp4[] = {
129 MALI_GPU_RESOURCES_MALI470_MP4_PMU(0x6F040000, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200)
130 };
131
132 static struct resource mali_gpu_resources_m470_mp3[] = {
133 MALI_GPU_RESOURCES_MALI470_MP3_PMU(0x6F040000, 200, 200, 200, 200, 200, 200, 200, 200, 200)
134 };
135
136 static struct resource mali_gpu_resources_m470_mp2[] = {
137 MALI_GPU_RESOURCES_MALI470_MP2_PMU(0x6F040000, 200, 200, 200, 200, 200, 200, 200)
138 };
139
140 static struct resource mali_gpu_resources_m470_mp1[] = {
141 MALI_GPU_RESOURCES_MALI470_MP1_PMU(0x6F040000, 200, 200, 200, 200, 200)
142 };
143
144 #else
145 static struct resource mali_gpu_resources_m450_mp8[] = {
146 MALI_GPU_RESOURCES_MALI450_MP8_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
147 };
148
149 static struct resource mali_gpu_resources_m450_mp6[] = {
150 MALI_GPU_RESOURCES_MALI450_MP6_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
151 };
152
153 static struct resource mali_gpu_resources_m450_mp4[] = {
154 MALI_GPU_RESOURCES_MALI450_MP4_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
155 };
156
157 static struct resource mali_gpu_resources_m470_mp4[] = {
158 MALI_GPU_RESOURCES_MALI470_MP4_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
159 };
160 #endif /* CONFIG_ARM64 */
161
162 #elif defined(CONFIG_ARCH_REALVIEW)
163
164 static struct resource mali_gpu_resources_m300[] = {
165 MALI_GPU_RESOURCES_MALI300_PMU(0xC0000000, -1, -1, -1, -1)
166 };
167
168 static struct resource mali_gpu_resources_m400_mp1[] = {
169 MALI_GPU_RESOURCES_MALI400_MP1_PMU(0xC0000000, -1, -1, -1, -1)
170 };
171
172 static struct resource mali_gpu_resources_m400_mp2[] = {
173 MALI_GPU_RESOURCES_MALI400_MP2_PMU(0xC0000000, -1, -1, -1, -1, -1, -1)
174 };
175
176 #endif
177 #endif
178
179 #if defined(CONFIG_MALI_DEVFREQ) && defined(CONFIG_DEVFREQ_THERMAL)
180
181 #define FALLBACK_STATIC_TEMPERATURE 55000
182
183 static struct thermal_zone_device *gpu_tz;
184
185 /* Calculate gpu static power example for reference */
arm_model_static_power(struct devfreq * devfreq,unsigned long voltage)186 static unsigned long arm_model_static_power(struct devfreq *devfreq,
187 unsigned long voltage)
188 {
189 int temperature, temp;
190 int temp_squared, temp_cubed, temp_scaling_factor;
191 const unsigned long coefficient = (410UL << 20) / (729000000UL >> 10);
192 const unsigned long voltage_cubed = (voltage * voltage * voltage) >> 10;
193 unsigned long static_power;
194
195 if (gpu_tz) {
196 int ret;
197
198 ret = gpu_tz->ops->get_temp(gpu_tz, &temperature);
199 if (ret) {
200 MALI_DEBUG_PRINT(2, ("Error reading temperature for gpu thermal zone: %d\n", ret));
201 temperature = FALLBACK_STATIC_TEMPERATURE;
202 }
203 } else {
204 temperature = FALLBACK_STATIC_TEMPERATURE;
205 }
206
207 /* Calculate the temperature scaling factor. To be applied to the
208 * voltage scaled power.
209 */
210 temp = temperature / 1000;
211 temp_squared = temp * temp;
212 temp_cubed = temp_squared * temp;
213 temp_scaling_factor =
214 (2 * temp_cubed)
215 - (80 * temp_squared)
216 + (4700 * temp)
217 + 32000;
218
219 static_power = (((coefficient * voltage_cubed) >> 20)
220 * temp_scaling_factor)
221 / 1000000;
222
223 return static_power;
224 }
225
226 /* Calculate gpu dynamic power example for reference */
arm_model_dynamic_power(struct devfreq * devfreq,unsigned long freq,unsigned long voltage)227 static unsigned long arm_model_dynamic_power(struct devfreq *devfreq,
228 unsigned long freq,
229 unsigned long voltage)
230 {
231 /* The inputs: freq (f) is in Hz, and voltage (v) in mV.
232 * The coefficient (c) is in mW/(MHz mV mV).
233 *
234 * This function calculates the dynamic power after this formula:
235 * Pdyn (mW) = c (mW/(MHz*mV*mV)) * v (mV) * v (mV) * f (MHz)
236 */
237 const unsigned long v2 = (voltage * voltage) / 1000; /* m*(V*V) */
238 const unsigned long f_mhz = freq / 1000000; /* MHz */
239 const unsigned long coefficient = 3600; /* mW/(MHz*mV*mV) */
240 unsigned long dynamic_power;
241
242 dynamic_power = (coefficient * v2 * f_mhz) / 1000000; /* mW */
243
244 return dynamic_power;
245 }
246
247 struct devfreq_cooling_power arm_cooling_ops = {
248 .get_static_power = arm_model_static_power,
249 .get_dynamic_power = arm_model_dynamic_power,
250 };
251 #endif
252
253 static struct mali_gpu_device_data mali_gpu_data = {
254 #ifndef CONFIG_MALI_DT
255 .pmu_switch_delay = 0xFF, /* do not have to be this high on FPGA, but it is good for testing to have a delay */
256 #if defined(CONFIG_ARCH_VEXPRESS)
257 .shared_mem_size = 256 * 1024 * 1024, /* 256MB */
258 #endif
259 #endif
260 .max_job_runtime = 60000, /* 60 seconds */
261
262 #if defined(CONFIG_ARCH_REALVIEW)
263 .dedicated_mem_start = 0x80000000, /* Physical start address (use 0xD0000000 for old indirect setup) */
264 .dedicated_mem_size = 0x10000000, /* 256MB */
265 #endif
266 #if defined(CONFIG_ARM64)
267 /* Some framebuffer drivers get the framebuffer dynamically, such as through GEM,
268 * in which the memory resource can't be predicted in advance.
269 */
270 .fb_start = 0x0,
271 .fb_size = 0xFFFFF000,
272 #else
273 .fb_start = 0xe0000000,
274 .fb_size = 0x01000000,
275 #endif
276 .control_interval = 1000, /* 1000ms */
277 .utilization_callback = mali_gpu_utilization_callback,
278 .get_clock_info = NULL,
279 .get_freq = NULL,
280 .set_freq = NULL,
281 #if defined(CONFIG_ARCH_VEXPRESS) && defined(CONFIG_ARM64)
282 .secure_mode_init = mali_secure_mode_init_juno,
283 .secure_mode_deinit = mali_secure_mode_deinit_juno,
284 .gpu_reset_and_secure_mode_enable = mali_gpu_reset_and_secure_mode_enable_juno,
285 .gpu_reset_and_secure_mode_disable = mali_gpu_reset_and_secure_mode_disable_juno,
286 #else
287 .secure_mode_init = NULL,
288 .secure_mode_deinit = NULL,
289 .gpu_reset_and_secure_mode_enable = NULL,
290 .gpu_reset_and_secure_mode_disable = NULL,
291 #endif
292 #if defined(CONFIG_MALI_DEVFREQ) && defined(CONFIG_DEVFREQ_THERMAL)
293 .gpu_cooling_ops = &arm_cooling_ops,
294 #endif
295 };
296
297 #ifndef CONFIG_MALI_DT
298 static struct platform_device mali_gpu_device = {
299 .name = MALI_GPU_NAME_UTGARD,
300 .id = 0,
301 .dev.release = mali_platform_device_release,
302 .dev.dma_mask = &mali_gpu_device.dev.coherent_dma_mask,
303 .dev.coherent_dma_mask = DMA_BIT_MASK(32),
304
305 .dev.platform_data = &mali_gpu_data,
306 };
307
mali_platform_device_register(void)308 int mali_platform_device_register(void)
309 {
310 int err = -1;
311 int num_pp_cores = 0;
312 #if defined(CONFIG_ARCH_REALVIEW)
313 u32 m400_gp_version;
314 #endif
315
316 MALI_DEBUG_PRINT(4, ("mali_platform_device_register() called\n"));
317
318 /* Detect present Mali GPU and connect the correct resources to the device */
319 #if defined(CONFIG_ARCH_VEXPRESS)
320
321 #if defined(CONFIG_ARM64)
322 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
323 mali_gpu_device.dev.archdata.dma_ops = &dummy_dma_ops;
324 #else
325 mali_gpu_device.dev.archdata.dma_ops = dma_ops;
326 #endif
327 if ((mali_read_phys(0x6F000000) & 0x00600450) == 0x00600450) {
328 MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP6 device\n"));
329 num_pp_cores = 6;
330 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m450_mp6);
331 mali_gpu_device.resource = mali_gpu_resources_m450_mp6;
332 } else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00400430) {
333 MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP4 device\n"));
334 num_pp_cores = 4;
335 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m470_mp4);
336 mali_gpu_device.resource = mali_gpu_resources_m470_mp4;
337 } else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00300430) {
338 MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP3 device\n"));
339 num_pp_cores = 3;
340 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m470_mp3);
341 mali_gpu_device.resource = mali_gpu_resources_m470_mp3;
342 } else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00200430) {
343 MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP2 device\n"));
344 num_pp_cores = 2;
345 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m470_mp2);
346 mali_gpu_device.resource = mali_gpu_resources_m470_mp2;
347 } else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00100430) {
348 MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP1 device\n"));
349 num_pp_cores = 1;
350 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m470_mp1);
351 mali_gpu_device.resource = mali_gpu_resources_m470_mp1;
352 }
353 #else
354 if (mali_read_phys(0xFC000000) == 0x00000450) {
355 MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP8 device\n"));
356 num_pp_cores = 8;
357 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m450_mp8);
358 mali_gpu_device.resource = mali_gpu_resources_m450_mp8;
359 } else if (mali_read_phys(0xFC000000) == 0x40600450) {
360 MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP6 device\n"));
361 num_pp_cores = 6;
362 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m450_mp6);
363 mali_gpu_device.resource = mali_gpu_resources_m450_mp6;
364 } else if (mali_read_phys(0xFC000000) == 0x40400450) {
365 MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP4 device\n"));
366 num_pp_cores = 4;
367 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m450_mp4);
368 mali_gpu_device.resource = mali_gpu_resources_m450_mp4;
369 } else if (mali_read_phys(0xFC000000) == 0xFFFFFFFF) {
370 MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP4 device\n"));
371 num_pp_cores = 4;
372 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m470_mp4);
373 mali_gpu_device.resource = mali_gpu_resources_m470_mp4;
374 }
375 #endif /* CONFIG_ARM64 */
376
377 #elif defined(CONFIG_ARCH_REALVIEW)
378
379 m400_gp_version = mali_read_phys(0xC000006C);
380 if ((m400_gp_version & 0xFFFF0000) == 0x0C070000) {
381 MALI_DEBUG_PRINT(4, ("Registering Mali-300 device\n"));
382 num_pp_cores = 1;
383 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m300);
384 mali_gpu_device.resource = mali_gpu_resources_m300;
385 mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
386 } else if ((m400_gp_version & 0xFFFF0000) == 0x0B070000) {
387 u32 fpga_fw_version = mali_read_phys(0xC0010000);
388 if (fpga_fw_version == 0x130C008F || fpga_fw_version == 0x110C008F) {
389 /* Mali-400 MP1 r1p0 or r1p1 */
390 MALI_DEBUG_PRINT(4, ("Registering Mali-400 MP1 device\n"));
391 num_pp_cores = 1;
392 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m400_mp1);
393 mali_gpu_device.resource = mali_gpu_resources_m400_mp1;
394 mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
395 } else if (fpga_fw_version == 0x130C000F) {
396 /* Mali-400 MP2 r1p1 */
397 MALI_DEBUG_PRINT(4, ("Registering Mali-400 MP2 device\n"));
398 num_pp_cores = 2;
399 mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m400_mp2);
400 mali_gpu_device.resource = mali_gpu_resources_m400_mp2;
401 mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
402 }
403 }
404
405 #endif
406 /* Register the platform device */
407 err = platform_device_register(&mali_gpu_device);
408 if (0 == err) {
409 #ifdef CONFIG_PM_RUNTIME
410 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
411 pm_runtime_set_autosuspend_delay(&(mali_gpu_device.dev), 1000);
412 pm_runtime_use_autosuspend(&(mali_gpu_device.dev));
413 #endif
414 pm_runtime_enable(&(mali_gpu_device.dev));
415 #endif
416 MALI_DEBUG_ASSERT(0 < num_pp_cores);
417 mali_core_scaling_init(num_pp_cores);
418
419 return 0;
420 }
421
422 return err;
423 }
424
mali_platform_device_unregister(void)425 void mali_platform_device_unregister(void)
426 {
427 MALI_DEBUG_PRINT(4, ("mali_platform_device_unregister() called\n"));
428
429 mali_core_scaling_term();
430 #ifdef CONFIG_PM_RUNTIME
431 pm_runtime_disable(&(mali_gpu_device.dev));
432 #endif
433 platform_device_unregister(&mali_gpu_device);
434
435 platform_device_put(&mali_gpu_device);
436
437 #if defined(CONFIG_ARCH_REALVIEW)
438 mali_write_phys(0xC0010020, 0x9); /* Restore default (legacy) memory mapping */
439 #endif
440 }
441
mali_platform_device_release(struct device * device)442 static void mali_platform_device_release(struct device *device)
443 {
444 MALI_DEBUG_PRINT(4, ("mali_platform_device_release() called\n"));
445 }
446
447 #else /* CONFIG_MALI_DT */
mali_platform_device_init(struct platform_device * device)448 int mali_platform_device_init(struct platform_device *device)
449 {
450 int num_pp_cores = 0;
451 int err = -1;
452 #if defined(CONFIG_ARCH_REALVIEW)
453 u32 m400_gp_version;
454 #endif
455
456 /* Detect present Mali GPU and connect the correct resources to the device */
457 #if defined(CONFIG_ARCH_VEXPRESS)
458
459 #if defined(CONFIG_ARM64)
460 if ((mali_read_phys(0x6F000000) & 0x00600450) == 0x00600450) {
461 MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP6 device\n"));
462 num_pp_cores = 6;
463 } else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00400430) {
464 MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP4 device\n"));
465 num_pp_cores = 4;
466 } else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00300430) {
467 MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP3 device\n"));
468 num_pp_cores = 3;
469 } else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00200430) {
470 MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP2 device\n"));
471 num_pp_cores = 2;
472 } else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00100430) {
473 MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP1 device\n"));
474 num_pp_cores = 1;
475 }
476 #else
477 if (mali_read_phys(0xFC000000) == 0x00000450) {
478 MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP8 device\n"));
479 num_pp_cores = 8;
480 } else if (mali_read_phys(0xFC000000) == 0x40400450) {
481 MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP4 device\n"));
482 num_pp_cores = 4;
483 } else if (mali_read_phys(0xFC000000) == 0xFFFFFFFF) {
484 MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP4 device\n"));
485 num_pp_cores = 4;
486 }
487 #endif
488
489 #elif defined(CONFIG_ARCH_REALVIEW)
490
491 m400_gp_version = mali_read_phys(0xC000006C);
492 if ((m400_gp_version & 0xFFFF0000) == 0x0C070000) {
493 MALI_DEBUG_PRINT(4, ("Registering Mali-300 device\n"));
494 num_pp_cores = 1;
495 mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
496 } else if ((m400_gp_version & 0xFFFF0000) == 0x0B070000) {
497 u32 fpga_fw_version = mali_read_phys(0xC0010000);
498 if (fpga_fw_version == 0x130C008F || fpga_fw_version == 0x110C008F) {
499 /* Mali-400 MP1 r1p0 or r1p1 */
500 MALI_DEBUG_PRINT(4, ("Registering Mali-400 MP1 device\n"));
501 num_pp_cores = 1;
502 mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
503 } else if (fpga_fw_version == 0x130C000F) {
504 /* Mali-400 MP2 r1p1 */
505 MALI_DEBUG_PRINT(4, ("Registering Mali-400 MP2 device\n"));
506 num_pp_cores = 2;
507 mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
508 }
509 }
510 #endif
511
512 /* After kernel 3.15 device tree will default set dev
513 * related parameters in of_platform_device_create_pdata.
514 * But kernel changes from version to version,
515 * For example 3.10 didn't include device->dev.dma_mask parameter setting,
516 * if we didn't include here will cause dma_mapping error,
517 * but in kernel 3.15 it include device->dev.dma_mask parameter setting,
518 * so it's better to set must need paramter by DDK itself.
519 */
520 if (!device->dev.dma_mask)
521 device->dev.dma_mask = &device->dev.coherent_dma_mask;
522 device->dev.archdata.dma_ops = dma_ops;
523
524 err = platform_device_add_data(device, &mali_gpu_data, sizeof(mali_gpu_data));
525
526 if (0 == err) {
527 #ifdef CONFIG_PM_RUNTIME
528 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
529 pm_runtime_set_autosuspend_delay(&(device->dev), 1000);
530 pm_runtime_use_autosuspend(&(device->dev));
531 #endif
532 pm_runtime_enable(&(device->dev));
533 #endif
534 MALI_DEBUG_ASSERT(0 < num_pp_cores);
535 mali_core_scaling_init(num_pp_cores);
536 }
537
538 #if defined(CONFIG_MALI_DEVFREQ) && defined(CONFIG_DEVFREQ_THERMAL)
539 /* Some Socs didn't support the devfreq thermal for mali */
540 if (of_machine_is_compatible("rockchip,rk3036"))
541 return 0;
542
543 /* Get thermal zone */
544 gpu_tz = thermal_zone_get_zone_by_name("soc_thermal");
545 if (IS_ERR(gpu_tz)) {
546 MALI_DEBUG_PRINT(2, ("Error getting gpu thermal zone (%ld), not yet ready?\n",
547 PTR_ERR(gpu_tz)));
548 gpu_tz = NULL;
549
550 err = -EPROBE_DEFER;
551 }
552 #endif
553
554 return err;
555 }
556
mali_platform_device_deinit(struct platform_device * device)557 int mali_platform_device_deinit(struct platform_device *device)
558 {
559 MALI_IGNORE(device);
560
561 MALI_DEBUG_PRINT(4, ("mali_platform_device_deinit() called\n"));
562
563 mali_core_scaling_term();
564 #ifdef CONFIG_PM_RUNTIME
565 pm_runtime_disable(&(device->dev));
566 #endif
567
568 #if defined(CONFIG_ARCH_REALVIEW)
569 mali_write_phys(0xC0010020, 0x9); /* Restore default (legacy) memory mapping */
570 #endif
571
572 return 0;
573 }
574
575 #endif /* CONFIG_MALI_DT */
576
mali_read_phys(u32 phys_addr)577 static u32 mali_read_phys(u32 phys_addr)
578 {
579 u32 phys_addr_page = phys_addr & 0xFFFFE000;
580 u32 phys_offset = phys_addr & 0x00001FFF;
581 u32 map_size = phys_offset + sizeof(u32);
582 u32 ret = 0xDEADBEEF;
583 void *mem_mapped = ioremap(phys_addr_page, map_size);
584 if (NULL != mem_mapped) {
585 ret = (u32)ioread32(((u8 *)mem_mapped) + phys_offset);
586 iounmap(mem_mapped);
587 }
588
589 return ret;
590 }
591
592 #if defined(CONFIG_ARCH_REALVIEW)
mali_write_phys(u32 phys_addr,u32 value)593 static void mali_write_phys(u32 phys_addr, u32 value)
594 {
595 u32 phys_addr_page = phys_addr & 0xFFFFE000;
596 u32 phys_offset = phys_addr & 0x00001FFF;
597 u32 map_size = phys_offset + sizeof(u32);
598 void *mem_mapped = ioremap(phys_addr_page, map_size);
599 if (NULL != mem_mapped) {
600 iowrite32(value, ((u8 *)mem_mapped) + phys_offset);
601 iounmap(mem_mapped);
602 }
603 }
604 #endif
605
param_set_core_scaling(const char * val,const struct kernel_param * kp)606 static int param_set_core_scaling(const char *val, const struct kernel_param *kp)
607 {
608 int ret = param_set_int(val, kp);
609
610 if (1 == mali_core_scaling_enable) {
611 mali_core_scaling_sync(mali_executor_get_num_cores_enabled());
612 }
613 return ret;
614 }
615
616 static struct kernel_param_ops param_ops_core_scaling = {
617 .set = param_set_core_scaling,
618 .get = param_get_int,
619 };
620
621 module_param_cb(mali_core_scaling_enable, ¶m_ops_core_scaling, &mali_core_scaling_enable, 0644);
622 MODULE_PARM_DESC(mali_core_scaling_enable, "1 means to enable core scaling policy, 0 means to disable core scaling policy");
623
mali_gpu_utilization_callback(struct mali_gpu_utilization_data * data)624 void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
625 {
626 if (1 == mali_core_scaling_enable) {
627 mali_core_scaling_update(data);
628 }
629 }
630