1 /*
2 * Copyright (C) 2010-2017 ARM Limited. All rights reserved.
3 *
4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2
5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
6 *
7 * A copy of the licence is included with the program, and can also be obtained from Free Software
8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
9 */
10
11
12 /**
13 * @file mali_osk_mali.c
14 * Implementation of the OS abstraction layer which is specific for the Mali kernel device driver
15 */
16 #include "../platform/rk/custom_log.h"
17
18 #include <linux/kernel.h>
19 #include <linux/uaccess.h>
20 #include <linux/platform_device.h>
21 #include <linux/mali/mali_utgard.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24
25 #include "mali_osk_mali.h"
26 #include "mali_kernel_common.h" /* MALI_xxx macros */
27 #include "mali_osk.h" /* kernel side OS functions */
28 #include "mali_kernel_linux.h"
29
30 static mali_bool mali_secure_mode_enabled = MALI_FALSE;
31 static mali_bool mali_secure_mode_supported = MALI_FALSE;
32
33 /* Function that init the mali gpu secure mode */
34 void (*mali_secure_mode_deinit)(void) = NULL;
35 /* Function that reset GPU and enable the mali gpu secure mode */
36 int (*mali_gpu_reset_and_secure_mode_enable)(void) = NULL;
37 /* Function that reset GPU and disable the mali gpu secure mode */
38 int (*mali_gpu_reset_and_secure_mode_disable)(void) = NULL;
39
40
41 #ifdef CONFIG_MALI_DT
42
43 #define MALI_OSK_INVALID_RESOURCE_ADDRESS 0xFFFFFFFF
44
45 /**
46 * Define the max number of resource we could have.
47 */
48 #define MALI_OSK_MAX_RESOURCE_NUMBER 27
49
50 /**
51 * Define the max number of resource with interrupts, and they are
52 * the first 20 elements in array mali_osk_resource_bank.
53 */
54 #define MALI_OSK_RESOURCE_WITH_IRQ_NUMBER 20
55
56 /**
57 * pp core start and end location in mali_osk_resource_bank array.
58 */
59 #define MALI_OSK_RESOURCE_PP_LOCATION_START 2
60 #define MALI_OSK_RESOURCE_PP_LOCATION_END 17
61
62 /**
63 * L2 cache start and end location in mali_osk_resource_bank array.
64 */
65 #define MALI_OSK_RESOURCE_L2_LOCATION_START 20
66 #define MALI_OSK_RESOURCE_l2_LOCATION_END 22
67
68 /**
69 * DMA unit location.
70 */
71 #define MALI_OSK_RESOURCE_DMA_LOCATION 26
72
73 static _mali_osk_resource_t mali_osk_resource_bank[MALI_OSK_MAX_RESOURCE_NUMBER] = {
74 /*-------------------------------------------------------*/
75 /* rk_ext : to use dts_for_mali_ko_befor_r5p0-01rel0. */
76 /* {.description = "Mali_GP", .base = MALI_OFFSET_GP, .irq_name = "IRQGP",}, */
77 {.description = "Mali_GP", .base = MALI_OFFSET_GP, .irq_name = "Mali_GP_IRQ",},
78 /* {.description = "Mali_GP_MMU", .base = MALI_OFFSET_GP_MMU, .irq_name = "IRQGPMMU",}, */
79 {.description = "Mali_GP_MMU", .base = MALI_OFFSET_GP_MMU, .irq_name = "Mali_GP_MMU_IRQ",},
80 /* {.description = "Mali_PP0", .base = MALI_OFFSET_PP0, .irq_name = "IRQPP0",}, */
81 {.description = "Mali_PP0", .base = MALI_OFFSET_PP0, .irq_name = "Mali_PP0_IRQ",},
82 /* {.description = "Mali_PP0_MMU", .base = MALI_OFFSET_PP0_MMU, .irq_name = "IRQPPMMU0",}, */
83 {.description = "Mali_PP0_MMU", .base = MALI_OFFSET_PP0_MMU, .irq_name = "Mali_PP0_MMU_IRQ",},
84 /* {.description = "Mali_PP1", .base = MALI_OFFSET_PP1, .irq_name = "IRQPP1",}, */
85 {.description = "Mali_PP1", .base = MALI_OFFSET_PP1, .irq_name = "Mali_PP1_IRQ",},
86 /* {.description = "Mali_PP1_MMU", .base = MALI_OFFSET_PP1_MMU, .irq_name = "IRQPPMMU1",}, */
87 {.description = "Mali_PP1_MMU", .base = MALI_OFFSET_PP1_MMU, .irq_name = "Mali_PP1_MMU_IRQ",},
88
89 {.description = "Mali_PP2", .base = MALI_OFFSET_PP2, .irq_name = "Mali_PP2_IRQ",},
90 {.description = "Mali_PP2_MMU", .base = MALI_OFFSET_PP2_MMU, .irq_name = "Mali_PP2_MMU_IRQ",},
91 {.description = "Mali_PP3", .base = MALI_OFFSET_PP3, .irq_name = "Mali_PP3_IRQ",},
92 {.description = "Mali_PP3_MMU", .base = MALI_OFFSET_PP3_MMU, .irq_name = "Mali_PP3_MMU_IRQ",},
93 /*-------------------------------------------------------*/
94 {.description = "Mali_PP4", .base = MALI_OFFSET_PP4, .irq_name = "IRQPP4",},
95 {.description = "Mali_PP4_MMU", .base = MALI_OFFSET_PP4_MMU, .irq_name = "IRQPPMMU4",},
96 {.description = "Mali_PP5", .base = MALI_OFFSET_PP5, .irq_name = "IRQPP5",},
97 {.description = "Mali_PP5_MMU", .base = MALI_OFFSET_PP5_MMU, .irq_name = "IRQPPMMU5",},
98 {.description = "Mali_PP6", .base = MALI_OFFSET_PP6, .irq_name = "IRQPP6",},
99 {.description = "Mali_PP6_MMU", .base = MALI_OFFSET_PP6_MMU, .irq_name = "IRQPPMMU6",},
100 {.description = "Mali_PP7", .base = MALI_OFFSET_PP7, .irq_name = "IRQPP7",},
101 {.description = "Mali_PP7_MMU", .base = MALI_OFFSET_PP7_MMU, .irq_name = "IRQPPMMU",},
102 {.description = "Mali_PP_Broadcast", .base = MALI_OFFSET_PP_BCAST, .irq_name = "IRQPP",},
103 {.description = "Mali_PMU", .base = MALI_OFFSET_PMU, .irq_name = "IRQPMU",},
104 {.description = "Mali_L2", .base = MALI_OFFSET_L2_RESOURCE0,},
105 {.description = "Mali_L2", .base = MALI_OFFSET_L2_RESOURCE1,},
106 {.description = "Mali_L2", .base = MALI_OFFSET_L2_RESOURCE2,},
107 {.description = "Mali_PP_MMU_Broadcast", .base = MALI_OFFSET_PP_BCAST_MMU,},
108 {.description = "Mali_Broadcast", .base = MALI_OFFSET_BCAST,},
109 {.description = "Mali_DLBU", .base = MALI_OFFSET_DLBU,},
110 {.description = "Mali_DMA", .base = MALI_OFFSET_DMA,},
111 };
112
_mali_osk_get_compatible_name(const char ** out_string)113 static int _mali_osk_get_compatible_name(const char **out_string)
114 {
115 struct device_node *node = mali_platform_device->dev.of_node;
116
117 MALI_DEBUG_ASSERT(NULL != node);
118
119 return of_property_read_string(node, "compatible", out_string);
120 }
121
_mali_osk_resource_initialize(void)122 _mali_osk_errcode_t _mali_osk_resource_initialize(void)
123 {
124 mali_bool mali_is_450 = MALI_FALSE, mali_is_470 = MALI_FALSE;
125 int i, pp_core_num = 0, l2_core_num = 0;
126 struct resource *res;
127 const char *compatible_name = NULL;
128
129 if (0 == _mali_osk_get_compatible_name(&compatible_name)) {
130 if (0 == strncmp(compatible_name, "arm,mali-450", strlen("arm,mali-450"))) {
131 mali_is_450 = MALI_TRUE;
132 MALI_DEBUG_PRINT(2, ("mali-450 device tree detected."));
133 } else if (0 == strncmp(compatible_name, "arm,mali-470", strlen("arm,mali-470"))) {
134 mali_is_470 = MALI_TRUE;
135 MALI_DEBUG_PRINT(2, ("mali-470 device tree detected."));
136 }
137 }
138
139 for (i = 0; i < MALI_OSK_RESOURCE_WITH_IRQ_NUMBER; i++) {
140 res = platform_get_resource_byname(mali_platform_device, IORESOURCE_IRQ, mali_osk_resource_bank[i].irq_name);
141 if (res) {
142 mali_osk_resource_bank[i].irq = res->start;
143 } else {
144 mali_osk_resource_bank[i].base = MALI_OSK_INVALID_RESOURCE_ADDRESS;
145 }
146 }
147
148 for (i = MALI_OSK_RESOURCE_PP_LOCATION_START; i <= MALI_OSK_RESOURCE_PP_LOCATION_END; i++) {
149 if (MALI_OSK_INVALID_RESOURCE_ADDRESS != mali_osk_resource_bank[i].base) {
150 pp_core_num++;
151 }
152 }
153
154 /* We have to divide by 2, because we caculate twice for only one pp(pp_core and pp_mmu_core). */
155 if (0 != pp_core_num % 2) {
156 MALI_DEBUG_PRINT(2, ("The value of pp core number isn't normal."));
157 return _MALI_OSK_ERR_FAULT;
158 }
159
160 pp_core_num /= 2;
161
162 /**
163 * we can caculate the number of l2 cache core according the number of pp core number
164 * and device type(mali400/mali450/mali470).
165 */
166 l2_core_num = 1;
167 if (mali_is_450) {
168 if (pp_core_num > 4) {
169 l2_core_num = 3;
170 } else if (pp_core_num <= 4) {
171 l2_core_num = 2;
172 }
173 }
174
175 for (i = MALI_OSK_RESOURCE_l2_LOCATION_END; i > MALI_OSK_RESOURCE_L2_LOCATION_START + l2_core_num - 1; i--) {
176 mali_osk_resource_bank[i].base = MALI_OSK_INVALID_RESOURCE_ADDRESS;
177 }
178
179 /* If device is not mali-450 type, we have to remove related resource from resource bank. */
180 if (!(mali_is_450 || mali_is_470)) {
181 for (i = MALI_OSK_RESOURCE_l2_LOCATION_END + 1; i < MALI_OSK_MAX_RESOURCE_NUMBER; i++) {
182 mali_osk_resource_bank[i].base = MALI_OSK_INVALID_RESOURCE_ADDRESS;
183 }
184 }
185
186 if (mali_is_470)
187 mali_osk_resource_bank[MALI_OSK_RESOURCE_DMA_LOCATION].base = MALI_OSK_INVALID_RESOURCE_ADDRESS;
188
189 return _MALI_OSK_ERR_OK;
190 }
191
_mali_osk_resource_find(u32 addr,_mali_osk_resource_t * res)192 _mali_osk_errcode_t _mali_osk_resource_find(u32 addr, _mali_osk_resource_t *res)
193 {
194 int i;
195
196 if (NULL == mali_platform_device) {
197 return _MALI_OSK_ERR_ITEM_NOT_FOUND;
198 }
199
200 /* Traverse all of resources in resources bank to find the matching one. */
201 for (i = 0; i < MALI_OSK_MAX_RESOURCE_NUMBER; i++) {
202 if (mali_osk_resource_bank[i].base == addr) {
203 if (NULL != res) {
204 res->base = addr + _mali_osk_resource_base_address();
205 res->description = mali_osk_resource_bank[i].description;
206 res->irq = mali_osk_resource_bank[i].irq;
207 }
208 return _MALI_OSK_ERR_OK;
209 }
210 }
211
212 return _MALI_OSK_ERR_ITEM_NOT_FOUND;
213 }
214
_mali_osk_resource_base_address(void)215 uintptr_t _mali_osk_resource_base_address(void)
216 {
217 struct resource *reg_res = NULL;
218 uintptr_t ret = 0;
219
220 reg_res = platform_get_resource(mali_platform_device, IORESOURCE_MEM, 0);
221
222 if (NULL != reg_res) {
223 ret = reg_res->start;
224 }
225
226 return ret;
227 }
228
_mali_osk_device_data_pmu_config_get(u16 * domain_config_array,int array_size)229 void _mali_osk_device_data_pmu_config_get(u16 *domain_config_array, int array_size)
230 {
231 struct device_node *node = mali_platform_device->dev.of_node;
232 struct property *prop;
233 const __be32 *p;
234 int length = 0, i = 0;
235 u32 u;
236
237 MALI_DEBUG_PRINT(2, ("Get pmu config from device tree configuration.\n"));
238
239 MALI_DEBUG_ASSERT(NULL != node);
240
241 if (!of_get_property(node, "pmu_domain_config", &length)) {
242 return;
243 }
244
245 if (array_size != length / sizeof(u32)) {
246 MALI_PRINT_ERROR(("Wrong pmu domain config in device tree."));
247 return;
248 }
249
250 of_property_for_each_u32(node, "pmu_domain_config", prop, p, u) {
251 domain_config_array[i] = (u16)u;
252 i++;
253 }
254
255 return;
256 }
257
_mali_osk_get_pmu_switch_delay(void)258 u32 _mali_osk_get_pmu_switch_delay(void)
259 {
260 struct device_node *node = mali_platform_device->dev.of_node;
261 u32 switch_delay;
262
263 MALI_DEBUG_ASSERT(NULL != node);
264
265 if (0 == of_property_read_u32(node, "pmu_switch_delay", &switch_delay)) {
266 return switch_delay;
267 } else {
268 MALI_DEBUG_PRINT(2, ("Couldn't find pmu_switch_delay in device tree configuration.\n"));
269 }
270
271 return 0;
272 }
273
274 #else /* CONFIG_MALI_DT */ /* 若未 定义 CONFIG_MALI_DT. */
275
_mali_osk_resource_find(u32 addr,_mali_osk_resource_t * res)276 _mali_osk_errcode_t _mali_osk_resource_find(u32 addr, _mali_osk_resource_t *res)
277 {
278 int i;
279 uintptr_t phys_addr;
280
281 if (NULL == mali_platform_device) {
282 /* Not connected to a device */
283 return _MALI_OSK_ERR_ITEM_NOT_FOUND;
284 }
285
286 phys_addr = addr + _mali_osk_resource_base_address();
287 for (i = 0; i < mali_platform_device->num_resources; i++) {
288 if (IORESOURCE_MEM == resource_type(&(mali_platform_device->resource[i])) &&
289 mali_platform_device->resource[i].start == phys_addr) {
290 if (NULL != res) {
291 res->base = phys_addr;
292 res->description = mali_platform_device->resource[i].name;
293
294 /* Any (optional) IRQ resource belonging to this resource will follow */
295 if ((i + 1) < mali_platform_device->num_resources &&
296 IORESOURCE_IRQ == resource_type(&(mali_platform_device->resource[i + 1]))) {
297 res->irq = mali_platform_device->resource[i + 1].start;
298 } else {
299 res->irq = -1;
300 }
301 }
302 return _MALI_OSK_ERR_OK;
303 }
304 }
305
306 return _MALI_OSK_ERR_ITEM_NOT_FOUND;
307 }
308
_mali_osk_resource_base_address(void)309 uintptr_t _mali_osk_resource_base_address(void)
310 {
311 uintptr_t lowest_addr = (uintptr_t)(0 - 1);
312 uintptr_t ret = 0;
313
314 if (NULL != mali_platform_device) {
315 int i;
316 for (i = 0; i < mali_platform_device->num_resources; i++) {
317 if (mali_platform_device->resource[i].flags & IORESOURCE_MEM &&
318 mali_platform_device->resource[i].start < lowest_addr) {
319 lowest_addr = mali_platform_device->resource[i].start;
320 ret = lowest_addr;
321 }
322 }
323 }
324
325 return ret;
326 }
327
_mali_osk_device_data_pmu_config_get(u16 * domain_config_array,int array_size)328 void _mali_osk_device_data_pmu_config_get(u16 *domain_config_array, int array_size)
329 {
330 _mali_osk_device_data data = { 0, };
331
332 MALI_DEBUG_PRINT(2, ("Get pmu config from platform device data.\n"));
333 if (_MALI_OSK_ERR_OK == _mali_osk_device_data_get(&data)) {
334 /* Copy the custom customer power domain config */
335 _mali_osk_memcpy(domain_config_array, data.pmu_domain_config, sizeof(data.pmu_domain_config));
336 }
337
338 return;
339 }
340
_mali_osk_get_pmu_switch_delay(void)341 u32 _mali_osk_get_pmu_switch_delay(void)
342 {
343 _mali_osk_errcode_t err;
344 _mali_osk_device_data data = { 0, };
345
346 err = _mali_osk_device_data_get(&data);
347
348 if (_MALI_OSK_ERR_OK == err) {
349 return data.pmu_switch_delay;
350 }
351
352 return 0;
353 }
354 #endif /* CONFIG_MALI_DT */
355
_mali_osk_device_data_get(_mali_osk_device_data * data)356 _mali_osk_errcode_t _mali_osk_device_data_get(_mali_osk_device_data *data)
357 {
358 MALI_DEBUG_ASSERT_POINTER(data);
359
360 if (NULL != mali_platform_device) {
361 struct mali_gpu_device_data *os_data = NULL;
362
363 os_data = (struct mali_gpu_device_data *)mali_platform_device->dev.platform_data;
364 if (NULL != os_data) {
365 /* Copy data from OS dependant struct to Mali neutral struct (identical!) */
366 BUILD_BUG_ON(sizeof(*os_data) != sizeof(*data));
367 _mali_osk_memcpy(data, os_data, sizeof(*os_data));
368
369 return _MALI_OSK_ERR_OK;
370 }
371 }
372
373 return _MALI_OSK_ERR_ITEM_NOT_FOUND;
374 }
375
_mali_osk_identify_gpu_resource(void)376 u32 _mali_osk_identify_gpu_resource(void)
377 {
378 if (_MALI_OSK_ERR_OK == _mali_osk_resource_find(MALI_OFFSET_L2_RESOURCE1, NULL))
379 /* Mali 450 */
380 return 0x450;
381
382 if (_MALI_OSK_ERR_OK == _mali_osk_resource_find(MALI_OFFSET_DLBU, NULL))
383 /* Mali 470 */
384 return 0x470;
385
386 /* Mali 400 */
387 return 0x400;
388 }
389
_mali_osk_shared_interrupts(void)390 mali_bool _mali_osk_shared_interrupts(void)
391 {
392 u32 irqs[128];
393 u32 i, j, irq, num_irqs_found = 0;
394
395 MALI_DEBUG_ASSERT_POINTER(mali_platform_device);
396 MALI_DEBUG_ASSERT(128 >= mali_platform_device->num_resources);
397
398 for (i = 0; i < mali_platform_device->num_resources; i++) {
399 if (IORESOURCE_IRQ & mali_platform_device->resource[i].flags) {
400 irq = mali_platform_device->resource[i].start;
401
402 for (j = 0; j < num_irqs_found; ++j) {
403 if (irq == irqs[j]) {
404 return MALI_TRUE;
405 }
406 }
407
408 irqs[num_irqs_found++] = irq;
409 }
410 }
411
412 return MALI_FALSE;
413 }
414
_mali_osk_gpu_secure_mode_init(void)415 _mali_osk_errcode_t _mali_osk_gpu_secure_mode_init(void)
416 {
417 _mali_osk_device_data data = { 0, };
418
419 if (_MALI_OSK_ERR_OK == _mali_osk_device_data_get(&data)) {
420 if ((NULL != data.secure_mode_init) && (NULL != data.secure_mode_deinit)
421 && (NULL != data.gpu_reset_and_secure_mode_enable) && (NULL != data.gpu_reset_and_secure_mode_disable)) {
422 int err = data.secure_mode_init();
423 if (err) {
424 MALI_DEBUG_PRINT(1, ("Failed to init gpu secure mode.\n"));
425 return _MALI_OSK_ERR_FAULT;
426 }
427
428 mali_secure_mode_deinit = data.secure_mode_deinit;
429 mali_gpu_reset_and_secure_mode_enable = data.gpu_reset_and_secure_mode_enable;
430 mali_gpu_reset_and_secure_mode_disable = data.gpu_reset_and_secure_mode_disable;
431
432 mali_secure_mode_supported = MALI_TRUE;
433 mali_secure_mode_enabled = MALI_FALSE;
434 return _MALI_OSK_ERR_OK;
435 }
436 }
437 MALI_DEBUG_PRINT(3, ("GPU secure mode not supported.\n"));
438 return _MALI_OSK_ERR_UNSUPPORTED;
439
440 }
441
_mali_osk_gpu_secure_mode_deinit(void)442 _mali_osk_errcode_t _mali_osk_gpu_secure_mode_deinit(void)
443 {
444 if (NULL != mali_secure_mode_deinit) {
445 mali_secure_mode_deinit();
446 mali_secure_mode_enabled = MALI_FALSE;
447 mali_secure_mode_supported = MALI_FALSE;
448 return _MALI_OSK_ERR_OK;
449 }
450 MALI_DEBUG_PRINT(3, ("GPU secure mode not supported.\n"));
451 return _MALI_OSK_ERR_UNSUPPORTED;
452
453 }
454
455
_mali_osk_gpu_reset_and_secure_mode_enable(void)456 _mali_osk_errcode_t _mali_osk_gpu_reset_and_secure_mode_enable(void)
457 {
458 /* the mali executor lock must be held before enter this function. */
459
460 MALI_DEBUG_ASSERT(MALI_FALSE == mali_secure_mode_enabled);
461
462 if (NULL != mali_gpu_reset_and_secure_mode_enable) {
463 if (mali_gpu_reset_and_secure_mode_enable()) {
464 MALI_DEBUG_PRINT(1, ("Failed to reset GPU or enable gpu secure mode.\n"));
465 return _MALI_OSK_ERR_FAULT;
466 }
467 mali_secure_mode_enabled = MALI_TRUE;
468 return _MALI_OSK_ERR_OK;
469 }
470 MALI_DEBUG_PRINT(1, ("GPU secure mode not supported.\n"));
471 return _MALI_OSK_ERR_UNSUPPORTED;
472 }
473
_mali_osk_gpu_reset_and_secure_mode_disable(void)474 _mali_osk_errcode_t _mali_osk_gpu_reset_and_secure_mode_disable(void)
475 {
476 /* the mali executor lock must be held before enter this function. */
477
478 MALI_DEBUG_ASSERT(MALI_TRUE == mali_secure_mode_enabled);
479
480 if (NULL != mali_gpu_reset_and_secure_mode_disable) {
481 if (mali_gpu_reset_and_secure_mode_disable()) {
482 MALI_DEBUG_PRINT(1, ("Failed to reset GPU or disable gpu secure mode.\n"));
483 return _MALI_OSK_ERR_FAULT;
484 }
485 mali_secure_mode_enabled = MALI_FALSE;
486
487 return _MALI_OSK_ERR_OK;
488
489 }
490 MALI_DEBUG_PRINT(1, ("GPU secure mode not supported.\n"));
491 return _MALI_OSK_ERR_UNSUPPORTED;
492
493 }
494
_mali_osk_gpu_secure_mode_is_enabled(void)495 mali_bool _mali_osk_gpu_secure_mode_is_enabled(void)
496 {
497 return mali_secure_mode_enabled;
498 }
499
_mali_osk_gpu_secure_mode_is_supported(void)500 mali_bool _mali_osk_gpu_secure_mode_is_supported(void)
501 {
502 return mali_secure_mode_supported;
503 }
504
505
506