1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * rockchip-rng.c Random Number Generator driver for the Rockchip
4 *
5 * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
6 * Author: Lin Jinhan <troy.lin@rock-chips.com>
7 *
8 */
9 #include <linux/clk.h>
10 #include <linux/hw_random.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17
18 #define _SBF(s, v) ((v) << (s))
19 #define HIWORD_UPDATE(val, mask, shift) \
20 ((val) << (shift) | (mask) << ((shift) + 16))
21
22 #define ROCKCHIP_AUTOSUSPEND_DELAY 100
23 #define ROCKCHIP_POLL_PERIOD_US 100
24 #define ROCKCHIP_POLL_TIMEOUT_US 50000
25 #define RK_MAX_RNG_BYTE (32)
26
27 /* start of CRYPTO V1 register define */
28 #define CRYPTO_V1_CTRL 0x0008
29 #define CRYPTO_V1_RNG_START BIT(8)
30 #define CRYPTO_V1_RNG_FLUSH BIT(9)
31
32 #define CRYPTO_V1_TRNG_CTRL 0x0200
33 #define CRYPTO_V1_OSC_ENABLE BIT(16)
34 #define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
35
36 #define CRYPTO_V1_TRNG_DOUT_0 0x0204
37 /* end of CRYPTO V1 register define */
38
39 /* start of CRYPTO V2 register define */
40 #define CRYPTO_V2_RNG_DEFAULT_OFFSET 0x0400
41 #define CRYPTO_V2_RNG_CTL 0x0
42 #define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
43 #define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
44 #define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
45 #define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
46 #define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
47 #define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
48 #define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
49 #define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
50 #define CRYPTO_V2_RNG_ENABLE BIT(1)
51 #define CRYPTO_V2_RNG_START BIT(0)
52 #define CRYPTO_V2_RNG_SAMPLE_CNT 0x0004
53 #define CRYPTO_V2_RNG_DOUT_0 0x0010
54 /* end of CRYPTO V2 register define */
55
56 /* start of TRNG_V1 register define */
57 /* TRNG is no longer subordinate to the Crypto module */
58 #define TRNG_V1_CTRL 0x0000
59 #define TRNG_V1_CTRL_NOP _SBF(0, 0x00)
60 #define TRNG_V1_CTRL_RAND _SBF(0, 0x01)
61 #define TRNG_V1_CTRL_SEED _SBF(0, 0x02)
62
63 #define TRNG_V1_STAT 0x0004
64 #define TRNG_V1_STAT_SEEDED BIT(9)
65 #define TRNG_V1_STAT_GENERATING BIT(30)
66 #define TRNG_V1_STAT_RESEEDING BIT(31)
67
68 #define TRNG_V1_MODE 0x0008
69 #define TRNG_V1_MODE_128_BIT _SBF(3, 0x00)
70 #define TRNG_V1_MODE_256_BIT _SBF(3, 0x01)
71
72 #define TRNG_V1_IE 0x0010
73 #define TRNG_V1_IE_GLBL_EN BIT(31)
74 #define TRNG_V1_IE_SEED_DONE_EN BIT(1)
75 #define TRNG_V1_IE_RAND_RDY_EN BIT(0)
76
77 #define TRNG_V1_ISTAT 0x0014
78 #define TRNG_V1_ISTAT_RAND_RDY BIT(0)
79
80 /* RAND0 ~ RAND7 */
81 #define TRNG_V1_RAND0 0x0020
82 #define TRNG_V1_RAND7 0x003C
83
84 #define TRNG_V1_AUTO_RQSTS 0x0060
85
86 #define TRNG_V1_VERSION 0x00F0
87 #define TRNG_v1_VERSION_CODE 0x46bc
88 /* end of TRNG_V1 register define */
89
90 /* start of RKRNG register define */
91 #define RKRNG_CTRL 0x0010
92 #define RKRNG_CTRL_INST_REQ BIT(0)
93 #define RKRNG_CTRL_RESEED_REQ BIT(1)
94 #define RKRNG_CTRL_TEST_REQ BIT(2)
95 #define RKRNG_CTRL_SW_DRNG_REQ BIT(3)
96 #define RKRNG_CTRL_SW_TRNG_REQ BIT(4)
97
98 #define RKRNG_STATE 0x0014
99 #define RKRNG_STATE_INST_ACK BIT(0)
100 #define RKRNG_STATE_RESEED_ACK BIT(1)
101 #define RKRNG_STATE_TEST_ACK BIT(2)
102 #define RKRNG_STATE_SW_DRNG_ACK BIT(3)
103 #define RKRNG_STATE_SW_TRNG_ACK BIT(4)
104
105 /* DRNG_DATA_0 ~ DNG_DATA_7 */
106 #define RKRNG_DRNG_DATA_0 0x0070
107 #define RKRNG_DRNG_DATA_7 0x008C
108
109 /* end of RKRNG register define */
110
111 struct rk_rng_soc_data {
112 u32 default_offset;
113
114 int (*rk_rng_init)(struct hwrng *rng);
115 int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
116 };
117
118 struct rk_rng {
119 struct device *dev;
120 struct hwrng rng;
121 void __iomem *mem;
122 struct rk_rng_soc_data *soc_data;
123 int clk_num;
124 struct clk_bulk_data *clk_bulks;
125 };
126
rk_rng_writel(struct rk_rng * rng,u32 val,u32 offset)127 static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
128 {
129 __raw_writel(val, rng->mem + offset);
130 }
131
rk_rng_readl(struct rk_rng * rng,u32 offset)132 static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
133 {
134 return __raw_readl(rng->mem + offset);
135 }
136
rk_rng_init(struct hwrng * rng)137 static int rk_rng_init(struct hwrng *rng)
138 {
139 int ret;
140 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
141
142 dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
143
144 ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
145 if (ret < 0) {
146 dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
147 return ret;
148 }
149
150 return 0;
151 }
152
rk_rng_cleanup(struct hwrng * rng)153 static void rk_rng_cleanup(struct hwrng *rng)
154 {
155 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
156
157 dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
158 clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
159 }
160
rk_rng_read(struct hwrng * rng,void * buf,size_t max,bool wait)161 static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
162 {
163 int ret;
164 int read_len = 0;
165 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
166
167 if (!rk_rng->soc_data->rk_rng_read)
168 return -EFAULT;
169
170 ret = pm_runtime_get_sync(rk_rng->dev);
171 if (ret < 0) {
172 pm_runtime_put_noidle(rk_rng->dev);
173 return ret;
174 }
175
176 ret = 0;
177 while (max > ret) {
178 read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
179 max - ret, wait);
180 if (read_len < 0) {
181 ret = read_len;
182 break;
183 }
184 ret += read_len;
185 }
186
187 pm_runtime_mark_last_busy(rk_rng->dev);
188 pm_runtime_put_sync_autosuspend(rk_rng->dev);
189
190 return ret;
191 }
192
rk_rng_read_regs(struct rk_rng * rng,u32 offset,void * buf,size_t size)193 static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
194 size_t size)
195 {
196 u32 i;
197
198 for (i = 0; i < size; i += 4)
199 *(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
200 }
201
crypto_v1_read(struct hwrng * rng,void * buf,size_t max,bool wait)202 static int crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
203 {
204 int ret = 0;
205 u32 reg_ctrl = 0;
206 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
207
208 /* enable osc_ring to get entropy, sample period is set as 100 */
209 reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
210 rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
211
212 reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
213
214 rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
215
216 ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
217 !(reg_ctrl & CRYPTO_V1_RNG_START),
218 ROCKCHIP_POLL_PERIOD_US,
219 ROCKCHIP_POLL_TIMEOUT_US, false,
220 rk_rng, CRYPTO_V1_CTRL);
221
222 if (ret < 0)
223 goto out;
224
225 ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
226
227 rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
228
229 out:
230 /* close TRNG */
231 rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
232 CRYPTO_V1_CTRL);
233
234 return ret;
235 }
236
crypto_v2_read(struct hwrng * rng,void * buf,size_t max,bool wait)237 static int crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
238 {
239 int ret = 0;
240 u32 reg_ctrl = 0;
241 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
242
243 /* enable osc_ring to get entropy, sample period is set as 100 */
244 rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
245
246 reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
247 reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
248 reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
249 reg_ctrl |= CRYPTO_V2_RNG_START;
250
251 rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
252 CRYPTO_V2_RNG_CTL);
253
254 ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
255 !(reg_ctrl & CRYPTO_V2_RNG_START),
256 ROCKCHIP_POLL_PERIOD_US,
257 ROCKCHIP_POLL_TIMEOUT_US, false,
258 rk_rng, CRYPTO_V2_RNG_CTL);
259 if (ret < 0)
260 goto out;
261
262 ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
263
264 rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
265
266 out:
267 /* close TRNG */
268 rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
269
270 return ret;
271 }
272
trng_v1_init(struct hwrng * rng)273 static int trng_v1_init(struct hwrng *rng)
274 {
275 int ret;
276 uint32_t auto_reseed_cnt = 1000;
277 uint32_t reg_ctrl, status, version;
278 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
279
280 version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
281 if (version != TRNG_v1_VERSION_CODE) {
282 dev_err(rk_rng->dev,
283 "wrong trng version, expected = %08x, actual = %08x\n",
284 TRNG_V1_VERSION, version);
285 ret = -EFAULT;
286 goto exit;
287 }
288
289 status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
290
291 /* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
292 if (!(status & TRNG_V1_STAT_SEEDED) ||
293 (status & TRNG_V1_STAT_GENERATING) ||
294 (status & TRNG_V1_STAT_RESEEDING)) {
295 uint32_t mask = TRNG_V1_STAT_SEEDED |
296 TRNG_V1_STAT_GENERATING |
297 TRNG_V1_STAT_RESEEDING;
298
299 udelay(10);
300
301 /* wait for GENERATING and RESEEDING flag to clear */
302 read_poll_timeout(rk_rng_readl, reg_ctrl,
303 (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
304 ROCKCHIP_POLL_PERIOD_US,
305 ROCKCHIP_POLL_TIMEOUT_US, false,
306 rk_rng, TRNG_V1_STAT);
307 }
308
309 /* clear ISTAT flag because trng may auto reseeding when power on */
310 reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
311 rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
312
313 /* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
314 rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
315
316 ret = 0;
317 exit:
318
319 return ret;
320 }
321
trng_v1_read(struct hwrng * rng,void * buf,size_t max,bool wait)322 static int trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
323 {
324 int ret = 0;
325 u32 reg_ctrl = 0;
326 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
327
328 /* clear ISTAT anyway */
329 reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
330 rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
331
332 /* generate 256bit random */
333 rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
334 rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
335
336 /*
337 * Generate2 56 bit random data will cost 1024 clock cycles.
338 * Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
339 */
340 udelay(10);
341 reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
342 if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
343 /* wait RAND_RDY triggered */
344 ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
345 (reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
346 ROCKCHIP_POLL_PERIOD_US,
347 ROCKCHIP_POLL_TIMEOUT_US, false,
348 rk_rng, TRNG_V1_ISTAT);
349 if (ret < 0)
350 goto out;
351 }
352
353 ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
354
355 rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
356
357 /* clear all status flag */
358 rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
359 out:
360 /* close TRNG */
361 rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
362
363 return ret;
364 }
365
rkrng_init(struct hwrng * rng)366 static int rkrng_init(struct hwrng *rng)
367 {
368 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
369 u32 reg = 0;
370
371 rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
372
373 reg = rk_rng_readl(rk_rng, RKRNG_STATE);
374 rk_rng_writel(rk_rng, reg, RKRNG_STATE);
375
376 return 0;
377 }
378
rkrng_read(struct hwrng * rng,void * buf,size_t max,bool wait)379 static int rkrng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
380 {
381 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
382 u32 reg_ctrl = 0;
383 int ret;
384
385 reg_ctrl = RKRNG_CTRL_SW_DRNG_REQ;
386
387 rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), RKRNG_CTRL);
388
389 ret = readl_poll_timeout(rk_rng->mem + RKRNG_STATE, reg_ctrl,
390 (reg_ctrl & RKRNG_STATE_SW_DRNG_ACK),
391 ROCKCHIP_POLL_PERIOD_US,
392 ROCKCHIP_POLL_TIMEOUT_US);
393
394 if (ret)
395 goto exit;
396
397 rk_rng_writel(rk_rng, reg_ctrl, RKRNG_STATE);
398
399 ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
400
401 rk_rng_read_regs(rk_rng, RKRNG_DRNG_DATA_0, buf, ret);
402
403 exit:
404 /* close TRNG */
405 rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
406
407 return ret;
408 }
409
410 static const struct rk_rng_soc_data crypto_v1_soc_data = {
411 .default_offset = 0,
412
413 .rk_rng_read = crypto_v1_read,
414 };
415
416 static const struct rk_rng_soc_data crypto_v2_soc_data = {
417 .default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
418
419 .rk_rng_read = crypto_v2_read,
420 };
421
422 static const struct rk_rng_soc_data trng_v1_soc_data = {
423 .default_offset = 0,
424
425 .rk_rng_init = trng_v1_init,
426 .rk_rng_read = trng_v1_read,
427 };
428
429 static const struct rk_rng_soc_data rkrng_soc_data = {
430 .default_offset = 0,
431
432 .rk_rng_init = rkrng_init,
433 .rk_rng_read = rkrng_read,
434 };
435
436 static const struct of_device_id rk_rng_dt_match[] = {
437 {
438 .compatible = "rockchip,cryptov1-rng",
439 .data = (void *)&crypto_v1_soc_data,
440 },
441 {
442 .compatible = "rockchip,cryptov2-rng",
443 .data = (void *)&crypto_v2_soc_data,
444 },
445 {
446 .compatible = "rockchip,trngv1",
447 .data = (void *)&trng_v1_soc_data,
448 },
449 {
450 .compatible = "rockchip,rkrng",
451 .data = (void *)&rkrng_soc_data,
452 },
453 { },
454 };
455
456 MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
457
rk_rng_probe(struct platform_device * pdev)458 static int rk_rng_probe(struct platform_device *pdev)
459 {
460 int ret;
461 struct rk_rng *rk_rng;
462 struct device_node *np = pdev->dev.of_node;
463 const struct of_device_id *match;
464 resource_size_t map_size;
465
466 dev_dbg(&pdev->dev, "probing...\n");
467 rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
468 if (!rk_rng)
469 return -ENOMEM;
470
471 match = of_match_node(rk_rng_dt_match, np);
472 rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
473
474 rk_rng->dev = &pdev->dev;
475 rk_rng->rng.name = "rockchip";
476 #ifndef CONFIG_PM
477 rk_rng->rng.init = rk_rng_init;
478 rk_rng->rng.cleanup = rk_rng_cleanup,
479 #endif
480 rk_rng->rng.read = rk_rng_read;
481 rk_rng->rng.quality = 999;
482
483 rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
484 if (IS_ERR(rk_rng->mem))
485 return PTR_ERR(rk_rng->mem);
486
487 /* compatible with crypto v2 module */
488 /*
489 * With old dtsi configurations, the RNG base was equal to the crypto
490 * base, so both drivers could not be enabled at the same time.
491 * RNG base = CRYPTO base + RNG offset
492 * (Since RK356X, RNG module is no longer belongs to CRYPTO module)
493 *
494 * With new dtsi configurations, CRYPTO regs is divided into two parts
495 * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
496 * RNG driver and CRYPTO driver could be enabled at the same time.
497 */
498 if (map_size > rk_rng->soc_data->default_offset)
499 rk_rng->mem += rk_rng->soc_data->default_offset;
500
501 rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
502 if (rk_rng->clk_num < 0) {
503 dev_err(&pdev->dev, "failed to get clks property\n");
504 return -ENODEV;
505 }
506
507 platform_set_drvdata(pdev, rk_rng);
508
509 pm_runtime_set_autosuspend_delay(&pdev->dev,
510 ROCKCHIP_AUTOSUSPEND_DELAY);
511 pm_runtime_use_autosuspend(&pdev->dev);
512 pm_runtime_enable(&pdev->dev);
513
514 ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
515 if (ret) {
516 pm_runtime_dont_use_autosuspend(&pdev->dev);
517 pm_runtime_disable(&pdev->dev);
518 }
519
520 /* for some platform need hardware operation when probe */
521 if (rk_rng->soc_data->rk_rng_init) {
522 pm_runtime_get_sync(rk_rng->dev);
523
524 ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
525
526 pm_runtime_mark_last_busy(rk_rng->dev);
527 pm_runtime_put_sync_autosuspend(rk_rng->dev);
528 }
529
530 return ret;
531 }
532
533 #ifdef CONFIG_PM
rk_rng_runtime_suspend(struct device * dev)534 static int rk_rng_runtime_suspend(struct device *dev)
535 {
536 struct rk_rng *rk_rng = dev_get_drvdata(dev);
537
538 rk_rng_cleanup(&rk_rng->rng);
539
540 return 0;
541 }
542
rk_rng_runtime_resume(struct device * dev)543 static int rk_rng_runtime_resume(struct device *dev)
544 {
545 struct rk_rng *rk_rng = dev_get_drvdata(dev);
546
547 return rk_rng_init(&rk_rng->rng);
548 }
549
550 static const struct dev_pm_ops rk_rng_pm_ops = {
551 SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
552 rk_rng_runtime_resume, NULL)
553 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
554 pm_runtime_force_resume)
555 };
556
557 #endif
558
559 static struct platform_driver rk_rng_driver = {
560 .driver = {
561 .name = "rockchip-rng",
562 #ifdef CONFIG_PM
563 .pm = &rk_rng_pm_ops,
564 #endif
565 .of_match_table = rk_rng_dt_match,
566 },
567 .probe = rk_rng_probe,
568 };
569
570 module_platform_driver(rk_rng_driver);
571
572 MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
573 MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
574 MODULE_LICENSE("GPL v2");
575