1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/usb/pd.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pwm/pwm.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/input/rk-input.h> 12#include <dt-bindings/display/drm_mipi_dsi.h> 13#include <dt-bindings/display/rockchip_vop.h> 14#include <dt-bindings/sensor-dev.h> 15#include "rk3588s.dtsi" 16#include "rk3588-android.dtsi" 17#include "rk3588-rk806-single.dtsi" 18 19/ { 20 adc_keys: adc-keys { 21 compatible = "adc-keys"; 22 io-channels = <&saradc 1>; 23 io-channel-names = "buttons"; 24 keyup-threshold-microvolt = <1800000>; 25 poll-interval = <100>; 26 27 vol-up-key { 28 label = "volume up"; 29 linux,code = <KEY_VOLUMEUP>; 30 press-threshold-microvolt = <17000>; 31 }; 32 33 vol-down-key { 34 label = "volume down"; 35 linux,code = <KEY_VOLUMEDOWN>; 36 press-threshold-microvolt = <417000>; 37 }; 38 }; 39 40 backlight: backlight { 41 compatible = "pwm-backlight"; 42 pwms = <&pwm14 0 25000 0>; 43 brightness-levels = < 44 0 20 20 21 21 22 22 23 45 23 24 24 25 25 26 26 27 46 27 28 28 29 29 30 30 31 47 31 32 32 33 33 34 34 35 48 35 36 36 37 37 38 38 39 49 40 41 42 43 44 45 46 47 50 48 49 50 51 52 53 54 55 51 56 57 58 59 60 61 62 63 52 64 65 66 67 68 69 70 71 53 72 73 74 75 76 77 78 79 54 80 81 82 83 84 85 86 87 55 88 89 90 91 92 93 94 95 56 96 97 98 99 100 101 102 103 57 104 105 106 107 108 109 110 111 58 112 113 114 115 116 117 118 119 59 120 121 122 123 124 125 126 127 60 128 129 130 131 132 133 134 135 61 136 137 138 139 140 141 142 143 62 144 145 146 147 148 149 150 151 63 152 153 154 155 156 157 158 159 64 160 161 162 163 164 165 166 167 65 168 169 170 171 172 173 174 175 66 176 177 178 179 180 181 182 183 67 184 185 186 187 188 189 190 191 68 192 193 194 195 196 197 198 199 69 200 201 202 203 204 205 206 207 70 208 209 210 211 212 213 214 215 71 216 217 218 219 220 221 222 223 72 224 225 226 227 228 229 230 231 73 232 233 234 235 236 237 238 239 74 240 241 242 243 244 245 246 247 75 248 249 250 251 252 253 254 255 76 >; 77 default-brightness-level = <200>; 78 }; 79 80 charge-animation { 81 compatible = "rockchip,uboot-charge"; 82 rockchip,uboot-charge-on = <1>; 83 rockchip,android-charge-on = <0>; 84 rockchip,uboot-low-power-voltage = <6800>; 85 rockchip,screen-on-voltage = <6900>; 86 rockchip,uboot-exit-charge-level = <2>; 87 rockchip,uboot-exit-charge-auto = <0>; 88 rockchip,system-suspend = <1>; 89 regulator-on-in-mem = <&vdd_log_s0>, <&vcc_2v0_pldo_s3>, 90 <&vdd2_ddr_s3>, <&vcc_1v8_s3>, <&avcc_1v8_s0>, 91 <&vcc_1v8_s0>, <&vdd_0v75_s3>, <&pldo6_s3>, 92 <&vcc_3v3_s3>; 93 94 regulator-off-in-mem = <&vdd_gpu_s0>, <&vdd_npu_s0>, 95 <&vdd_vdenc_s0>, <&vdd_gpu_mem_s0>, <&vdd_npu_mem_s0>, 96 <&vdd_vdenc_mem_s0>, <&vcc_3v3_s0>, 97 <&vccio_sd_s0>, <&avdd_0v75_s0>, <&vdd_0v85_s0>, 98 <&vdd_cpu_big1_s0>, <&vdd_cpu_big0_s0>, <&vdd_cpu_lit_s0>, 99 <&vdd_cpu_big1_mem_s0>, <&vdd_cpu_big0_mem_s0>, <&vdd_cpu_lit_mem_s0>, 100 <&vddq_ddr_s0>, <&vdd_ddr_s0>, <&vdd_ddr_pll_s0>, 101 <&avdd_1v2_s0>, <&vdd_0v75_s0>; 102 status = "okay"; 103 }; 104 105 es7202_sound_micarray: es7202-sound-micarray { 106 status = "okay"; 107 compatible = "simple-audio-card"; 108 simple-audio-card,format = "i2s"; 109 simple-audio-card,name = "rockchip,sound-micarray"; 110 simple-audio-card,mclk-fs = <256>; 111 simple-audio-card,dai-link@0 { 112 format = "pdm"; 113 cpu { 114 sound-dai = <&pdm0>; 115 }; 116 codec { 117 sound-dai = <&es7202>; 118 }; 119 }; 120 }; 121 122 es8388_sound: es8388-sound { 123 status = "okay"; 124 compatible = "rockchip,multicodecs-card"; 125 rockchip,card-name = "rockchip,es8388-codec"; 126 hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; 127 io-channels = <&saradc 3>; 128 io-channel-names = "adc-detect"; 129 keyup-threshold-microvolt = <1800000>; 130 poll-interval = <100>; 131 spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 132 hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; 133 rockchip,format = "i2s"; 134 rockchip,mclk-fs = <256>; 135 rockchip,cpu = <&i2s0_8ch>; 136 rockchip,codec = <&es8388>; 137 rockchip,audio-routing = 138 "Headphone", "LOUT1", 139 "Headphone", "ROUT1", 140 "Speaker", "LOUT2", 141 "Speaker", "ROUT2", 142 "Headphone", "Headphone Power", 143 "Headphone", "Headphone Power", 144 "Speaker", "Speaker Power", 145 "Speaker", "Speaker Power", 146 "LINPUT1", "Main Mic", 147 "LINPUT2", "Main Mic", 148 "RINPUT1", "Headset Mic", 149 "RINPUT2", "Headset Mic"; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&hp_det>; 152 play-pause-key { 153 label = "playpause"; 154 linux,code = <KEY_PLAYPAUSE>; 155 press-threshold-microvolt = <2000>; 156 }; 157 }; 158 159 hall_sensor: hall-mh248 { 160 compatible = "hall-mh248"; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&mh248_irq_gpio>; 163 irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_EDGE_BOTH>; 164 hall-active = <1>; 165 status = "okay"; 166 }; 167 168 panel-edp { 169 compatible = "innolux,p120zdg-bf4", "simple-panel"; 170 backlight = <&backlight>; 171 power-supply = <&vcc3v3_lcd_edp>; 172 prepare-delay-ms = <120>; 173 enable-delay-ms = <120>; 174 unprepare-delay-ms = <500>; 175 disable-delay-ms = <120>; 176 width-mm = <254>; 177 height-mm = <169>; 178 179 panel-timing { 180 clock-frequency = <206000000>; 181 hactive = <2160>; 182 vactive = <1440>; 183 hfront-porch = <48>; 184 hsync-len = <32>; 185 hback-porch = <80>; 186 vfront-porch = <3>; 187 vsync-len = <10>; 188 vback-porch = <27>; 189 hsync-active = <0>; 190 vsync-active = <0>; 191 de-active = <0>; 192 pixelclk-active = <0>; 193 }; 194 195 port { 196 panel_in_edp: endpoint { 197 remote-endpoint = <&edp_out_panel>; 198 }; 199 }; 200 }; 201 202 sdio_pwrseq: sdio-pwrseq { 203 compatible = "mmc-pwrseq-simple"; 204 clocks = <&hym8563>; 205 clock-names = "ext_clock"; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&wifi_enable_h>; 208 /* 209 * On the module itself this is one of these (depending 210 * on the actual card populated): 211 * - SDIO_RESET_L_WL_REG_ON 212 * - PDN (power down when low) 213 */ 214 post-power-on-delay-ms = <200>; 215 reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; 216 }; 217 218 vcc5v0_sys: vcc5v0-sys { 219 compatible = "regulator-fixed"; 220 regulator-name = "vcc5v0_sys"; 221 regulator-always-on; 222 regulator-boot-on; 223 regulator-min-microvolt = <5000000>; 224 regulator-max-microvolt = <5000000>; 225 }; 226 227 vcc5v0_usb: vcc5v0-usb { 228 compatible = "regulator-fixed"; 229 regulator-name = "vcc5v0_usb"; 230 regulator-always-on; 231 regulator-boot-on; 232 regulator-min-microvolt = <5000000>; 233 regulator-max-microvolt = <5000000>; 234 enable-active-high; 235 gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; 236 vin-supply = <&vcc5v0_sys>; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&vcc5v0_usb_en>; 239 }; 240 241 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { 242 compatible = "regulator-fixed"; 243 regulator-name = "vcc_1v1_nldo_s3"; 244 regulator-always-on; 245 regulator-boot-on; 246 regulator-min-microvolt = <1100000>; 247 regulator-max-microvolt = <1100000>; 248 vin-supply = <&vcc5v0_sys>; 249 }; 250 251 vcc3v3_lcd_edp: vcc3v3-lcd-edp { 252 compatible = "regulator-fixed"; 253 regulator-name = "vcc3v3_lcd_edp"; 254 regulator-boot-on; 255 gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; 256 enable-active-high; 257 vin-supply = <&vcc_3v3_s3>; 258 }; 259 260 vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { 261 compatible = "regulator-fixed"; 262 enable-active-high; 263 gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&sd_s0_pwr>; 266 regulator-always-on; 267 regulator-max-microvolt = <3000000>; 268 regulator-min-microvolt = <3000000>; 269 regulator-name = "vcc_3v3_sd_s0"; 270 vin-supply = <&vcc_3v3_s3>; 271 }; 272 273 vcc5v0_host: vcc5v0-host { 274 compatible = "regulator-fixed"; 275 regulator-name = "vcc5v0_host"; 276 regulator-boot-on; 277 regulator-always-on; 278 regulator-min-microvolt = <5000000>; 279 regulator-max-microvolt = <5000000>; 280 enable-active-high; 281 gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; 282 vin-supply = <&vcc5v0_usb>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&vcc5v0_host_en>; 285 }; 286 287 vcc_mipidcphy: vcc-mipidcphy-regulator { 288 compatible = "regulator-fixed"; 289 gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&mipidcphy_pwr>; 292 regulator-name = "vcc_mipidcphy"; 293 enable-active-high; 294 regulator-boot-on; 295 }; 296 297 wireless_bluetooth: wireless-bluetooth { 298 compatible = "bluetooth-platdata"; 299 clocks = <&hym8563>; 300 clock-names = "ext_clock"; 301 uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; 302 pinctrl-names = "default", "rts_gpio"; 303 pinctrl-0 = <&uart7m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 304 pinctrl-1 = <&uart7_gpios>; 305 BT,reset_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; 306 BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 307 BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 308 status = "okay"; 309 }; 310 311 wireless_wlan: wireless-wlan { 312 compatible = "wlan-platdata"; 313 wifi_chip_type = "ap6398s"; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&wifi_host_wake_irq>; 316 WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 317 WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 318 status = "okay"; 319 }; 320}; 321 322&av1d_mmu { 323 status = "okay"; 324}; 325 326&combphy0_ps { 327 status = "okay"; 328}; 329 330&cpu_l0 { 331 cpu-supply = <&vdd_cpu_lit_s0>; 332 mem-supply = <&vdd_cpu_lit_mem_s0>; 333}; 334 335&cpu_b0 { 336 cpu-supply = <&vdd_cpu_big0_s0>; 337 mem-supply = <&vdd_cpu_big0_mem_s0>; 338}; 339 340&cpu_b2 { 341 cpu-supply = <&vdd_cpu_big1_s0>; 342 mem-supply = <&vdd_cpu_big1_mem_s0>; 343}; 344 345&csi2_dcphy0 { 346 status = "okay"; 347 348 ports { 349 #address-cells = <1>; 350 #size-cells = <0>; 351 port@0 { 352 reg = <0>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 356 mipi_in_ov50c40: endpoint@1 { 357 reg = <1>; 358 remote-endpoint = <&ov50c40_out>; 359 data-lanes = <1 2 3 4>; 360 }; 361 }; 362 port@1 { 363 reg = <1>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 367 csidcphy0_out: endpoint@0 { 368 reg = <0>; 369 remote-endpoint = <&mipi0_csi2_input>; 370 }; 371 }; 372 }; 373}; 374 375&csi2_dcphy1 { 376 status = "okay"; 377 378 ports { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 port@0 { 382 reg = <0>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 mipi_in_ucam1: endpoint@1 { 387 reg = <1>; 388 remote-endpoint = <&ov13855_out>; 389 data-lanes = <1 2 3 4>; 390 }; 391 }; 392 port@1 { 393 reg = <1>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 397 csidcphy1_out: endpoint@0 { 398 reg = <0>; 399 remote-endpoint = <&mipi1_csi2_input>; 400 }; 401 }; 402 }; 403}; 404 405&dp0 { 406 status = "okay"; 407}; 408 409&dp0_in_vp1 { 410 status = "okay"; 411}; 412 413&edp0 { 414 support-psr; 415 force-hpd; 416 status = "okay"; 417 418 ports { 419 port@1 { 420 reg = <1>; 421 422 edp_out_panel: endpoint { 423 remote-endpoint = <&panel_in_edp>; 424 }; 425 }; 426 }; 427}; 428 429&edp0_in_vp2 { 430 status = "okay"; 431}; 432 433&gpu { 434 mali-supply = <&vdd_gpu_s0>; 435 mem-supply = <&vdd_gpu_mem_s0>; 436 upthreshold = <60>; 437 downdifferential = <30>; 438 status = "okay"; 439}; 440 441&hdptxphy0 { 442 /* Single Vdiff Training Table for power reduction (optional) */ 443 training-table = /bits/ 8 < 444 /* voltage swing 0, pre-emphasis 0->3 */ 445 0x0d 0x00 0x00 0x00 0x00 0x00 446 0x0d 0x00 0x00 0x00 0x00 0x00 447 0x0d 0x00 0x00 0x00 0x00 0x00 448 0x0d 0x00 0x00 0x00 0x00 0x00 449 /* voltage swing 1, pre-emphasis 0->2 */ 450 0x0d 0x00 0x00 0x00 0x00 0x00 451 0x0d 0x00 0x00 0x00 0x00 0x00 452 0x0d 0x00 0x00 0x00 0x00 0x00 453 /* voltage swing 2, pre-emphasis 0->1 */ 454 0x0d 0x00 0x00 0x00 0x00 0x00 455 0x0d 0x00 0x00 0x00 0x00 0x00 456 /* voltage swing 3, pre-emphasis 0 */ 457 0x0d 0x00 0x00 0x00 0x00 0x00 458 >; 459 status = "okay"; 460}; 461 462&i2c0 { 463 status = "okay"; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&i2c0m2_xfer>; 466 467 vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 468 compatible = "rockchip,rk8602"; 469 reg = <0x42>; 470 vin-supply = <&vcc5v0_sys>; 471 regulator-compatible = "rk860x-reg"; 472 regulator-name = "vdd_cpu_big0_s0"; 473 regulator-min-microvolt = <550000>; 474 regulator-max-microvolt = <1050000>; 475 regulator-ramp-delay = <2300>; 476 rockchip,suspend-voltage-selector = <1>; 477 regulator-boot-on; 478 regulator-always-on; 479 regulator-state-mem { 480 regulator-off-in-suspend; 481 }; 482 }; 483 484 vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 485 compatible = "rockchip,rk8603"; 486 reg = <0x43>; 487 vin-supply = <&vcc5v0_sys>; 488 regulator-compatible = "rk860x-reg"; 489 regulator-name = "vdd_cpu_big1_s0"; 490 regulator-min-microvolt = <550000>; 491 regulator-max-microvolt = <1050000>; 492 regulator-ramp-delay = <2300>; 493 rockchip,suspend-voltage-selector = <1>; 494 regulator-boot-on; 495 regulator-always-on; 496 regulator-state-mem { 497 regulator-off-in-suspend; 498 }; 499 }; 500}; 501 502&i2c2 { 503 status = "okay"; 504 505 vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 506 compatible = "rockchip,rk8602"; 507 reg = <0x42>; 508 vin-supply = <&vcc5v0_sys>; 509 regulator-compatible = "rk860x-reg"; 510 regulator-name = "vdd_npu_s0"; 511 regulator-min-microvolt = <550000>; 512 regulator-max-microvolt = <950000>; 513 regulator-ramp-delay = <2300>; 514 rockchip,suspend-voltage-selector = <1>; 515 regulator-boot-on; 516 regulator-always-on; 517 regulator-state-mem { 518 regulator-off-in-suspend; 519 }; 520 }; 521}; 522 523&i2c3 { 524 status = "okay"; 525 526 es8388: es8388@11 { 527 status = "okay"; 528 #sound-dai-cells = <0>; 529 compatible = "everest,es8388", "everest,es8323"; 530 reg = <0x11>; 531 clocks = <&mclkout_i2s0>; 532 clock-names = "mclk"; 533 assigned-clocks = <&mclkout_i2s0>; 534 assigned-clock-rates = <12288000>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&i2s0_mclk>; 537 }; 538 539 es7202: es7202@32 { 540 status = "okay"; 541 #sound-dai-cells = <0>; 542 compatible = "ES7202_PDM_ADC_1"; 543 power-supply = <&avcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ 544 reg = <0x32>; 545 }; 546}; 547 548&i2c4 { 549 status = "okay"; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&i2c4m3_xfer>; 552 553 elan_touch: elan_ktf@10 { 554 status = "okay"; 555 compatible = "elan,ektf"; 556 reg = <0x10>; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&touch_gpio>; 559 elan,rst-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; 560 elan,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; 561 chip_type = <0x01>; /* 1:HID IIC, 0: NORMAL IIC */ 562 report_type = <0x01>; /* 1:B protocol, 0:A protocol */ 563 }; 564}; 565 566&i2c5 { 567 status = "okay"; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&i2c5m2_xfer>; 570 571 mpu6500_acc: mpu_acc@68 { 572 status = "okay"; 573 compatible = "mpu6500_acc"; 574 reg = <0x68>; 575 irq-gpio = <&gpio1 RK_PD3 IRQ_TYPE_EDGE_RISING>; 576 irq_enable = <0>; 577 poll_delay_ms = <30>; 578 type = <SENSOR_TYPE_ACCEL>; 579 layout = <5>; 580 }; 581 582 mpu6500_gyro: mpu_gyro@68 { 583 status = "okay"; 584 compatible = "mpu6500_gyro"; 585 reg = <0x68>; 586 poll_delay_ms = <30>; 587 type = <SENSOR_TYPE_GYROSCOPE>; 588 layout = <5>; 589 }; 590}; 591 592&i2c6 { 593 status = "okay"; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&i2c6m3_xfer>; 596 597 hym8563: hym8563@51 { 598 compatible = "haoyu,hym8563"; 599 reg = <0x51>; 600 #clock-cells = <0>; 601 clock-frequency = <32768>; 602 clock-output-names = "hym8563"; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&rtc_int>; 605 606 interrupt-parent = <&gpio0>; 607 interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 608 wakeup-source; 609 }; 610 611 cw2015@62 { 612 status = "okay"; 613 compatible = "cellwise,cw2015"; 614 reg = <0x62>; 615 cellwise,battery-profile = /bits/ 8 616 <0x17 0x67 0x6C 0x66 0x65 0x64 0x61 0x5B 617 0x5F 0x75 0x49 0x52 0x50 0x51 0x48 0x3D 618 0x34 0x2C 0x29 0x21 0x23 0x2D 0x40 0x49 619 0x25 0x5C 0x0B 0x85 0x10 0x1F 0x31 0x49 620 0x58 0x5E 0x63 0x6C 0x3E 0x1D 0x9A 0x35 621 0x0A 0x33 0x15 0x3B 0x70 0x99 0xAB 0x17 622 0x40 0x75 0x99 0xC4 0x80 0xB5 0xDE 0xCB 623 0x2F 0x00 0x64 0xA5 0xB5 0x00 0xF8 0x39>; 624 cellwise,dual-cell = <1>; 625 cellwise,monitor-interval-ms = <5000>; 626 power-supplies = <&bq25703>; 627 }; 628 629 bq25703: bq25703@6b { 630 status = "okay"; 631 compatible = "ti,bq25703"; 632 reg = <0x6b>; 633 ti,usb-charger-detection = <&usbc0>; 634 635 interrupt-parent = <&gpio0>; 636 interrupts = <RK_PD5 IRQ_TYPE_LEVEL_LOW>; 637 otg-mode-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&charger_ok>; 640 extcon = <&u2phy0>; 641 ti,charge-current = <2500000>; 642 ti,max-input-voltage = <20000000>; 643 ti,max-input-current = <6000000>; 644 ti,max-charge-voltage = <8750000>; 645 ti,input-current = <500000>; 646 ti,input-current-sdp = <500000>; 647 ti,input-current-dcp = <2000000>; 648 ti,input-current-cdp = <2000000>; 649 ti,minimum-sys-voltage = <7400000>; 650 ti,otg-voltage = <5000000>; 651 ti,otg-current = <1500000>; 652 pd-charge-only = <0>; 653 regulators { 654 vbus5v0_typec: vbus5v0-typec { 655 regulator-compatible = "otg-vbus"; 656 regulator-name = "vbus5v0_typec"; 657 }; 658 }; 659 }; 660}; 661 662&i2c7 { 663 status = "okay"; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&i2c7m2_xfer>; 666 667 aw8601: aw8601@c { 668 compatible = "awinic,aw8601"; 669 status = "okay"; 670 reg = <0x0c>; 671 rockchip,vcm-start-current = <56>; 672 rockchip,vcm-rated-current = <96>; 673 rockchip,vcm-step-mode = <4>; 674 rockchip,camera-module-index = <0>; 675 rockchip,camera-module-facing = "back"; 676 }; 677 678 ov13855: ov13855@10 { 679 compatible = "ovti,ov13855"; 680 status = "okay"; 681 reg = <0x10>; 682 clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; 683 clock-names = "xvclk"; 684 power-domains = <&power RK3588_PD_VI>; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&mipim1_camera4_clk>; 687 rockchip,grf = <&sys_grf>; 688 reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; 689 pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; 690 avdd-supply = <&vcc_mipidcphy>; 691 rockchip,camera-module-index = <1>; 692 rockchip,camera-module-facing = "front"; 693 rockchip,camera-module-name = "CMK-OT2016-FV1"; 694 rockchip,camera-module-lens-name = "default"; 695 port { 696 ov13855_out: endpoint { 697 remote-endpoint = <&mipi_in_ucam1>; 698 data-lanes = <1 2 3 4>; 699 }; 700 }; 701 }; 702 703 ov50c40: ov50c40@36 { 704 compatible = "ovti,ov50c40"; 705 status = "okay"; 706 reg = <0x36>; 707 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; 708 clock-names = "xvclk"; 709 power-domains = <&power RK3588_PD_VI>; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&mipim1_camera1_clk>; 712 rockchip,grf = <&sys_grf>; 713 reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; 714 pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; 715 avdd-supply = <&vcc_mipidcphy>; 716 rockchip,camera-module-index = <0>; 717 rockchip,camera-module-facing = "back"; 718 rockchip,camera-module-name = "HZGA06"; 719 rockchip,camera-module-lens-name = "ZE0082C1"; 720 eeprom-ctrl = <&otp_eeprom>; 721 lens-focus = <&aw8601>; 722 port { 723 ov50c40_out: endpoint { 724 remote-endpoint = <&mipi_in_ov50c40>; 725 data-lanes = <1 2 3 4>; 726 }; 727 }; 728 }; 729 730 otp_eeprom: otp_eeprom@50 { 731 compatible = "rk,otp_eeprom"; 732 status = "okay"; 733 reg = <0x50>; 734 }; 735}; 736 737&i2c8 { 738 status = "okay"; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&i2c8m2_xfer>; 741 742 usbc0: fusb302@22 { 743 compatible = "fcs,fusb302"; 744 reg = <0x22>; 745 interrupt-parent = <&gpio0>; 746 interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>; 747 int-n-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; 748 pinctrl-names = "default"; 749 pinctrl-0 = <&usbc0_int>; 750 vbus-supply = <&vbus5v0_typec>; 751 status = "okay"; 752 753 ports { 754 #address-cells = <1>; 755 #size-cells = <0>; 756 757 port@0 { 758 reg = <0>; 759 usbc0_role_sw: endpoint@0 { 760 remote-endpoint = <&dwc3_0_role_switch>; 761 }; 762 }; 763 }; 764 765 usb_con: connector { 766 compatible = "usb-c-connector"; 767 label = "USB-C"; 768 data-role = "dual"; 769 power-role = "dual"; 770 try-power-role = "sink"; 771 op-sink-microwatt = <1000000>; 772 sink-pdos = 773 <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 774 PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM) 775 PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>; 776 source-pdos = 777 <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 778 779 altmodes { 780 #address-cells = <1>; 781 #size-cells = <0>; 782 783 altmode@0 { 784 reg = <0>; 785 svid = <0xff01>; 786 vdo = <0xffffffff>; 787 }; 788 }; 789 790 ports { 791 #address-cells = <1>; 792 #size-cells = <0>; 793 794 port@0 { 795 reg = <0>; 796 usbc0_orien_sw: endpoint { 797 remote-endpoint = <&usbdp_phy0_orientation_switch>; 798 }; 799 }; 800 801 port@1 { 802 reg = <1>; 803 dp_altmode_mux: endpoint { 804 remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 805 }; 806 }; 807 }; 808 }; 809 }; 810}; 811 812&i2s0_8ch { 813 status = "okay"; 814 rockchip,clk-trcm = <1>; 815 pinctrl-0 = <&i2s0_lrck 816 &i2s0_sclk 817 &i2s0_sdi0 818 &i2s0_sdo0>; 819}; 820 821&iep { 822 status = "okay"; 823}; 824 825&iep_mmu { 826 status = "okay"; 827}; 828 829&jpegd { 830 status = "okay"; 831}; 832 833&jpegd_mmu { 834 status = "okay"; 835}; 836 837&jpege_ccu { 838 status = "okay"; 839}; 840 841&jpege0 { 842 status = "okay"; 843}; 844 845&jpege0_mmu { 846 status = "okay"; 847}; 848 849&jpege1 { 850 status = "okay"; 851}; 852 853&jpege1_mmu { 854 status = "okay"; 855}; 856 857&jpege2 { 858 status = "okay"; 859}; 860 861&jpege2_mmu { 862 status = "okay"; 863}; 864 865&jpege3 { 866 status = "okay"; 867}; 868 869&jpege3_mmu { 870 status = "okay"; 871}; 872 873&mipi_dcphy0 { 874 status = "okay"; 875}; 876 877&mipi_dcphy1 { 878 status = "okay"; 879}; 880 881&mipi0_csi2 { 882 status = "okay"; 883 884 ports { 885 #address-cells = <1>; 886 #size-cells = <0>; 887 888 port@0 { 889 reg = <0>; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 893 mipi0_csi2_input: endpoint@1 { 894 reg = <1>; 895 remote-endpoint = <&csidcphy0_out>; 896 }; 897 }; 898 899 port@1 { 900 reg = <1>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 904 mipi0_csi2_output: endpoint@0 { 905 reg = <0>; 906 remote-endpoint = <&cif_mipi_in0>; 907 }; 908 }; 909 }; 910}; 911 912&mipi1_csi2 { 913 status = "okay"; 914 915 ports { 916 #address-cells = <1>; 917 #size-cells = <0>; 918 919 port@0 { 920 reg = <0>; 921 #address-cells = <1>; 922 #size-cells = <0>; 923 924 mipi1_csi2_input: endpoint@1 { 925 reg = <1>; 926 remote-endpoint = <&csidcphy1_out>; 927 }; 928 }; 929 930 port@1 { 931 reg = <1>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 935 mipi1_csi2_output: endpoint@0 { 936 reg = <0>; 937 remote-endpoint = <&cif_mipi_in1>; 938 }; 939 }; 940 }; 941}; 942 943&mpp_srv { 944 status = "okay"; 945}; 946 947&pdm0 { 948 rockchip,path-map = <2 0 1 3>; 949 status = "okay"; 950}; 951 952&pinctrl { 953 cam { 954 mipidcphy_pwr: mipidcphy-pwr { 955 rockchip,pins = 956 /* camera power en */ 957 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; 958 }; 959 }; 960 961 charger { 962 charger_ok: charger_ok { 963 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; 964 }; 965 }; 966 967 headphone { 968 hp_det: hp-det { 969 rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 970 }; 971 }; 972 973 hym8563 { 974 rtc_int: rtc-int { 975 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 976 }; 977 }; 978 979 sdio-pwrseq { 980 wifi_enable_h: wifi-enable-h { 981 rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 982 }; 983 }; 984 985 sdmmc { 986 sd_s0_pwr: sd-s0-pwr { 987 rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 988 }; 989 }; 990 991 sensor { 992 mpu6500_irq_gpio: mpu6500-irq-gpio { 993 rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 994 }; 995 996 mh248_irq_gpio: mh248-irq-gpio { 997 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; 998 }; 999 }; 1000 1001 touch { 1002 touch_gpio: touch-gpio { 1003 rockchip,pins = 1004 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, 1005 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1006 }; 1007 }; 1008 1009 usb { 1010 vcc5v0_host_en: vcc5v0-host-en { 1011 rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1012 }; 1013 vcc5v0_usb_en: vcc5v0-usb-en { 1014 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 1015 }; 1016 }; 1017 1018 usb-typec { 1019 usbc0_int: usbc0-int { 1020 rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; 1021 }; 1022 }; 1023 1024 wireless-bluetooth { 1025 uart7_gpios: uart7-gpios { 1026 rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; 1027 }; 1028 1029 bt_reset_gpio: bt-reset-gpio { 1030 rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 1031 }; 1032 1033 bt_wake_gpio: bt-wake-gpio { 1034 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 1035 }; 1036 1037 bt_irq_gpio: bt-irq-gpio { 1038 rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; 1039 }; 1040 }; 1041 1042 wireless-wlan { 1043 wifi_host_wake_irq: wifi-host-wake-irq { 1044 rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; 1045 }; 1046 1047 wifi_poweren_gpio: wifi-poweren-gpio { 1048 rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 1049 }; 1050 }; 1051}; 1052 1053&pwm14 { 1054 pinctrl-0 = <&pwm14m1_pins>; 1055 status = "okay"; 1056}; 1057 1058&rga3_core0 { 1059 status = "okay"; 1060}; 1061 1062&rga3_0_mmu { 1063 status = "okay"; 1064}; 1065 1066&rga3_core1 { 1067 status = "okay"; 1068}; 1069 1070&rga3_1_mmu { 1071 status = "okay"; 1072}; 1073 1074&rga2 { 1075 status = "okay"; 1076}; 1077 1078&rkcif { 1079 status = "okay"; 1080}; 1081 1082&rkcif_mipi_lvds { 1083 status = "okay"; 1084 1085 port { 1086 cif_mipi_in0: endpoint { 1087 remote-endpoint = <&mipi0_csi2_output>; 1088 }; 1089 }; 1090}; 1091 1092&rkcif_mipi_lvds_sditf { 1093 status = "okay"; 1094 1095 port { 1096 mipi_lvds_sditf: endpoint { 1097 remote-endpoint = <&isp1_in1>; 1098 }; 1099 }; 1100}; 1101 1102&rkcif_mipi_lvds1 { 1103 status = "okay"; 1104 1105 port { 1106 cif_mipi_in1: endpoint { 1107 remote-endpoint = <&mipi1_csi2_output>; 1108 }; 1109 }; 1110}; 1111 1112&rkcif_mipi_lvds1_sditf { 1113 status = "okay"; 1114 1115 port { 1116 mipi1_lvds_sditf: endpoint { 1117 remote-endpoint = <&isp1_in2>; 1118 }; 1119 }; 1120}; 1121 1122&rkcif_mmu { 1123 status = "okay"; 1124}; 1125 1126&rkisp_unite { 1127 status = "okay"; 1128 1129}; 1130 1131&rkisp_unite_mmu { 1132 status = "okay"; 1133}; 1134 1135&rkisp0_vir0 { 1136 status = "okay"; 1137 /* 1138 * dual isp process image case 1139 * other rkisp hw and virtual nodes should disabled 1140 */ 1141 rockchip,hw = <&rkisp_unite>; 1142 port { 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 1146 isp1_in1: endpoint@0 { 1147 reg = <0>; 1148 remote-endpoint = <&mipi_lvds_sditf>; 1149 }; 1150 isp1_in2: endpoint@1 { 1151 reg = <1>; 1152 remote-endpoint = <&mipi1_lvds_sditf>; 1153 }; 1154 }; 1155}; 1156 1157&rknpu { 1158 rknpu-supply = <&vdd_npu_s0>; 1159 mem-supply = <&vdd_npu_mem_s0>; 1160 status = "okay"; 1161}; 1162 1163&rknpu_mmu { 1164 status = "okay"; 1165}; 1166 1167&rkvdec_ccu { 1168 status = "okay"; 1169}; 1170 1171&rkvdec0 { 1172 status = "okay"; 1173}; 1174 1175&rkvdec0_mmu { 1176 status = "okay"; 1177}; 1178 1179&rkvdec1 { 1180 status = "okay"; 1181}; 1182 1183&rkvdec1_mmu { 1184 status = "okay"; 1185}; 1186 1187&vepu { 1188 status = "okay"; 1189}; 1190 1191&rkvenc_ccu { 1192 status = "okay"; 1193}; 1194 1195&rkvenc0 { 1196 venc-supply = <&vdd_vdenc_s0>; 1197 mem-supply = <&vdd_vdenc_mem_s0>; 1198 status = "okay"; 1199}; 1200 1201&rkvenc0_mmu { 1202 status = "okay"; 1203}; 1204 1205&rkvenc1 { 1206 venc-supply = <&vdd_vdenc_s0>; 1207 mem-supply = <&vdd_vdenc_mem_s0>; 1208 status = "okay"; 1209}; 1210 1211&rkvenc1_mmu { 1212 status = "okay"; 1213}; 1214 1215&rockchip_suspend { 1216 status = "okay"; 1217 rockchip,sleep-debug-en = <1>; 1218}; 1219 1220&route_edp0 { 1221 connect = <&vp2_out_edp0>; 1222 status = "okay"; 1223}; 1224 1225&saradc { 1226 status = "okay"; 1227 vref-supply = <&vcc_1v8_s0>; 1228}; 1229 1230&sdhci { 1231 bus-width = <8>; 1232 no-sdio; 1233 no-sd; 1234 non-removable; 1235 max-frequency = <200000000>; 1236 mmc-hs400-1_8v; 1237 mmc-hs400-enhanced-strobe; 1238 status = "okay"; 1239}; 1240 1241&sdio { 1242 max-frequency = <150000000>; 1243 no-sd; 1244 no-mmc; 1245 bus-width = <4>; 1246 disable-wp; 1247 cap-sd-highspeed; 1248 cap-sdio-irq; 1249 keep-power-in-suspend; 1250 mmc-pwrseq = <&sdio_pwrseq>; 1251 non-removable; 1252 pinctrl-names = "default"; 1253 pinctrl-0 = <&sdiom1_pins>; 1254 sd-uhs-sdr104; 1255 status = "okay"; 1256}; 1257 1258&sdmmc { 1259 max-frequency = <150000000>; 1260 no-sdio; 1261 no-mmc; 1262 bus-width = <4>; 1263 cap-mmc-highspeed; 1264 cap-sd-highspeed; 1265 disable-wp; 1266 sd-uhs-sdr104; 1267 vmmc-supply = <&vcc_3v3_sd_s0>; 1268 vqmmc-supply = <&vccio_sd_s0>; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; 1271 status = "okay"; 1272}; 1273 1274&tsadc { 1275 status = "okay"; 1276}; 1277 1278&uart7 { 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&uart7m1_xfer &uart7m1_ctsn>; 1281 status = "okay"; 1282}; 1283 1284&u2phy0 { 1285 status = "okay"; 1286}; 1287 1288&u2phy2 { 1289 status = "okay"; 1290}; 1291 1292&u2phy0_otg { 1293 rockchip,typec-vbus-det; 1294 status = "okay"; 1295}; 1296 1297&u2phy2_host { 1298 status = "okay"; 1299 phy-supply = <&vcc5v0_host>; 1300}; 1301 1302&usb_host0_ehci { 1303 status = "okay"; 1304}; 1305 1306&usb_host0_ohci { 1307 status = "okay"; 1308}; 1309 1310&usbdp_phy0 { 1311 orientation-switch; 1312 svid = <0xff01>; 1313 sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; 1314 sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; 1315 status = "okay"; 1316 1317 port { 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 usbdp_phy0_orientation_switch: endpoint@0 { 1321 reg = <0>; 1322 remote-endpoint = <&usbc0_orien_sw>; 1323 }; 1324 1325 usbdp_phy0_dp_altmode_mux: endpoint@1 { 1326 reg = <1>; 1327 remote-endpoint = <&dp_altmode_mux>; 1328 }; 1329 }; 1330}; 1331 1332&usbdp_phy0_dp { 1333 status = "okay"; 1334}; 1335 1336&usbdp_phy0_u3 { 1337 status = "okay"; 1338}; 1339 1340&usbdrd3_0 { 1341 status = "okay"; 1342}; 1343 1344&usbdrd_dwc3_0 { 1345 dr_mode = "otg"; 1346 status = "okay"; 1347 1348 usb-role-switch; 1349 port { 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 dwc3_0_role_switch: endpoint@0 { 1353 reg = <0>; 1354 remote-endpoint = <&usbc0_role_sw>; 1355 }; 1356 }; 1357}; 1358 1359&usbhost3_0 { 1360 status = "disabled"; 1361}; 1362 1363&usbhost_dwc3_0 { 1364 status = "disabled"; 1365}; 1366 1367&vdpu { 1368 status = "okay"; 1369}; 1370 1371&vdpu_mmu { 1372 status = "okay"; 1373}; 1374 1375&vop { 1376 status = "okay"; 1377}; 1378 1379&vop_mmu { 1380 status = "okay"; 1381}; 1382 1383&vp1 { 1384 rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | 1385 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; 1386 rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>; 1387}; 1388 1389&vp2 { 1390 rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | 1391 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; 1392 rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>; 1393}; 1394