1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7&csi2_dcphy0 { 8 status = "okay"; 9 10 ports { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 port@0 { 14 reg = <0>; 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 dp_mipi_in: endpoint@1 { 19 reg = <1>; 20 remote-endpoint = <<7911d_out>; 21 data-lanes = <1 2 3 4>; 22 }; 23 mipi_in_dcphy0: endpoint@2 { 24 reg = <2>; 25 remote-endpoint = <&ov50c40_out0>; 26 data-lanes = <1 2 3 4>; 27 }; 28 }; 29 30 port@1 { 31 reg = <1>; 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 csidcphy0_out: endpoint@0 { 36 reg = <0>; 37 remote-endpoint = <&mipi0_csi2_input>; 38 }; 39 }; 40 }; 41}; 42 43&csi2_dcphy1 { 44 status = "okay"; 45 46 ports { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 port@0 { 50 reg = <0>; 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 mipi_in_dcphy1: endpoint@1 { 55 reg = <1>; 56 remote-endpoint = <&ov50c40_out1>; 57 data-lanes = <1 2 3 4>; 58 }; 59 }; 60 port@1 { 61 reg = <1>; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 65 csidcphy1_out: endpoint@0 { 66 reg = <0>; 67 remote-endpoint = <&mipi1_csi2_input>; 68 }; 69 }; 70 }; 71}; 72 73&i2c6 { 74 status = "okay"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&i2c6m4_xfer>; 77 78 aw8601: aw8601@c { 79 compatible = "awinic,aw8601"; 80 status = "okay"; 81 reg = <0x0c>; 82 rockchip,vcm-start-current = <56>; 83 rockchip,vcm-rated-current = <96>; 84 rockchip,vcm-step-mode = <4>; 85 rockchip,camera-module-index = <0>; 86 rockchip,camera-module-facing = "back"; 87 }; 88 89 lt7911d: lt7911d@2b { 90 compatible = "lontium,lt7911d"; 91 status = "okay"; 92 reg = <0x2b>; 93 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; 94 clock-names = "xvclk"; 95 interrupt-parent = <&gpio3>; 96 interrupts = <RK_PD4 IRQ_TYPE_EDGE_RISING>; 97 power-domains = <&power RK3588_PD_VI>; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&mipim1_camera1_clk>; 100 reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; 101 power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; 102 // hpd-ctl-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; 103 // plugin-det-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; 104 rockchip,camera-module-index = <0>; 105 rockchip,camera-module-facing = "back"; 106 rockchip,camera-module-name = "LT7911D"; 107 rockchip,camera-module-lens-name = "NC"; 108 port { 109 lt7911d_out: endpoint { 110 remote-endpoint = <&dp_mipi_in>; 111 data-lanes = <1 2 3 4>; 112 }; 113 }; 114 }; 115 116 ov50c40: ov50c40@36 { 117 compatible = "ovti,ov50c40"; 118 status = "okay"; 119 reg = <0x36>; 120 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; 121 clock-names = "xvclk"; 122 power-domains = <&power RK3588_PD_VI>; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&mipim1_camera1_clk>; 125 rockchip,grf = <&sys_grf>; 126 reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; 127 pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; 128 rockchip,camera-module-index = <0>; 129 rockchip,camera-module-facing = "back"; 130 rockchip,camera-module-name = "HZGA06"; 131 rockchip,camera-module-lens-name = "ZE0082C1"; 132 eeprom-ctrl = <&otp_eeprom>; 133 lens-focus = <&aw8601>; 134 port { 135 ov50c40_out0: endpoint { 136 remote-endpoint = <&mipi_in_dcphy0>; 137 data-lanes = <1 2 3 4>; 138 }; 139 }; 140 }; 141 142 otp_eeprom: otp_eeprom@50 { 143 compatible = "rk,otp_eeprom"; 144 status = "okay"; 145 reg = <0x50>; 146 }; 147}; 148 149&i2c7 { 150 status = "okay"; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&i2c7m2_xfer>; 153 154 aw8601b: aw8601b@c { 155 compatible = "awinic,aw8601"; 156 status = "okay"; 157 reg = <0x0c>; 158 rockchip,vcm-start-current = <56>; 159 rockchip,vcm-rated-current = <96>; 160 rockchip,vcm-step-mode = <4>; 161 rockchip,camera-module-index = <1>; 162 rockchip,camera-module-facing = "back"; 163 }; 164 165 ov50c40b: ov50c40b@36 { 166 compatible = "ovti,ov50c40"; 167 status = "okay"; 168 reg = <0x36>; 169 clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; 170 clock-names = "xvclk"; 171 power-domains = <&power RK3588_PD_VI>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&mipim1_camera2_clk>; 174 rockchip,grf = <&sys_grf>; 175 reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; 176 pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; 177 rockchip,camera-module-index = <1>; 178 rockchip,camera-module-facing = "back"; 179 rockchip,camera-module-name = "HZGA06"; 180 rockchip,camera-module-lens-name = "ZE0082C1"; 181 eeprom-ctrl = <&otp_eeprom_b>; 182 lens-focus = <&aw8601b>; 183 port { 184 ov50c40_out1: endpoint { 185 remote-endpoint = <&mipi_in_dcphy1>; 186 data-lanes = <1 2 3 4>; 187 }; 188 }; 189 }; 190 191 otp_eeprom_b: otp_eeprom_b@50 { 192 compatible = "rk,otp_eeprom"; 193 status = "okay"; 194 reg = <0x50>; 195 }; 196}; 197 198&mipi_dcphy0 { 199 status = "okay"; 200}; 201 202&mipi_dcphy1 { 203 status = "okay"; 204}; 205 206&mipi0_csi2 { 207 status = "okay"; 208 209 ports { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 213 port@0 { 214 reg = <0>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 218 mipi0_csi2_input: endpoint@1 { 219 reg = <1>; 220 remote-endpoint = <&csidcphy0_out>; 221 }; 222 }; 223 224 port@1 { 225 reg = <1>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 229 mipi0_csi2_output: endpoint@0 { 230 reg = <0>; 231 remote-endpoint = <&cif_mipi_in0>; 232 }; 233 }; 234 }; 235}; 236 237&mipi1_csi2 { 238 status = "okay"; 239 240 ports { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 244 port@0 { 245 reg = <0>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 249 mipi1_csi2_input: endpoint@1 { 250 reg = <1>; 251 remote-endpoint = <&csidcphy1_out>; 252 }; 253 }; 254 255 port@1 { 256 reg = <1>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 260 mipi1_csi2_output: endpoint@0 { 261 reg = <0>; 262 remote-endpoint = <&cif_mipi_in1>; 263 }; 264 }; 265 }; 266}; 267 268&rkcif { 269 status = "okay"; 270}; 271 272&rkcif_mipi_lvds { 273 status = "okay"; 274 275 port { 276 cif_mipi_in0: endpoint { 277 remote-endpoint = <&mipi0_csi2_output>; 278 }; 279 }; 280}; 281 282&rkcif_mipi_lvds_sditf { 283 status = "okay"; 284 285 port { 286 mipi_lvds_sditf: endpoint { 287 remote-endpoint = <&isp1_in1>; 288 }; 289 }; 290}; 291 292&rkcif_mipi_lvds1 { 293 status = "okay"; 294 295 port { 296 cif_mipi_in1: endpoint { 297 remote-endpoint = <&mipi1_csi2_output>; 298 }; 299 }; 300}; 301 302&rkcif_mipi_lvds1_sditf { 303 status = "okay"; 304 305 port { 306 mipi1_lvds_sditf: endpoint { 307 remote-endpoint = <&isp1_in2>; 308 }; 309 }; 310}; 311 312&rkcif_mmu { 313 status = "okay"; 314}; 315 316&rkisp_unite { 317 status = "okay"; 318 319}; 320 321&rkisp_unite_mmu { 322 status = "okay"; 323}; 324 325&rkisp0_vir0 { 326 status = "okay"; 327 /* 328 * dual isp process image case 329 * other rkisp hw and virtual nodes should disabled 330 */ 331 rockchip,hw = <&rkisp_unite>; 332 port { 333 #address-cells = <1>; 334 #size-cells = <0>; 335 336 isp1_in1: endpoint@0 { 337 reg = <0>; 338 remote-endpoint = <&mipi_lvds_sditf>; 339 }; 340 isp1_in2: endpoint@1 { 341 reg = <1>; 342 remote-endpoint = <&mipi1_lvds_sditf>; 343 }; 344 }; 345}; 346