1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 lt7911d { 9 compatible = "lontium,lt7911d-fb-notifier"; 10 reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, 11 <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>, 12 <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>, 13 <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; 14 }; 15 16 dsi2lvds_backlight1: dsi2lvds_backlight1 { 17 compatible = "pwm-backlight"; 18 brightness-levels = < 19 0 20 20 21 21 22 22 23 20 23 24 24 25 25 26 26 27 21 27 28 28 29 29 30 30 31 22 31 32 32 33 33 34 34 35 23 35 36 36 37 37 38 38 39 24 40 41 42 43 44 45 46 47 25 48 49 50 51 52 53 54 55 26 56 57 58 59 60 61 62 63 27 64 65 66 67 68 69 70 71 28 72 73 74 75 76 77 78 79 29 80 81 82 83 84 85 86 87 30 88 89 90 91 92 93 94 95 31 96 97 98 99 100 101 102 103 32 104 105 106 107 108 109 110 111 33 112 113 114 115 116 117 118 119 34 120 121 122 123 124 125 126 127 35 128 129 130 131 132 133 134 135 36 136 137 138 139 140 141 142 143 37 144 145 146 147 148 149 150 151 38 152 153 154 155 156 157 158 159 39 160 161 162 163 164 165 166 167 40 168 169 170 171 172 173 174 175 41 176 177 178 179 180 181 182 183 42 184 185 186 187 188 189 190 191 43 192 193 194 195 196 197 198 199 44 200 201 202 203 204 205 206 207 45 208 209 210 211 212 213 214 215 46 216 217 218 219 220 221 222 223 47 224 225 226 227 228 229 230 231 48 232 233 234 235 236 237 238 239 49 240 241 242 243 244 245 246 247 50 248 249 250 251 252 253 254 255 51 >; 52 default-brightness-level = <200>; 53 }; 54 55 dp2lvds_backlight0: dp2lvds_backlight0 { 56 compatible = "pwm-backlight"; 57 brightness-levels = < 58 0 20 20 21 21 22 22 23 59 23 24 24 25 25 26 26 27 60 27 28 28 29 29 30 30 31 61 31 32 32 33 33 34 34 35 62 35 36 36 37 37 38 38 39 63 40 41 42 43 44 45 46 47 64 48 49 50 51 52 53 54 55 65 56 57 58 59 60 61 62 63 66 64 65 66 67 68 69 70 71 67 72 73 74 75 76 77 78 79 68 80 81 82 83 84 85 86 87 69 88 89 90 91 92 93 94 95 70 96 97 98 99 100 101 102 103 71 104 105 106 107 108 109 110 111 72 112 113 114 115 116 117 118 119 73 120 121 122 123 124 125 126 127 74 128 129 130 131 132 133 134 135 75 136 137 138 139 140 141 142 143 76 144 145 146 147 148 149 150 151 77 152 153 154 155 156 157 158 159 78 160 161 162 163 164 165 166 167 79 168 169 170 171 172 173 174 175 80 176 177 178 179 180 181 182 183 81 184 185 186 187 188 189 190 191 82 192 193 194 195 196 197 198 199 83 200 201 202 203 204 205 206 207 84 208 209 210 211 212 213 214 215 85 216 217 218 219 220 221 222 223 86 224 225 226 227 228 229 230 231 87 232 233 234 235 236 237 238 239 88 240 241 242 243 244 245 246 247 89 248 249 250 251 252 253 254 255 90 >; 91 default-brightness-level = <200>; 92 }; 93 94 dp2lvds_backlight1: dp2lvds_backlight1 { 95 compatible = "pwm-backlight"; 96 brightness-levels = < 97 0 20 20 21 21 22 22 23 98 23 24 24 25 25 26 26 27 99 27 28 28 29 29 30 30 31 100 31 32 32 33 33 34 34 35 101 35 36 36 37 37 38 38 39 102 40 41 42 43 44 45 46 47 103 48 49 50 51 52 53 54 55 104 56 57 58 59 60 61 62 63 105 64 65 66 67 68 69 70 71 106 72 73 74 75 76 77 78 79 107 80 81 82 83 84 85 86 87 108 88 89 90 91 92 93 94 95 109 96 97 98 99 100 101 102 103 110 104 105 106 107 108 109 110 111 111 112 113 114 115 116 117 118 119 112 120 121 122 123 124 125 126 127 113 128 129 130 131 132 133 134 135 114 136 137 138 139 140 141 142 143 115 144 145 146 147 148 149 150 151 116 152 153 154 155 156 157 158 159 117 160 161 162 163 164 165 166 167 118 168 169 170 171 172 173 174 175 119 176 177 178 179 180 181 182 183 120 184 185 186 187 188 189 190 191 121 192 193 194 195 196 197 198 199 122 200 201 202 203 204 205 206 207 123 208 209 210 211 212 213 214 215 124 216 217 218 219 220 221 222 223 125 224 225 226 227 228 229 230 231 126 232 233 234 235 236 237 238 239 127 240 241 242 243 244 245 246 247 128 248 249 250 251 252 253 254 255 129 >; 130 default-brightness-level = <200>; 131 }; 132 133 edp2lvds_backlight0: edp2lvds_backlight0 { 134 compatible = "pwm-backlight"; 135 brightness-levels = < 136 0 20 20 21 21 22 22 23 137 23 24 24 25 25 26 26 27 138 27 28 28 29 29 30 30 31 139 31 32 32 33 33 34 34 35 140 35 36 36 37 37 38 38 39 141 40 41 42 43 44 45 46 47 142 48 49 50 51 52 53 54 55 143 56 57 58 59 60 61 62 63 144 64 65 66 67 68 69 70 71 145 72 73 74 75 76 77 78 79 146 80 81 82 83 84 85 86 87 147 88 89 90 91 92 93 94 95 148 96 97 98 99 100 101 102 103 149 104 105 106 107 108 109 110 111 150 112 113 114 115 116 117 118 119 151 120 121 122 123 124 125 126 127 152 128 129 130 131 132 133 134 135 153 136 137 138 139 140 141 142 143 154 144 145 146 147 148 149 150 151 155 152 153 154 155 156 157 158 159 156 160 161 162 163 164 165 166 167 157 168 169 170 171 172 173 174 175 158 176 177 178 179 180 181 182 183 159 184 185 186 187 188 189 190 191 160 192 193 194 195 196 197 198 199 161 200 201 202 203 204 205 206 207 162 208 209 210 211 212 213 214 215 163 216 217 218 219 220 221 222 223 164 224 225 226 227 228 229 230 231 165 232 233 234 235 236 237 238 239 166 240 241 242 243 244 245 246 247 167 248 249 250 251 252 253 254 255 168 >; 169 default-brightness-level = <200>; 170 }; 171 172 edp2lvds_backlight1: edp2lvds_backlight1 { 173 compatible = "pwm-backlight"; 174 brightness-levels = < 175 0 20 20 21 21 22 22 23 176 23 24 24 25 25 26 26 27 177 27 28 28 29 29 30 30 31 178 31 32 32 33 33 34 34 35 179 35 36 36 37 37 38 38 39 180 40 41 42 43 44 45 46 47 181 48 49 50 51 52 53 54 55 182 56 57 58 59 60 61 62 63 183 64 65 66 67 68 69 70 71 184 72 73 74 75 76 77 78 79 185 80 81 82 83 84 85 86 87 186 88 89 90 91 92 93 94 95 187 96 97 98 99 100 101 102 103 188 104 105 106 107 108 109 110 111 189 112 113 114 115 116 117 118 119 190 120 121 122 123 124 125 126 127 191 128 129 130 131 132 133 134 135 192 136 137 138 139 140 141 142 143 193 144 145 146 147 148 149 150 151 194 152 153 154 155 156 157 158 159 195 160 161 162 163 164 165 166 167 196 168 169 170 171 172 173 174 175 197 176 177 178 179 180 181 182 183 198 184 185 186 187 188 189 190 191 199 192 193 194 195 196 197 198 199 200 200 201 202 203 204 205 206 207 201 208 209 210 211 212 213 214 215 202 216 217 218 219 220 221 222 223 203 224 225 226 227 228 229 230 231 204 232 233 234 235 236 237 238 239 205 240 241 242 243 244 245 246 247 206 248 249 250 251 252 253 254 255 207 >; 208 default-brightness-level = <200>; 209 }; 210 211 dsi2lvds_panel0 { 212 compatible = "simple-panel"; 213 backlight = <&backlight>; 214 215 display-timings { 216 native-mode = <&dsi2lvds0>; 217 dsi2lvds0: timing0 { 218 clock-frequency = <88208000>; 219 hactive = <1920>; 220 vactive = <720>; 221 hfront-porch = <32>; 222 hsync-len = <10>; 223 hback-porch = <22>; 224 vfront-porch = <10>; 225 vsync-len = <4>; 226 vback-porch = <7>; 227 hsync-active = <0>; 228 vsync-active = <0>; 229 de-active = <0>; 230 pixelclk-active = <0>; 231 }; 232 }; 233 234 ports { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 238 port@0 { 239 reg = <0>; 240 panel0_in_i2c2_bu18rl82: endpoint { 241 remote-endpoint = <&i2c2_bu18rl82_out_panel0>; 242 }; 243 }; 244 }; 245 }; 246 247 dsi2lvds_panel1 { 248 compatible = "simple-panel"; 249 backlight = <&dsi2lvds_backlight1>; 250 251 display-timings { 252 native-mode = <&dsi2lvds1>; 253 dsi2lvds1: timing0 { 254 clock-frequency = <88208000>; 255 hactive = <1920>; 256 vactive = <720>; 257 hfront-porch = <32>; 258 hsync-len = <10>; 259 hback-porch = <22>; 260 vfront-porch = <10>; 261 vsync-len = <4>; 262 vback-porch = <7>; 263 hsync-active = <0>; 264 vsync-active = <0>; 265 de-active = <0>; 266 pixelclk-active = <0>; 267 }; 268 }; 269 270 ports { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 274 port@0 { 275 reg = <0>; 276 panel1_in_i2c6_bu18rl82: endpoint { 277 remote-endpoint = <&i2c6_bu18rl82_out_panel1>; 278 }; 279 }; 280 }; 281 }; 282 283 dp2lvds_panel0 { 284 compatible = "simple-panel"; 285 backlight = <&dp2lvds_backlight0>; 286 status = "okay"; 287 288 panel-timing { 289 clock-frequency = <148500000>; 290 hactive = <1920>; 291 vactive = <1080>; 292 hfront-porch = <140>; 293 hsync-len = <40>; 294 hback-porch = <100>; 295 vfront-porch = <15>; 296 vsync-len = <20>; 297 vback-porch = <10>; 298 hsync-active = <0>; 299 vsync-active = <0>; 300 de-active = <0>; 301 pixelclk-active = <0>; 302 }; 303 304 port { 305 panel0_in_i2c4_bu18rl82: endpoint { 306 remote-endpoint = <&i2c4_bu18rl82_out_panel0>; 307 }; 308 }; 309 }; 310 311 dp2lvds_panel1 { 312 compatible = "simple-panel"; 313 backlight = <&dp2lvds_backlight1>; 314 status = "okay"; 315 316 panel-timing { 317 clock-frequency = <148500000>; 318 hactive = <1920>; 319 vactive = <1080>; 320 hfront-porch = <140>; 321 hsync-len = <40>; 322 hback-porch = <100>; 323 vfront-porch = <15>; 324 vsync-len = <20>; 325 vback-porch = <10>; 326 hsync-active = <0>; 327 vsync-active = <0>; 328 de-active = <0>; 329 pixelclk-active = <0>; 330 }; 331 332 port { 333 panel1_in_i2c8_bu18rl82: endpoint { 334 remote-endpoint = <&i2c8_bu18rl82_out_panel1>; 335 }; 336 }; 337 }; 338 339 edp2lvds_panel0 { 340 compatible = "simple-panel"; 341 backlight = <&edp2lvds_backlight0>; 342 status = "okay"; 343 344 panel-timing { 345 clock-frequency = <148500000>; 346 hactive = <1920>; 347 vactive = <1080>; 348 hfront-porch = <140>; 349 hsync-len = <40>; 350 hback-porch = <100>; 351 vfront-porch = <15>; 352 vsync-len = <20>; 353 vback-porch = <10>; 354 hsync-active = <0>; 355 vsync-active = <0>; 356 de-active = <0>; 357 pixelclk-active = <0>; 358 }; 359 360 port { 361 panel0_in_i2c5_bu18rl82: endpoint { 362 remote-endpoint = <&i2c5_bu18rl82_out_panel0>; 363 }; 364 }; 365 }; 366 367 edp2lvds_panel1 { 368 compatible = "simple-panel"; 369 backlight = <&edp2lvds_backlight1>; 370 status = "okay"; 371 372 panel-timing { 373 clock-frequency = <148500000>; 374 hactive = <1920>; 375 vactive = <1080>; 376 hfront-porch = <140>; 377 hsync-len = <40>; 378 hback-porch = <100>; 379 vfront-porch = <15>; 380 vsync-len = <20>; 381 vback-porch = <10>; 382 hsync-active = <0>; 383 vsync-active = <0>; 384 de-active = <0>; 385 pixelclk-active = <0>; 386 }; 387 388 port { 389 panel1_in_i2c7_bu18rl82: endpoint { 390 remote-endpoint = <&i2c7_bu18rl82_out_panel1>; 391 }; 392 }; 393 }; 394}; 395 396&backlight { 397 pwms = <&pwm0 0 25000 0>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&bl0_enable_pin>; 400 enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; 401 status = "okay"; 402}; 403 404&dsi2lvds_backlight1 { 405 pwms = <&pwm13 0 25000 0>; 406 pinctrl-names = "default"; 407 pinctrl-0 = <&bl1_enable_pin>; 408 enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; 409 status = "okay"; 410}; 411 412&dp0 { 413 split-mode; 414 force-hpd; 415 status = "okay"; 416 417 ports { 418 port@1 { 419 reg = <1>; 420 421 dp0_out_i2c4_bu18tl82: endpoint { 422 remote-endpoint = <&i2c4_bu18tl82_in_dp0>; 423 }; 424 }; 425 }; 426}; 427 428&dp0_in_vp0 { 429 status = "okay"; 430}; 431 432&dp0_in_vp1 { 433 status = "disabled"; 434}; 435 436&dp0_in_vp2 { 437 status = "disabled"; 438}; 439 440&dp1 { 441 force-hpd; 442 status = "okay"; 443 444 ports { 445 port@1 { 446 reg = <1>; 447 448 dp1_out_i2c8_bu18tl82: endpoint { 449 remote-endpoint = <&i2c8_bu18tl82_in_dp1>; 450 }; 451 }; 452 }; 453}; 454 455&dp1_in_vp0 { 456 status = "okay"; 457}; 458 459&dp1_in_vp1 { 460 status = "disabled"; 461}; 462 463&dp1_in_vp2 { 464 status = "disabled"; 465}; 466 467&dp2lvds_backlight0 { 468 pwms = <&pwm10 0 25000 0>; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&bl2_enable_pin>; 471 enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; 472 status = "okay"; 473}; 474 475&dp2lvds_backlight1 { 476 pwms = <&pwm14 0 25000 0>; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&bl3_enable_pin>; 479 enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; 480 status = "okay"; 481}; 482 483/* 484 * mipi_dcphy0 needs to be enabled 485 * when dsi0 is enabled 486 */ 487&dsi0 { 488 status = "okay"; 489 490 ports { 491 #address-cells = <1>; 492 #size-cells = <0>; 493 494 port@1 { 495 reg = <1>; 496 497 dsi0_out_i2c2_bu18tl82: endpoint { 498 remote-endpoint = <&i2c2_bu18tl82_in_dsi0>; 499 }; 500 }; 501 }; 502}; 503 504&dsi0_in_vp2 { 505 status = "okay"; 506}; 507 508&dsi0_in_vp3 { 509 status = "disabled"; 510}; 511 512/* 513 * mipi_dcphy1 needs to be enabled 514 * when dsi1 is enabled 515 */ 516&dsi1 { 517 status = "okay"; 518 519 ports { 520 #address-cells = <1>; 521 #size-cells = <0>; 522 523 port@1 { 524 reg = <1>; 525 526 dsi1_out_i2c6_bu18tl82: endpoint { 527 remote-endpoint = <&i2c6_bu18tl82_in_dsi1>; 528 }; 529 }; 530 }; 531}; 532 533&dsi1_in_vp2 { 534 status = "disabled"; 535}; 536 537&dsi1_in_vp3 { 538 status = "okay"; 539}; 540 541&edp0 { 542 split-mode; 543 force-hpd; 544 status = "okay"; 545 546 ports { 547 port@1 { 548 reg = <1>; 549 550 edp0_out_i2c5_bu18tl82: endpoint { 551 remote-endpoint = <&i2c5_bu18tl82_in_edp0>; 552 }; 553 }; 554 }; 555}; 556 557&edp0_in_vp0 { 558 status = "disabled"; 559}; 560 561&edp0_in_vp1 { 562 status = "okay"; 563}; 564 565&edp0_in_vp2 { 566 status = "disabled"; 567}; 568 569&edp1 { 570 force-hpd; 571 status = "okay"; 572 573 ports { 574 port@1 { 575 reg = <1>; 576 577 edp1_out_i2c7_bu18tl82: endpoint { 578 remote-endpoint = <&i2c7_bu18tl82_in_edp1>; 579 }; 580 }; 581 }; 582}; 583 584&edp1_in_vp0 { 585 status = "disabled"; 586}; 587 588&edp1_in_vp1 { 589 status = "okay"; 590}; 591 592&edp1_in_vp2 { 593 status = "disabled"; 594}; 595 596&edp2lvds_backlight0 { 597 pwms = <&pwm7 0 25000 0>; 598 pinctrl-names = "default"; 599 pinctrl-0 = <&bl4_enable_pin>; 600 enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; 601 status = "okay"; 602}; 603 604&edp2lvds_backlight1 { 605 pwms = <&pwm11 0 25000 0>; 606 pinctrl-names = "default"; 607 pinctrl-0 = <&bl5_enable_pin>; 608 enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; 609 status = "okay"; 610}; 611 612&hdmi0 { 613 status = "disabled"; 614}; 615 616&hdmi1 { 617 status = "disabled"; 618}; 619 620&hdptxphy0 { 621 status = "okay"; 622}; 623 624&hdptxphy1 { 625 status = "okay"; 626}; 627 628&hdptxphy_hdmi0 { 629 status = "disabled"; 630}; 631 632&hdptxphy_hdmi1 { 633 status = "disabled"; 634}; 635 636&i2c2 { 637 status = "okay"; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&i2c2m4_xfer>; 640 clock-frequency = <400000>; 641 642 bu18tl82: bu18tl82@10 { 643 compatible = "rohm,bu18tl82"; 644 reg = <0x10>; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&ser0_rst_pin>; 647 reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; 648 sel-mipi; 649 status = "okay"; 650 651 serdes-init-sequence = [ 652 0021 0008 653 0022 0008 654 0023 0009 655 0024 000a 656 0013 0010 657 0014 0010 658 002a 0018 659 002d 0018 660 0030 0018 661 0033 0018 662 02a7 0002 663 02a8 0003 664 02a9 0004 665 02aa 0005 666 0045 0080 667 0046 0007 668 0047 0080 669 0048 0007 670 004b 00d0 671 004c 0002 672 004d 00d0 673 004e 0002 674 0051 0080 675 0052 0007 676 0053 0000 677 0054 00c0 678 022b 0076 679 022c 0062 680 022d 0037 681 024d 0061 682 0252 0005 683 0253 0000 684 0258 0000 685 025c 0000 686 025f 0000 687 0274 0030 688 0275 0020 689 032b 002f 690 032c 00a1 691 032d 001d 692 034d 0060 693 0353 0000 694 0358 0000 695 035c 0000 696 035f 0000 697 0018 00a5 698 0019 0069 699 0267 003d 700 0268 002c 701 0269 002c 702 026a 002c 703 026b 002c 704 0367 003d 705 0368 002c 706 0369 002c 707 036a 002c 708 036b 002c 709 0013 0019 710 0014 0001 711 022e 0080 712 0296 0004 713 0297 000d 714 032e 0080 715 038e 0000 716 0396 0004 717 0397 000a 718 0060 0001 719 0061 0001 720 0018 0000 721 0019 0000 722 /* TL82 Pattern Gen Set 1 723 * Horizontal Gray Scale 256 steps 724 */ 725 040A 0010 726 040B 0080 727 040C 0080 728 040D 0080 729 0444 0019 730 0445 0020 731 0446 001f 732 ]; 733 734 ports { 735 #address-cells = <1>; 736 #size-cells = <0>; 737 738 port@0 { 739 reg = <0>; 740 741 i2c2_bu18tl82_in_dsi0: endpoint { 742 remote-endpoint = <&dsi0_out_i2c2_bu18tl82>; 743 }; 744 }; 745 746 port@1 { 747 reg = <1>; 748 749 i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint { 750 remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>; 751 }; 752 }; 753 }; 754 }; 755 756 bu18rl82: bu18rl82@30 { 757 compatible = "rohm,bu18rl82"; 758 reg = <0x30>; 759 status = "okay"; 760 serdes-init-sequence = [ 761 0011 000b 762 0012 0002 763 0013 0001 764 001d 0008 765 001f 0006 766 0020 0006 767 0057 0000 768 0058 0002 769 005a 0000 770 005b 0003 771 005d 0000 772 005e 0001 773 0060 0000 774 0061 0005 775 0073 0080 776 0074 0007 777 0075 0080 778 0076 0007 779 0079 0009 780 007b 00d0 781 007c 0002 782 007d 00d0 783 007e 0002 784 0081 0003 785 0082 000a 786 0084 001e 787 0086 0001 788 0087 0003 789 0088 0005 790 0089 0014 791 008b 0028 792 008d 0002 793 008e 0004 794 008f 000f 795 0090 0001 796 0091 0003 797 0423 00ab 798 0424 00aa 799 0425 001a 800 0429 000a 801 045d 0001 802 0523 0097 803 0524 00d0 804 0525 000e 805 0529 000a 806 055d 0001 807 0426 0080 808 0526 0080 809 /* RL82 Pattern Gen Set 810 * Vertical Gray Scale Color Bar 811 */ 812 060A 00B0 813 060B 00FF 814 060C 00FF 815 060D 00FF 816 0644 0019 817 0645 0020 818 0646 001f 819 ]; 820 821 ports { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 825 port@0 { 826 reg = <0>; 827 828 i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint { 829 remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>; 830 }; 831 }; 832 833 port@1 { 834 reg = <1>; 835 836 i2c2_bu18rl82_out_panel0: endpoint { 837 remote-endpoint = <&panel0_in_i2c2_bu18rl82>; 838 }; 839 }; 840 }; 841 }; 842}; 843 844&i2c4 { 845 pinctrl-names = "default"; 846 pinctrl-0 = <&i2c4m2_xfer>; 847 clock-frequency = <400000>; 848 status = "okay"; 849 850 bu18tl82@10 { 851 compatible = "rohm,bu18tl82"; 852 reg = <0x10>; 853 status = "okay"; 854 855 serdes-init-sequence = [ 856 0013 001a 857 0014 000a 858 0021 0008 859 0023 0009 860 0024 0009 861 002a 0018 862 002d 0018 863 0030 0018 864 0033 0018 865 0045 0080 866 0046 0007 867 004b 0038 868 004c 0004 869 0053 0064 870 022b 0062 871 022c 0027 872 022d 002e 873 0274 0030 874 0275 0020 875 0296 0004 876 0297 000d 877 02b2 00c8 878 02b4 0001 879 02b8 00ff 880 02b9 000f 881 02ba 00ff 882 02bb 000f 883 02be 00ff 884 02bf 001f 885 02c2 00ff 886 02c3 001f 887 0396 0004 888 0397 000d 889 03b2 00c8 890 03b4 0001 891 03b8 00ff 892 03b9 000f 893 03ba 00ff 894 03bb 000f 895 03be 00ff 896 03bf 001f 897 03c2 00ff 898 03c3 001f 899 0060 0001 900 0061 0003 901 022e 0080 902 032e 0080 903 /* TL82 Pattern Gen Set 1 904 * Horizontal Gray Scale 256 steps 905 */ 906 040A 0010 907 040B 0080 908 040C 0080 909 040D 0080 910 0444 0019 911 0445 0020 912 0446 001f 913 ]; 914 915 ports { 916 #address-cells = <1>; 917 #size-cells = <0>; 918 919 port@0 { 920 reg = <0>; 921 922 i2c4_bu18tl82_in_dp0: endpoint { 923 remote-endpoint = <&dp0_out_i2c4_bu18tl82>; 924 }; 925 }; 926 927 port@1 { 928 reg = <1>; 929 930 i2c4_bu18tl82_out_i2c4_bu18rl82: endpoint { 931 remote-endpoint = <&i2c4_bu18rl82_in_i2c4_bu18tl82>; 932 }; 933 }; 934 }; 935 }; 936 937 bu18rl82@30 { 938 compatible = "rohm,bu18rl82"; 939 reg = <0x30>; 940 status = "okay"; 941 serdes-init-sequence = [ 942 0011 000b 943 0012 0003 944 0013 0001 945 001d 0008 946 001f 0002 947 0020 0002 948 0057 0000 949 0058 0002 950 005a 0000 951 005b 0003 952 005d 0000 953 005e 0004 954 0060 0000 955 0061 0005 956 0073 0080 957 0074 0007 958 0079 000a 959 007b 0038 960 007c 0004 961 0081 0003 962 0082 0010 963 0084 0020 964 0086 0002 965 0087 0002 966 0088 0010 967 0089 0010 968 008b 0020 969 008d 0002 970 008e 0002 971 008f 0010 972 00d0 0040 973 00d8 0042 974 00d9 0004 975 0423 0002 976 0424 00ec 977 0425 0027 978 0429 000a 979 045d 0001 980 0529 000a 981 055d 0003 982 0090 0001 983 0091 0003 984 0426 0080 985 /* RL82 Pattern Gen Set 986 * Vertical Gray Scale Color Bar 987 */ 988 060A 00B0 989 060B 00FF 990 060C 00FF 991 060D 00FF 992 0644 0019 993 0645 0020 994 0646 001f 995 ]; 996 997 ports { 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 1001 port@0 { 1002 reg = <0>; 1003 1004 i2c4_bu18rl82_in_i2c4_bu18tl82: endpoint { 1005 remote-endpoint = <&i2c4_bu18tl82_out_i2c4_bu18rl82>; 1006 }; 1007 }; 1008 1009 port@1 { 1010 reg = <1>; 1011 1012 i2c4_bu18rl82_out_panel0: endpoint { 1013 remote-endpoint = <&panel0_in_i2c4_bu18rl82>; 1014 }; 1015 }; 1016 }; 1017 }; 1018}; 1019 1020&i2c5 { 1021 clock-frequency = <400000>; 1022 status = "okay"; 1023 1024 bu18tl82@10 { 1025 compatible = "rohm,bu18tl82"; 1026 reg = <0x10>; 1027 status = "okay"; 1028 1029 serdes-init-sequence = [ 1030 0013 001a 1031 0014 000a 1032 0021 0008 1033 0023 0009 1034 0024 0009 1035 002a 0018 1036 002e 0004 1037 002d 0018 1038 0030 0000 1039 0033 0018 1040 027c 0041 1041 027d 0041 1042 0045 0080 1043 0046 0007 1044 004b 0038 1045 004c 0004 1046 0053 0064 1047 022b 0062 1048 022c 0027 1049 022d 002e 1050 0274 0030 1051 0275 0020 1052 0296 0004 1053 0297 000d 1054 02b2 00c8 1055 02b4 0001 1056 02b8 00ff 1057 02b9 000f 1058 02ba 00ff 1059 02bb 000f 1060 02be 00ff 1061 02bf 001f 1062 02c2 00ff 1063 02c3 001f 1064 0396 0004 1065 0397 000d 1066 03b2 00c8 1067 03b4 0001 1068 03b8 00ff 1069 03b9 000f 1070 03ba 00ff 1071 03bb 000f 1072 03be 00ff 1073 03bf 001f 1074 03c2 00ff 1075 03c3 001f 1076 0060 0001 1077 0061 0003 1078 022e 0080 1079 032e 0080 1080 /* TL82 Pattern Gen Set 1 1081 * Horizontal Gray Scale 256 steps 1082 */ 1083 040A 0010 1084 040B 0080 1085 040C 0080 1086 040D 0080 1087 0444 0019 1088 0445 0020 1089 0446 001f 1090 ]; 1091 1092 ports { 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 1096 port@0 { 1097 reg = <0>; 1098 1099 i2c5_bu18tl82_in_edp0: endpoint { 1100 remote-endpoint = <&edp0_out_i2c5_bu18tl82>; 1101 }; 1102 }; 1103 1104 port@1 { 1105 reg = <1>; 1106 1107 i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint { 1108 remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>; 1109 }; 1110 }; 1111 }; 1112 }; 1113 1114 bu18rl82@30 { 1115 compatible = "rohm,bu18rl82"; 1116 reg = <0x30>; 1117 status = "okay"; 1118 serdes-init-sequence = [ 1119 0011 000b 1120 0012 0003 1121 0013 0001 1122 001d 0008 1123 001f 0002 1124 0020 0002 1125 0031 0041 1126 0032 0041 1127 0057 0000 1128 0058 0002 1129 005a 0000 1130 005b 0003 1131 005d 0008 1132 005e 0004 1133 0060 0000 1134 0061 0005 1135 0073 0080 1136 0074 0007 1137 0079 000a 1138 007b 0038 1139 007c 0004 1140 0081 0003 1141 0082 0010 1142 0084 0020 1143 0086 0002 1144 0087 0002 1145 0088 0010 1146 0089 0010 1147 008b 0020 1148 008d 0002 1149 008e 0002 1150 008f 0010 1151 00d0 0040 1152 00d8 0042 1153 00d9 0004 1154 0423 0002 1155 0424 00ec 1156 0425 0027 1157 0429 000a 1158 045d 0001 1159 0529 000a 1160 055d 0003 1161 0090 0001 1162 0091 0003 1163 0426 0080 1164 042d 0004 1165 /* RL82 Pattern Gen Set 1166 * Vertical Gray Scale Color Bar 1167 */ 1168 060A 00B0 1169 060B 00FF 1170 060C 00FF 1171 060D 00FF 1172 0644 0019 1173 0645 0020 1174 0646 001f 1175 ]; 1176 1177 ports { 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 1181 port@0 { 1182 reg = <0>; 1183 1184 i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint { 1185 remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>; 1186 }; 1187 }; 1188 1189 port@1 { 1190 reg = <1>; 1191 1192 i2c5_bu18rl82_out_panel0: endpoint { 1193 remote-endpoint = <&panel0_in_i2c5_bu18rl82>; 1194 }; 1195 }; 1196 }; 1197 }; 1198 1199 ilitek@41 { 1200 compatible = "ilitek,ili251x"; 1201 reg = <0x41>; 1202 interrupt-parent = <&gpio0>; 1203 interrupts = <RK_PD1 IRQ_TYPE_LEVEL_LOW>; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&touch_pin>; 1206 reset-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; 1207 ilitek,name = "ilitek_i2c"; 1208 }; 1209}; 1210 1211&i2c6 { 1212 status = "okay"; 1213 pinctrl-names = "default"; 1214 pinctrl-0 = <&i2c6m3_xfer>; 1215 clock-frequency = <400000>; 1216 1217 bu18tl82@10 { 1218 compatible = "rohm,bu18tl82"; 1219 reg = <0x10>; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&ser1_rst_pin>; 1222 reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; 1223 sel-mipi; 1224 status = "okay"; 1225 serdes-init-sequence = [ 1226 0021 0008 1227 0022 0008 1228 0023 0009 1229 0024 000a 1230 0013 0010 1231 0014 0010 1232 002a 0018 1233 002d 0018 1234 0030 0018 1235 0033 0018 1236 027c 0070 1237 027d 0070 1238 02a7 0002 1239 02a8 0003 1240 02a9 0004 1241 02aa 0005 1242 0045 0080 1243 0046 0007 1244 0047 0080 1245 0048 0007 1246 004b 00d0 1247 004c 0002 1248 004d 00d0 1249 004e 0002 1250 0051 0080 1251 0052 0007 1252 0053 0000 1253 0054 00c0 1254 022b 0076 1255 022c 0062 1256 022d 0037 1257 024d 0061 1258 0252 0005 1259 0253 0000 1260 0258 0000 1261 025c 0000 1262 025f 0000 1263 0274 0030 1264 0275 0020 1265 032b 002f 1266 032c 00a1 1267 032d 001d 1268 034d 0060 1269 0353 0000 1270 0358 0000 1271 035c 0000 1272 035f 0000 1273 0018 00a5 1274 0019 0069 1275 0267 003d 1276 0268 002c 1277 0269 002c 1278 026a 002c 1279 026b 002c 1280 0367 003d 1281 0368 002c 1282 0369 002c 1283 036a 002c 1284 036b 002c 1285 0013 0019 1286 0014 0001 1287 022e 0080 1288 0296 0004 1289 0297 000d 1290 032e 0080 1291 038e 0000 1292 0396 0004 1293 0397 000a 1294 0060 0001 1295 0061 0001 1296 0018 0000 1297 0019 0000 1298 /* TL82 Pattern Gen Set 1 1299 * Horizontal Gray Scale 256 steps 1300 */ 1301 040A 0010 1302 040B 0080 1303 040C 0080 1304 040D 0080 1305 0444 0019 1306 0445 0020 1307 0446 001f 1308 ]; 1309 1310 ports { 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 1314 port@0 { 1315 reg = <0>; 1316 1317 i2c6_bu18tl82_in_dsi1: endpoint { 1318 remote-endpoint = <&dsi1_out_i2c6_bu18tl82>; 1319 }; 1320 }; 1321 1322 port@1 { 1323 reg = <1>; 1324 1325 i2c6_bu18tl82_out_i2c6_bu18rl82: endpoint { 1326 remote-endpoint = <&i2c6_bu18rl82_in_i2c6_bu18tl82>; 1327 }; 1328 }; 1329 }; 1330 }; 1331 1332 bu18rl82@30 { 1333 compatible = "rohm,bu18rl82"; 1334 reg = <0x30>; 1335 status = "okay"; 1336 serdes-init-sequence = [ 1337 0011 000b 1338 0012 0002 1339 0013 0001 1340 001d 0008 1341 001f 0006 1342 0020 0006 1343 0031 0070 1344 0032 0038 1345 0057 0000 1346 0058 0002 1347 005a 0000 1348 005b 0003 1349 005d 0000 1350 005e 0001 1351 0060 0000 1352 0061 0005 1353 0073 0080 1354 0074 0007 1355 0075 0080 1356 0076 0007 1357 0079 0009 1358 007b 00d0 1359 007c 0002 1360 007d 00d0 1361 007e 0002 1362 0081 0003 1363 0082 000a 1364 0084 001e 1365 0086 0001 1366 0087 0003 1367 0088 0005 1368 0089 0014 1369 008b 0028 1370 008d 0002 1371 008e 0004 1372 008f 000f 1373 0090 0001 1374 0091 0003 1375 0423 00ab 1376 0424 00aa 1377 0425 001a 1378 0429 000a 1379 045d 0001 1380 0523 0097 1381 0524 00d0 1382 0525 000e 1383 0529 000a 1384 055d 0001 1385 0426 0080 1386 0526 0080 1387 /* RL82 Pattern Gen Set 1388 * Vertical Gray Scale Color Bar 1389 */ 1390 060A 00B0 1391 060B 00FF 1392 060C 00FF 1393 060D 00FF 1394 0644 0019 1395 0645 0020 1396 0646 001f 1397 ]; 1398 1399 ports { 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 1403 port@0 { 1404 reg = <0>; 1405 1406 i2c6_bu18rl82_in_i2c6_bu18tl82: endpoint { 1407 remote-endpoint = <&i2c6_bu18tl82_out_i2c6_bu18rl82>; 1408 }; 1409 }; 1410 1411 port@1 { 1412 reg = <1>; 1413 1414 i2c6_bu18rl82_out_panel1: endpoint { 1415 remote-endpoint = <&panel1_in_i2c6_bu18rl82>; 1416 }; 1417 }; 1418 }; 1419 }; 1420}; 1421 1422&i2c7 { 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&i2c7m3_xfer>; 1425 clock-frequency = <400000>; 1426 status = "okay"; 1427 1428 bu18tl82@10 { 1429 compatible = "rohm,bu18tl82"; 1430 reg = <0x10>; 1431 status = "okay"; 1432 1433 serdes-init-sequence = [ 1434 0013 001a 1435 0014 000a 1436 0021 0008 1437 0023 0009 1438 0024 0009 1439 002a 0018 1440 002d 0018 1441 0030 0018 1442 0033 0018 1443 0045 0080 1444 0046 0007 1445 004b 0038 1446 004c 0004 1447 0053 0064 1448 022b 0062 1449 022c 0027 1450 022d 002e 1451 0274 0030 1452 0275 0020 1453 0296 0004 1454 0297 000d 1455 02b2 00c8 1456 02b4 0001 1457 02b8 00ff 1458 02b9 000f 1459 02ba 00ff 1460 02bb 000f 1461 02be 00ff 1462 02bf 001f 1463 02c2 00ff 1464 02c3 001f 1465 0396 0004 1466 0397 000d 1467 03b2 00c8 1468 03b4 0001 1469 03b8 00ff 1470 03b9 000f 1471 03ba 00ff 1472 03bb 000f 1473 03be 00ff 1474 03bf 001f 1475 03c2 00ff 1476 03c3 001f 1477 0060 0001 1478 0061 0003 1479 022e 0080 1480 032e 0080 1481 /* TL82 Pattern Gen Set 1 1482 * Horizontal Gray Scale 256 steps 1483 */ 1484 040A 0010 1485 040B 0080 1486 040C 0080 1487 040D 0080 1488 0444 0019 1489 0445 0020 1490 0446 001f 1491 ]; 1492 1493 ports { 1494 #address-cells = <1>; 1495 #size-cells = <0>; 1496 1497 port@0 { 1498 reg = <0>; 1499 1500 i2c7_bu18tl82_in_edp1: endpoint { 1501 remote-endpoint = <&edp1_out_i2c7_bu18tl82>; 1502 }; 1503 }; 1504 1505 port@1 { 1506 reg = <1>; 1507 1508 i2c7_bu18tl82_out_i2c7_bu18rl82: endpoint { 1509 remote-endpoint = <&i2c7_bu18rl82_in_i2c7_bu18tl82>; 1510 }; 1511 }; 1512 }; 1513 }; 1514 1515 bu18rl82@30 { 1516 compatible = "rohm,bu18rl82"; 1517 reg = <0x30>; 1518 status = "okay"; 1519 serdes-init-sequence = [ 1520 0011 000b 1521 0012 0003 1522 0013 0001 1523 001d 0008 1524 001f 0002 1525 0020 0002 1526 0057 0000 1527 0058 0002 1528 005a 0000 1529 005b 0003 1530 005d 0000 1531 005e 0004 1532 0060 0000 1533 0061 0005 1534 0073 0080 1535 0074 0007 1536 0079 000a 1537 007b 0038 1538 007c 0004 1539 0081 0003 1540 0082 0010 1541 0084 0020 1542 0086 0002 1543 0087 0002 1544 0088 0010 1545 0089 0010 1546 008b 0020 1547 008d 0002 1548 008e 0002 1549 008f 0010 1550 00d0 0040 1551 00d8 0042 1552 00d9 0004 1553 0423 0002 1554 0424 00ec 1555 0425 0027 1556 0429 000a 1557 045d 0001 1558 0529 000a 1559 055d 0003 1560 0090 0001 1561 0091 0003 1562 0426 0080 1563 /* RL82 Pattern Gen Set 1564 * Vertical Gray Scale Color Bar 1565 */ 1566 060A 00B0 1567 060B 00FF 1568 060C 00FF 1569 060D 00FF 1570 0644 0019 1571 0645 0020 1572 0646 001f 1573 ]; 1574 1575 ports { 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 1579 port@0 { 1580 reg = <0>; 1581 1582 i2c7_bu18rl82_in_i2c7_bu18tl82: endpoint { 1583 remote-endpoint = <&i2c7_bu18tl82_out_i2c7_bu18rl82>; 1584 }; 1585 }; 1586 1587 port@1 { 1588 reg = <1>; 1589 1590 i2c7_bu18rl82_out_panel1: endpoint { 1591 remote-endpoint = <&panel1_in_i2c7_bu18rl82>; 1592 }; 1593 }; 1594 }; 1595 }; 1596}; 1597 1598&i2c8 { 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&i2c8m2_xfer>; 1601 clock-frequency = <400000>; 1602 status = "okay"; 1603 1604 bu18tl82@10 { 1605 compatible = "rohm,bu18tl82"; 1606 reg = <0x10>; 1607 status = "okay"; 1608 1609 serdes-init-sequence = [ 1610 0013 001a 1611 0014 000a 1612 0021 0008 1613 0023 0009 1614 0024 0009 1615 002a 0018 1616 002d 0018 1617 0030 0018 1618 0033 0018 1619 0045 0080 1620 0046 0007 1621 004b 0038 1622 004c 0004 1623 0053 0064 1624 022b 0062 1625 022c 0027 1626 022d 002e 1627 0274 0030 1628 0275 0020 1629 0296 0004 1630 0297 000d 1631 02b2 00c8 1632 02b4 0001 1633 02b8 00ff 1634 02b9 000f 1635 02ba 00ff 1636 02bb 000f 1637 02be 00ff 1638 02bf 001f 1639 02c2 00ff 1640 02c3 001f 1641 0396 0004 1642 0397 000d 1643 03b2 00c8 1644 03b4 0001 1645 03b8 00ff 1646 03b9 000f 1647 03ba 00ff 1648 03bb 000f 1649 03be 00ff 1650 03bf 001f 1651 03c2 00ff 1652 03c3 001f 1653 0060 0001 1654 0061 0003 1655 022e 0080 1656 032e 0080 1657 /* TL82 Pattern Gen Set 1 1658 * Horizontal Gray Scale 256 steps 1659 */ 1660 040A 0010 1661 040B 0080 1662 040C 0080 1663 040D 0080 1664 0444 0019 1665 0445 0020 1666 0446 001f 1667 ]; 1668 1669 ports { 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 1673 port@0 { 1674 reg = <0>; 1675 1676 i2c8_bu18tl82_in_dp1: endpoint { 1677 remote-endpoint = <&dp1_out_i2c8_bu18tl82>; 1678 }; 1679 }; 1680 1681 port@1 { 1682 reg = <1>; 1683 1684 i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint { 1685 remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>; 1686 }; 1687 }; 1688 }; 1689 }; 1690 1691 bu18rl82@30 { 1692 compatible = "rohm,bu18rl82"; 1693 reg = <0x30>; 1694 status = "okay"; 1695 serdes-init-sequence = [ 1696 0011 000b 1697 0012 0003 1698 0013 0001 1699 001d 0008 1700 001f 0002 1701 0020 0002 1702 0057 0000 1703 0058 0002 1704 005a 0000 1705 005b 0003 1706 005d 0000 1707 005e 0004 1708 0060 0000 1709 0061 0005 1710 0073 0080 1711 0074 0007 1712 0079 000a 1713 007b 0038 1714 007c 0004 1715 0081 0003 1716 0082 0010 1717 0084 0020 1718 0086 0002 1719 0087 0002 1720 0088 0010 1721 0089 0010 1722 008b 0020 1723 008d 0002 1724 008e 0002 1725 008f 0010 1726 00d0 0040 1727 00d8 0042 1728 00d9 0004 1729 0423 0002 1730 0424 00ec 1731 0425 0027 1732 0429 000a 1733 045d 0001 1734 0529 000a 1735 055d 0003 1736 0090 0001 1737 0091 0003 1738 0426 0080 1739 /* RL82 Pattern Gen Set 1740 * Vertical Gray Scale Color Bar 1741 */ 1742 060A 00B0 1743 060B 00FF 1744 060C 00FF 1745 060D 00FF 1746 0644 0019 1747 0645 0020 1748 0646 001f 1749 ]; 1750 1751 ports { 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 1755 port@0 { 1756 reg = <0>; 1757 1758 i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint { 1759 remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>; 1760 }; 1761 }; 1762 1763 port@1 { 1764 reg = <1>; 1765 1766 i2c8_bu18rl82_out_panel1: endpoint { 1767 remote-endpoint = <&panel1_in_i2c8_bu18rl82>; 1768 }; 1769 }; 1770 }; 1771 }; 1772}; 1773 1774&mipi_dcphy0 { 1775 status = "okay"; 1776}; 1777 1778&mipi_dcphy1 { 1779 status = "okay"; 1780}; 1781 1782 1783&pinctrl { 1784 1785 bl { 1786 bl0_enable_pin: bl0-enable-pin { 1787 rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; 1788 }; 1789 1790 bl1_enable_pin: bl1-enable-pin { 1791 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 1792 }; 1793 1794 bl2_enable_pin: bl2-enable-pin { 1795 rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 1796 }; 1797 1798 bl3_enable_pin: bl3-enable-pin { 1799 rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 1800 }; 1801 1802 bl4_enable_pin: bl4-enable-pin { 1803 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 1804 }; 1805 1806 bl5_enable_pin: bl5-enable-pin { 1807 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1808 }; 1809 }; 1810 1811 serdes { 1812 //dsi0 1813 ser0_rst_pin: ser0-rst-pin { 1814 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 1815 }; 1816 1817 //dsi1 1818 ser1_rst_pin: ser1-rst-pin { 1819 rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1820 }; 1821 }; 1822 1823 touch { 1824 touch_pin: touch-pin { 1825 rockchip,pins = 1826 <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, //INT 1827 <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; //RST 1828 }; 1829 }; 1830}; 1831 1832/* dsi0->serdes->lvds_panel */ 1833&pwm0 { 1834 status = "okay"; 1835 pinctrl-0 = <&pwm0m2_pins>; 1836}; 1837 1838/* dp0->serdes->lvds_panel */ 1839&pwm10 { 1840 pinctrl-0 = <&pwm10m2_pins>; 1841 status = "okay"; 1842}; 1843 1844/* edp1->serdes->lvds_panel */ 1845&pwm11 { 1846 pinctrl-0 = <&pwm11m3_pins>; 1847 status = "okay"; 1848}; 1849 1850/* edp0->serdes->lvds_panel */ 1851&pwm7 { 1852 pinctrl-0 = <&pwm7m0_pins>; 1853 status = "okay"; 1854}; 1855 1856/* dsi1->serdes->lvds_panel */ 1857&pwm13 { 1858 status = "okay"; 1859 pinctrl-0 = <&pwm13m1_pins>; 1860}; 1861 1862/* dp1->serdes->lvds_panel */ 1863&pwm14 { 1864 pinctrl-0 = <&pwm14m0_pins>; 1865 status = "okay"; 1866}; 1867 1868&route_dp0 { 1869 status = "disabled"; 1870 connect = <&vp0_out_dp0>; 1871 logo,uboot = "logo34.bmp"; 1872 logo,kernel = "logo34.bmp"; 1873}; 1874 1875&route_dp1 { 1876 status = "disabled"; 1877 connect = <&vp0_out_dp1>; 1878 logo,uboot = "logo34.bmp"; 1879 logo,kernel = "logo34.bmp"; 1880}; 1881 1882&route_dsi0 { 1883 status = "okay"; 1884 connect = <&vp2_out_dsi0>; 1885 logo,uboot = "logo1.bmp"; 1886 logo,kernel = "logo1.bmp"; 1887}; 1888 1889&route_dsi1 { 1890 status = "okay"; 1891 connect = <&vp3_out_dsi1>; 1892 logo,uboot = "logo2.bmp"; 1893 logo,kernel = "logo2.bmp"; 1894}; 1895 1896&route_edp0 { 1897 status = "disabled"; 1898 connect = <&vp1_out_edp0>; 1899 logo,uboot = "logo56.bmp"; 1900 logo,kernel = "logo56.bmp"; 1901}; 1902 1903&route_edp1 { 1904 status = "disabled"; 1905 connect = <&vp1_out_edp1>; 1906 logo,uboot = "logo56.bmp"; 1907 logo,kernel = "logo56.bmp"; 1908}; 1909 1910&usbdp_phy0 { 1911 rockchip,dp-lane-mux = <0 1 2 3>; 1912 status = "okay"; 1913}; 1914 1915&usbdp_phy1 { 1916 rockchip,dp-lane-mux = <0 1 2 3>; 1917 status = "okay"; 1918}; 1919 1920&vop { 1921 assigned-clocks = <&cru PLL_V0PLL>; 1922 assigned-clock-rates = <1152000000>; 1923}; 1924 1925&vp0 { 1926 assigned-clocks = <&cru DCLK_VOP0_SRC>; 1927 assigned-clock-parents = <&cru PLL_V0PLL>; 1928}; 1929 1930&vp1 { 1931 assigned-clocks = <&cru DCLK_VOP1_SRC>; 1932 assigned-clock-parents = <&cru PLL_GPLL>; 1933}; 1934 1935&vp2 { 1936 assigned-clocks = <&cru DCLK_VOP2_SRC>; 1937 assigned-clock-parents = <&cru PLL_V0PLL>; 1938}; 1939 1940&vp3 { 1941 assigned-clocks = <&cru DCLK_VOP3>; 1942 assigned-clock-parents = <&cru PLL_V0PLL>; 1943}; 1944
