1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h" 8*4882a593Smuzhiyun#include "rk3588.dtsi" 9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 10*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 11*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 12*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h> 13*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 14*4882a593Smuzhiyun#include <dt-bindings/display/rockchip_vop.h> 15*4882a593Smuzhiyun#include "rk3588-rk806-single.dtsi" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/ { 18*4882a593Smuzhiyun adc_keys: adc-keys { 19*4882a593Smuzhiyun compatible = "adc-keys"; 20*4882a593Smuzhiyun io-channels = <&saradc 1>; 21*4882a593Smuzhiyun io-channel-names = "buttons"; 22*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 23*4882a593Smuzhiyun poll-interval = <100>; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun vol-up-key { 26*4882a593Smuzhiyun label = "volume up"; 27*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 28*4882a593Smuzhiyun press-threshold-microvolt = <17000>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun dp0_sound: dp0-sound { 33*4882a593Smuzhiyun status = "disabled"; 34*4882a593Smuzhiyun compatible = "rockchip,hdmi"; 35*4882a593Smuzhiyun rockchip,card-name= "rockchip-dp0"; 36*4882a593Smuzhiyun rockchip,mclk-fs = <512>; 37*4882a593Smuzhiyun rockchip,cpu = <&spdif_tx2>; 38*4882a593Smuzhiyun rockchip,codec = <&dp0 1>; 39*4882a593Smuzhiyun rockchip,jack-det; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun hdmi1_sound: hdmi1-sound { 43*4882a593Smuzhiyun status = "disabled"; 44*4882a593Smuzhiyun compatible = "rockchip,hdmi"; 45*4882a593Smuzhiyun rockchip,mclk-fs = <128>; 46*4882a593Smuzhiyun rockchip,card-name = "rockchip-hdmi1"; 47*4882a593Smuzhiyun rockchip,cpu = <&i2s6_8ch>; 48*4882a593Smuzhiyun rockchip,codec = <&hdmi1>; 49*4882a593Smuzhiyun rockchip,jack-det; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun leds: leds { 53*4882a593Smuzhiyun compatible = "gpio-leds"; 54*4882a593Smuzhiyun work_led: work { 55*4882a593Smuzhiyun gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 56*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun pcie30_avdd1v8: pcie30-avdd1v8 { 61*4882a593Smuzhiyun compatible = "regulator-fixed"; 62*4882a593Smuzhiyun regulator-name = "pcie30_avdd1v8"; 63*4882a593Smuzhiyun regulator-boot-on; 64*4882a593Smuzhiyun regulator-always-on; 65*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 66*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 67*4882a593Smuzhiyun vin-supply = <&avcc_1v8_s0>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun pcie30_avdd0v75: pcie30-avdd0v75 { 71*4882a593Smuzhiyun compatible = "regulator-fixed"; 72*4882a593Smuzhiyun regulator-name = "pcie30_avdd0v75"; 73*4882a593Smuzhiyun regulator-boot-on; 74*4882a593Smuzhiyun regulator-always-on; 75*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 76*4882a593Smuzhiyun regulator-max-microvolt = <750000>; 77*4882a593Smuzhiyun vin-supply = <&avdd_0v75_s0>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun reserved-memory { 81*4882a593Smuzhiyun #address-cells = <2>; 82*4882a593Smuzhiyun #size-cells = <2>; 83*4882a593Smuzhiyun ranges; 84*4882a593Smuzhiyun bar0_region: bar0-region@3c000000 { 85*4882a593Smuzhiyun reg = <0x0 0x3c000000 0x0 0x00400000>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun bar2_region: bar2-region@40000000 { 88*4882a593Smuzhiyun reg = <0x0 0x40000000 0x0 0x04000000>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun test-power { 93*4882a593Smuzhiyun status = "okay"; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun vbus5v0_typec: vbus5v0-typec { 97*4882a593Smuzhiyun compatible = "regulator-fixed"; 98*4882a593Smuzhiyun regulator-name = "vbus5v0_typec"; 99*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 100*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 101*4882a593Smuzhiyun enable-active-high; 102*4882a593Smuzhiyun gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; 103*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 104*4882a593Smuzhiyun pinctrl-names = "default"; 105*4882a593Smuzhiyun pinctrl-0 = <&typec5v_pwren>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun vcc12v_dcin: vcc12v-dcin { 109*4882a593Smuzhiyun compatible = "regulator-fixed"; 110*4882a593Smuzhiyun regulator-name = "vcc12v_dcin"; 111*4882a593Smuzhiyun regulator-always-on; 112*4882a593Smuzhiyun regulator-boot-on; 113*4882a593Smuzhiyun regulator-min-microvolt = <12000000>; 114*4882a593Smuzhiyun regulator-max-microvolt = <12000000>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun vcc5v0_usb: vcc5v0-usb { 118*4882a593Smuzhiyun compatible = "regulator-fixed"; 119*4882a593Smuzhiyun regulator-name = "vcc5v0_usb"; 120*4882a593Smuzhiyun regulator-always-on; 121*4882a593Smuzhiyun regulator-boot-on; 122*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 123*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 124*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun vcc5v0_sys: vcc5v0-sys { 128*4882a593Smuzhiyun compatible = "regulator-fixed"; 129*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 130*4882a593Smuzhiyun regulator-always-on; 131*4882a593Smuzhiyun regulator-boot-on; 132*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 133*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 134*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { 138*4882a593Smuzhiyun compatible = "regulator-fixed"; 139*4882a593Smuzhiyun regulator-name = "vcc_1v1_nldo_s3"; 140*4882a593Smuzhiyun regulator-always-on; 141*4882a593Smuzhiyun regulator-boot-on; 142*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 143*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 144*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun}; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun&av1d_mmu { 149*4882a593Smuzhiyun status = "okay"; 150*4882a593Smuzhiyun}; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun&cpu_l0 { 153*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_lit_s0>; 154*4882a593Smuzhiyun mem-supply = <&vdd_cpu_lit_mem_s0>; 155*4882a593Smuzhiyun}; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun&cpu_b0 { 158*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_big0_s0>; 159*4882a593Smuzhiyun mem-supply = <&vdd_cpu_big0_mem_s0>; 160*4882a593Smuzhiyun}; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun&cpu_b2 { 163*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_big1_s0>; 164*4882a593Smuzhiyun mem-supply = <&vdd_cpu_big1_mem_s0>; 165*4882a593Smuzhiyun}; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun&dp0 { 168*4882a593Smuzhiyun status = "okay"; 169*4882a593Smuzhiyun}; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun&dp0_in_vp2 { 172*4882a593Smuzhiyun status = "okay"; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun&gpu { 176*4882a593Smuzhiyun mali-supply = <&vdd_gpu_s0>; 177*4882a593Smuzhiyun mem-supply = <&vdd_gpu_mem_s0>; 178*4882a593Smuzhiyun status = "okay"; 179*4882a593Smuzhiyun}; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun&hdmi1 { 182*4882a593Smuzhiyun enable-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; 183*4882a593Smuzhiyun pinctrl-names = "default"; 184*4882a593Smuzhiyun pinctrl-0 = <&hdmim2_tx1_cec &hdmim1_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; 185*4882a593Smuzhiyun status = "okay"; 186*4882a593Smuzhiyun}; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun&hdmi1_in_vp0 { 189*4882a593Smuzhiyun status = "okay"; 190*4882a593Smuzhiyun}; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun&hdmi1_sound { 193*4882a593Smuzhiyun status = "okay"; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&hdptxphy_hdmi1 { 197*4882a593Smuzhiyun status = "okay"; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&gmac0 { 201*4882a593Smuzhiyun /* Use rgmii-rxid mode to disable rx delay inside Soc */ 202*4882a593Smuzhiyun phy-mode = "rgmii-rxid"; 203*4882a593Smuzhiyun clock_in_out = "output"; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun snps,reset-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; 206*4882a593Smuzhiyun snps,reset-active-low; 207*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 208*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun pinctrl-names = "default"; 211*4882a593Smuzhiyun pinctrl-0 = <&gmac0_miim 212*4882a593Smuzhiyun &gmac0_tx_bus2 213*4882a593Smuzhiyun &gmac0_rx_bus2 214*4882a593Smuzhiyun &gmac0_rgmii_clk 215*4882a593Smuzhiyun &gmac0_rgmii_bus 216*4882a593Smuzhiyun ð0_pins>; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun tx_delay = <0x44>; 219*4882a593Smuzhiyun /* rx_delay = <0x4f>; */ 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun phy-handle = <&rgmii_phy0>; 222*4882a593Smuzhiyun status = "okay"; 223*4882a593Smuzhiyun}; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun&iep { 226*4882a593Smuzhiyun status = "okay"; 227*4882a593Smuzhiyun}; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun&iep_mmu { 230*4882a593Smuzhiyun status = "okay"; 231*4882a593Smuzhiyun}; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun&i2c0 { 234*4882a593Smuzhiyun status = "okay"; 235*4882a593Smuzhiyun pinctrl-names = "default"; 236*4882a593Smuzhiyun pinctrl-0 = <&i2c0m2_xfer>; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 239*4882a593Smuzhiyun compatible = "rockchip,rk8602"; 240*4882a593Smuzhiyun reg = <0x42>; 241*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 242*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 243*4882a593Smuzhiyun regulator-name = "vdd_cpu_big0_s0"; 244*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 245*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 246*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 247*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 248*4882a593Smuzhiyun regulator-boot-on; 249*4882a593Smuzhiyun regulator-always-on; 250*4882a593Smuzhiyun regulator-state-mem { 251*4882a593Smuzhiyun regulator-off-in-suspend; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 256*4882a593Smuzhiyun compatible = "rockchip,rk8603"; 257*4882a593Smuzhiyun reg = <0x43>; 258*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 259*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 260*4882a593Smuzhiyun regulator-name = "vdd_cpu_big1_s0"; 261*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 262*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 263*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 264*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 265*4882a593Smuzhiyun regulator-boot-on; 266*4882a593Smuzhiyun regulator-always-on; 267*4882a593Smuzhiyun regulator-state-mem { 268*4882a593Smuzhiyun regulator-off-in-suspend; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun}; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun&i2c1 { 274*4882a593Smuzhiyun status = "okay"; 275*4882a593Smuzhiyun pinctrl-names = "default"; 276*4882a593Smuzhiyun pinctrl-0 = <&i2c1m2_xfer>; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 279*4882a593Smuzhiyun compatible = "rockchip,rk8602"; 280*4882a593Smuzhiyun reg = <0x42>; 281*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 282*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 283*4882a593Smuzhiyun regulator-name = "vdd_npu_s0"; 284*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 285*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 286*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 287*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 288*4882a593Smuzhiyun regulator-boot-on; 289*4882a593Smuzhiyun regulator-always-on; 290*4882a593Smuzhiyun regulator-state-mem { 291*4882a593Smuzhiyun regulator-off-in-suspend; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun}; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun&i2c4 { 297*4882a593Smuzhiyun status = "okay"; 298*4882a593Smuzhiyun pinctrl-names = "default"; 299*4882a593Smuzhiyun pinctrl-0 = <&i2c4m2_xfer>; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun usbc0: fusb302@22 { 302*4882a593Smuzhiyun compatible = "fcs,fusb302"; 303*4882a593Smuzhiyun reg = <0x22>; 304*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 305*4882a593Smuzhiyun interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 306*4882a593Smuzhiyun pinctrl-names = "default"; 307*4882a593Smuzhiyun pinctrl-0 = <&usbc0_int>; 308*4882a593Smuzhiyun vbus-supply = <&vbus5v0_typec>; 309*4882a593Smuzhiyun status = "okay"; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun ports { 312*4882a593Smuzhiyun #address-cells = <1>; 313*4882a593Smuzhiyun #size-cells = <0>; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun port@0 { 316*4882a593Smuzhiyun reg = <0>; 317*4882a593Smuzhiyun usbc0_role_sw: endpoint@0 { 318*4882a593Smuzhiyun remote-endpoint = <&dwc3_0_role_switch>; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun }; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun usb_con: connector { 324*4882a593Smuzhiyun compatible = "usb-c-connector"; 325*4882a593Smuzhiyun label = "USB-C"; 326*4882a593Smuzhiyun data-role = "dual"; 327*4882a593Smuzhiyun power-role = "dual"; 328*4882a593Smuzhiyun try-power-role = "sink"; 329*4882a593Smuzhiyun op-sink-microwatt = <1000000>; 330*4882a593Smuzhiyun sink-pdos = 331*4882a593Smuzhiyun <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 332*4882a593Smuzhiyun source-pdos = 333*4882a593Smuzhiyun <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun altmodes { 336*4882a593Smuzhiyun #address-cells = <1>; 337*4882a593Smuzhiyun #size-cells = <0>; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun altmode@0 { 340*4882a593Smuzhiyun reg = <0>; 341*4882a593Smuzhiyun svid = <0xff01>; 342*4882a593Smuzhiyun vdo = <0xffffffff>; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun ports { 347*4882a593Smuzhiyun #address-cells = <1>; 348*4882a593Smuzhiyun #size-cells = <0>; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun port@0 { 351*4882a593Smuzhiyun reg = <0>; 352*4882a593Smuzhiyun usbc0_orien_sw: endpoint { 353*4882a593Smuzhiyun remote-endpoint = <&usbdp_phy0_orientation_switch>; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun }; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun port@1 { 358*4882a593Smuzhiyun reg = <1>; 359*4882a593Smuzhiyun dp_altmode_mux: endpoint { 360*4882a593Smuzhiyun remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun }; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun}; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun&i2s6_8ch { 369*4882a593Smuzhiyun status = "okay"; 370*4882a593Smuzhiyun}; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun&jpegd { 373*4882a593Smuzhiyun status = "okay"; 374*4882a593Smuzhiyun}; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun&jpegd_mmu { 377*4882a593Smuzhiyun status = "okay"; 378*4882a593Smuzhiyun}; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun&jpege_ccu { 381*4882a593Smuzhiyun status = "okay"; 382*4882a593Smuzhiyun}; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun&jpege0 { 385*4882a593Smuzhiyun status = "okay"; 386*4882a593Smuzhiyun}; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun&jpege0_mmu { 389*4882a593Smuzhiyun status = "okay"; 390*4882a593Smuzhiyun}; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun&jpege1 { 393*4882a593Smuzhiyun status = "okay"; 394*4882a593Smuzhiyun}; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun&jpege1_mmu { 397*4882a593Smuzhiyun status = "okay"; 398*4882a593Smuzhiyun}; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun&jpege2 { 401*4882a593Smuzhiyun status = "okay"; 402*4882a593Smuzhiyun}; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun&jpege2_mmu { 405*4882a593Smuzhiyun status = "okay"; 406*4882a593Smuzhiyun}; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun&jpege3 { 409*4882a593Smuzhiyun status = "okay"; 410*4882a593Smuzhiyun}; 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun&jpege3_mmu { 413*4882a593Smuzhiyun status = "okay"; 414*4882a593Smuzhiyun}; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun&mdio0 { 417*4882a593Smuzhiyun rgmii_phy0: phy@1 { 418*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 419*4882a593Smuzhiyun reg = <0x1>; 420*4882a593Smuzhiyun clocks = <&cru REFCLKO25M_ETH0_OUT>; 421*4882a593Smuzhiyun }; 422*4882a593Smuzhiyun}; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun&mpp_srv { 425*4882a593Smuzhiyun status = "okay"; 426*4882a593Smuzhiyun}; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun&pcie30phy { 429*4882a593Smuzhiyun status = "okay"; 430*4882a593Smuzhiyun}; 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun&pcie3x4 { 433*4882a593Smuzhiyun compatible = "rockchip,rk3588-pcie-std-ep"; 434*4882a593Smuzhiyun memory-region = <&bar0_region>, <&bar2_region>; 435*4882a593Smuzhiyun memory-region-names = "bar0", "bar2"; 436*4882a593Smuzhiyun status = "okay"; 437*4882a593Smuzhiyun}; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun&rga3_core0 { 440*4882a593Smuzhiyun status = "okay"; 441*4882a593Smuzhiyun}; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun&rga3_0_mmu { 444*4882a593Smuzhiyun status = "okay"; 445*4882a593Smuzhiyun}; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun&rga3_core1 { 448*4882a593Smuzhiyun status = "okay"; 449*4882a593Smuzhiyun}; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun&rga3_1_mmu { 452*4882a593Smuzhiyun status = "okay"; 453*4882a593Smuzhiyun}; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun&rga2 { 456*4882a593Smuzhiyun status = "okay"; 457*4882a593Smuzhiyun}; 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun&rknpu { 460*4882a593Smuzhiyun rknpu-supply = <&vdd_npu_s0>; 461*4882a593Smuzhiyun mem-supply = <&vdd_npu_mem_s0>; 462*4882a593Smuzhiyun status = "okay"; 463*4882a593Smuzhiyun}; 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun&rknpu_mmu { 466*4882a593Smuzhiyun status = "okay"; 467*4882a593Smuzhiyun}; 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun&rkvdec_ccu { 470*4882a593Smuzhiyun status = "okay"; 471*4882a593Smuzhiyun}; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun&rkvdec0 { 474*4882a593Smuzhiyun status = "okay"; 475*4882a593Smuzhiyun}; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun&rkvdec0_mmu { 478*4882a593Smuzhiyun status = "okay"; 479*4882a593Smuzhiyun}; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun&rkvdec1 { 482*4882a593Smuzhiyun status = "okay"; 483*4882a593Smuzhiyun}; 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun&rkvdec1_mmu { 486*4882a593Smuzhiyun status = "okay"; 487*4882a593Smuzhiyun}; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun&rkvenc_ccu { 490*4882a593Smuzhiyun status = "okay"; 491*4882a593Smuzhiyun}; 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun&rkvenc0 { 494*4882a593Smuzhiyun status = "okay"; 495*4882a593Smuzhiyun}; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun&rkvenc0_mmu { 498*4882a593Smuzhiyun status = "okay"; 499*4882a593Smuzhiyun}; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun&rkvenc1 { 502*4882a593Smuzhiyun status = "okay"; 503*4882a593Smuzhiyun}; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun&rkvenc1_mmu { 506*4882a593Smuzhiyun status = "okay"; 507*4882a593Smuzhiyun}; 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun&rockchip_suspend { 510*4882a593Smuzhiyun status = "okay"; 511*4882a593Smuzhiyun rockchip,sleep-debug-en = <1>; 512*4882a593Smuzhiyun}; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun&route_hdmi1 { 515*4882a593Smuzhiyun status = "okay"; 516*4882a593Smuzhiyun}; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun&saradc { 519*4882a593Smuzhiyun status = "okay"; 520*4882a593Smuzhiyun vref-supply = <&vcc_1v8_s0>; 521*4882a593Smuzhiyun}; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun&sdhci { 524*4882a593Smuzhiyun bus-width = <8>; 525*4882a593Smuzhiyun no-sdio; 526*4882a593Smuzhiyun no-sd; 527*4882a593Smuzhiyun non-removable; 528*4882a593Smuzhiyun max-frequency = <200000000>; 529*4882a593Smuzhiyun mmc-hs400-1_8v; 530*4882a593Smuzhiyun mmc-hs400-enhanced-strobe; 531*4882a593Smuzhiyun status = "okay"; 532*4882a593Smuzhiyun}; 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun&tsadc { 535*4882a593Smuzhiyun status = "okay"; 536*4882a593Smuzhiyun}; 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun&u2phy0 { 539*4882a593Smuzhiyun status = "okay"; 540*4882a593Smuzhiyun}; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun&u2phy0_otg { 543*4882a593Smuzhiyun status = "okay"; 544*4882a593Smuzhiyun}; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun&usbdp_phy0_dp { 547*4882a593Smuzhiyun status = "okay"; 548*4882a593Smuzhiyun}; 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun&usbdp_phy0_u3 { 551*4882a593Smuzhiyun status = "okay"; 552*4882a593Smuzhiyun}; 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun&usbdrd3_0 { 555*4882a593Smuzhiyun status = "okay"; 556*4882a593Smuzhiyun}; 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun&usbdp_phy0 { 559*4882a593Smuzhiyun status = "okay"; 560*4882a593Smuzhiyun orientation-switch; 561*4882a593Smuzhiyun svid = <0xff01>; 562*4882a593Smuzhiyun sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 563*4882a593Smuzhiyun sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun port { 566*4882a593Smuzhiyun #address-cells = <1>; 567*4882a593Smuzhiyun #size-cells = <0>; 568*4882a593Smuzhiyun usbdp_phy0_orientation_switch: endpoint@0 { 569*4882a593Smuzhiyun reg = <0>; 570*4882a593Smuzhiyun remote-endpoint = <&usbc0_orien_sw>; 571*4882a593Smuzhiyun }; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun usbdp_phy0_dp_altmode_mux: endpoint@1 { 574*4882a593Smuzhiyun reg = <1>; 575*4882a593Smuzhiyun remote-endpoint = <&dp_altmode_mux>; 576*4882a593Smuzhiyun }; 577*4882a593Smuzhiyun }; 578*4882a593Smuzhiyun}; 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun&usbdrd_dwc3_0 { 581*4882a593Smuzhiyun status = "okay"; 582*4882a593Smuzhiyun dr_mode = "otg"; 583*4882a593Smuzhiyun usb-role-switch; 584*4882a593Smuzhiyun port { 585*4882a593Smuzhiyun #address-cells = <1>; 586*4882a593Smuzhiyun #size-cells = <0>; 587*4882a593Smuzhiyun dwc3_0_role_switch: endpoint@0 { 588*4882a593Smuzhiyun reg = <0>; 589*4882a593Smuzhiyun remote-endpoint = <&usbc0_role_sw>; 590*4882a593Smuzhiyun }; 591*4882a593Smuzhiyun }; 592*4882a593Smuzhiyun}; 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun&vdpu { 595*4882a593Smuzhiyun status = "okay"; 596*4882a593Smuzhiyun}; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun&vdpu_mmu { 599*4882a593Smuzhiyun status = "okay"; 600*4882a593Smuzhiyun}; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun&vepu { 603*4882a593Smuzhiyun status = "okay"; 604*4882a593Smuzhiyun}; 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun&vop { 607*4882a593Smuzhiyun status = "okay"; 608*4882a593Smuzhiyun}; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun&vop_mmu { 611*4882a593Smuzhiyun status = "okay"; 612*4882a593Smuzhiyun}; 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun/* vp0 & vp1 splice for 8K output */ 615*4882a593Smuzhiyun&vp0 { 616*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; 617*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>; 618*4882a593Smuzhiyun}; 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun&vp1 { 621*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; 622*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>; 623*4882a593Smuzhiyun}; 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun&vp2 { 626*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; 627*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>; 628*4882a593Smuzhiyun}; 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun&pinctrl { 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun usb-typec { 633*4882a593Smuzhiyun usbc0_int: usbc0-int { 634*4882a593Smuzhiyun rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 635*4882a593Smuzhiyun }; 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun typec5v_pwren: typec5v-pwren { 638*4882a593Smuzhiyun rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; 639*4882a593Smuzhiyun }; 640*4882a593Smuzhiyun }; 641*4882a593Smuzhiyun}; 642