1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "dt-bindings/usb/pd.h" 8#include "rk3588.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/pwm/pwm.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/input/rk-input.h> 13#include <dt-bindings/display/drm_mipi_dsi.h> 14#include <dt-bindings/display/rockchip_vop.h> 15#include "rk3588-rk806-single.dtsi" 16 17/ { 18 adc_keys: adc-keys { 19 compatible = "adc-keys"; 20 io-channels = <&saradc 1>; 21 io-channel-names = "buttons"; 22 keyup-threshold-microvolt = <1800000>; 23 poll-interval = <100>; 24 25 vol-up-key { 26 label = "volume up"; 27 linux,code = <KEY_VOLUMEUP>; 28 press-threshold-microvolt = <17000>; 29 }; 30 }; 31 32 dp0_sound: dp0-sound { 33 status = "disabled"; 34 compatible = "rockchip,hdmi"; 35 rockchip,card-name= "rockchip-dp0"; 36 rockchip,mclk-fs = <512>; 37 rockchip,cpu = <&spdif_tx2>; 38 rockchip,codec = <&dp0 1>; 39 rockchip,jack-det; 40 }; 41 42 hdmi1_sound: hdmi1-sound { 43 status = "disabled"; 44 compatible = "rockchip,hdmi"; 45 rockchip,mclk-fs = <128>; 46 rockchip,card-name = "rockchip-hdmi1"; 47 rockchip,cpu = <&i2s6_8ch>; 48 rockchip,codec = <&hdmi1>; 49 rockchip,jack-det; 50 }; 51 52 leds: leds { 53 compatible = "gpio-leds"; 54 work_led: work { 55 gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 56 linux,default-trigger = "heartbeat"; 57 }; 58 }; 59 60 pcie30_avdd1v8: pcie30-avdd1v8 { 61 compatible = "regulator-fixed"; 62 regulator-name = "pcie30_avdd1v8"; 63 regulator-boot-on; 64 regulator-always-on; 65 regulator-min-microvolt = <1800000>; 66 regulator-max-microvolt = <1800000>; 67 vin-supply = <&avcc_1v8_s0>; 68 }; 69 70 pcie30_avdd0v75: pcie30-avdd0v75 { 71 compatible = "regulator-fixed"; 72 regulator-name = "pcie30_avdd0v75"; 73 regulator-boot-on; 74 regulator-always-on; 75 regulator-min-microvolt = <750000>; 76 regulator-max-microvolt = <750000>; 77 vin-supply = <&avdd_0v75_s0>; 78 }; 79 80 reserved-memory { 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges; 84 bar0_region: bar0-region@3c000000 { 85 reg = <0x0 0x3c000000 0x0 0x00400000>; 86 }; 87 bar2_region: bar2-region@40000000 { 88 reg = <0x0 0x40000000 0x0 0x04000000>; 89 }; 90 }; 91 92 test-power { 93 status = "okay"; 94 }; 95 96 vbus5v0_typec: vbus5v0-typec { 97 compatible = "regulator-fixed"; 98 regulator-name = "vbus5v0_typec"; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 enable-active-high; 102 gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; 103 vin-supply = <&vcc5v0_usb>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&typec5v_pwren>; 106 }; 107 108 vcc12v_dcin: vcc12v-dcin { 109 compatible = "regulator-fixed"; 110 regulator-name = "vcc12v_dcin"; 111 regulator-always-on; 112 regulator-boot-on; 113 regulator-min-microvolt = <12000000>; 114 regulator-max-microvolt = <12000000>; 115 }; 116 117 vcc5v0_usb: vcc5v0-usb { 118 compatible = "regulator-fixed"; 119 regulator-name = "vcc5v0_usb"; 120 regulator-always-on; 121 regulator-boot-on; 122 regulator-min-microvolt = <5000000>; 123 regulator-max-microvolt = <5000000>; 124 vin-supply = <&vcc12v_dcin>; 125 }; 126 127 vcc5v0_sys: vcc5v0-sys { 128 compatible = "regulator-fixed"; 129 regulator-name = "vcc5v0_sys"; 130 regulator-always-on; 131 regulator-boot-on; 132 regulator-min-microvolt = <5000000>; 133 regulator-max-microvolt = <5000000>; 134 vin-supply = <&vcc12v_dcin>; 135 }; 136 137 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { 138 compatible = "regulator-fixed"; 139 regulator-name = "vcc_1v1_nldo_s3"; 140 regulator-always-on; 141 regulator-boot-on; 142 regulator-min-microvolt = <1100000>; 143 regulator-max-microvolt = <1100000>; 144 vin-supply = <&vcc5v0_sys>; 145 }; 146}; 147 148&av1d_mmu { 149 status = "okay"; 150}; 151 152&cpu_l0 { 153 cpu-supply = <&vdd_cpu_lit_s0>; 154 mem-supply = <&vdd_cpu_lit_mem_s0>; 155}; 156 157&cpu_b0 { 158 cpu-supply = <&vdd_cpu_big0_s0>; 159 mem-supply = <&vdd_cpu_big0_mem_s0>; 160}; 161 162&cpu_b2 { 163 cpu-supply = <&vdd_cpu_big1_s0>; 164 mem-supply = <&vdd_cpu_big1_mem_s0>; 165}; 166 167&dp0 { 168 status = "okay"; 169}; 170 171&dp0_in_vp2 { 172 status = "okay"; 173}; 174 175&gpu { 176 mali-supply = <&vdd_gpu_s0>; 177 mem-supply = <&vdd_gpu_mem_s0>; 178 status = "okay"; 179}; 180 181&hdmi1 { 182 enable-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&hdmim2_tx1_cec &hdmim1_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; 185 status = "okay"; 186}; 187 188&hdmi1_in_vp0 { 189 status = "okay"; 190}; 191 192&hdmi1_sound { 193 status = "okay"; 194}; 195 196&hdptxphy_hdmi1 { 197 status = "okay"; 198}; 199 200&gmac0 { 201 /* Use rgmii-rxid mode to disable rx delay inside Soc */ 202 phy-mode = "rgmii-rxid"; 203 clock_in_out = "output"; 204 205 snps,reset-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; 206 snps,reset-active-low; 207 /* Reset time is 20ms, 100ms for rtl8211f */ 208 snps,reset-delays-us = <0 20000 100000>; 209 210 pinctrl-names = "default"; 211 pinctrl-0 = <&gmac0_miim 212 &gmac0_tx_bus2 213 &gmac0_rx_bus2 214 &gmac0_rgmii_clk 215 &gmac0_rgmii_bus 216 ð0_pins>; 217 218 tx_delay = <0x44>; 219 /* rx_delay = <0x4f>; */ 220 221 phy-handle = <&rgmii_phy0>; 222 status = "okay"; 223}; 224 225&iep { 226 status = "okay"; 227}; 228 229&iep_mmu { 230 status = "okay"; 231}; 232 233&i2c0 { 234 status = "okay"; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&i2c0m2_xfer>; 237 238 vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 239 compatible = "rockchip,rk8602"; 240 reg = <0x42>; 241 vin-supply = <&vcc5v0_sys>; 242 regulator-compatible = "rk860x-reg"; 243 regulator-name = "vdd_cpu_big0_s0"; 244 regulator-min-microvolt = <550000>; 245 regulator-max-microvolt = <1050000>; 246 regulator-ramp-delay = <2300>; 247 rockchip,suspend-voltage-selector = <1>; 248 regulator-boot-on; 249 regulator-always-on; 250 regulator-state-mem { 251 regulator-off-in-suspend; 252 }; 253 }; 254 255 vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 256 compatible = "rockchip,rk8603"; 257 reg = <0x43>; 258 vin-supply = <&vcc5v0_sys>; 259 regulator-compatible = "rk860x-reg"; 260 regulator-name = "vdd_cpu_big1_s0"; 261 regulator-min-microvolt = <550000>; 262 regulator-max-microvolt = <1050000>; 263 regulator-ramp-delay = <2300>; 264 rockchip,suspend-voltage-selector = <1>; 265 regulator-boot-on; 266 regulator-always-on; 267 regulator-state-mem { 268 regulator-off-in-suspend; 269 }; 270 }; 271}; 272 273&i2c1 { 274 status = "okay"; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&i2c1m2_xfer>; 277 278 vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 279 compatible = "rockchip,rk8602"; 280 reg = <0x42>; 281 vin-supply = <&vcc5v0_sys>; 282 regulator-compatible = "rk860x-reg"; 283 regulator-name = "vdd_npu_s0"; 284 regulator-min-microvolt = <550000>; 285 regulator-max-microvolt = <950000>; 286 regulator-ramp-delay = <2300>; 287 rockchip,suspend-voltage-selector = <1>; 288 regulator-boot-on; 289 regulator-always-on; 290 regulator-state-mem { 291 regulator-off-in-suspend; 292 }; 293 }; 294}; 295 296&i2c4 { 297 status = "okay"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&i2c4m2_xfer>; 300 301 usbc0: fusb302@22 { 302 compatible = "fcs,fusb302"; 303 reg = <0x22>; 304 interrupt-parent = <&gpio0>; 305 interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&usbc0_int>; 308 vbus-supply = <&vbus5v0_typec>; 309 status = "okay"; 310 311 ports { 312 #address-cells = <1>; 313 #size-cells = <0>; 314 315 port@0 { 316 reg = <0>; 317 usbc0_role_sw: endpoint@0 { 318 remote-endpoint = <&dwc3_0_role_switch>; 319 }; 320 }; 321 }; 322 323 usb_con: connector { 324 compatible = "usb-c-connector"; 325 label = "USB-C"; 326 data-role = "dual"; 327 power-role = "dual"; 328 try-power-role = "sink"; 329 op-sink-microwatt = <1000000>; 330 sink-pdos = 331 <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 332 source-pdos = 333 <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 334 335 altmodes { 336 #address-cells = <1>; 337 #size-cells = <0>; 338 339 altmode@0 { 340 reg = <0>; 341 svid = <0xff01>; 342 vdo = <0xffffffff>; 343 }; 344 }; 345 346 ports { 347 #address-cells = <1>; 348 #size-cells = <0>; 349 350 port@0 { 351 reg = <0>; 352 usbc0_orien_sw: endpoint { 353 remote-endpoint = <&usbdp_phy0_orientation_switch>; 354 }; 355 }; 356 357 port@1 { 358 reg = <1>; 359 dp_altmode_mux: endpoint { 360 remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 361 }; 362 }; 363 }; 364 }; 365 }; 366}; 367 368&i2s6_8ch { 369 status = "okay"; 370}; 371 372&jpegd { 373 status = "okay"; 374}; 375 376&jpegd_mmu { 377 status = "okay"; 378}; 379 380&jpege_ccu { 381 status = "okay"; 382}; 383 384&jpege0 { 385 status = "okay"; 386}; 387 388&jpege0_mmu { 389 status = "okay"; 390}; 391 392&jpege1 { 393 status = "okay"; 394}; 395 396&jpege1_mmu { 397 status = "okay"; 398}; 399 400&jpege2 { 401 status = "okay"; 402}; 403 404&jpege2_mmu { 405 status = "okay"; 406}; 407 408&jpege3 { 409 status = "okay"; 410}; 411 412&jpege3_mmu { 413 status = "okay"; 414}; 415 416&mdio0 { 417 rgmii_phy0: phy@1 { 418 compatible = "ethernet-phy-ieee802.3-c22"; 419 reg = <0x1>; 420 clocks = <&cru REFCLKO25M_ETH0_OUT>; 421 }; 422}; 423 424&mpp_srv { 425 status = "okay"; 426}; 427 428&pcie30phy { 429 status = "okay"; 430}; 431 432&pcie3x4 { 433 compatible = "rockchip,rk3588-pcie-std-ep"; 434 memory-region = <&bar0_region>, <&bar2_region>; 435 memory-region-names = "bar0", "bar2"; 436 status = "okay"; 437}; 438 439&rga3_core0 { 440 status = "okay"; 441}; 442 443&rga3_0_mmu { 444 status = "okay"; 445}; 446 447&rga3_core1 { 448 status = "okay"; 449}; 450 451&rga3_1_mmu { 452 status = "okay"; 453}; 454 455&rga2 { 456 status = "okay"; 457}; 458 459&rknpu { 460 rknpu-supply = <&vdd_npu_s0>; 461 mem-supply = <&vdd_npu_mem_s0>; 462 status = "okay"; 463}; 464 465&rknpu_mmu { 466 status = "okay"; 467}; 468 469&rkvdec_ccu { 470 status = "okay"; 471}; 472 473&rkvdec0 { 474 status = "okay"; 475}; 476 477&rkvdec0_mmu { 478 status = "okay"; 479}; 480 481&rkvdec1 { 482 status = "okay"; 483}; 484 485&rkvdec1_mmu { 486 status = "okay"; 487}; 488 489&rkvenc_ccu { 490 status = "okay"; 491}; 492 493&rkvenc0 { 494 status = "okay"; 495}; 496 497&rkvenc0_mmu { 498 status = "okay"; 499}; 500 501&rkvenc1 { 502 status = "okay"; 503}; 504 505&rkvenc1_mmu { 506 status = "okay"; 507}; 508 509&rockchip_suspend { 510 status = "okay"; 511 rockchip,sleep-debug-en = <1>; 512}; 513 514&route_hdmi1 { 515 status = "okay"; 516}; 517 518&saradc { 519 status = "okay"; 520 vref-supply = <&vcc_1v8_s0>; 521}; 522 523&sdhci { 524 bus-width = <8>; 525 no-sdio; 526 no-sd; 527 non-removable; 528 max-frequency = <200000000>; 529 mmc-hs400-1_8v; 530 mmc-hs400-enhanced-strobe; 531 status = "okay"; 532}; 533 534&tsadc { 535 status = "okay"; 536}; 537 538&u2phy0 { 539 status = "okay"; 540}; 541 542&u2phy0_otg { 543 status = "okay"; 544}; 545 546&usbdp_phy0_dp { 547 status = "okay"; 548}; 549 550&usbdp_phy0_u3 { 551 status = "okay"; 552}; 553 554&usbdrd3_0 { 555 status = "okay"; 556}; 557 558&usbdp_phy0 { 559 status = "okay"; 560 orientation-switch; 561 svid = <0xff01>; 562 sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 563 sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 564 565 port { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 usbdp_phy0_orientation_switch: endpoint@0 { 569 reg = <0>; 570 remote-endpoint = <&usbc0_orien_sw>; 571 }; 572 573 usbdp_phy0_dp_altmode_mux: endpoint@1 { 574 reg = <1>; 575 remote-endpoint = <&dp_altmode_mux>; 576 }; 577 }; 578}; 579 580&usbdrd_dwc3_0 { 581 status = "okay"; 582 dr_mode = "otg"; 583 usb-role-switch; 584 port { 585 #address-cells = <1>; 586 #size-cells = <0>; 587 dwc3_0_role_switch: endpoint@0 { 588 reg = <0>; 589 remote-endpoint = <&usbc0_role_sw>; 590 }; 591 }; 592}; 593 594&vdpu { 595 status = "okay"; 596}; 597 598&vdpu_mmu { 599 status = "okay"; 600}; 601 602&vepu { 603 status = "okay"; 604}; 605 606&vop { 607 status = "okay"; 608}; 609 610&vop_mmu { 611 status = "okay"; 612}; 613 614/* vp0 & vp1 splice for 8K output */ 615&vp0 { 616 rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; 617 rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>; 618}; 619 620&vp1 { 621 rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; 622 rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>; 623}; 624 625&vp2 { 626 rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; 627 rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>; 628}; 629 630&pinctrl { 631 632 usb-typec { 633 usbc0_int: usbc0-int { 634 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 635 }; 636 637 typec5v_pwren: typec5v-pwren { 638 rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; 639 }; 640 }; 641}; 642