1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h" 8*4882a593Smuzhiyun#include "rk3588.dtsi" 9*4882a593Smuzhiyun#include "rk3588-evb.dtsi" 10*4882a593Smuzhiyun#include "rk3588-rk806-single.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun /* If hdmirx node is disabled, delete the reserved-memory node here. */ 14*4882a593Smuzhiyun reserved-memory { 15*4882a593Smuzhiyun #address-cells = <2>; 16*4882a593Smuzhiyun #size-cells = <2>; 17*4882a593Smuzhiyun ranges; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ 20*4882a593Smuzhiyun cma { 21*4882a593Smuzhiyun compatible = "shared-dma-pool"; 22*4882a593Smuzhiyun reusable; 23*4882a593Smuzhiyun reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; 24*4882a593Smuzhiyun linux,cma-default; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun es8388_sound: es8388-sound { 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun compatible = "rockchip,multicodecs-card"; 31*4882a593Smuzhiyun rockchip,card-name = "rockchip-es8388"; 32*4882a593Smuzhiyun hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; 33*4882a593Smuzhiyun io-channels = <&saradc 3>; 34*4882a593Smuzhiyun io-channel-names = "adc-detect"; 35*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 36*4882a593Smuzhiyun poll-interval = <100>; 37*4882a593Smuzhiyun spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 38*4882a593Smuzhiyun hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 39*4882a593Smuzhiyun rockchip,format = "i2s"; 40*4882a593Smuzhiyun rockchip,mclk-fs = <256>; 41*4882a593Smuzhiyun rockchip,cpu = <&i2s0_8ch>; 42*4882a593Smuzhiyun rockchip,codec = <&es8388>; 43*4882a593Smuzhiyun rockchip,audio-routing = 44*4882a593Smuzhiyun "Headphone", "LOUT1", 45*4882a593Smuzhiyun "Headphone", "ROUT1", 46*4882a593Smuzhiyun "Speaker", "LOUT2", 47*4882a593Smuzhiyun "Speaker", "ROUT2", 48*4882a593Smuzhiyun "Headphone", "Headphone Power", 49*4882a593Smuzhiyun "Headphone", "Headphone Power", 50*4882a593Smuzhiyun "Speaker", "Speaker Power", 51*4882a593Smuzhiyun "Speaker", "Speaker Power", 52*4882a593Smuzhiyun "LINPUT1", "Main Mic", 53*4882a593Smuzhiyun "LINPUT2", "Main Mic", 54*4882a593Smuzhiyun "RINPUT1", "Headset Mic", 55*4882a593Smuzhiyun "RINPUT2", "Headset Mic"; 56*4882a593Smuzhiyun pinctrl-names = "default"; 57*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 58*4882a593Smuzhiyun play-pause-key { 59*4882a593Smuzhiyun label = "playpause"; 60*4882a593Smuzhiyun linux,code = <KEY_PLAYPAUSE>; 61*4882a593Smuzhiyun press-threshold-microvolt = <2000>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun fan: pwm-fan { 66*4882a593Smuzhiyun compatible = "pwm-fan"; 67*4882a593Smuzhiyun #cooling-cells = <2>; 68*4882a593Smuzhiyun pwms = <&pwm3 0 50000 0>; 69*4882a593Smuzhiyun cooling-levels = <0 50 100 150 200 255>; 70*4882a593Smuzhiyun rockchip,temp-trips = < 71*4882a593Smuzhiyun 50000 1 72*4882a593Smuzhiyun 55000 2 73*4882a593Smuzhiyun 60000 3 74*4882a593Smuzhiyun 65000 4 75*4882a593Smuzhiyun 70000 5 76*4882a593Smuzhiyun >; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun hdmiin-sound { 80*4882a593Smuzhiyun compatible = "rockchip,hdmi"; 81*4882a593Smuzhiyun rockchip,mclk-fs = <128>; 82*4882a593Smuzhiyun rockchip,format = "i2s"; 83*4882a593Smuzhiyun rockchip,bitclock-master = <&hdmirx_ctrler>; 84*4882a593Smuzhiyun rockchip,frame-master = <&hdmirx_ctrler>; 85*4882a593Smuzhiyun rockchip,card-name = "rockchip,hdmiin"; 86*4882a593Smuzhiyun rockchip,cpu = <&i2s7_8ch>; 87*4882a593Smuzhiyun rockchip,codec = <&hdmirx_ctrler 0>; 88*4882a593Smuzhiyun rockchip,jack-det; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun pcie20_avdd0v85: pcie20-avdd0v85 { 92*4882a593Smuzhiyun compatible = "regulator-fixed"; 93*4882a593Smuzhiyun regulator-name = "pcie20_avdd0v85"; 94*4882a593Smuzhiyun regulator-boot-on; 95*4882a593Smuzhiyun regulator-always-on; 96*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 97*4882a593Smuzhiyun regulator-max-microvolt = <850000>; 98*4882a593Smuzhiyun vin-supply = <&vdd_0v85_s0>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun pcie20_avdd1v8: pcie20-avdd1v8 { 102*4882a593Smuzhiyun compatible = "regulator-fixed"; 103*4882a593Smuzhiyun regulator-name = "pcie20_avdd1v8"; 104*4882a593Smuzhiyun regulator-boot-on; 105*4882a593Smuzhiyun regulator-always-on; 106*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 107*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 108*4882a593Smuzhiyun vin-supply = <&avcc_1v8_s0>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun pcie30_avdd0v75: pcie30-avdd0v75 { 112*4882a593Smuzhiyun compatible = "regulator-fixed"; 113*4882a593Smuzhiyun regulator-name = "pcie30_avdd0v75"; 114*4882a593Smuzhiyun regulator-boot-on; 115*4882a593Smuzhiyun regulator-always-on; 116*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 117*4882a593Smuzhiyun regulator-max-microvolt = <750000>; 118*4882a593Smuzhiyun vin-supply = <&avdd_0v75_s0>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun pcie30_avdd1v8: pcie30-avdd1v8 { 122*4882a593Smuzhiyun compatible = "regulator-fixed"; 123*4882a593Smuzhiyun regulator-name = "pcie30_avdd1v8"; 124*4882a593Smuzhiyun regulator-boot-on; 125*4882a593Smuzhiyun regulator-always-on; 126*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 127*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 128*4882a593Smuzhiyun vin-supply = <&avcc_1v8_s0>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 132*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 133*4882a593Smuzhiyun clocks = <&hym8563>; 134*4882a593Smuzhiyun clock-names = "ext_clock"; 135*4882a593Smuzhiyun pinctrl-names = "default"; 136*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 137*4882a593Smuzhiyun /* 138*4882a593Smuzhiyun * On the module itself this is one of these (depending 139*4882a593Smuzhiyun * on the actual card populated): 140*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 141*4882a593Smuzhiyun * - PDN (power down when low) 142*4882a593Smuzhiyun */ 143*4882a593Smuzhiyun post-power-on-delay-ms = <200>; 144*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun rk_headset: rk-headset { 148*4882a593Smuzhiyun status = "disabled"; 149*4882a593Smuzhiyun compatible = "rockchip_headset"; 150*4882a593Smuzhiyun headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 151*4882a593Smuzhiyun pinctrl-names = "default"; 152*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 153*4882a593Smuzhiyun io-channels = <&saradc 3>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { 158*4882a593Smuzhiyun compatible = "regulator-fixed"; 159*4882a593Smuzhiyun regulator-name = "vcc_1v1_nldo_s3"; 160*4882a593Smuzhiyun regulator-always-on; 161*4882a593Smuzhiyun regulator-boot-on; 162*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 163*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 164*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun vbus5v0_typec: vbus5v0-typec { 168*4882a593Smuzhiyun compatible = "regulator-fixed"; 169*4882a593Smuzhiyun regulator-name = "vbus5v0_typec"; 170*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 171*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 172*4882a593Smuzhiyun enable-active-high; 173*4882a593Smuzhiyun gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 174*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 175*4882a593Smuzhiyun pinctrl-names = "default"; 176*4882a593Smuzhiyun pinctrl-0 = <&typec5v_pwren>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun vcc3v3_lcd_n: vcc3v3-lcd0-n { 180*4882a593Smuzhiyun compatible = "regulator-fixed"; 181*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd0_n"; 182*4882a593Smuzhiyun regulator-boot-on; 183*4882a593Smuzhiyun enable-active-high; 184*4882a593Smuzhiyun gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 185*4882a593Smuzhiyun vin-supply = <&vcc_1v8_s0>; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun vcc3v3_pcie30: vcc3v3-pcie30 { 189*4882a593Smuzhiyun compatible = "regulator-fixed"; 190*4882a593Smuzhiyun regulator-name = "vcc3v3_pcie30"; 191*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 192*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 193*4882a593Smuzhiyun enable-active-high; 194*4882a593Smuzhiyun gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; 195*4882a593Smuzhiyun startup-delay-us = <5000>; 196*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun vcc5v0_host: vcc5v0-host { 200*4882a593Smuzhiyun compatible = "regulator-fixed"; 201*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 202*4882a593Smuzhiyun regulator-boot-on; 203*4882a593Smuzhiyun regulator-always-on; 204*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 205*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 206*4882a593Smuzhiyun enable-active-high; 207*4882a593Smuzhiyun gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 208*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 209*4882a593Smuzhiyun pinctrl-names = "default"; 210*4882a593Smuzhiyun pinctrl-0 = <&vcc5v0_host_en>; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun vcc_mipicsi0: vcc-mipicsi0-regulator { 214*4882a593Smuzhiyun compatible = "regulator-fixed"; 215*4882a593Smuzhiyun gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; 216*4882a593Smuzhiyun pinctrl-names = "default"; 217*4882a593Smuzhiyun pinctrl-0 = <&mipicsi0_pwr>; 218*4882a593Smuzhiyun regulator-name = "vcc_mipicsi0"; 219*4882a593Smuzhiyun enable-active-high; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun vcc_mipicsi1: vcc-mipicsi1-regulator { 223*4882a593Smuzhiyun compatible = "regulator-fixed"; 224*4882a593Smuzhiyun gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 225*4882a593Smuzhiyun pinctrl-names = "default"; 226*4882a593Smuzhiyun pinctrl-0 = <&mipicsi1_pwr>; 227*4882a593Smuzhiyun regulator-name = "vcc_mipicsi1"; 228*4882a593Smuzhiyun enable-active-high; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun vcc_mipidcphy0: vcc-mipidcphy0-regulator { 232*4882a593Smuzhiyun compatible = "regulator-fixed"; 233*4882a593Smuzhiyun gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; 234*4882a593Smuzhiyun pinctrl-names = "default"; 235*4882a593Smuzhiyun pinctrl-0 = <&mipidcphy0_pwr>; 236*4882a593Smuzhiyun regulator-name = "vcc_mipidcphy0"; 237*4882a593Smuzhiyun enable-active-high; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { 241*4882a593Smuzhiyun compatible = "regulator-fixed"; 242*4882a593Smuzhiyun gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 243*4882a593Smuzhiyun pinctrl-names = "default"; 244*4882a593Smuzhiyun pinctrl-0 = <&sd_s0_pwr>; 245*4882a593Smuzhiyun regulator-name = "vcc_3v3_sd_s0"; 246*4882a593Smuzhiyun enable-active-high; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun wireless_bluetooth: wireless-bluetooth { 250*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 251*4882a593Smuzhiyun clocks = <&hym8563>; 252*4882a593Smuzhiyun clock-names = "ext_clock"; 253*4882a593Smuzhiyun uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; 254*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 255*4882a593Smuzhiyun pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 256*4882a593Smuzhiyun pinctrl-1 = <&uart9_gpios>; 257*4882a593Smuzhiyun BT,reset_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 258*4882a593Smuzhiyun BT,wake_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 259*4882a593Smuzhiyun BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 260*4882a593Smuzhiyun status = "okay"; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun wireless_wlan: wireless-wlan { 264*4882a593Smuzhiyun compatible = "wlan-platdata"; 265*4882a593Smuzhiyun wifi_chip_type = "ap6398s"; 266*4882a593Smuzhiyun pinctrl-names = "default"; 267*4882a593Smuzhiyun pinctrl-0 = <&wifi_host_wake_irq>; 268*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; 269*4882a593Smuzhiyun WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; 270*4882a593Smuzhiyun status = "okay"; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun}; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&backlight { 275*4882a593Smuzhiyun pwms = <&pwm1 0 25000 0>; 276*4882a593Smuzhiyun status = "okay"; 277*4882a593Smuzhiyun}; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun&combphy0_ps { 280*4882a593Smuzhiyun status = "okay"; 281*4882a593Smuzhiyun}; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun&combphy1_ps { 284*4882a593Smuzhiyun status = "okay"; 285*4882a593Smuzhiyun}; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun&combphy2_psu { 288*4882a593Smuzhiyun status = "okay"; 289*4882a593Smuzhiyun}; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun&dp0 { 292*4882a593Smuzhiyun status = "okay"; 293*4882a593Smuzhiyun}; 294*4882a593Smuzhiyun&dp0_in_vp2 { 295*4882a593Smuzhiyun status = "okay"; 296*4882a593Smuzhiyun}; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun&dp0_sound{ 299*4882a593Smuzhiyun status = "okay"; 300*4882a593Smuzhiyun}; 301*4882a593Smuzhiyun&dp1 { 302*4882a593Smuzhiyun pinctrl-names = "default"; 303*4882a593Smuzhiyun pinctrl-0 = <&dp1m0_pins>; 304*4882a593Smuzhiyun status = "okay"; 305*4882a593Smuzhiyun}; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun&dp1_in_vp2 { 308*4882a593Smuzhiyun status = "okay"; 309*4882a593Smuzhiyun}; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun/* 312*4882a593Smuzhiyun * mipi_dcphy0 needs to be enabled 313*4882a593Smuzhiyun * when dsi0 is enabled 314*4882a593Smuzhiyun */ 315*4882a593Smuzhiyun&dsi0 { 316*4882a593Smuzhiyun status = "okay"; 317*4882a593Smuzhiyun}; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun&dsi0_in_vp2 { 320*4882a593Smuzhiyun status = "disabled"; 321*4882a593Smuzhiyun}; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun&dsi0_in_vp3 { 324*4882a593Smuzhiyun status = "okay"; 325*4882a593Smuzhiyun}; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun&dsi0_panel { 328*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_n>; 329*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; 330*4882a593Smuzhiyun pinctrl-names = "default"; 331*4882a593Smuzhiyun pinctrl-0 = <&lcd_rst_gpio>; 332*4882a593Smuzhiyun}; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun/* 335*4882a593Smuzhiyun * mipi_dcphy1 needs to be enabled 336*4882a593Smuzhiyun * when dsi1 is enabled 337*4882a593Smuzhiyun */ 338*4882a593Smuzhiyun&dsi1 { 339*4882a593Smuzhiyun status = "disabled"; 340*4882a593Smuzhiyun}; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun&dsi1_in_vp2 { 343*4882a593Smuzhiyun status = "disabled"; 344*4882a593Smuzhiyun}; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun&dsi1_in_vp3 { 347*4882a593Smuzhiyun status = "disabled"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun&dsi1_panel { 351*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_n>; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun /* 354*4882a593Smuzhiyun * because in hardware, the two screens share the reset pin, 355*4882a593Smuzhiyun * so reset-gpios need only in dsi1 enable and dsi0 disabled 356*4882a593Smuzhiyun * case. 357*4882a593Smuzhiyun */ 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun //reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; 360*4882a593Smuzhiyun //pinctrl-names = "default"; 361*4882a593Smuzhiyun //pinctrl-0 = <&lcd_rst_gpio>; 362*4882a593Smuzhiyun}; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun&gmac1 { 365*4882a593Smuzhiyun /* Use rgmii-rxid mode to disable rx delay inside Soc */ 366*4882a593Smuzhiyun phy-mode = "rgmii-rxid"; 367*4882a593Smuzhiyun clock_in_out = "output"; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 370*4882a593Smuzhiyun snps,reset-active-low; 371*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 372*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun pinctrl-names = "default"; 375*4882a593Smuzhiyun pinctrl-0 = <&gmac1_miim 376*4882a593Smuzhiyun &gmac1_tx_bus2 377*4882a593Smuzhiyun &gmac1_rx_bus2 378*4882a593Smuzhiyun &gmac1_rgmii_clk 379*4882a593Smuzhiyun &gmac1_rgmii_bus>; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun tx_delay = <0x43>; 382*4882a593Smuzhiyun /* rx_delay = <0x3f>; */ 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun phy-handle = <&rgmii_phy>; 385*4882a593Smuzhiyun status = "okay"; 386*4882a593Smuzhiyun}; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun&hdmi0 { 389*4882a593Smuzhiyun enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 390*4882a593Smuzhiyun status = "okay"; 391*4882a593Smuzhiyun}; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun&hdmi0_in_vp0 { 394*4882a593Smuzhiyun status = "okay"; 395*4882a593Smuzhiyun}; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun&hdmi0_sound { 398*4882a593Smuzhiyun status = "okay"; 399*4882a593Smuzhiyun}; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun&hdmi1 { 402*4882a593Smuzhiyun enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 403*4882a593Smuzhiyun status = "okay"; 404*4882a593Smuzhiyun}; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun&hdmi1_in_vp1 { 407*4882a593Smuzhiyun status = "okay"; 408*4882a593Smuzhiyun}; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun&hdmi1_sound { 411*4882a593Smuzhiyun status = "okay"; 412*4882a593Smuzhiyun}; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun/* Should work with at least 128MB cma reserved above. */ 415*4882a593Smuzhiyun&hdmirx_ctrler { 416*4882a593Smuzhiyun status = "okay"; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun #sound-dai-cells = <1>; 419*4882a593Smuzhiyun /* Effective level used to trigger HPD: 0-low, 1-high */ 420*4882a593Smuzhiyun hpd-trigger-level = <1>; 421*4882a593Smuzhiyun hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 422*4882a593Smuzhiyun pinctrl-names = "default"; 423*4882a593Smuzhiyun pinctrl-0 = <&hdmim1_rx &hdmirx_det>; 424*4882a593Smuzhiyun}; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun&hdptxphy_hdmi0 { 427*4882a593Smuzhiyun status = "okay"; 428*4882a593Smuzhiyun}; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun&hdptxphy_hdmi1 { 431*4882a593Smuzhiyun status = "okay"; 432*4882a593Smuzhiyun}; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun&i2c0 { 435*4882a593Smuzhiyun status = "okay"; 436*4882a593Smuzhiyun pinctrl-names = "default"; 437*4882a593Smuzhiyun pinctrl-0 = <&i2c0m2_xfer>; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 440*4882a593Smuzhiyun compatible = "rockchip,rk8602"; 441*4882a593Smuzhiyun reg = <0x42>; 442*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 443*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 444*4882a593Smuzhiyun regulator-name = "vdd_cpu_big0_s0"; 445*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 446*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 447*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 448*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 449*4882a593Smuzhiyun regulator-boot-on; 450*4882a593Smuzhiyun regulator-always-on; 451*4882a593Smuzhiyun regulator-state-mem { 452*4882a593Smuzhiyun regulator-off-in-suspend; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 457*4882a593Smuzhiyun compatible = "rockchip,rk8603"; 458*4882a593Smuzhiyun reg = <0x43>; 459*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 460*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 461*4882a593Smuzhiyun regulator-name = "vdd_cpu_big1_s0"; 462*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 463*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 464*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 465*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 466*4882a593Smuzhiyun regulator-boot-on; 467*4882a593Smuzhiyun regulator-always-on; 468*4882a593Smuzhiyun regulator-state-mem { 469*4882a593Smuzhiyun regulator-off-in-suspend; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun}; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun&i2c1 { 475*4882a593Smuzhiyun status = "okay"; 476*4882a593Smuzhiyun pinctrl-names = "default"; 477*4882a593Smuzhiyun pinctrl-0 = <&i2c1m2_xfer>; 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 480*4882a593Smuzhiyun compatible = "rockchip,rk8602"; 481*4882a593Smuzhiyun reg = <0x42>; 482*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 483*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 484*4882a593Smuzhiyun regulator-name = "vdd_npu_s0"; 485*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 486*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 487*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 488*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 489*4882a593Smuzhiyun regulator-boot-on; 490*4882a593Smuzhiyun regulator-always-on; 491*4882a593Smuzhiyun regulator-state-mem { 492*4882a593Smuzhiyun regulator-off-in-suspend; 493*4882a593Smuzhiyun }; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun}; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun&i2c4 { 498*4882a593Smuzhiyun status = "okay"; 499*4882a593Smuzhiyun pinctrl-0 = <&i2c4m1_xfer>; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun ls_stk3332: light@47 { 502*4882a593Smuzhiyun compatible = "ls_stk3332"; 503*4882a593Smuzhiyun status = "disabled"; 504*4882a593Smuzhiyun reg = <0x47>; 505*4882a593Smuzhiyun type = <SENSOR_TYPE_LIGHT>; 506*4882a593Smuzhiyun irq_enable = <0>; 507*4882a593Smuzhiyun als_threshold_high = <100>; 508*4882a593Smuzhiyun als_threshold_low = <10>; 509*4882a593Smuzhiyun als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ 510*4882a593Smuzhiyun poll_delay_ms = <100>; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun ps_stk3332: proximity@47 { 514*4882a593Smuzhiyun compatible = "ps_stk3332"; 515*4882a593Smuzhiyun status = "disabled"; 516*4882a593Smuzhiyun reg = <0x47>; 517*4882a593Smuzhiyun type = <SENSOR_TYPE_PROXIMITY>; 518*4882a593Smuzhiyun //pinctrl-names = "default"; 519*4882a593Smuzhiyun //pinctrl-0 = <&gpio3_c6>; 520*4882a593Smuzhiyun //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; 521*4882a593Smuzhiyun //irq_enable = <1>; 522*4882a593Smuzhiyun ps_threshold_high = <0x200>; 523*4882a593Smuzhiyun ps_threshold_low = <0x100>; 524*4882a593Smuzhiyun ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ 525*4882a593Smuzhiyun ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ 526*4882a593Smuzhiyun poll_delay_ms = <100>; 527*4882a593Smuzhiyun }; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun icm42607_acc: icm_acc@68 { 530*4882a593Smuzhiyun status = "okay"; 531*4882a593Smuzhiyun compatible = "icm42607_acc"; 532*4882a593Smuzhiyun reg = <0x68>; 533*4882a593Smuzhiyun irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_EDGE_RISING>; 534*4882a593Smuzhiyun irq_enable = <0>; 535*4882a593Smuzhiyun poll_delay_ms = <30>; 536*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 537*4882a593Smuzhiyun layout = <0>; 538*4882a593Smuzhiyun }; 539*4882a593Smuzhiyun 540*4882a593Smuzhiyun icm42607_gyro: icm_gyro@68 { 541*4882a593Smuzhiyun status = "okay"; 542*4882a593Smuzhiyun compatible = "icm42607_gyro"; 543*4882a593Smuzhiyun reg = <0x68>; 544*4882a593Smuzhiyun poll_delay_ms = <30>; 545*4882a593Smuzhiyun type = <SENSOR_TYPE_GYROSCOPE>; 546*4882a593Smuzhiyun layout = <0>; 547*4882a593Smuzhiyun }; 548*4882a593Smuzhiyun}; 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun&i2c5 { 551*4882a593Smuzhiyun status = "okay"; 552*4882a593Smuzhiyun gt1x: gt1x@14 { 553*4882a593Smuzhiyun compatible = "goodix,gt1x"; 554*4882a593Smuzhiyun reg = <0x14>; 555*4882a593Smuzhiyun pinctrl-names = "default"; 556*4882a593Smuzhiyun pinctrl-0 = <&touch_gpio>; 557*4882a593Smuzhiyun goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; 558*4882a593Smuzhiyun goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; 559*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_n>; 560*4882a593Smuzhiyun }; 561*4882a593Smuzhiyun}; 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun&i2c6 { 564*4882a593Smuzhiyun status = "okay"; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun usbc0: husb311@4e { 567*4882a593Smuzhiyun compatible = "hynetek,husb311"; 568*4882a593Smuzhiyun reg = <0x4e>; 569*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 570*4882a593Smuzhiyun interrupts = <RK_PB6 IRQ_TYPE_LEVEL_LOW>; 571*4882a593Smuzhiyun pinctrl-names = "default"; 572*4882a593Smuzhiyun pinctrl-0 = <&usbc0_int>; 573*4882a593Smuzhiyun vbus-supply = <&vbus5v0_typec>; 574*4882a593Smuzhiyun status = "okay"; 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun ports { 577*4882a593Smuzhiyun #address-cells = <1>; 578*4882a593Smuzhiyun #size-cells = <0>; 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun port@0 { 581*4882a593Smuzhiyun reg = <0>; 582*4882a593Smuzhiyun usbc0_role_sw: endpoint@0 { 583*4882a593Smuzhiyun remote-endpoint = <&dwc3_0_role_switch>; 584*4882a593Smuzhiyun }; 585*4882a593Smuzhiyun }; 586*4882a593Smuzhiyun }; 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun usb_con: connector { 589*4882a593Smuzhiyun compatible = "usb-c-connector"; 590*4882a593Smuzhiyun label = "USB-C"; 591*4882a593Smuzhiyun data-role = "dual"; 592*4882a593Smuzhiyun power-role = "dual"; 593*4882a593Smuzhiyun try-power-role = "sink"; 594*4882a593Smuzhiyun op-sink-microwatt = <1000000>; 595*4882a593Smuzhiyun sink-pdos = 596*4882a593Smuzhiyun <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 597*4882a593Smuzhiyun source-pdos = 598*4882a593Smuzhiyun <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun altmodes { 601*4882a593Smuzhiyun #address-cells = <1>; 602*4882a593Smuzhiyun #size-cells = <0>; 603*4882a593Smuzhiyun 604*4882a593Smuzhiyun altmode@0 { 605*4882a593Smuzhiyun reg = <0>; 606*4882a593Smuzhiyun svid = <0xff01>; 607*4882a593Smuzhiyun vdo = <0xffffffff>; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun }; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun ports { 612*4882a593Smuzhiyun #address-cells = <1>; 613*4882a593Smuzhiyun #size-cells = <0>; 614*4882a593Smuzhiyun 615*4882a593Smuzhiyun port@0 { 616*4882a593Smuzhiyun reg = <0>; 617*4882a593Smuzhiyun usbc0_orien_sw: endpoint { 618*4882a593Smuzhiyun remote-endpoint = <&usbdp_phy0_orientation_switch>; 619*4882a593Smuzhiyun }; 620*4882a593Smuzhiyun }; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun port@1 { 623*4882a593Smuzhiyun reg = <1>; 624*4882a593Smuzhiyun dp_altmode_mux: endpoint { 625*4882a593Smuzhiyun remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 626*4882a593Smuzhiyun }; 627*4882a593Smuzhiyun }; 628*4882a593Smuzhiyun }; 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun }; 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun hym8563: hym8563@51 { 633*4882a593Smuzhiyun compatible = "haoyu,hym8563"; 634*4882a593Smuzhiyun reg = <0x51>; 635*4882a593Smuzhiyun #clock-cells = <0>; 636*4882a593Smuzhiyun clock-frequency = <32768>; 637*4882a593Smuzhiyun clock-output-names = "hym8563"; 638*4882a593Smuzhiyun pinctrl-names = "default"; 639*4882a593Smuzhiyun pinctrl-0 = <&hym8563_int>; 640*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 641*4882a593Smuzhiyun interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 642*4882a593Smuzhiyun wakeup-source; 643*4882a593Smuzhiyun }; 644*4882a593Smuzhiyun}; 645*4882a593Smuzhiyun 646*4882a593Smuzhiyun&i2c7 { 647*4882a593Smuzhiyun status = "okay"; 648*4882a593Smuzhiyun es8388: es8388@11 { 649*4882a593Smuzhiyun status = "okay"; 650*4882a593Smuzhiyun #sound-dai-cells = <0>; 651*4882a593Smuzhiyun compatible = "everest,es8388", "everest,es8323"; 652*4882a593Smuzhiyun reg = <0x11>; 653*4882a593Smuzhiyun clocks = <&mclkout_i2s0>; 654*4882a593Smuzhiyun clock-names = "mclk"; 655*4882a593Smuzhiyun assigned-clocks = <&mclkout_i2s0>; 656*4882a593Smuzhiyun assigned-clock-rates = <12288000>; 657*4882a593Smuzhiyun pinctrl-names = "default"; 658*4882a593Smuzhiyun pinctrl-0 = <&i2s0_mclk>; 659*4882a593Smuzhiyun }; 660*4882a593Smuzhiyun}; 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun&i2s5_8ch { 663*4882a593Smuzhiyun status = "okay"; 664*4882a593Smuzhiyun}; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun&i2s6_8ch { 667*4882a593Smuzhiyun status = "okay"; 668*4882a593Smuzhiyun}; 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun&i2s7_8ch { 671*4882a593Smuzhiyun status = "okay"; 672*4882a593Smuzhiyun}; 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun&mdio1 { 675*4882a593Smuzhiyun rgmii_phy: phy@1 { 676*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 677*4882a593Smuzhiyun reg = <0x1>; 678*4882a593Smuzhiyun }; 679*4882a593Smuzhiyun}; 680*4882a593Smuzhiyun 681*4882a593Smuzhiyun&mipi_dcphy0 { 682*4882a593Smuzhiyun status = "okay"; 683*4882a593Smuzhiyun}; 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun&mipi_dcphy1 { 686*4882a593Smuzhiyun status = "disabled"; 687*4882a593Smuzhiyun}; 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun&pcie2x1l0 { 690*4882a593Smuzhiyun reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; 691*4882a593Smuzhiyun status = "okay"; 692*4882a593Smuzhiyun}; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun&pcie30phy { 695*4882a593Smuzhiyun rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>; 696*4882a593Smuzhiyun status = "okay"; 697*4882a593Smuzhiyun}; 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun&pcie3x4 { 700*4882a593Smuzhiyun reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 701*4882a593Smuzhiyun vpcie3v3-supply = <&vcc3v3_pcie30>; 702*4882a593Smuzhiyun pinctrl-names = "default"; 703*4882a593Smuzhiyun pinctrl-0 = <&pcie20x1_0_clkreqn_m1>; 704*4882a593Smuzhiyun status = "okay"; 705*4882a593Smuzhiyun}; 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun&pinctrl { 708*4882a593Smuzhiyun cam { 709*4882a593Smuzhiyun mipicsi0_pwr: mipicsi0-pwr { 710*4882a593Smuzhiyun rockchip,pins = 711*4882a593Smuzhiyun /* camera power en */ 712*4882a593Smuzhiyun <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 713*4882a593Smuzhiyun }; 714*4882a593Smuzhiyun mipicsi1_pwr: mipicsi1-pwr { 715*4882a593Smuzhiyun rockchip,pins = 716*4882a593Smuzhiyun /* camera power en */ 717*4882a593Smuzhiyun <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 718*4882a593Smuzhiyun }; 719*4882a593Smuzhiyun mipidcphy0_pwr: mipidcphy0-pwr { 720*4882a593Smuzhiyun rockchip,pins = 721*4882a593Smuzhiyun /* camera power en */ 722*4882a593Smuzhiyun <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 723*4882a593Smuzhiyun }; 724*4882a593Smuzhiyun }; 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun hdmi { 728*4882a593Smuzhiyun hdmirx_det: hdmirx-det { 729*4882a593Smuzhiyun rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; 730*4882a593Smuzhiyun }; 731*4882a593Smuzhiyun }; 732*4882a593Smuzhiyun 733*4882a593Smuzhiyun headphone { 734*4882a593Smuzhiyun hp_det: hp-det { 735*4882a593Smuzhiyun rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 736*4882a593Smuzhiyun }; 737*4882a593Smuzhiyun }; 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun hym8563 { 740*4882a593Smuzhiyun hym8563_int: hym8563-int { 741*4882a593Smuzhiyun rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 742*4882a593Smuzhiyun }; 743*4882a593Smuzhiyun }; 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun lcd { 746*4882a593Smuzhiyun lcd_rst_gpio: lcd-rst-gpio { 747*4882a593Smuzhiyun rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 748*4882a593Smuzhiyun }; 749*4882a593Smuzhiyun }; 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun leds { 752*4882a593Smuzhiyun work_leds_gpio: work-leds-gpio { 753*4882a593Smuzhiyun rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; 754*4882a593Smuzhiyun }; 755*4882a593Smuzhiyun }; 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun sdio-pwrseq { 758*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 759*4882a593Smuzhiyun rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; 760*4882a593Smuzhiyun }; 761*4882a593Smuzhiyun }; 762*4882a593Smuzhiyun 763*4882a593Smuzhiyun sdmmc { 764*4882a593Smuzhiyun sd_s0_pwr: sd-s0-pwr { 765*4882a593Smuzhiyun rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; 766*4882a593Smuzhiyun }; 767*4882a593Smuzhiyun }; 768*4882a593Smuzhiyun 769*4882a593Smuzhiyun touch { 770*4882a593Smuzhiyun touch_gpio: touch-gpio { 771*4882a593Smuzhiyun rockchip,pins = 772*4882a593Smuzhiyun <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, 773*4882a593Smuzhiyun <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; 774*4882a593Smuzhiyun }; 775*4882a593Smuzhiyun }; 776*4882a593Smuzhiyun 777*4882a593Smuzhiyun usb { 778*4882a593Smuzhiyun vcc5v0_host_en: vcc5v0-host-en { 779*4882a593Smuzhiyun rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 780*4882a593Smuzhiyun }; 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun usb-typec { 784*4882a593Smuzhiyun usbc0_int: usbc0-int { 785*4882a593Smuzhiyun rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; 786*4882a593Smuzhiyun }; 787*4882a593Smuzhiyun 788*4882a593Smuzhiyun typec5v_pwren: typec5v-pwren { 789*4882a593Smuzhiyun rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 790*4882a593Smuzhiyun }; 791*4882a593Smuzhiyun }; 792*4882a593Smuzhiyun 793*4882a593Smuzhiyun wireless-bluetooth { 794*4882a593Smuzhiyun uart9_gpios: uart9-gpios { 795*4882a593Smuzhiyun rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 796*4882a593Smuzhiyun }; 797*4882a593Smuzhiyun 798*4882a593Smuzhiyun bt_reset_gpio: bt-reset-gpio { 799*4882a593Smuzhiyun rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 800*4882a593Smuzhiyun }; 801*4882a593Smuzhiyun 802*4882a593Smuzhiyun bt_wake_gpio: bt-wake-gpio { 803*4882a593Smuzhiyun rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 804*4882a593Smuzhiyun }; 805*4882a593Smuzhiyun 806*4882a593Smuzhiyun bt_irq_gpio: bt-irq-gpio { 807*4882a593Smuzhiyun rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; 808*4882a593Smuzhiyun }; 809*4882a593Smuzhiyun }; 810*4882a593Smuzhiyun 811*4882a593Smuzhiyun wireless-wlan { 812*4882a593Smuzhiyun wifi_host_wake_irq: wifi-host-wake-irq { 813*4882a593Smuzhiyun rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 814*4882a593Smuzhiyun }; 815*4882a593Smuzhiyun }; 816*4882a593Smuzhiyun 817*4882a593Smuzhiyun pcie { 818*4882a593Smuzhiyun pcie20x1_0_clkreqn_m1: pcie20x1-0-clkreqn-m1 { 819*4882a593Smuzhiyun rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_output_low>; 820*4882a593Smuzhiyun }; 821*4882a593Smuzhiyun }; 822*4882a593Smuzhiyun}; 823*4882a593Smuzhiyun 824*4882a593Smuzhiyun&pwm1 { 825*4882a593Smuzhiyun status = "okay"; 826*4882a593Smuzhiyun}; 827*4882a593Smuzhiyun 828*4882a593Smuzhiyun&pwm3 { 829*4882a593Smuzhiyun pinctrl-0 = <&pwm3m1_pins>; 830*4882a593Smuzhiyun status = "okay"; 831*4882a593Smuzhiyun}; 832*4882a593Smuzhiyun 833*4882a593Smuzhiyun&route_dsi0 { 834*4882a593Smuzhiyun status = "okay"; 835*4882a593Smuzhiyun connect = <&vp3_out_dsi0>; 836*4882a593Smuzhiyun}; 837*4882a593Smuzhiyun 838*4882a593Smuzhiyun&route_dsi1 { 839*4882a593Smuzhiyun status = "disabled"; 840*4882a593Smuzhiyun connect = <&vp3_out_dsi1>; 841*4882a593Smuzhiyun}; 842*4882a593Smuzhiyun 843*4882a593Smuzhiyun&route_hdmi0 { 844*4882a593Smuzhiyun status = "okay"; 845*4882a593Smuzhiyun}; 846*4882a593Smuzhiyun 847*4882a593Smuzhiyun&route_hdmi1 { 848*4882a593Smuzhiyun status = "okay"; 849*4882a593Smuzhiyun}; 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun&sata0 { 852*4882a593Smuzhiyun status = "okay"; 853*4882a593Smuzhiyun}; 854*4882a593Smuzhiyun 855*4882a593Smuzhiyun&sdio { 856*4882a593Smuzhiyun max-frequency = <150000000>; 857*4882a593Smuzhiyun no-sd; 858*4882a593Smuzhiyun no-mmc; 859*4882a593Smuzhiyun bus-width = <4>; 860*4882a593Smuzhiyun disable-wp; 861*4882a593Smuzhiyun cap-sd-highspeed; 862*4882a593Smuzhiyun cap-sdio-irq; 863*4882a593Smuzhiyun keep-power-in-suspend; 864*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 865*4882a593Smuzhiyun non-removable; 866*4882a593Smuzhiyun pinctrl-names = "default"; 867*4882a593Smuzhiyun pinctrl-0 = <&sdiom0_pins>; 868*4882a593Smuzhiyun sd-uhs-sdr104; 869*4882a593Smuzhiyun status = "okay"; 870*4882a593Smuzhiyun}; 871*4882a593Smuzhiyun 872*4882a593Smuzhiyun&sdmmc { 873*4882a593Smuzhiyun status = "okay"; 874*4882a593Smuzhiyun vmmc-supply = <&vcc_3v3_sd_s0>; 875*4882a593Smuzhiyun}; 876*4882a593Smuzhiyun 877*4882a593Smuzhiyun&uart9 { 878*4882a593Smuzhiyun status = "okay"; 879*4882a593Smuzhiyun pinctrl-names = "default"; 880*4882a593Smuzhiyun pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; 881*4882a593Smuzhiyun}; 882*4882a593Smuzhiyun 883*4882a593Smuzhiyun&u2phy0_otg { 884*4882a593Smuzhiyun rockchip,typec-vbus-det; 885*4882a593Smuzhiyun}; 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun&u2phy1_otg { 888*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 889*4882a593Smuzhiyun}; 890*4882a593Smuzhiyun 891*4882a593Smuzhiyun&u2phy2_host { 892*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 893*4882a593Smuzhiyun}; 894*4882a593Smuzhiyun 895*4882a593Smuzhiyun&u2phy3_host { 896*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 897*4882a593Smuzhiyun}; 898*4882a593Smuzhiyun 899*4882a593Smuzhiyun&usbdp_phy0 { 900*4882a593Smuzhiyun orientation-switch; 901*4882a593Smuzhiyun svid = <0xff01>; 902*4882a593Smuzhiyun sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; 903*4882a593Smuzhiyun sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; 904*4882a593Smuzhiyun 905*4882a593Smuzhiyun port { 906*4882a593Smuzhiyun #address-cells = <1>; 907*4882a593Smuzhiyun #size-cells = <0>; 908*4882a593Smuzhiyun usbdp_phy0_orientation_switch: endpoint@0 { 909*4882a593Smuzhiyun reg = <0>; 910*4882a593Smuzhiyun remote-endpoint = <&usbc0_orien_sw>; 911*4882a593Smuzhiyun }; 912*4882a593Smuzhiyun 913*4882a593Smuzhiyun usbdp_phy0_dp_altmode_mux: endpoint@1 { 914*4882a593Smuzhiyun reg = <1>; 915*4882a593Smuzhiyun remote-endpoint = <&dp_altmode_mux>; 916*4882a593Smuzhiyun }; 917*4882a593Smuzhiyun }; 918*4882a593Smuzhiyun}; 919*4882a593Smuzhiyun 920*4882a593Smuzhiyun&usbdp_phy1 { 921*4882a593Smuzhiyun rockchip,dp-lane-mux = <0 1 2 3>; 922*4882a593Smuzhiyun}; 923*4882a593Smuzhiyun 924*4882a593Smuzhiyun&usbdrd_dwc3_0 { 925*4882a593Smuzhiyun dr_mode = "otg"; 926*4882a593Smuzhiyun usb-role-switch; 927*4882a593Smuzhiyun port { 928*4882a593Smuzhiyun #address-cells = <1>; 929*4882a593Smuzhiyun #size-cells = <0>; 930*4882a593Smuzhiyun dwc3_0_role_switch: endpoint@0 { 931*4882a593Smuzhiyun reg = <0>; 932*4882a593Smuzhiyun remote-endpoint = <&usbc0_role_sw>; 933*4882a593Smuzhiyun }; 934*4882a593Smuzhiyun }; 935*4882a593Smuzhiyun}; 936*4882a593Smuzhiyun 937*4882a593Smuzhiyun&usbhost3_0 { 938*4882a593Smuzhiyun status = "disabled"; 939*4882a593Smuzhiyun}; 940*4882a593Smuzhiyun 941*4882a593Smuzhiyun&usbhost_dwc3_0 { 942*4882a593Smuzhiyun status = "disabled"; 943*4882a593Smuzhiyun}; 944*4882a593Smuzhiyun 945*4882a593Smuzhiyun&work_led { 946*4882a593Smuzhiyun gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; 947*4882a593Smuzhiyun pinctrl-names = "default"; 948*4882a593Smuzhiyun pinctrl-0 = <&work_leds_gpio>; 949*4882a593Smuzhiyun}; 950