1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "dt-bindings/usb/pd.h" 8#include "rk3588.dtsi" 9#include "rk3588-evb.dtsi" 10#include "rk3588-rk806-single.dtsi" 11 12/ { 13 /* If hdmirx node is disabled, delete the reserved-memory node here. */ 14 reserved-memory { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 ranges; 18 19 /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ 20 cma { 21 compatible = "shared-dma-pool"; 22 reusable; 23 reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; 24 linux,cma-default; 25 }; 26 }; 27 28 es8388_sound: es8388-sound { 29 status = "okay"; 30 compatible = "rockchip,multicodecs-card"; 31 rockchip,card-name = "rockchip-es8388"; 32 hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; 33 io-channels = <&saradc 3>; 34 io-channel-names = "adc-detect"; 35 keyup-threshold-microvolt = <1800000>; 36 poll-interval = <100>; 37 spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 38 hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 39 rockchip,format = "i2s"; 40 rockchip,mclk-fs = <256>; 41 rockchip,cpu = <&i2s0_8ch>; 42 rockchip,codec = <&es8388>; 43 rockchip,audio-routing = 44 "Headphone", "LOUT1", 45 "Headphone", "ROUT1", 46 "Speaker", "LOUT2", 47 "Speaker", "ROUT2", 48 "Headphone", "Headphone Power", 49 "Headphone", "Headphone Power", 50 "Speaker", "Speaker Power", 51 "Speaker", "Speaker Power", 52 "LINPUT1", "Main Mic", 53 "LINPUT2", "Main Mic", 54 "RINPUT1", "Headset Mic", 55 "RINPUT2", "Headset Mic"; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&hp_det>; 58 play-pause-key { 59 label = "playpause"; 60 linux,code = <KEY_PLAYPAUSE>; 61 press-threshold-microvolt = <2000>; 62 }; 63 }; 64 65 fan: pwm-fan { 66 compatible = "pwm-fan"; 67 #cooling-cells = <2>; 68 pwms = <&pwm3 0 50000 0>; 69 cooling-levels = <0 50 100 150 200 255>; 70 rockchip,temp-trips = < 71 50000 1 72 55000 2 73 60000 3 74 65000 4 75 70000 5 76 >; 77 }; 78 79 hdmiin-sound { 80 compatible = "rockchip,hdmi"; 81 rockchip,mclk-fs = <128>; 82 rockchip,format = "i2s"; 83 rockchip,bitclock-master = <&hdmirx_ctrler>; 84 rockchip,frame-master = <&hdmirx_ctrler>; 85 rockchip,card-name = "rockchip,hdmiin"; 86 rockchip,cpu = <&i2s7_8ch>; 87 rockchip,codec = <&hdmirx_ctrler 0>; 88 rockchip,jack-det; 89 }; 90 91 pcie20_avdd0v85: pcie20-avdd0v85 { 92 compatible = "regulator-fixed"; 93 regulator-name = "pcie20_avdd0v85"; 94 regulator-boot-on; 95 regulator-always-on; 96 regulator-min-microvolt = <850000>; 97 regulator-max-microvolt = <850000>; 98 vin-supply = <&vdd_0v85_s0>; 99 }; 100 101 pcie20_avdd1v8: pcie20-avdd1v8 { 102 compatible = "regulator-fixed"; 103 regulator-name = "pcie20_avdd1v8"; 104 regulator-boot-on; 105 regulator-always-on; 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 vin-supply = <&avcc_1v8_s0>; 109 }; 110 111 pcie30_avdd0v75: pcie30-avdd0v75 { 112 compatible = "regulator-fixed"; 113 regulator-name = "pcie30_avdd0v75"; 114 regulator-boot-on; 115 regulator-always-on; 116 regulator-min-microvolt = <750000>; 117 regulator-max-microvolt = <750000>; 118 vin-supply = <&avdd_0v75_s0>; 119 }; 120 121 pcie30_avdd1v8: pcie30-avdd1v8 { 122 compatible = "regulator-fixed"; 123 regulator-name = "pcie30_avdd1v8"; 124 regulator-boot-on; 125 regulator-always-on; 126 regulator-min-microvolt = <1800000>; 127 regulator-max-microvolt = <1800000>; 128 vin-supply = <&avcc_1v8_s0>; 129 }; 130 131 sdio_pwrseq: sdio-pwrseq { 132 compatible = "mmc-pwrseq-simple"; 133 clocks = <&hym8563>; 134 clock-names = "ext_clock"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&wifi_enable_h>; 137 /* 138 * On the module itself this is one of these (depending 139 * on the actual card populated): 140 * - SDIO_RESET_L_WL_REG_ON 141 * - PDN (power down when low) 142 */ 143 post-power-on-delay-ms = <200>; 144 reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; 145 }; 146 147 rk_headset: rk-headset { 148 status = "disabled"; 149 compatible = "rockchip_headset"; 150 headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&hp_det>; 153 io-channels = <&saradc 3>; 154 }; 155 156 157 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { 158 compatible = "regulator-fixed"; 159 regulator-name = "vcc_1v1_nldo_s3"; 160 regulator-always-on; 161 regulator-boot-on; 162 regulator-min-microvolt = <1100000>; 163 regulator-max-microvolt = <1100000>; 164 vin-supply = <&vcc5v0_sys>; 165 }; 166 167 vbus5v0_typec: vbus5v0-typec { 168 compatible = "regulator-fixed"; 169 regulator-name = "vbus5v0_typec"; 170 regulator-min-microvolt = <5000000>; 171 regulator-max-microvolt = <5000000>; 172 enable-active-high; 173 gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 174 vin-supply = <&vcc5v0_usb>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&typec5v_pwren>; 177 }; 178 179 vcc3v3_lcd_n: vcc3v3-lcd0-n { 180 compatible = "regulator-fixed"; 181 regulator-name = "vcc3v3_lcd0_n"; 182 regulator-boot-on; 183 enable-active-high; 184 gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 185 vin-supply = <&vcc_1v8_s0>; 186 }; 187 188 vcc3v3_pcie30: vcc3v3-pcie30 { 189 compatible = "regulator-fixed"; 190 regulator-name = "vcc3v3_pcie30"; 191 regulator-min-microvolt = <3300000>; 192 regulator-max-microvolt = <3300000>; 193 enable-active-high; 194 gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; 195 startup-delay-us = <5000>; 196 vin-supply = <&vcc12v_dcin>; 197 }; 198 199 vcc5v0_host: vcc5v0-host { 200 compatible = "regulator-fixed"; 201 regulator-name = "vcc5v0_host"; 202 regulator-boot-on; 203 regulator-always-on; 204 regulator-min-microvolt = <5000000>; 205 regulator-max-microvolt = <5000000>; 206 enable-active-high; 207 gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 208 vin-supply = <&vcc5v0_usb>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&vcc5v0_host_en>; 211 }; 212 213 vcc_mipicsi0: vcc-mipicsi0-regulator { 214 compatible = "regulator-fixed"; 215 gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&mipicsi0_pwr>; 218 regulator-name = "vcc_mipicsi0"; 219 enable-active-high; 220 }; 221 222 vcc_mipicsi1: vcc-mipicsi1-regulator { 223 compatible = "regulator-fixed"; 224 gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&mipicsi1_pwr>; 227 regulator-name = "vcc_mipicsi1"; 228 enable-active-high; 229 }; 230 231 vcc_mipidcphy0: vcc-mipidcphy0-regulator { 232 compatible = "regulator-fixed"; 233 gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&mipidcphy0_pwr>; 236 regulator-name = "vcc_mipidcphy0"; 237 enable-active-high; 238 }; 239 240 vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { 241 compatible = "regulator-fixed"; 242 gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&sd_s0_pwr>; 245 regulator-name = "vcc_3v3_sd_s0"; 246 enable-active-high; 247 }; 248 249 wireless_bluetooth: wireless-bluetooth { 250 compatible = "bluetooth-platdata"; 251 clocks = <&hym8563>; 252 clock-names = "ext_clock"; 253 uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; 254 pinctrl-names = "default", "rts_gpio"; 255 pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 256 pinctrl-1 = <&uart9_gpios>; 257 BT,reset_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 258 BT,wake_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 259 BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 260 status = "okay"; 261 }; 262 263 wireless_wlan: wireless-wlan { 264 compatible = "wlan-platdata"; 265 wifi_chip_type = "ap6398s"; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&wifi_host_wake_irq>; 268 WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; 269 WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; 270 status = "okay"; 271 }; 272}; 273 274&backlight { 275 pwms = <&pwm1 0 25000 0>; 276 status = "okay"; 277}; 278 279&combphy0_ps { 280 status = "okay"; 281}; 282 283&combphy1_ps { 284 status = "okay"; 285}; 286 287&combphy2_psu { 288 status = "okay"; 289}; 290 291&dp0 { 292 status = "okay"; 293}; 294&dp0_in_vp2 { 295 status = "okay"; 296}; 297 298&dp0_sound{ 299 status = "okay"; 300}; 301&dp1 { 302 pinctrl-names = "default"; 303 pinctrl-0 = <&dp1m0_pins>; 304 status = "okay"; 305}; 306 307&dp1_in_vp2 { 308 status = "okay"; 309}; 310 311/* 312 * mipi_dcphy0 needs to be enabled 313 * when dsi0 is enabled 314 */ 315&dsi0 { 316 status = "okay"; 317}; 318 319&dsi0_in_vp2 { 320 status = "disabled"; 321}; 322 323&dsi0_in_vp3 { 324 status = "okay"; 325}; 326 327&dsi0_panel { 328 power-supply = <&vcc3v3_lcd_n>; 329 reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&lcd_rst_gpio>; 332}; 333 334/* 335 * mipi_dcphy1 needs to be enabled 336 * when dsi1 is enabled 337 */ 338&dsi1 { 339 status = "disabled"; 340}; 341 342&dsi1_in_vp2 { 343 status = "disabled"; 344}; 345 346&dsi1_in_vp3 { 347 status = "disabled"; 348}; 349 350&dsi1_panel { 351 power-supply = <&vcc3v3_lcd_n>; 352 353 /* 354 * because in hardware, the two screens share the reset pin, 355 * so reset-gpios need only in dsi1 enable and dsi0 disabled 356 * case. 357 */ 358 359 //reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; 360 //pinctrl-names = "default"; 361 //pinctrl-0 = <&lcd_rst_gpio>; 362}; 363 364&gmac1 { 365 /* Use rgmii-rxid mode to disable rx delay inside Soc */ 366 phy-mode = "rgmii-rxid"; 367 clock_in_out = "output"; 368 369 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 370 snps,reset-active-low; 371 /* Reset time is 20ms, 100ms for rtl8211f */ 372 snps,reset-delays-us = <0 20000 100000>; 373 374 pinctrl-names = "default"; 375 pinctrl-0 = <&gmac1_miim 376 &gmac1_tx_bus2 377 &gmac1_rx_bus2 378 &gmac1_rgmii_clk 379 &gmac1_rgmii_bus>; 380 381 tx_delay = <0x43>; 382 /* rx_delay = <0x3f>; */ 383 384 phy-handle = <&rgmii_phy>; 385 status = "okay"; 386}; 387 388&hdmi0 { 389 enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 390 status = "okay"; 391}; 392 393&hdmi0_in_vp0 { 394 status = "okay"; 395}; 396 397&hdmi0_sound { 398 status = "okay"; 399}; 400 401&hdmi1 { 402 enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 403 status = "okay"; 404}; 405 406&hdmi1_in_vp1 { 407 status = "okay"; 408}; 409 410&hdmi1_sound { 411 status = "okay"; 412}; 413 414/* Should work with at least 128MB cma reserved above. */ 415&hdmirx_ctrler { 416 status = "okay"; 417 418 #sound-dai-cells = <1>; 419 /* Effective level used to trigger HPD: 0-low, 1-high */ 420 hpd-trigger-level = <1>; 421 hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&hdmim1_rx &hdmirx_det>; 424}; 425 426&hdptxphy_hdmi0 { 427 status = "okay"; 428}; 429 430&hdptxphy_hdmi1 { 431 status = "okay"; 432}; 433 434&i2c0 { 435 status = "okay"; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&i2c0m2_xfer>; 438 439 vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 440 compatible = "rockchip,rk8602"; 441 reg = <0x42>; 442 vin-supply = <&vcc5v0_sys>; 443 regulator-compatible = "rk860x-reg"; 444 regulator-name = "vdd_cpu_big0_s0"; 445 regulator-min-microvolt = <550000>; 446 regulator-max-microvolt = <1050000>; 447 regulator-ramp-delay = <2300>; 448 rockchip,suspend-voltage-selector = <1>; 449 regulator-boot-on; 450 regulator-always-on; 451 regulator-state-mem { 452 regulator-off-in-suspend; 453 }; 454 }; 455 456 vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 457 compatible = "rockchip,rk8603"; 458 reg = <0x43>; 459 vin-supply = <&vcc5v0_sys>; 460 regulator-compatible = "rk860x-reg"; 461 regulator-name = "vdd_cpu_big1_s0"; 462 regulator-min-microvolt = <550000>; 463 regulator-max-microvolt = <1050000>; 464 regulator-ramp-delay = <2300>; 465 rockchip,suspend-voltage-selector = <1>; 466 regulator-boot-on; 467 regulator-always-on; 468 regulator-state-mem { 469 regulator-off-in-suspend; 470 }; 471 }; 472}; 473 474&i2c1 { 475 status = "okay"; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&i2c1m2_xfer>; 478 479 vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 480 compatible = "rockchip,rk8602"; 481 reg = <0x42>; 482 vin-supply = <&vcc5v0_sys>; 483 regulator-compatible = "rk860x-reg"; 484 regulator-name = "vdd_npu_s0"; 485 regulator-min-microvolt = <550000>; 486 regulator-max-microvolt = <950000>; 487 regulator-ramp-delay = <2300>; 488 rockchip,suspend-voltage-selector = <1>; 489 regulator-boot-on; 490 regulator-always-on; 491 regulator-state-mem { 492 regulator-off-in-suspend; 493 }; 494 }; 495}; 496 497&i2c4 { 498 status = "okay"; 499 pinctrl-0 = <&i2c4m1_xfer>; 500 501 ls_stk3332: light@47 { 502 compatible = "ls_stk3332"; 503 status = "disabled"; 504 reg = <0x47>; 505 type = <SENSOR_TYPE_LIGHT>; 506 irq_enable = <0>; 507 als_threshold_high = <100>; 508 als_threshold_low = <10>; 509 als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ 510 poll_delay_ms = <100>; 511 }; 512 513 ps_stk3332: proximity@47 { 514 compatible = "ps_stk3332"; 515 status = "disabled"; 516 reg = <0x47>; 517 type = <SENSOR_TYPE_PROXIMITY>; 518 //pinctrl-names = "default"; 519 //pinctrl-0 = <&gpio3_c6>; 520 //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; 521 //irq_enable = <1>; 522 ps_threshold_high = <0x200>; 523 ps_threshold_low = <0x100>; 524 ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ 525 ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ 526 poll_delay_ms = <100>; 527 }; 528 529 icm42607_acc: icm_acc@68 { 530 status = "okay"; 531 compatible = "icm42607_acc"; 532 reg = <0x68>; 533 irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_EDGE_RISING>; 534 irq_enable = <0>; 535 poll_delay_ms = <30>; 536 type = <SENSOR_TYPE_ACCEL>; 537 layout = <0>; 538 }; 539 540 icm42607_gyro: icm_gyro@68 { 541 status = "okay"; 542 compatible = "icm42607_gyro"; 543 reg = <0x68>; 544 poll_delay_ms = <30>; 545 type = <SENSOR_TYPE_GYROSCOPE>; 546 layout = <0>; 547 }; 548}; 549 550&i2c5 { 551 status = "okay"; 552 gt1x: gt1x@14 { 553 compatible = "goodix,gt1x"; 554 reg = <0x14>; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&touch_gpio>; 557 goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; 558 goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; 559 power-supply = <&vcc3v3_lcd_n>; 560 }; 561}; 562 563&i2c6 { 564 status = "okay"; 565 566 usbc0: husb311@4e { 567 compatible = "hynetek,husb311"; 568 reg = <0x4e>; 569 interrupt-parent = <&gpio3>; 570 interrupts = <RK_PB6 IRQ_TYPE_LEVEL_LOW>; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&usbc0_int>; 573 vbus-supply = <&vbus5v0_typec>; 574 status = "okay"; 575 576 ports { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 580 port@0 { 581 reg = <0>; 582 usbc0_role_sw: endpoint@0 { 583 remote-endpoint = <&dwc3_0_role_switch>; 584 }; 585 }; 586 }; 587 588 usb_con: connector { 589 compatible = "usb-c-connector"; 590 label = "USB-C"; 591 data-role = "dual"; 592 power-role = "dual"; 593 try-power-role = "sink"; 594 op-sink-microwatt = <1000000>; 595 sink-pdos = 596 <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 597 source-pdos = 598 <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 599 600 altmodes { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 604 altmode@0 { 605 reg = <0>; 606 svid = <0xff01>; 607 vdo = <0xffffffff>; 608 }; 609 }; 610 611 ports { 612 #address-cells = <1>; 613 #size-cells = <0>; 614 615 port@0 { 616 reg = <0>; 617 usbc0_orien_sw: endpoint { 618 remote-endpoint = <&usbdp_phy0_orientation_switch>; 619 }; 620 }; 621 622 port@1 { 623 reg = <1>; 624 dp_altmode_mux: endpoint { 625 remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 626 }; 627 }; 628 }; 629 }; 630 }; 631 632 hym8563: hym8563@51 { 633 compatible = "haoyu,hym8563"; 634 reg = <0x51>; 635 #clock-cells = <0>; 636 clock-frequency = <32768>; 637 clock-output-names = "hym8563"; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&hym8563_int>; 640 interrupt-parent = <&gpio0>; 641 interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 642 wakeup-source; 643 }; 644}; 645 646&i2c7 { 647 status = "okay"; 648 es8388: es8388@11 { 649 status = "okay"; 650 #sound-dai-cells = <0>; 651 compatible = "everest,es8388", "everest,es8323"; 652 reg = <0x11>; 653 clocks = <&mclkout_i2s0>; 654 clock-names = "mclk"; 655 assigned-clocks = <&mclkout_i2s0>; 656 assigned-clock-rates = <12288000>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&i2s0_mclk>; 659 }; 660}; 661 662&i2s5_8ch { 663 status = "okay"; 664}; 665 666&i2s6_8ch { 667 status = "okay"; 668}; 669 670&i2s7_8ch { 671 status = "okay"; 672}; 673 674&mdio1 { 675 rgmii_phy: phy@1 { 676 compatible = "ethernet-phy-ieee802.3-c22"; 677 reg = <0x1>; 678 }; 679}; 680 681&mipi_dcphy0 { 682 status = "okay"; 683}; 684 685&mipi_dcphy1 { 686 status = "disabled"; 687}; 688 689&pcie2x1l0 { 690 reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; 691 status = "okay"; 692}; 693 694&pcie30phy { 695 rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>; 696 status = "okay"; 697}; 698 699&pcie3x4 { 700 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 701 vpcie3v3-supply = <&vcc3v3_pcie30>; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&pcie20x1_0_clkreqn_m1>; 704 status = "okay"; 705}; 706 707&pinctrl { 708 cam { 709 mipicsi0_pwr: mipicsi0-pwr { 710 rockchip,pins = 711 /* camera power en */ 712 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 713 }; 714 mipicsi1_pwr: mipicsi1-pwr { 715 rockchip,pins = 716 /* camera power en */ 717 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 718 }; 719 mipidcphy0_pwr: mipidcphy0-pwr { 720 rockchip,pins = 721 /* camera power en */ 722 <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 723 }; 724 }; 725 726 727 hdmi { 728 hdmirx_det: hdmirx-det { 729 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; 730 }; 731 }; 732 733 headphone { 734 hp_det: hp-det { 735 rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 736 }; 737 }; 738 739 hym8563 { 740 hym8563_int: hym8563-int { 741 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 742 }; 743 }; 744 745 lcd { 746 lcd_rst_gpio: lcd-rst-gpio { 747 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 748 }; 749 }; 750 751 leds { 752 work_leds_gpio: work-leds-gpio { 753 rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; 754 }; 755 }; 756 757 sdio-pwrseq { 758 wifi_enable_h: wifi-enable-h { 759 rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; 760 }; 761 }; 762 763 sdmmc { 764 sd_s0_pwr: sd-s0-pwr { 765 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; 766 }; 767 }; 768 769 touch { 770 touch_gpio: touch-gpio { 771 rockchip,pins = 772 <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, 773 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; 774 }; 775 }; 776 777 usb { 778 vcc5v0_host_en: vcc5v0-host-en { 779 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 780 }; 781 }; 782 783 usb-typec { 784 usbc0_int: usbc0-int { 785 rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; 786 }; 787 788 typec5v_pwren: typec5v-pwren { 789 rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 790 }; 791 }; 792 793 wireless-bluetooth { 794 uart9_gpios: uart9-gpios { 795 rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 796 }; 797 798 bt_reset_gpio: bt-reset-gpio { 799 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 800 }; 801 802 bt_wake_gpio: bt-wake-gpio { 803 rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 804 }; 805 806 bt_irq_gpio: bt-irq-gpio { 807 rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; 808 }; 809 }; 810 811 wireless-wlan { 812 wifi_host_wake_irq: wifi-host-wake-irq { 813 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 814 }; 815 }; 816 817 pcie { 818 pcie20x1_0_clkreqn_m1: pcie20x1-0-clkreqn-m1 { 819 rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_output_low>; 820 }; 821 }; 822}; 823 824&pwm1 { 825 status = "okay"; 826}; 827 828&pwm3 { 829 pinctrl-0 = <&pwm3m1_pins>; 830 status = "okay"; 831}; 832 833&route_dsi0 { 834 status = "okay"; 835 connect = <&vp3_out_dsi0>; 836}; 837 838&route_dsi1 { 839 status = "disabled"; 840 connect = <&vp3_out_dsi1>; 841}; 842 843&route_hdmi0 { 844 status = "okay"; 845}; 846 847&route_hdmi1 { 848 status = "okay"; 849}; 850 851&sata0 { 852 status = "okay"; 853}; 854 855&sdio { 856 max-frequency = <150000000>; 857 no-sd; 858 no-mmc; 859 bus-width = <4>; 860 disable-wp; 861 cap-sd-highspeed; 862 cap-sdio-irq; 863 keep-power-in-suspend; 864 mmc-pwrseq = <&sdio_pwrseq>; 865 non-removable; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&sdiom0_pins>; 868 sd-uhs-sdr104; 869 status = "okay"; 870}; 871 872&sdmmc { 873 status = "okay"; 874 vmmc-supply = <&vcc_3v3_sd_s0>; 875}; 876 877&uart9 { 878 status = "okay"; 879 pinctrl-names = "default"; 880 pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; 881}; 882 883&u2phy0_otg { 884 rockchip,typec-vbus-det; 885}; 886 887&u2phy1_otg { 888 phy-supply = <&vcc5v0_host>; 889}; 890 891&u2phy2_host { 892 phy-supply = <&vcc5v0_host>; 893}; 894 895&u2phy3_host { 896 phy-supply = <&vcc5v0_host>; 897}; 898 899&usbdp_phy0 { 900 orientation-switch; 901 svid = <0xff01>; 902 sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; 903 sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; 904 905 port { 906 #address-cells = <1>; 907 #size-cells = <0>; 908 usbdp_phy0_orientation_switch: endpoint@0 { 909 reg = <0>; 910 remote-endpoint = <&usbc0_orien_sw>; 911 }; 912 913 usbdp_phy0_dp_altmode_mux: endpoint@1 { 914 reg = <1>; 915 remote-endpoint = <&dp_altmode_mux>; 916 }; 917 }; 918}; 919 920&usbdp_phy1 { 921 rockchip,dp-lane-mux = <0 1 2 3>; 922}; 923 924&usbdrd_dwc3_0 { 925 dr_mode = "otg"; 926 usb-role-switch; 927 port { 928 #address-cells = <1>; 929 #size-cells = <0>; 930 dwc3_0_role_switch: endpoint@0 { 931 reg = <0>; 932 remote-endpoint = <&usbc0_role_sw>; 933 }; 934 }; 935}; 936 937&usbhost3_0 { 938 status = "disabled"; 939}; 940 941&usbhost_dwc3_0 { 942 status = "disabled"; 943}; 944 945&work_led { 946 gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&work_leds_gpio>; 949}; 950